VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 1241

Last change on this file since 1241 was 1212, checked in by vboxsync, 18 years ago

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1/* $Id: CPUM.cpp 1212 2007-03-05 12:56:49Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager)
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_CPUM
27#include <VBox/cpum.h>
28#include <VBox/cpumdis.h>
29#include <VBox/pgm.h>
30#include <VBox/mm.h>
31#include <VBox/selm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/ssm.h>
35#include "CPUMInternal.h"
36#include <VBox/vm.h>
37
38#include <VBox/param.h>
39#include <VBox/dis.h>
40#include <VBox/err.h>
41#include <VBox/log.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <iprt/system.h>
46#include "x86context.h"
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51/** The saved state version. */
52#define CPUM_SAVED_STATE_VERSION 3
53
54
55/*******************************************************************************
56* Structures and Typedefs *
57*******************************************************************************/
58
59/**
60 * What kind of cpu info dump to performe.
61 */
62typedef enum CPUMDUMPTYPE
63{
64 CPUMDUMPTYPE_TERSE,
65 CPUMDUMPTYPE_DEFAULT,
66 CPUMDUMPTYPE_VERBOSE
67
68} CPUMDUMPTYPE, *PCPUMDUMPTYPE;
69
70
71/*******************************************************************************
72* Internal Functions *
73*******************************************************************************/
74static int cpumR3CpuIdInit(PVM pVM);
75static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
76static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
77static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
78static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
79static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
80static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
81static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
82
83
84/**
85 * Initializes the CPUM.
86 *
87 * @returns VBox status code.
88 * @param pVM The VM to operate on.
89 */
90CPUMR3DECL(int) CPUMR3Init(PVM pVM)
91{
92 LogFlow(("CPUMR3Init\n"));
93
94 /*
95 * Assert alignment and sizes.
96 */
97 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
98 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
99
100 /*
101 * Setup any fixed pointers and offsets.
102 */
103 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
104 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
105 pVM->cpum.s.pHyperCoreHC = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
106
107 /* Hidden selector registers are invalid by default. */
108 pVM->cpum.s.fValidHiddenSelRegs = false;
109
110 /*
111 * Check that the CPU supports the minimum features we require.
112 */
113 /** @todo check the contract! */
114 if (!ASMHasCpuId())
115 {
116 Log(("The CPU doesn't support CPUID!\n"));
117 return VERR_UNSUPPORTED_CPU;
118 }
119 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
120
121 /* Setup the CR4 AND and OR masks used in the switcher */
122 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
123 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
124 {
125 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
126 /* No FXSAVE implies no SSE */
127 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
128 pVM->cpum.s.CR4.OrMask = 0;
129 }
130 else
131 {
132 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
133 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
134 }
135
136 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
137 {
138 Log(("The CPU doesn't support MMX!\n"));
139 return VERR_UNSUPPORTED_CPU;
140 }
141 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
142 {
143 Log(("The CPU doesn't support TSC!\n"));
144 return VERR_UNSUPPORTED_CPU;
145 }
146 /* Bogus on AMD? */
147 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
148 {
149 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
150 }
151
152 /*
153 * Setup hypervisor startup values.
154 */
155
156 /*
157 * Register saved state data item.
158 */
159 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
160 NULL, cpumR3Save, NULL,
161 NULL, cpumR3Load, NULL);
162 if (VBOX_FAILURE(rc))
163 return rc;
164
165 /*
166 * Register info handlers.
167 */
168 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
169 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
170 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
171 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
172 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leafs.", &cpumR3CpuIdInfo);
173
174 /*
175 * Initialize the Guest CPU state.
176 */
177 rc = cpumR3CpuIdInit(pVM);
178 if (VBOX_FAILURE(rc))
179 return rc;
180 CPUMR3Reset(pVM);
181 return VINF_SUCCESS;
182}
183
184
185/**
186 * Initializes the emulated CPU's cpuid information.
187 *
188 * @returns VBox status code.
189 * @param pVM The VM to operate on.
190 */
191static int cpumR3CpuIdInit(PVM pVM)
192{
193 PCPUM pCPUM = &pVM->cpum.s;
194 uint32_t i;
195
196 /*
197 * Get the host CPUIDs.
198 */
199 for (i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
200 ASMCpuId(i,
201 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
202 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
203 for (i = 0; i < ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
204 ASMCpuId(0x80000000 + i,
205 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
206 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
207
208 /*
209 * Only report features we can support.
210 */
211 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
212 //| X86_CPUID_FEATURE_EDX_VME - recompiler doesn't do this.
213 | X86_CPUID_FEATURE_EDX_DE
214 | X86_CPUID_FEATURE_EDX_PSE
215 | X86_CPUID_FEATURE_EDX_TSC
216 | X86_CPUID_FEATURE_EDX_MSR
217 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
218 | X86_CPUID_FEATURE_EDX_MCE
219 | X86_CPUID_FEATURE_EDX_CX8
220 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
221 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
222 //| X86_CPUID_FEATURE_EDX_SEP
223 //| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
224 | X86_CPUID_FEATURE_EDX_PGE
225 //| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
226 | X86_CPUID_FEATURE_EDX_CMOV
227 //| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
228 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
229 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
230 //| X86_CPUID_FEATURE_EDX_CLFSH - no CLFLUSH instruction.
231 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
232 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
233 | X86_CPUID_FEATURE_EDX_MMX
234 | X86_CPUID_FEATURE_EDX_FXSR
235 | X86_CPUID_FEATURE_EDX_SSE
236 | X86_CPUID_FEATURE_EDX_SSE2
237 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
238 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
239 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
240 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
241 | 0;
242 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
243 | X86_CPUID_FEATURE_ECX_MONITOR
244 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
245 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
246 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
247 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
248 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
249 | 0;
250
251#if 1 /* we didn't used to do this, but I guess we should */
252 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
253 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
254 //| X86_CPUID_AMD_FEATURE_EDX_VME - recompiler doesn't do this.
255 | X86_CPUID_AMD_FEATURE_EDX_DE
256 | X86_CPUID_AMD_FEATURE_EDX_PSE
257 | X86_CPUID_AMD_FEATURE_EDX_TSC
258 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
259 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
260 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
261 | X86_CPUID_AMD_FEATURE_EDX_CX8
262 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
263 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
264 //| X86_CPUID_AMD_FEATURE_EDX_SEP
265 //| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
266 | X86_CPUID_AMD_FEATURE_EDX_PGE
267 //| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
268 | X86_CPUID_AMD_FEATURE_EDX_CMOV
269 | X86_CPUID_AMD_FEATURE_EDX_PAT
270 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
271 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
272 | X86_CPUID_AMD_FEATURE_EDX_MMX
273 | X86_CPUID_AMD_FEATURE_EDX_FXSR
274 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
275 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - definintly not.
276 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
277 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
278 | 0;
279 pCPUM->aGuestCpuIdExt[1].ecx &= 0//X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
280 | 0;
281#endif
282
283#if 0 /* this is what we used to do. */
284 /*
285 * Set BrandIndex=0, CLFLUSH-line-size=0, Num-Logical-Cpus=0 and APIC-ID=0.
286 */
287 pCPUM->aGuestCpuIdStd[1].ebx = 0;
288
289 /*
290 * Set the max standard index to 2.
291 */
292 pCPUM->aGuestCpuIdStd[0].eax = 2;
293 pCPUM->GuestCpuIdDef = pCPUM->aGuestCpuIdStd[2]; /** @todo this default is *NOT* right for AMD, only Intel CPUs. (see tstInlineAsm) */
294
295#else /* this is what we probably should do */
296 /*
297 * Hide HTT, multicode, SMP, whatever.
298 * (APIC-ID := 0 and #LogCpus := 0)
299 */
300 pCPUM->aGuestCpuIdStd[1].ebx = 0x0000ffff;
301
302 /*
303 * Determin the default value and limit it the number of entries.
304 * Intel returns values of the highest standard function, while AMD returns zeros.
305 */
306 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
307 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
308 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
309
310 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
311 pCPUM->aGuestCpuIdStd[0].eax = 2;
312
313 if (pCPUM->aGuestCpuIdExt[0].eax > 0x80000004)
314 pCPUM->aGuestCpuIdExt[0].eax = 0x80000004;
315
316#endif
317
318 /*
319 * Assign defaults to the entries we chopped off.
320 */
321 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
322 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
323 for (i = pCPUM->aGuestCpuIdExt[0].eax - 0x80000000 + 1; i < ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
324 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
325
326 /*
327 * Load CPUID overrides from configuration.
328 */
329 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
330 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
331 for (;;)
332 {
333 while (cElements-- < 0)
334 {
335 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
336 if (pNode)
337 {
338 uint32_t u32;
339 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
340 if (VBOX_SUCCESS(rc))
341 pCpuId->eax = u32;
342 else
343 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
344
345 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
346 if (VBOX_SUCCESS(rc))
347 pCpuId->ebx = u32;
348 else
349 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
350
351 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
352 if (VBOX_SUCCESS(rc))
353 pCpuId->ecx = u32;
354 else
355 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
356
357 rc = CFGMR3QueryU32(pNode, "edx", &u32);
358 if (VBOX_SUCCESS(rc))
359 pCpuId->edx = u32;
360 else
361 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
362 }
363 }
364
365 /* next */
366 if (i & 0x80000000)
367 break;
368 pCpuId = &pCPUM->aGuestCpuIdExt[0];
369 cElements = ELEMENTS(pCPUM->aGuestCpuIdExt);
370 i = 0x80000000;
371 }
372
373 /*
374 * Log the cpuid and we're good.
375 */
376 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
377 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
378 LogRel(("************************* CPUID dump ************************\n"));
379 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
380 LogRel(("\n"));
381 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
382 LogRel(("******************** End of CPUID dump **********************\n"));
383 return VINF_SUCCESS;
384}
385
386
387
388
389/**
390 * Applies relocations to data and code managed by this
391 * component. This function will be called at init and
392 * whenever the VMM need to relocate it self inside the GC.
393 *
394 * The CPUM will update the addresses used by the switcher.
395 *
396 * @param pVM The VM.
397 */
398CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
399{
400 LogFlow(("CPUMR3Relocate\n"));
401 /*
402 * Switcher pointers.
403 */
404 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
405 pVM->cpum.s.pHyperCoreGC = MMHyperHC2GC(pVM, pVM->cpum.s.pHyperCoreHC);
406}
407
408
409/**
410 * Queries the pointer to the internal CPUMCTX structure
411 *
412 * @returns VBox status code.
413 * @param pVM Handle to the virtual machine.
414 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
415 */
416CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx)
417{
418 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
419 /*
420 * Store the address. (Later we might check how's calling, thus the RC.)
421 */
422 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
423 return VINF_SUCCESS;
424}
425
426
427/**
428 * Terminates the CPUM.
429 *
430 * Termination means cleaning up and freeing all resources,
431 * the VM it self is at this point powered off or suspended.
432 *
433 * @returns VBox status code.
434 * @param pVM The VM to operate on.
435 */
436CPUMR3DECL(int) CPUMR3Term(PVM pVM)
437{
438 /** @todo */
439 return 0;
440}
441
442
443/**
444 * Resets the CPU.
445 *
446 * @returns VINF_SUCCESS.
447 * @param pVM The VM handle.
448 */
449CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
450{
451 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
452
453 /*
454 * Initialize everything to ZERO first.
455 */
456 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
457 memset(pCtx, 0, sizeof(*pCtx));
458 pVM->cpum.s.fUseFlags = fUseFlags;
459
460 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
461 pCtx->eip = 0x0000fff0;
462 pCtx->edx = 0x00000600; /* P6 processor */
463 pCtx->eflags.Bits.u1Reserved0 = 1;
464
465 pCtx->cs = 0xf000;
466 pCtx->csHid.u32Base = 0xffff0000;
467 pCtx->csHid.u32Limit = 0x0000ffff;
468 pCtx->dsHid.u32Limit = 0x0000ffff;
469 pCtx->esHid.u32Limit = 0x0000ffff;
470 pCtx->fsHid.u32Limit = 0x0000ffff;
471 pCtx->gsHid.u32Limit = 0x0000ffff;
472 pCtx->ssHid.u32Limit = 0x0000ffff;
473 pCtx->idtr.cbIdt = 0xffff;
474 pCtx->gdtr.cbGdt = 0xffff;
475 pCtx->ldtrHid.u32Limit = 0xffff;
476 pCtx->ldtrHid.Attr.u = X86_DESC_P;
477 pCtx->trHid.u32Limit = 0xffff;
478 pCtx->trHid.Attr.u = X86_DESC_P;
479
480 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
481 pCtx->fpu.FCW = 0x37f;
482}
483
484
485
486/**
487 * Execute state save operation.
488 *
489 * @returns VBox status code.
490 * @param pVM VM Handle.
491 * @param pSSM SSM operation handle.
492 */
493static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
494{
495 /*
496 * Save.
497 */
498 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
499 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
500 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
501 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
502
503 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
504 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
505
506 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
507 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
508
509 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
510
511 /* Add the cpuid for checking that the cpu is unchanged. */
512 uint32_t au32CpuId[8] = {0};
513 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
514 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
515 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
516}
517
518
519/**
520 * Execute state load operation.
521 *
522 * @returns VBox status code.
523 * @param pVM VM Handle.
524 * @param pSSM SSM operation handle.
525 * @param u32Version Data layout version.
526 */
527static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
528{
529 /*
530 * Validate version.
531 */
532 if (u32Version != CPUM_SAVED_STATE_VERSION)
533 {
534 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
535 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
536 }
537
538 /*
539 * Restore.
540 */
541 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
542 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
543 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
544 pVM->cpum.s.Hyper.cr3 = uCR3;
545 pVM->cpum.s.Hyper.esp = uESP;
546 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
547 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
548 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
549
550 uint32_t cElements;
551 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
552 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
553 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
554 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
555
556 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
557 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
558 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
559 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
560
561 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
562
563 /*
564 * Check that the basic cpuid id information is unchanged.
565 */
566 uint32_t au32CpuId[8] = {0};
567 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
568 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
569 uint32_t au32CpuIdSaved[8];
570 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
571 if (VBOX_SUCCESS(rc))
572 {
573 /* Ignore APIC ID (AMD specs). */
574 au32CpuId[5] &= ~0xff000000;
575 au32CpuIdSaved[5] &= ~0xff000000;
576 /* Ignore the number of Logical CPUs (AMD specs). */
577 au32CpuId[5] &= ~0x00ff0000;
578 au32CpuIdSaved[5] &= ~0x00ff0000;
579
580 /* do the compare */
581 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
582 {
583 Log(("cpumR3Load: CpuId mismatch!\n"
584 "Saved=%.*Vhxs\n"
585 "Real =%.*Vhxs\n",
586 sizeof(au32CpuIdSaved), au32CpuIdSaved,
587 sizeof(au32CpuId), au32CpuId));
588 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
589 }
590 }
591
592 return rc;
593}
594
595
596/**
597 * Formats the EFLAGS value into mnemonics.
598 *
599 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
600 * @param efl The EFLAGS value.
601 */
602static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
603{
604 /*
605 * Format the flags.
606 */
607 static struct
608 {
609 const char *pszSet; const char *pszClear; uint32_t fFlag;
610 } s_aFlags[] =
611 {
612 { "vip",NULL, X86_EFL_VIP },
613 { "vif",NULL, X86_EFL_VIF },
614 { "ac", NULL, X86_EFL_AC },
615 { "vm", NULL, X86_EFL_VM },
616 { "rf", NULL, X86_EFL_RF },
617 { "nt", NULL, X86_EFL_NT },
618 { "ov", "nv", X86_EFL_OF },
619 { "dn", "up", X86_EFL_DF },
620 { "ei", "di", X86_EFL_IF },
621 { "tf", NULL, X86_EFL_TF },
622 { "nt", "pl", X86_EFL_SF },
623 { "nz", "zr", X86_EFL_ZF },
624 { "ac", "na", X86_EFL_AF },
625 { "po", "pe", X86_EFL_PF },
626 { "cy", "nc", X86_EFL_CF },
627 };
628 char *psz = pszEFlags;
629 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
630 {
631 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
632 if (pszAdd)
633 {
634 strcpy(psz, pszAdd);
635 psz += strlen(pszAdd);
636 *psz++ = ' ';
637 }
638 }
639 psz[-1] = '\0';
640}
641
642
643/**
644 * Formats a full register dump.
645 *
646 * @param pCtx The context to format.
647 * @param pCtxCore The context core to format.
648 * @param pHlp Output functions.
649 * @param enmType The dump type.
650 * @param pszPrefix Register name prefix.
651 */
652static void cpumR3InfoOne(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
653{
654 /*
655 * Format the EFLAGS.
656 */
657 uint32_t efl = pCtxCore->eflags.u32;
658 char szEFlags[80];
659 cpumR3InfoFormatFlags(&szEFlags[0], efl);
660
661 /*
662 * Format the registers.
663 */
664 switch (enmType)
665 {
666 case CPUMDUMPTYPE_TERSE:
667 pHlp->pfnPrintf(pHlp,
668 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
669 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
670 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
671 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
672 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
673 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
674 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
675 break;
676
677 case CPUMDUMPTYPE_DEFAULT:
678 pHlp->pfnPrintf(pHlp,
679 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
680 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
681 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n"
682 "%scr0=%08x %scr2=%08x %scr3=%08x %scr4=%08x %sgdtr=%08x:%04x %sldtr=%04x\n"
683 ,
684 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
685 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
686 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
687 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl,
688 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
689 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
690 break;
691
692 case CPUMDUMPTYPE_VERBOSE:
693 pHlp->pfnPrintf(pHlp,
694 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
695 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
696 "%scs={%04x base=%08x limit=%08x flags=%08x} %sdr0=%08x %sdr1=%08x\n"
697 "%sds={%04x base=%08x limit=%08x flags=%08x} %sdr2=%08x %sdr3=%08x\n"
698 "%ses={%04x base=%08x limit=%08x flags=%08x} %sdr4=%08x %sdr5=%08x\n"
699 "%sfs={%04x base=%08x limit=%08x flags=%08x} %sdr6=%08x %sdr7=%08x\n"
700 "%sgs={%04x base=%08x limit=%08x flags=%08x} %scr0=%08x %scr2=%08x\n"
701 "%sss={%04x base=%08x limit=%08x flags=%08x} %scr3=%08x %scr4=%08x\n"
702 "%sgdtr=%08x:%04x %sidtr=%08x:%04x %seflags=%08x\n"
703 "%sldtr={%04x base=%08x limit=%08x flags=%08x}\n"
704 "%str ={%04x base=%08x limit=%08x flags=%08x}\n"
705 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
706 "%sFCW=%04x %sFSW=%04x %sFTW=%04x\n"
707 ,
708 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
709 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
710 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
711 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
712 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
713 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
714 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
715 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
716 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
717 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u32Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
718 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u32Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
719 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
720 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW);
721 break;
722 }
723}
724
725
726/**
727 * Display all cpu states and any other cpum info.
728 *
729 * @param pVM VM Handle.
730 * @param pHlp The info helper functions.
731 * @param pszArgs Arguments, ignored.
732 */
733static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
734{
735 cpumR3InfoGuest(pVM, pHlp, pszArgs);
736 cpumR3InfoHyper(pVM, pHlp, pszArgs);
737 cpumR3InfoHost(pVM, pHlp, pszArgs);
738}
739
740
741/**
742 * Parses the info argument.
743 *
744 * The argument starts with 'verbose', 'terse' or 'default' and then
745 * continues with the comment string.
746 *
747 * @param pszArgs The pointer to the argument string.
748 * @param penmType Where to store the dump type request.
749 * @param ppszComment Where to store the pointer to the comment string.
750 */
751static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
752{
753 if (!pszArgs)
754 {
755 *penmType = CPUMDUMPTYPE_DEFAULT;
756 *ppszComment = "";
757 }
758 else
759 {
760 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
761 {
762 pszArgs += 5;
763 *penmType = CPUMDUMPTYPE_VERBOSE;
764 }
765 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
766 {
767 pszArgs += 5;
768 *penmType = CPUMDUMPTYPE_TERSE;
769 }
770 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
771 {
772 pszArgs += 7;
773 *penmType = CPUMDUMPTYPE_DEFAULT;
774 }
775 else
776 *penmType = CPUMDUMPTYPE_DEFAULT;
777 *ppszComment = RTStrStripL(pszArgs);
778 }
779}
780
781
782/**
783 * Display the guest cpu state.
784 *
785 * @param pVM VM Handle.
786 * @param pHlp The info helper functions.
787 * @param pszArgs Arguments, ignored.
788 */
789static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
790{
791 CPUMDUMPTYPE enmType;
792 const char *pszComment;
793 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
794 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
795 cpumR3InfoOne(&pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
796}
797
798
799/**
800 * Display the hypervisor cpu state.
801 *
802 * @param pVM VM Handle.
803 * @param pHlp The info helper functions.
804 * @param pszArgs Arguments, ignored.
805 */
806static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
807{
808 CPUMDUMPTYPE enmType;
809 const char *pszComment;
810 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
811 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
812 cpumR3InfoOne(&pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreHC, pHlp, enmType, ".");
813 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
814}
815
816
817/**
818 * Display the host cpu state.
819 *
820 * @param pVM VM Handle.
821 * @param pHlp The info helper functions.
822 * @param pszArgs Arguments, ignored.
823 */
824static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
825{
826 CPUMDUMPTYPE enmType;
827 const char *pszComment;
828 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
829 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
830
831 /*
832 * Format the EFLAGS.
833 */
834 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
835#if HC_ARCH_BITS == 32
836 uint32_t efl = pCtx->eflags.u32;
837#else
838 uint64_t efl = pCtx->rflags;
839#endif
840 char szEFlags[80];
841 cpumR3InfoFormatFlags(&szEFlags[0], efl);
842
843 /*
844 * Format the registers.
845 */
846#if HC_ARCH_BITS == 32
847 pHlp->pfnPrintf(pHlp,
848 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
849 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
850 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
851 "cr0=%08x cr2=xxxxxxxx cr3=%08x cr4=%08x gdtr=%08x:%04x ldtr=%04x\n"
852 "dr0=%08x dr1=%08x dr2=%08x dr3=%08x dr6=%08x dr7=%08x\n"
853 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
854 ,
855 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
856 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
857 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
858 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
859 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
860 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, (RTSEL)pCtx->ldtr,
861 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
862#else /* 64-bit */
863 pHlp->pfnPrintf(pHlp,
864 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
865 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
866 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
867 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
868 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
869 "r14=%016RX64 r15=%016RX64\n"
870 "iopl=%d %31s\n"
871 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
872 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
873 "cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
874 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
875 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
876 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
877 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
878 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
879 ,
880 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
881 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
882 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
883 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
884 pCtx->r11, pCtx->r12, pCtx->r13,
885 pCtx->r14, pCtx->r15,
886 X86_EFL_GET_IOPL(efl), szEFlags,
887 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
888 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
889 pCtx->cr4, pCtx->cr8, pCtx->ldtr, pCtx->tr,
890 pCtx->dr0, pCtx->dr1, pCtx->dr2,
891 pCtx->dr3, pCtx->dr6, pCtx->dr7,
892 *(uint64_t *)&pCtx->gdtr[2], *(uint16_t *)&pCtx->gdtr[0], *(uint64_t *)&pCtx->idtr[2], *(uint16_t *)&pCtx->idtr[0],
893 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
894 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
895#endif
896}
897
898/**
899 * Get L1 cache / TLS associativity.
900 */
901static const char *getCacheAss(unsigned u, char *pszBuf)
902{
903 if (u == 0)
904 return "res0 ";
905 if (u == 1)
906 return "direct";
907 if (u >= 256)
908 return "???";
909
910 RTStrPrintf(pszBuf, 16, "%d way", u);
911 return pszBuf;
912}
913
914
915/**
916 * Get L2 cache soociativity.
917 */
918const char *getL2CacheAss(unsigned u)
919{
920 switch (u)
921 {
922 case 0: return "off ";
923 case 1: return "direct";
924 case 2: return "2 way ";
925 case 3: return "res3 ";
926 case 4: return "4 way ";
927 case 5: return "res5 ";
928 case 6: return "8 way ";
929 case 7: return "res7 ";
930 case 8: return "16 way";
931 case 9: return "res9 ";
932 case 10: return "res10 ";
933 case 11: return "res11 ";
934 case 12: return "res12 ";
935 case 13: return "res13 ";
936 case 14: return "res14 ";
937 case 15: return "fully ";
938 default:
939 return "????";
940 }
941}
942
943
944/**
945 * Display the guest CpuId leafs.
946 *
947 * @param pVM VM Handle.
948 * @param pHlp The info helper functions.
949 * @param pszArgs "terse", "default" or "verbose".
950 */
951static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
952{
953 /*
954 * Parse the argument.
955 */
956 unsigned iVerbosity = 1;
957 if (pszArgs)
958 {
959 pszArgs = RTStrStripL(pszArgs);
960 if (!strcmp(pszArgs, "terse"))
961 iVerbosity--;
962 else if (!strcmp(pszArgs, "verbose"))
963 iVerbosity++;
964 }
965
966 /*
967 * Start cracking.
968 */
969 CPUMCPUID Host;
970 CPUMCPUID Guest;
971 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
972
973 pHlp->pfnPrintf(pHlp,
974 " RAW Standard CPUIDs\n"
975 " Function eax ebx ecx edx\n");
976 for (unsigned i = 0; i <= ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
977 {
978 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
979 ASMCpuId(i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
980
981 pHlp->pfnPrintf(pHlp,
982 "Gst: %08x %08x %08x %08x %08x%s\n"
983 "Hst: %08x %08x %08x %08x\n",
984 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
985 i <= cStdMax ? "" : "*",
986 Host.eax, Host.ebx, Host.ecx, Host.edx);
987 }
988
989 /*
990 * If verbose, decode it.
991 */
992 if (iVerbosity)
993 {
994 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
995 pHlp->pfnPrintf(pHlp,
996 "Name: %.04s%.04s%.04s\n"
997 "Supports: 0-%x\n",
998 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
999 }
1000
1001 /*
1002 * Get Features.
1003 */
1004 if (cStdMax >= 1 && iVerbosity)
1005 {
1006 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1007 uint32_t uEAX = Guest.eax;
1008
1009 pHlp->pfnPrintf(pHlp,
1010 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1011 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1012 "Stepping: %d\n"
1013 "APIC ID: %#04x\n"
1014 "Logical CPUs: %d\n"
1015 "CLFLUSH Size: %d\n"
1016 "Brand ID: %#04x\n",
1017 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1018 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1019 (uEAX >> 0) & 0xf,
1020 (Guest.ebx >> 24) & 0xff,
1021 (Guest.ebx >> 16) & 0xff,
1022 (Guest.ebx >> 8) & 0xff,
1023 (Guest.ebx >> 0) & 0xff);
1024 if (iVerbosity == 1)
1025 {
1026 uint32_t uEDX = Guest.edx;
1027 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1028 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1029 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1030 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1031 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1032 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1033 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1034 if (uEDX & BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1035 if (uEDX & BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1036 if (uEDX & BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1037 if (uEDX & BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1038 if (uEDX & BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1039 if (uEDX & BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1040 if (uEDX & BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1041 if (uEDX & BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1042 if (uEDX & BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1043 if (uEDX & BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1044 if (uEDX & BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1045 if (uEDX & BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1046 if (uEDX & BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1047 if (uEDX & BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1048 if (uEDX & BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1049 if (uEDX & BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1050 if (uEDX & BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1051 if (uEDX & BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1052 if (uEDX & BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1053 if (uEDX & BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1054 if (uEDX & BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1055 if (uEDX & BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1056 if (uEDX & BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1057 if (uEDX & BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1058 if (uEDX & BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1059 if (uEDX & BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1060 pHlp->pfnPrintf(pHlp, "\n");
1061
1062 uint32_t uECX = Guest.ecx;
1063 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1064 if (uECX & BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1065 if (uECX & BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1066 if (uECX & BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1067 if (uECX & BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1068 if (uECX & BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1069 if (uECX & BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1070 if (uECX & BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1071 if (uECX & BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1072 if (uECX & BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1073 if (uECX & BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1074 if (uECX & BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1075 if (uECX & BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1076 if (uECX & BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1077 if (uECX & BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1078 for (unsigned iBit = 14; iBit < 32; iBit++)
1079 if (uECX & BIT(iBit))
1080 pHlp->pfnPrintf(pHlp, " %d", iBit);
1081 pHlp->pfnPrintf(pHlp, "\n");
1082 }
1083 else
1084 {
1085 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1086
1087 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1088 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1089 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1090 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1091
1092 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1093 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1094 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1095 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1096 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1097 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1098 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1099 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1100 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1101 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1102 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1103 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1104 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1105 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1106 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1107 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1108 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1109 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1110 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1111 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1112 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1113 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1114 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1115 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1116 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1117 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1118 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1119 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1120 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1121 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1122 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1123 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1124 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1125
1126 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1127 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1128 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1129 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1130 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1131 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1132 pHlp->pfnPrintf(pHlp, "Enh. SpeedStep Tech = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1133 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1134 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved3, EcxHost.u1Reserved3);
1135 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1136 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1137 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1138 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u18Reserved5, EcxHost.u18Reserved5);
1139 }
1140 }
1141 if (cStdMax >= 2 && iVerbosity)
1142 {
1143 /** @todo */
1144 }
1145
1146 /*
1147 * Extended.
1148 * Implemented after AMD specs.
1149 */
1150 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1151
1152 pHlp->pfnPrintf(pHlp,
1153 "\n"
1154 " RAW Extended CPUIDs\n"
1155 " Function eax ebx ecx edx\n");
1156 for (unsigned i = 0; i <= ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1157 {
1158 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1159 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1160
1161 pHlp->pfnPrintf(pHlp,
1162 "Gst: %08x %08x %08x %08x %08x%s\n"
1163 "Hst: %08x %08x %08x %08x\n",
1164 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1165 i <= cExtMax ? "" : "*",
1166 Host.eax, Host.ebx, Host.ecx, Host.edx);
1167 }
1168
1169 /*
1170 * Understandable output
1171 */
1172 if (iVerbosity && cExtMax >= 0)
1173 {
1174 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1175 pHlp->pfnPrintf(pHlp,
1176 "Ext Name: %.4s%.4s%.4s\n"
1177 "Ext Supports: 0x80000000-%#010x\n",
1178 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1179 }
1180
1181 if (iVerbosity && cExtMax >= 1)
1182 {
1183 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1184 uint32_t uEAX = Guest.eax;
1185 pHlp->pfnPrintf(pHlp,
1186 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1187 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1188 "Stepping: %d\n"
1189 "Brand ID: %#05x\n",
1190 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1191 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1192 (uEAX >> 0) & 0xf,
1193 Guest.ebx & 0xfff);
1194
1195 if (iVerbosity == 1)
1196 {
1197 uint32_t uEDX = Guest.edx;
1198 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1199 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1200 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1201 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1202 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1203 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1204 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1205 if (uEDX & BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1206 if (uEDX & BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1207 if (uEDX & BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1208 if (uEDX & BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1209 if (uEDX & BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1210 if (uEDX & BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1211 if (uEDX & BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1212 if (uEDX & BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1213 if (uEDX & BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1214 if (uEDX & BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1215 if (uEDX & BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1216 if (uEDX & BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1217 if (uEDX & BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1218 if (uEDX & BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1219 if (uEDX & BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1220 if (uEDX & BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1221 if (uEDX & BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1222 if (uEDX & BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1223 if (uEDX & BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1224 if (uEDX & BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1225 if (uEDX & BIT(26)) pHlp->pfnPrintf(pHlp, " 26");
1226 if (uEDX & BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1227 if (uEDX & BIT(28)) pHlp->pfnPrintf(pHlp, " 29");
1228 if (uEDX & BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1229 if (uEDX & BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1230 if (uEDX & BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1231 pHlp->pfnPrintf(pHlp, "\n");
1232
1233 uint32_t uECX = Guest.ecx;
1234 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1235 if (uECX & BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1236 if (uECX & BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1237 if (uECX & BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1238 if (uECX & BIT(3)) pHlp->pfnPrintf(pHlp, " SVM");
1239 if (uECX & BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1240 for (unsigned iBit = 5; iBit < 32; iBit++)
1241 if (uECX & BIT(iBit))
1242 pHlp->pfnPrintf(pHlp, " %d", iBit);
1243 pHlp->pfnPrintf(pHlp, "\n");
1244 }
1245 else
1246 {
1247 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1248
1249 uint32_t uEdxGst = Guest.edx;
1250 uint32_t uEdxHst = Host.edx;
1251 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1252 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & BIT( 0)), !!(uEdxHst & BIT( 0)));
1253 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & BIT( 1)), !!(uEdxHst & BIT( 1)));
1254 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & BIT( 2)), !!(uEdxHst & BIT( 2)));
1255 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & BIT( 3)), !!(uEdxHst & BIT( 3)));
1256 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & BIT( 4)), !!(uEdxHst & BIT( 4)));
1257 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & BIT( 5)), !!(uEdxHst & BIT( 5)));
1258 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & BIT( 6)), !!(uEdxHst & BIT( 6)));
1259 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & BIT( 7)), !!(uEdxHst & BIT( 7)));
1260 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & BIT( 8)), !!(uEdxHst & BIT( 8)));
1261 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & BIT( 9)), !!(uEdxHst & BIT( 9)));
1262 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(10)), !!(uEdxHst & BIT(10)));
1263 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & BIT(11)), !!(uEdxHst & BIT(11)));
1264 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & BIT(12)), !!(uEdxHst & BIT(12)));
1265 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & BIT(13)), !!(uEdxHst & BIT(13)));
1266 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & BIT(14)), !!(uEdxHst & BIT(14)));
1267 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & BIT(15)), !!(uEdxHst & BIT(15)));
1268 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & BIT(16)), !!(uEdxHst & BIT(16)));
1269 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & BIT(17)), !!(uEdxHst & BIT(17)));
1270 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(18)), !!(uEdxHst & BIT(18)));
1271 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(19)), !!(uEdxHst & BIT(19)));
1272 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & BIT(20)), !!(uEdxHst & BIT(20)));
1273 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & BIT(21)), !!(uEdxHst & BIT(21)));
1274 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & BIT(22)), !!(uEdxHst & BIT(22)));
1275 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & BIT(23)), !!(uEdxHst & BIT(23)));
1276 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & BIT(24)), !!(uEdxHst & BIT(24)));
1277 pHlp->pfnPrintf(pHlp, "?? - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & BIT(25)), !!(uEdxHst & BIT(25)));
1278 pHlp->pfnPrintf(pHlp, "26 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(26)), !!(uEdxHst & BIT(26)));
1279 pHlp->pfnPrintf(pHlp, "27 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(27)), !!(uEdxHst & BIT(27)));
1280 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(28)), !!(uEdxHst & BIT(28)));
1281 pHlp->pfnPrintf(pHlp, "?? - AMD Long Mode = %d (%d)\n", !!(uEdxGst & BIT(29)), !!(uEdxHst & BIT(29)));
1282 pHlp->pfnPrintf(pHlp, "?? - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & BIT(30)), !!(uEdxHst & BIT(30)));
1283 pHlp->pfnPrintf(pHlp, "?? - AMD 3DNow = %d (%d)\n", !!(uEdxGst & BIT(31)), !!(uEdxHst & BIT(31)));
1284
1285 uint32_t uEcxGst = Guest.ecx;
1286 uint32_t uEcxHst = Host.ecx;
1287 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & BIT( 0)), !!(uEcxHst & BIT( 0)));
1288 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & BIT( 1)), !!(uEcxHst & BIT( 1)));
1289 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & BIT( 2)), !!(uEcxHst & BIT( 2)));
1290 pHlp->pfnPrintf(pHlp, "3 - Reserved = %d (%d)\n", !!(uEcxGst & BIT( 3)), !!(uEcxHst & BIT( 3)));
1291 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & BIT( 4)), !!(uEcxHst & BIT( 4)));
1292 pHlp->pfnPrintf(pHlp, "31:5 - Reserved = %#x (%#x)\n", uEcxGst >> 5, uEcxHst >> 5);
1293 }
1294 }
1295
1296 if (iVerbosity && cExtMax >= 2)
1297 {
1298 char szString[4*4*3+1] = {0};
1299 uint32_t *pu32 = (uint32_t *)szString;
1300 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1301 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1302 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1303 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1304 if (cExtMax >= 3)
1305 {
1306 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1307 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1308 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1309 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1310 }
1311 if (cExtMax >= 4)
1312 {
1313 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1314 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1315 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1316 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1317 }
1318 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1319 }
1320
1321 if (iVerbosity && cExtMax >= 5)
1322 {
1323 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1324 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1325 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1326 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1327 char sz1[32];
1328 char sz2[32];
1329
1330 pHlp->pfnPrintf(pHlp,
1331 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1332 "TLB 2/4M Data: %s %3d entries\n",
1333 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1334 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1335 pHlp->pfnPrintf(pHlp,
1336 "TLB 4K Instr/Uni: %s %3d entries\n"
1337 "TLB 4K Data: %s %3d entries\n",
1338 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1339 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1340 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1341 "L1 Instr Cache Lines Per Tag: %d\n"
1342 "L1 Instr Cache Associativity: %s\n"
1343 "L1 Instr Cache Size: %d KB\n",
1344 (uEDX >> 0) & 0xff,
1345 (uEDX >> 8) & 0xff,
1346 getCacheAss((uEDX >> 16) & 0xff, sz1),
1347 (uEDX >> 24) & 0xff);
1348 pHlp->pfnPrintf(pHlp,
1349 "L1 Data Cache Line Size: %d bytes\n"
1350 "L1 Data Cache Lines Per Tag: %d\n"
1351 "L1 Data Cache Associativity: %s\n"
1352 "L1 Data Cache Size: %d KB\n",
1353 (uECX >> 0) & 0xff,
1354 (uECX >> 8) & 0xff,
1355 getCacheAss((uECX >> 16) & 0xff, sz1),
1356 (uECX >> 24) & 0xff);
1357 }
1358
1359 if (iVerbosity && cExtMax >= 6)
1360 {
1361 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1362 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1363 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1364
1365 pHlp->pfnPrintf(pHlp,
1366 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1367 "L2 TLB 2/4M Data: %s %4d entries\n",
1368 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1369 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1370 pHlp->pfnPrintf(pHlp,
1371 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1372 "L2 TLB 4K Data: %s %4d entries\n",
1373 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1374 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1375 pHlp->pfnPrintf(pHlp,
1376 "L2 Cache Line Size: %d bytes\n"
1377 "L2 Cache Lines Per Tag: %d\n"
1378 "L2 Cache Associativity: %s\n"
1379 "L2 Cache Size: %d KB\n",
1380 (uEDX >> 0) & 0xff,
1381 (uEDX >> 8) & 0xf,
1382 getL2CacheAss((uEDX >> 12) & 0xf),
1383 (uEDX >> 16) & 0xffff);
1384 }
1385
1386 if (iVerbosity && cExtMax >= 7)
1387 {
1388 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1389
1390 pHlp->pfnPrintf(pHlp, "APM Features: ");
1391 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1392 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1393 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1394 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1395 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1396 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1397 for (unsigned iBit = 6; iBit < 32; iBit++)
1398 if (uEDX & BIT(iBit))
1399 pHlp->pfnPrintf(pHlp, " %d", iBit);
1400 pHlp->pfnPrintf(pHlp, "\n");
1401 }
1402
1403 if (iVerbosity && cExtMax >= 8)
1404 {
1405 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1406 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1407
1408 pHlp->pfnPrintf(pHlp,
1409 "Physical Address Width: %d bits\n"
1410 "Virtual Address Width: %d bits\n",
1411 (uEAX >> 0) & 0xff,
1412 (uEAX >> 8) & 0xff);
1413 pHlp->pfnPrintf(pHlp,
1414 "Physical Core Count: %d\n",
1415 (uECX >> 0) & 0xff);
1416 }
1417}
1418
1419
1420/**
1421 * Structure used when disassembling and instructions in DBGF.
1422 * This is used so the reader function can get the stuff it needs.
1423 */
1424typedef struct CPUMDISASSTATE
1425{
1426 /** Pointer to the CPU structure. */
1427 PDISCPUSTATE pCpu;
1428 /** The VM handle. */
1429 PVM pVM;
1430 /** Pointer to the first byte in the segemnt. */
1431 RTGCUINTPTR GCPtrSegBase;
1432 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1433 RTGCUINTPTR GCPtrSegEnd;
1434 /** The size of the segment minus 1. */
1435 RTGCUINTPTR cbSegLimit;
1436 /** Pointer to the current page - HC Ptr. */
1437 void *pvPageHC;
1438 /** Pointer to the current page - GC Ptr. */
1439 RTGCPTR pvPageGC;
1440 /** The rc of the operation.
1441 *
1442 * @todo r=bird: it's rather annoying that we have to keep track of the status code of the operation.
1443 * When we've got time we should adjust the disassembler to use VBox status codes and not
1444 * boolean returns.
1445 */
1446 int rc;
1447} CPUMDISASSTATE, *PCPUMDISASSTATE;
1448
1449
1450/**
1451 * Instruction reader.
1452 *
1453 * @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
1454 * @param PtrSrc Address to read from.
1455 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1456 * @param pu8Dst Where to store the bytes.
1457 * @param cbRead Number of bytes to read.
1458 * @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
1459 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1460 * @todo r=bird: The status code should be an int. The PtrSrc should *NOT* be a RTHCUINTPTR. The uDisCpu could just as well be
1461 * declared as what it actually is a PDISCPUSTATE.
1462 */
1463static DECLCALLBACK(int32_t) cpumR3DisasInstrRead(RTHCUINTPTR PtrSrc, uint8_t *pu8Dst, uint32_t cbRead, RTHCUINTPTR uDisCpu)
1464{
1465 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1466 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->dwUserData[0]; /** @todo r=bird: Invalid prefix, dw='double word' which it isn't. Besides it's an array too. And btw. RTHCUINTPTR isn't the right thing either in a 32-bit host 64-bit guest situation */
1467 Assert(cbRead > 0);
1468 for (;;)
1469 {
1470 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1471
1472 /* Need to update the page translation? */
1473 if ( !pState->pvPageHC
1474 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1475 {
1476 /* translate the address */
1477 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1478 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1479 {
1480 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1481 if (!pState->pvPageHC)
1482 pState->rc = VERR_INVALID_POINTER;
1483 }
1484 else
1485 pState->rc = PGMPhysGCPtr2HCPtr(pState->pVM, pState->pvPageGC, &pState->pvPageHC);
1486 if (VBOX_FAILURE(pState->rc))
1487 {
1488 pState->pvPageHC = NULL;
1489 return pState->rc;
1490 }
1491 }
1492
1493 /* check the segemnt limit */
1494 if (PtrSrc > pState->cbSegLimit)
1495 return pState->rc = VERR_OUT_OF_SELECTOR_BOUNDS;
1496
1497 /* calc how much we can read */
1498 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1499 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1500 if (cb > cbSeg && !cbSeg)
1501 cb = cbSeg;
1502 if (cb > cbRead)
1503 cb = cbRead;
1504
1505 /* read and advance */
1506 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1507 cbRead -= cb;
1508 if (!cbRead)
1509 return VINF_SUCCESS;
1510 pu8Dst += cb;
1511 PtrSrc += cb;
1512 }
1513}
1514
1515
1516/**
1517 * Disassemble an instruction and return the information in the provided structure.
1518 *
1519 * @returns VBox status code.
1520 * @param pVM VM Handle
1521 * @param pCtx CPU context
1522 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1523 * @param pCpu Disassembly state
1524 * @param pszPrefix String prefix for logging (debug only)
1525 *
1526 */
1527CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1528{
1529 CPUMDISASSTATE State;
1530 int rc;
1531
1532 State.pCpu = pCpu;
1533 State.pvPageGC = 0;
1534 State.pvPageHC = NULL;
1535 State.rc = VINF_SUCCESS;
1536 State.pVM = pVM;
1537 /*
1538 * Get selector information.
1539 */
1540 if (pCtx->eflags.Bits.u1VM == 0)
1541 {
1542 if (CPUMAreHiddenSelRegsValid(pVM))
1543 {
1544 State.GCPtrSegBase = pCtx->csHid.u32Base;
1545 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u32Base;
1546 State.cbSegLimit = pCtx->csHid.u32Limit;
1547 pCpu->mode = pCtx->csHid.Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1548 }
1549 else
1550 {
1551 SELMSELINFO SelInfo;
1552
1553 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1554 if (!VBOX_SUCCESS(rc))
1555 {
1556 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1557 return rc;
1558 }
1559
1560 /*
1561 * Validate the selector.
1562 */
1563 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1564 if (!VBOX_SUCCESS(rc))
1565 {
1566 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1567 return rc;
1568 }
1569 State.GCPtrSegBase = SelInfo.GCPtrBase;
1570 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1571 State.cbSegLimit = SelInfo.cbLimit;
1572 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1573 }
1574 }
1575 else
1576 {
1577 /* V86 mode */
1578 pCpu->mode = CPUMODE_16BIT; /* @todo */
1579 State.GCPtrSegBase = pCtx->cs * 16;
1580 State.GCPtrSegEnd = 0xFFFFFFFF;
1581 State.cbSegLimit = 0xFFFFFFFF;
1582 }
1583
1584 /*
1585 * Disassemble the instruction.
1586 */
1587 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
1588 pCpu->dwUserData[0] = (uintptr_t)&State;
1589
1590 uint32_t cbInstr;
1591#ifdef LOG_ENABLED
1592 if (DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL))
1593 {
1594#else
1595 char szOutput[160];
1596 if (DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]))
1597 {
1598 /* log it */
1599 if (pszPrefix)
1600 Log(("%s: %s", pszPrefix, szOutput));
1601 else
1602 Log(("%s", szOutput));
1603#endif
1604 return VINF_SUCCESS;
1605 }
1606
1607 /* DISInstr failure */
1608 if (VBOX_FAILURE(State.rc))
1609 {
1610 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, State.rc));
1611 return State.rc;
1612 }
1613 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv\n", pCtx->cs, GCPtrPC));
1614 rc = VERR_GENERAL_FAILURE;
1615 return rc;
1616}
1617
1618
1619#ifdef DEBUG
1620/**
1621 * Disassemble an instruction and dump it to the log
1622 *
1623 * @returns VBox status code.
1624 * @param pVM VM Handle
1625 * @param pCtx CPU context
1626 * @param pc GC instruction pointer
1627 * @param prefix String prefix for logging
1628 * @deprecated Use DBGFR3DisasInstrCurrentLog().
1629 *
1630 */
1631CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
1632{
1633 DISCPUSTATE cpu;
1634
1635 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1636}
1637
1638/**
1639 * Disassemble an instruction and dump it to the log
1640 *
1641 * @returns VBox status code.
1642 * @param pVM VM Handle
1643 * @param pCtx CPU context
1644 * @param pc GC instruction pointer
1645 * @param prefix String prefix for logging
1646 * @param nrInstructions
1647 *
1648 */
1649CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
1650{
1651 for(int i=0;i<nrInstructions;i++)
1652 {
1653 DISCPUSTATE cpu;
1654
1655 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1656 pc += cpu.opsize;
1657 }
1658}
1659
1660#endif
1661
1662#ifdef DEBUG
1663/**
1664 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
1665 *
1666 * @internal
1667 */
1668CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
1669{
1670 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
1671}
1672#endif
1673
1674
1675/**
1676 * API for controlling a few of the CPU features found in CR4.
1677 *
1678 * Currently only X86_CR4_TSD is accepted as input.
1679 *
1680 * @returns VBox status code.
1681 *
1682 * @param pVM The VM handle.
1683 * @param fOr The CR4 OR mask.
1684 * @param fAnd The CR4 AND mask.
1685 */
1686CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
1687{
1688 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
1689 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
1690
1691 pVM->cpum.s.CR4.OrMask &= fAnd;
1692 pVM->cpum.s.CR4.OrMask |= fOr;
1693
1694 return VINF_SUCCESS;
1695}
1696
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