VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 12578

Last change on this file since 12578 was 12578, checked in by vboxsync, 16 years ago

Enable hardware breakpoint support for VT-x and AMD-V.
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1/* $Id: CPUM.cpp 12578 2008-09-18 14:58:57Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * that floats around inside the guest address space. When running in raw-mode
31 * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host
32 * context for saving and restoring registers accross world switches. This latter
33 * is done in cooperation with the world switcher (@see pg_vmm).
34 */
35
36/*******************************************************************************
37* Header Files *
38*******************************************************************************/
39#define LOG_GROUP LOG_GROUP_CPUM
40#include <VBox/cpum.h>
41#include <VBox/cpumdis.h>
42#include <VBox/pgm.h>
43#include <VBox/pdm.h>
44#include <VBox/mm.h>
45#include <VBox/selm.h>
46#include <VBox/dbgf.h>
47#include <VBox/patm.h>
48#include <VBox/ssm.h>
49#include "CPUMInternal.h"
50#include <VBox/vm.h>
51
52#include <VBox/param.h>
53#include <VBox/dis.h>
54#include <VBox/err.h>
55#include <VBox/log.h>
56#include <iprt/assert.h>
57#include <iprt/asm.h>
58#include <iprt/string.h>
59#include <iprt/mp.h>
60#include <iprt/cpuset.h>
61
62
63/*******************************************************************************
64* Defined Constants And Macros *
65*******************************************************************************/
66/** The saved state version. */
67#define CPUM_SAVED_STATE_VERSION_VER1_6 6
68#define CPUM_SAVED_STATE_VERSION 8
69
70
71/*******************************************************************************
72* Structures and Typedefs *
73*******************************************************************************/
74
75/**
76 * What kind of cpu info dump to perform.
77 */
78typedef enum CPUMDUMPTYPE
79{
80 CPUMDUMPTYPE_TERSE,
81 CPUMDUMPTYPE_DEFAULT,
82 CPUMDUMPTYPE_VERBOSE
83
84} CPUMDUMPTYPE;
85/** Pointer to a cpu info dump type. */
86typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
87
88/*******************************************************************************
89* Internal Functions *
90*******************************************************************************/
91static int cpumR3CpuIdInit(PVM pVM);
92static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
93static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
94static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
95static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
96static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
97static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
98static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
99static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
100
101
102/**
103 * Initializes the CPUM.
104 *
105 * @returns VBox status code.
106 * @param pVM The VM to operate on.
107 */
108CPUMR3DECL(int) CPUMR3Init(PVM pVM)
109{
110 LogFlow(("CPUMR3Init\n"));
111
112 /*
113 * Assert alignment and sizes.
114 */
115 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
116 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
117
118 /*
119 * Setup any fixed pointers and offsets.
120 */
121 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
122 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
123 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
124 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
125
126 /* Hidden selector registers are invalid by default. */
127 pVM->cpum.s.fValidHiddenSelRegs = false;
128
129 /*
130 * Check that the CPU supports the minimum features we require.
131 */
132 /** @todo check the contract! */
133 if (!ASMHasCpuId())
134 {
135 Log(("The CPU doesn't support CPUID!\n"));
136 return VERR_UNSUPPORTED_CPU;
137 }
138 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
139 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
140
141 /* Setup the CR4 AND and OR masks used in the switcher */
142 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
143 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
144 {
145 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
146 /* No FXSAVE implies no SSE */
147 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
148 pVM->cpum.s.CR4.OrMask = 0;
149 }
150 else
151 {
152 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
153 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
154 }
155
156 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
157 {
158 Log(("The CPU doesn't support MMX!\n"));
159 return VERR_UNSUPPORTED_CPU;
160 }
161 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
162 {
163 Log(("The CPU doesn't support TSC!\n"));
164 return VERR_UNSUPPORTED_CPU;
165 }
166 /* Bogus on AMD? */
167 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
168 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
169
170 /*
171 * Setup hypervisor startup values.
172 */
173
174 /*
175 * Register saved state data item.
176 */
177 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
178 NULL, cpumR3Save, NULL,
179 NULL, cpumR3Load, NULL);
180 if (VBOX_FAILURE(rc))
181 return rc;
182
183 /* Query the CPU manufacturer. */
184 uint32_t uEAX, uEBX, uECX, uEDX;
185 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
186 if ( uEAX >= 1
187 && uEBX == X86_CPUID_VENDOR_AMD_EBX
188 && uECX == X86_CPUID_VENDOR_AMD_ECX
189 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
190 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
191 else if ( uEAX >= 1
192 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
193 && uECX == X86_CPUID_VENDOR_INTEL_ECX
194 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
195 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
196 else /** @todo Via */
197 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
198
199 /*
200 * Register info handlers.
201 */
202 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
203 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
204 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
205 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
206 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
207 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
208
209 /*
210 * Initialize the Guest CPU state.
211 */
212 rc = cpumR3CpuIdInit(pVM);
213 if (VBOX_FAILURE(rc))
214 return rc;
215 CPUMR3Reset(pVM);
216 return VINF_SUCCESS;
217}
218
219
220/**
221 * Initializes the emulated CPU's cpuid information.
222 *
223 * @returns VBox status code.
224 * @param pVM The VM to operate on.
225 */
226static int cpumR3CpuIdInit(PVM pVM)
227{
228 PCPUM pCPUM = &pVM->cpum.s;
229 uint32_t i;
230
231 /*
232 * Get the host CPUIDs.
233 */
234 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
235 ASMCpuId_Idx_ECX(i, 0,
236 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
237 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
238 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
239 ASMCpuId(0x80000000 + i,
240 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
241 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
242 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
243 ASMCpuId(0xc0000000 + i,
244 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
245 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
246
247
248 /*
249 * Only report features we can support.
250 */
251 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
252 | X86_CPUID_FEATURE_EDX_VME
253 | X86_CPUID_FEATURE_EDX_DE
254 | X86_CPUID_FEATURE_EDX_PSE
255 | X86_CPUID_FEATURE_EDX_TSC
256 | X86_CPUID_FEATURE_EDX_MSR
257 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
258 | X86_CPUID_FEATURE_EDX_MCE
259 | X86_CPUID_FEATURE_EDX_CX8
260 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
261 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
262 //| X86_CPUID_FEATURE_EDX_SEP
263 | X86_CPUID_FEATURE_EDX_MTRR
264 | X86_CPUID_FEATURE_EDX_PGE
265 | X86_CPUID_FEATURE_EDX_MCA
266 | X86_CPUID_FEATURE_EDX_CMOV
267 | X86_CPUID_FEATURE_EDX_PAT
268 | X86_CPUID_FEATURE_EDX_PSE36
269 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
270 | X86_CPUID_FEATURE_EDX_CLFSH
271 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
272 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
273 | X86_CPUID_FEATURE_EDX_MMX
274 | X86_CPUID_FEATURE_EDX_FXSR
275 | X86_CPUID_FEATURE_EDX_SSE
276 | X86_CPUID_FEATURE_EDX_SSE2
277 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
278 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
279 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
280 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
281 | 0;
282 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
283 | X86_CPUID_FEATURE_ECX_MONITOR
284 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
285 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
286 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
287 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
288 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
289 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
290 //| X86_CPUID_FEATURE_ECX_CX16
291 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
292 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
293 /* ECX Bit 23 - POPCOUNT instruction. */
294 //| X86_CPUID_FEATURE_ECX_POPCOUNT
295 | 0;
296
297 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
298 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
299 | X86_CPUID_AMD_FEATURE_EDX_VME
300 | X86_CPUID_AMD_FEATURE_EDX_DE
301 | X86_CPUID_AMD_FEATURE_EDX_PSE
302 | X86_CPUID_AMD_FEATURE_EDX_TSC
303 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
304 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
305 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
306 | X86_CPUID_AMD_FEATURE_EDX_CX8
307 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
308 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
309 //| X86_CPUID_AMD_FEATURE_EDX_SEP
310 | X86_CPUID_AMD_FEATURE_EDX_MTRR
311 | X86_CPUID_AMD_FEATURE_EDX_PGE
312 | X86_CPUID_AMD_FEATURE_EDX_MCA
313 | X86_CPUID_AMD_FEATURE_EDX_CMOV
314 | X86_CPUID_AMD_FEATURE_EDX_PAT
315 | X86_CPUID_AMD_FEATURE_EDX_PSE36
316 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
317 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
318 | X86_CPUID_AMD_FEATURE_EDX_MMX
319 | X86_CPUID_AMD_FEATURE_EDX_FXSR
320 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
321 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
322 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
323 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
324 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
325 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
326 | 0;
327 pCPUM->aGuestCpuIdExt[1].ecx &= 0
328 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
329 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
330 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
331 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
332 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
333 //| X86_CPUID_AMD_FEATURE_ECX_ABM
334 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
335 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
336 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
337 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
338 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
339 //| X86_CPUID_AMD_FEATURE_ECX_WDT
340 | 0;
341
342 /*
343 * Hide HTT, multicode, SMP, whatever.
344 * (APIC-ID := 0 and #LogCpus := 0)
345 */
346 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
347
348 /* Cpuid 2:
349 * Intel: Cache and TLB information
350 * AMD: Reserved
351 * Safe to expose
352 */
353
354 /* Cpuid 3:
355 * Intel: EAX, EBX - reserved
356 * ECX, EDX - Processor Serial Number if available, otherwise reserved
357 * AMD: Reserved
358 * Safe to expose
359 */
360 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
361 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
362
363 /* Cpuid 4:
364 * Intel: Deterministic Cache Parameters Leaf
365 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
366 * AMD: Reserved
367 * Safe to expose, except for EAX:
368 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
369 * Bits 31-26: Maximum number of processor cores in this physical package**
370 */
371 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
372 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
373
374 /* Cpuid 5: Monitor/mwait Leaf
375 * Intel: ECX, EDX - reserved
376 * EAX, EBX - Smallest and largest monitor line size
377 * AMD: EDX - reserved
378 * EAX, EBX - Smallest and largest monitor line size
379 * ECX - extensions (ignored for now)
380 * Safe to expose
381 */
382 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
383 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
384
385 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
386
387 /*
388 * Determine the default.
389 *
390 * Intel returns values of the highest standard function, while AMD
391 * returns zeros. VIA on the other hand seems to returning nothing or
392 * perhaps some random garbage, we don't try to duplicate this behavior.
393 */
394 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
395 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
396 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
397
398 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
399 * Safe to pass on to the guest.
400 *
401 * Intel: 0x800000005 reserved
402 * 0x800000006 L2 cache information
403 * AMD: 0x800000005 L1 cache information
404 * 0x800000006 L2/L3 cache information
405 */
406
407 /* Cpuid 0x800000007:
408 * AMD: EAX, EBX, ECX - reserved
409 * EDX: Advanced Power Management Information
410 * Intel: Reserved
411 */
412 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
413 {
414 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
415
416 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
417
418 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
419 {
420 /* Only expose the TSC invariant capability bit to the guest. */
421 pCPUM->aGuestCpuIdExt[7].edx &= 0
422 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
423 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
424 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
425 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
426 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
427 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
428 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
429 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
430 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
431 | 0;
432 }
433 else
434 pCPUM->aGuestCpuIdExt[7].edx = 0;
435 }
436
437 /* Cpuid 0x800000008:
438 * AMD: EBX, EDX - reserved
439 * EAX: Virtual/Physical address Size
440 * ECX: Number of cores + APICIdCoreIdSize
441 * Intel: EAX: Virtual/Physical address Size
442 * EBX, ECX, EDX - reserved
443 */
444 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
445 {
446 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
447 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
448 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
449 * NC (0-7) Number of cores; 0 equals 1 core */
450 pCPUM->aGuestCpuIdExt[8].ecx = 0;
451 }
452
453 /*
454 * Limit it the number of entries and fill the remaining with the defaults.
455 *
456 * The limits are masking off stuff about power saving and similar, this
457 * is perhaps a bit crudely done as there is probably some relatively harmless
458 * info too in these leaves (like words about having a constant TSC).
459 */
460#if 0
461 /** @todo NT4 installation regression - investigate */
462 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
463 pCPUM->aGuestCpuIdStd[0].eax = 5;
464#else
465 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
466 pCPUM->aGuestCpuIdStd[0].eax = 2;
467#endif
468 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
469 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
470
471 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
472 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
473 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
474 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
475 : 0;
476 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
477 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
478
479 /*
480 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
481 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
482 * We currently don't support more than 1 processor.
483 */
484 pCPUM->aGuestCpuIdStd[4].eax = 0;
485
486 /*
487 * Centaur stuff (VIA).
488 *
489 * The important part here (we think) is to make sure the 0xc0000000
490 * function returns 0xc0000001. As for the features, we don't currently
491 * let on about any of those... 0xc0000002 seems to be some
492 * temperature/hz/++ stuff, include it as well (static).
493 */
494 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
495 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
496 {
497 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
498 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
499 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
500 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
501 i++)
502 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
503 }
504 else
505 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
506 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
507
508
509 /*
510 * Load CPUID overrides from configuration.
511 */
512 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
513 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
514 for (i=0;; )
515 {
516 while (cElements-- > 0)
517 {
518 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
519 if (pNode)
520 {
521 uint32_t u32;
522 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
523 if (VBOX_SUCCESS(rc))
524 pCpuId->eax = u32;
525 else
526 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
527
528 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
529 if (VBOX_SUCCESS(rc))
530 pCpuId->ebx = u32;
531 else
532 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
533
534 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
535 if (VBOX_SUCCESS(rc))
536 pCpuId->ecx = u32;
537 else
538 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
539
540 rc = CFGMR3QueryU32(pNode, "edx", &u32);
541 if (VBOX_SUCCESS(rc))
542 pCpuId->edx = u32;
543 else
544 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
545 }
546 pCpuId++;
547 i++;
548 }
549
550 /* next */
551 if ((i & UINT32_C(0xc0000000)) == 0)
552 {
553 pCpuId = &pCPUM->aGuestCpuIdExt[0];
554 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
555 i = UINT32_C(0x80000000);
556 }
557 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
558 {
559 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
560 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
561 i = UINT32_C(0xc0000000);
562 }
563 else
564 break;
565 }
566
567 /* Check if PAE was explicitely enabled by the user. */
568 bool fEnable = false;
569 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
570 if (VBOX_SUCCESS(rc) && fEnable)
571 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
572
573 /*
574 * Log the cpuid and we're good.
575 */
576 RTCPUSET OnlineSet;
577 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
578 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
579 LogRel(("************************* CPUID dump ************************\n"));
580 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
581 LogRel(("\n"));
582 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
583 LogRel(("******************** End of CPUID dump **********************\n"));
584 return VINF_SUCCESS;
585}
586
587
588
589
590/**
591 * Applies relocations to data and code managed by this
592 * component. This function will be called at init and
593 * whenever the VMM need to relocate it self inside the GC.
594 *
595 * The CPUM will update the addresses used by the switcher.
596 *
597 * @param pVM The VM.
598 */
599CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
600{
601 LogFlow(("CPUMR3Relocate\n"));
602 /*
603 * Switcher pointers.
604 */
605 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
606 pVM->cpum.s.pHyperCoreGC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
607 Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
608}
609
610
611/**
612 * Queries the pointer to the internal CPUMCTX structure
613 *
614 * @returns VBox status code.
615 * @param pVM Handle to the virtual machine.
616 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
617 */
618CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
619{
620 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
621 /*
622 * Store the address. (Later we might check how's calling, thus the RC.)
623 */
624 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
625 return VINF_SUCCESS;
626}
627
628
629/**
630 * Terminates the CPUM.
631 *
632 * Termination means cleaning up and freeing all resources,
633 * the VM it self is at this point powered off or suspended.
634 *
635 * @returns VBox status code.
636 * @param pVM The VM to operate on.
637 */
638CPUMR3DECL(int) CPUMR3Term(PVM pVM)
639{
640 /** @todo ? */
641 return 0;
642}
643
644
645/**
646 * Resets the CPU.
647 *
648 * @returns VINF_SUCCESS.
649 * @param pVM The VM handle.
650 */
651CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
652{
653 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
654
655 /*
656 * Initialize everything to ZERO first.
657 */
658 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
659 memset(pCtx, 0, sizeof(*pCtx));
660 pVM->cpum.s.fUseFlags = fUseFlags;
661
662 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
663 pCtx->eip = 0x0000fff0;
664 pCtx->edx = 0x00000600; /* P6 processor */
665 pCtx->eflags.Bits.u1Reserved0 = 1;
666
667 pCtx->cs = 0xf000;
668 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
669 pCtx->csHid.u32Limit = 0x0000ffff;
670 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
671 pCtx->csHid.Attr.n.u1Present = 1;
672 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
673
674 pCtx->dsHid.u32Limit = 0x0000ffff;
675 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
676 pCtx->dsHid.Attr.n.u1Present = 1;
677 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
678
679 pCtx->esHid.u32Limit = 0x0000ffff;
680 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
681 pCtx->esHid.Attr.n.u1Present = 1;
682 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
683
684 pCtx->fsHid.u32Limit = 0x0000ffff;
685 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
686 pCtx->fsHid.Attr.n.u1Present = 1;
687 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
688
689 pCtx->gsHid.u32Limit = 0x0000ffff;
690 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
691 pCtx->gsHid.Attr.n.u1Present = 1;
692 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
693
694 pCtx->ssHid.u32Limit = 0x0000ffff;
695 pCtx->ssHid.Attr.n.u1Present = 1;
696 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
697 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
698
699 pCtx->idtr.cbIdt = 0xffff;
700 pCtx->gdtr.cbGdt = 0xffff;
701
702 pCtx->ldtrHid.u32Limit = 0xffff;
703 pCtx->ldtrHid.Attr.n.u1Present = 1;
704 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
705
706 pCtx->trHid.u32Limit = 0xffff;
707 pCtx->trHid.Attr.n.u1Present = 1;
708 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
709
710 pCtx->dr6 = X86_DR6_INIT_VAL;
711 pCtx->dr7 = X86_DR7_INIT_VAL;
712
713 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
714 pCtx->fpu.FCW = 0x37f;
715
716 /* Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
717 pCtx->fpu.MXCSR = 0x1F80;
718
719 /* Init PAT MSR */
720 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
721
722 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
723 * The Intel docs don't mention it.
724 */
725 pCtx->msrEFER = 0;
726}
727
728
729/**
730 * Execute state save operation.
731 *
732 * @returns VBox status code.
733 * @param pVM VM Handle.
734 * @param pSSM SSM operation handle.
735 */
736static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
737{
738 /* Set the size of RTGCPTR for use of SSMR3Get/PutGCPtr. */
739 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
740
741 /*
742 * Save.
743 */
744 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
745 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
746 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
747 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
748
749 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
750 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
751
752 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
753 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
754
755 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
756 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
757
758 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
759
760 /* Add the cpuid for checking that the cpu is unchanged. */
761 uint32_t au32CpuId[8] = {0};
762 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
763 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
764 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
765}
766
767/**
768 * Load a version 1.6 CPUMCTX structure.
769 *
770 * @returns VBox status code.
771 * @param pVM VM Handle.
772 * @param pCpumctx16 Version 1.6 CPUMCTX
773 */
774static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
775{
776#define CPUMCTX16_LOADREG(regname) pVM->cpum.s.Guest.regname = pCpumctx16->regname;
777
778#define CPUMCTX16_LOADHIDREG(regname) \
779 pVM->cpum.s.Guest.regname##Hid.u64Base = pCpumctx16->regname##Hid.u32Base; \
780 pVM->cpum.s.Guest.regname##Hid.u32Limit = pCpumctx16->regname##Hid.u32Limit; \
781 pVM->cpum.s.Guest.regname##Hid.Attr = pCpumctx16->regname##Hid.Attr;
782
783#define CPUMCTX16_LOADSEGREG(regname) \
784 pVM->cpum.s.Guest.regname = pCpumctx16->regname; \
785 CPUMCTX16_LOADHIDREG(regname);
786
787 pVM->cpum.s.Guest.fpu = pCpumctx16->fpu;
788
789 CPUMCTX16_LOADREG(rax);
790 CPUMCTX16_LOADREG(rbx);
791 CPUMCTX16_LOADREG(rcx);
792 CPUMCTX16_LOADREG(rdx);
793 CPUMCTX16_LOADREG(rdi);
794 CPUMCTX16_LOADREG(rsi);
795 CPUMCTX16_LOADREG(rbp);
796 CPUMCTX16_LOADREG(esp);
797 CPUMCTX16_LOADREG(rip);
798 CPUMCTX16_LOADREG(rflags);
799
800 CPUMCTX16_LOADSEGREG(cs);
801 CPUMCTX16_LOADSEGREG(ds);
802 CPUMCTX16_LOADSEGREG(es);
803 CPUMCTX16_LOADSEGREG(fs);
804 CPUMCTX16_LOADSEGREG(gs);
805 CPUMCTX16_LOADSEGREG(ss);
806
807 CPUMCTX16_LOADREG(r8);
808 CPUMCTX16_LOADREG(r9);
809 CPUMCTX16_LOADREG(r10);
810 CPUMCTX16_LOADREG(r11);
811 CPUMCTX16_LOADREG(r12);
812 CPUMCTX16_LOADREG(r13);
813 CPUMCTX16_LOADREG(r14);
814 CPUMCTX16_LOADREG(r15);
815
816 CPUMCTX16_LOADREG(cr0);
817 CPUMCTX16_LOADREG(cr2);
818 CPUMCTX16_LOADREG(cr3);
819 CPUMCTX16_LOADREG(cr4);
820
821 CPUMCTX16_LOADREG(dr0);
822 CPUMCTX16_LOADREG(dr1);
823 CPUMCTX16_LOADREG(dr2);
824 CPUMCTX16_LOADREG(dr3);
825 CPUMCTX16_LOADREG(dr4);
826 CPUMCTX16_LOADREG(dr5);
827 CPUMCTX16_LOADREG(dr6);
828 CPUMCTX16_LOADREG(dr7);
829
830 pVM->cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
831 pVM->cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
832 pVM->cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
833 pVM->cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
834
835 CPUMCTX16_LOADREG(ldtr);
836 CPUMCTX16_LOADREG(tr);
837
838 pVM->cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
839
840 CPUMCTX16_LOADREG(msrEFER);
841 CPUMCTX16_LOADREG(msrSTAR);
842 CPUMCTX16_LOADREG(msrPAT);
843 CPUMCTX16_LOADREG(msrLSTAR);
844 CPUMCTX16_LOADREG(msrCSTAR);
845 CPUMCTX16_LOADREG(msrSFMASK);
846 CPUMCTX16_LOADREG(msrKERNELGSBASE);
847
848 CPUMCTX16_LOADHIDREG(ldtr);
849 CPUMCTX16_LOADHIDREG(tr);
850
851#undef CPUMCTX16_LOADHIDREG
852#undef CPUMCTX16_LOADSEGREG
853#undef CPUMCTX16_LOADREG
854}
855
856/**
857 * Execute state load operation.
858 *
859 * @returns VBox status code.
860 * @param pVM VM Handle.
861 * @param pSSM SSM operation handle.
862 * @param u32Version Data layout version.
863 */
864static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
865{
866 /*
867 * Validate version.
868 */
869 if ( u32Version != CPUM_SAVED_STATE_VERSION
870 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
871 {
872 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
873 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
874 }
875
876 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
877 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
878 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
879 else
880 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
881
882 /*
883 * Restore.
884 */
885 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
886 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
887 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
888 pVM->cpum.s.Hyper.cr3 = uCR3;
889 pVM->cpum.s.Hyper.esp = uESP;
890 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
891 {
892 CPUMCTX_VER1_6 cpumctx16;
893 memset(&pVM->cpum.s.Guest, 0, sizeof(pVM->cpum.s.Guest));
894 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
895
896 /* Save the old cpumctx state into the new one. */
897 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
898 }
899 else
900 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
901
902 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
903 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
904
905 uint32_t cElements;
906 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
907 /* Support old saved states with a smaller standard cpuid array. */
908 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
909 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
910 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
911
912 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
913 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
914 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
915 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
916
917 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
918 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
919 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
920 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
921
922 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
923
924 /*
925 * Check that the basic cpuid id information is unchanged.
926 */
927 uint32_t au32CpuId[8] = {0};
928 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
929 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
930 uint32_t au32CpuIdSaved[8];
931 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
932 if (VBOX_SUCCESS(rc))
933 {
934 /* Ignore APIC ID (AMD specs). */
935 au32CpuId[5] &= ~0xff000000;
936 au32CpuIdSaved[5] &= ~0xff000000;
937 /* Ignore the number of Logical CPUs (AMD specs). */
938 au32CpuId[5] &= ~0x00ff0000;
939 au32CpuIdSaved[5] &= ~0x00ff0000;
940
941 /* do the compare */
942 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
943 {
944 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
945 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
946 "Saved=%.*Vhxs\n"
947 "Real =%.*Vhxs\n",
948 sizeof(au32CpuIdSaved), au32CpuIdSaved,
949 sizeof(au32CpuId), au32CpuId));
950 else
951 {
952 LogRel(("cpumR3Load: CpuId mismatch!\n"
953 "Saved=%.*Vhxs\n"
954 "Real =%.*Vhxs\n",
955 sizeof(au32CpuIdSaved), au32CpuIdSaved,
956 sizeof(au32CpuId), au32CpuId));
957 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
958 }
959 }
960 }
961
962 return rc;
963}
964
965
966/**
967 * Formats the EFLAGS value into mnemonics.
968 *
969 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
970 * @param efl The EFLAGS value.
971 */
972static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
973{
974 /*
975 * Format the flags.
976 */
977 static struct
978 {
979 const char *pszSet; const char *pszClear; uint32_t fFlag;
980 } s_aFlags[] =
981 {
982 { "vip",NULL, X86_EFL_VIP },
983 { "vif",NULL, X86_EFL_VIF },
984 { "ac", NULL, X86_EFL_AC },
985 { "vm", NULL, X86_EFL_VM },
986 { "rf", NULL, X86_EFL_RF },
987 { "nt", NULL, X86_EFL_NT },
988 { "ov", "nv", X86_EFL_OF },
989 { "dn", "up", X86_EFL_DF },
990 { "ei", "di", X86_EFL_IF },
991 { "tf", NULL, X86_EFL_TF },
992 { "nt", "pl", X86_EFL_SF },
993 { "nz", "zr", X86_EFL_ZF },
994 { "ac", "na", X86_EFL_AF },
995 { "po", "pe", X86_EFL_PF },
996 { "cy", "nc", X86_EFL_CF },
997 };
998 char *psz = pszEFlags;
999 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1000 {
1001 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1002 if (pszAdd)
1003 {
1004 strcpy(psz, pszAdd);
1005 psz += strlen(pszAdd);
1006 *psz++ = ' ';
1007 }
1008 }
1009 psz[-1] = '\0';
1010}
1011
1012
1013/**
1014 * Formats a full register dump.
1015 *
1016 * @param pVM VM Handle.
1017 * @param pCtx The context to format.
1018 * @param pCtxCore The context core to format.
1019 * @param pHlp Output functions.
1020 * @param enmType The dump type.
1021 * @param pszPrefix Register name prefix.
1022 */
1023static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1024{
1025 /*
1026 * Format the EFLAGS.
1027 */
1028 uint32_t efl = pCtxCore->eflags.u32;
1029 char szEFlags[80];
1030 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1031
1032 /*
1033 * Format the registers.
1034 */
1035 switch (enmType)
1036 {
1037 case CPUMDUMPTYPE_TERSE:
1038 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1039 {
1040 pHlp->pfnPrintf(pHlp,
1041 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1042 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1043 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1044 "%sr14=%016RX64 %sr15=%016RX64\n"
1045 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1046 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1047 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1048 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1049 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1050 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1051 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1052 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1053 }
1054 else
1055 pHlp->pfnPrintf(pHlp,
1056 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1057 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1058 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1059 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1060 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1061 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1062 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1063 break;
1064
1065 case CPUMDUMPTYPE_DEFAULT:
1066 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1067 {
1068 pHlp->pfnPrintf(pHlp,
1069 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1070 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1071 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1072 "%sr14=%016RX64 %sr15=%016RX64\n"
1073 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1074 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1075 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
1076 ,
1077 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1078 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1079 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1080 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1081 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1082 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1083 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1084 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1085 }
1086 else
1087 pHlp->pfnPrintf(pHlp,
1088 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1089 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1090 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1091 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
1092 ,
1093 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1094 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1095 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1096 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1097 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1098 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1099 break;
1100
1101 case CPUMDUMPTYPE_VERBOSE:
1102 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1103 {
1104 pHlp->pfnPrintf(pHlp,
1105 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1106 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1107 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1108 "%sr14=%016RX64 %sr15=%016RX64\n"
1109 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1110 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1111 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1112 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1113 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1114 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1115 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1116 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1117 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1118 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1119 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1120 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1121 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1122 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1123 ,
1124 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1125 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1126 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1127 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1128 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1129 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1130 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1131 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1132 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1133 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1134 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1135 pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
1136 pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
1137 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1138 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1139 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1140 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1141 }
1142 else
1143 pHlp->pfnPrintf(pHlp,
1144 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1145 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1146 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1147 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1148 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1149 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1150 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1151 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1152 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1153 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1154 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1155 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1156 ,
1157 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1158 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1159 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
1160 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
1161 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
1162 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
1163 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1164 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1165 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1166 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1167 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1168 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1169
1170 pHlp->pfnPrintf(pHlp,
1171 "FPU:\n"
1172 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1173 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1174 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1175 ,
1176 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1177 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1178 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1179 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1180
1181
1182 pHlp->pfnPrintf(pHlp,
1183 "MSR:\n"
1184 "%sEFER =%016RX64\n"
1185 "%sPAT =%016RX64\n"
1186 "%sSTAR =%016RX64\n"
1187 "%sCSTAR =%016RX64\n"
1188 "%sLSTAR =%016RX64\n"
1189 "%sSFMASK =%016RX64\n"
1190 "%sKERNELGSBASE =%016RX64\n",
1191 pszPrefix, pCtx->msrEFER,
1192 pszPrefix, pCtx->msrPAT,
1193 pszPrefix, pCtx->msrSTAR,
1194 pszPrefix, pCtx->msrCSTAR,
1195 pszPrefix, pCtx->msrLSTAR,
1196 pszPrefix, pCtx->msrSFMASK,
1197 pszPrefix, pCtx->msrKERNELGSBASE);
1198
1199 break;
1200 }
1201}
1202
1203
1204/**
1205 * Display all cpu states and any other cpum info.
1206 *
1207 * @param pVM VM Handle.
1208 * @param pHlp The info helper functions.
1209 * @param pszArgs Arguments, ignored.
1210 */
1211static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1212{
1213 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1214 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1215 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1216 cpumR3InfoHost(pVM, pHlp, pszArgs);
1217}
1218
1219
1220/**
1221 * Parses the info argument.
1222 *
1223 * The argument starts with 'verbose', 'terse' or 'default' and then
1224 * continues with the comment string.
1225 *
1226 * @param pszArgs The pointer to the argument string.
1227 * @param penmType Where to store the dump type request.
1228 * @param ppszComment Where to store the pointer to the comment string.
1229 */
1230static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1231{
1232 if (!pszArgs)
1233 {
1234 *penmType = CPUMDUMPTYPE_DEFAULT;
1235 *ppszComment = "";
1236 }
1237 else
1238 {
1239 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1240 {
1241 pszArgs += 5;
1242 *penmType = CPUMDUMPTYPE_VERBOSE;
1243 }
1244 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1245 {
1246 pszArgs += 5;
1247 *penmType = CPUMDUMPTYPE_TERSE;
1248 }
1249 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1250 {
1251 pszArgs += 7;
1252 *penmType = CPUMDUMPTYPE_DEFAULT;
1253 }
1254 else
1255 *penmType = CPUMDUMPTYPE_DEFAULT;
1256 *ppszComment = RTStrStripL(pszArgs);
1257 }
1258}
1259
1260
1261/**
1262 * Display the guest cpu state.
1263 *
1264 * @param pVM VM Handle.
1265 * @param pHlp The info helper functions.
1266 * @param pszArgs Arguments, ignored.
1267 */
1268static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1269{
1270 CPUMDUMPTYPE enmType;
1271 const char *pszComment;
1272 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1273 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1274 cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
1275}
1276
1277/**
1278 * Display the current guest instruction
1279 *
1280 * @param pVM VM Handle.
1281 * @param pHlp The info helper functions.
1282 * @param pszArgs Arguments, ignored.
1283 */
1284static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1285{
1286 char szInstruction[256];
1287 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1288 if (VBOX_SUCCESS(rc))
1289 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1290}
1291
1292
1293/**
1294 * Display the hypervisor cpu state.
1295 *
1296 * @param pVM VM Handle.
1297 * @param pHlp The info helper functions.
1298 * @param pszArgs Arguments, ignored.
1299 */
1300static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1301{
1302 CPUMDUMPTYPE enmType;
1303 const char *pszComment;
1304 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1305 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1306 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1307 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1308}
1309
1310
1311/**
1312 * Display the host cpu state.
1313 *
1314 * @param pVM VM Handle.
1315 * @param pHlp The info helper functions.
1316 * @param pszArgs Arguments, ignored.
1317 */
1318static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1319{
1320 CPUMDUMPTYPE enmType;
1321 const char *pszComment;
1322 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1323 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1324
1325 /*
1326 * Format the EFLAGS.
1327 */
1328 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
1329#if HC_ARCH_BITS == 32
1330 uint32_t efl = pCtx->eflags.u32;
1331#else
1332 uint64_t efl = pCtx->rflags;
1333#endif
1334 char szEFlags[80];
1335 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1336
1337 /*
1338 * Format the registers.
1339 */
1340#if HC_ARCH_BITS == 32
1341# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1342 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1343# endif
1344 {
1345 pHlp->pfnPrintf(pHlp,
1346 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1347 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1348 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1349 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1350 "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
1351 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1352 ,
1353 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1354 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1355 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1356 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1357 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1358 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1359 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1360 }
1361# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1362 else
1363# endif
1364#endif
1365#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1366 {
1367 pHlp->pfnPrintf(pHlp,
1368 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1369 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1370 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1371 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1372 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1373 "r14=%016RX64 r15=%016RX64\n"
1374 "iopl=%d %31s\n"
1375 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1376 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1377 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1378 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
1379 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1380 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1381 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1382 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1383 ,
1384 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1385 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1386 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1387 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1388 pCtx->r11, pCtx->r12, pCtx->r13,
1389 pCtx->r14, pCtx->r15,
1390 X86_EFL_GET_IOPL(efl), szEFlags,
1391 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1392 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1393 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1394 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1395 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1396 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1397 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1398 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1399 }
1400#endif
1401}
1402
1403
1404/**
1405 * Get L1 cache / TLS associativity.
1406 */
1407static const char *getCacheAss(unsigned u, char *pszBuf)
1408{
1409 if (u == 0)
1410 return "res0 ";
1411 if (u == 1)
1412 return "direct";
1413 if (u >= 256)
1414 return "???";
1415
1416 RTStrPrintf(pszBuf, 16, "%d way", u);
1417 return pszBuf;
1418}
1419
1420
1421/**
1422 * Get L2 cache soociativity.
1423 */
1424const char *getL2CacheAss(unsigned u)
1425{
1426 switch (u)
1427 {
1428 case 0: return "off ";
1429 case 1: return "direct";
1430 case 2: return "2 way ";
1431 case 3: return "res3 ";
1432 case 4: return "4 way ";
1433 case 5: return "res5 ";
1434 case 6: return "8 way "; case 7: return "res7 ";
1435 case 8: return "16 way";
1436 case 9: return "res9 ";
1437 case 10: return "res10 ";
1438 case 11: return "res11 ";
1439 case 12: return "res12 ";
1440 case 13: return "res13 ";
1441 case 14: return "res14 ";
1442 case 15: return "fully ";
1443 default:
1444 return "????";
1445 }
1446}
1447
1448
1449/**
1450 * Display the guest CpuId leaves.
1451 *
1452 * @param pVM VM Handle.
1453 * @param pHlp The info helper functions.
1454 * @param pszArgs "terse", "default" or "verbose".
1455 */
1456static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1457{
1458 /*
1459 * Parse the argument.
1460 */
1461 unsigned iVerbosity = 1;
1462 if (pszArgs)
1463 {
1464 pszArgs = RTStrStripL(pszArgs);
1465 if (!strcmp(pszArgs, "terse"))
1466 iVerbosity--;
1467 else if (!strcmp(pszArgs, "verbose"))
1468 iVerbosity++;
1469 }
1470
1471 /*
1472 * Start cracking.
1473 */
1474 CPUMCPUID Host;
1475 CPUMCPUID Guest;
1476 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1477
1478 pHlp->pfnPrintf(pHlp,
1479 " RAW Standard CPUIDs\n"
1480 " Function eax ebx ecx edx\n");
1481 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1482 {
1483 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1484 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1485
1486 pHlp->pfnPrintf(pHlp,
1487 "Gst: %08x %08x %08x %08x %08x%s\n"
1488 "Hst: %08x %08x %08x %08x\n",
1489 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1490 i <= cStdMax ? "" : "*",
1491 Host.eax, Host.ebx, Host.ecx, Host.edx);
1492 }
1493
1494 /*
1495 * If verbose, decode it.
1496 */
1497 if (iVerbosity)
1498 {
1499 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1500 pHlp->pfnPrintf(pHlp,
1501 "Name: %.04s%.04s%.04s\n"
1502 "Supports: 0-%x\n",
1503 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1504 }
1505
1506 /*
1507 * Get Features.
1508 */
1509 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1510 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1511 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1512 if (cStdMax >= 1 && iVerbosity)
1513 {
1514 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1515 uint32_t uEAX = Guest.eax;
1516
1517 pHlp->pfnPrintf(pHlp,
1518 "Family: %d \tExtended: %d \tEffective: %d\n"
1519 "Model: %d \tExtended: %d \tEffective: %d\n"
1520 "Stepping: %d\n"
1521 "APIC ID: %#04x\n"
1522 "Logical CPUs: %d\n"
1523 "CLFLUSH Size: %d\n"
1524 "Brand ID: %#04x\n",
1525 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1526 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1527 ASMGetCpuStepping(uEAX),
1528 (Guest.ebx >> 24) & 0xff,
1529 (Guest.ebx >> 16) & 0xff,
1530 (Guest.ebx >> 8) & 0xff,
1531 (Guest.ebx >> 0) & 0xff);
1532 if (iVerbosity == 1)
1533 {
1534 uint32_t uEDX = Guest.edx;
1535 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1536 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1537 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1538 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1539 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1540 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1541 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1542 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1543 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1544 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1545 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1546 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1547 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1548 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1549 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1550 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1551 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1552 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1553 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1554 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1555 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1556 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1557 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1558 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1559 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1560 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1561 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1562 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1563 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1564 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1565 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1566 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1567 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1568 pHlp->pfnPrintf(pHlp, "\n");
1569
1570 uint32_t uECX = Guest.ecx;
1571 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1572 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1573 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1574 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1575 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1576 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1577 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1578 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1579 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1580 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1581 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1582 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1583 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1584 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1585 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1586 for (unsigned iBit = 14; iBit < 32; iBit++)
1587 if (uECX & RT_BIT(iBit))
1588 pHlp->pfnPrintf(pHlp, " %d", iBit);
1589 pHlp->pfnPrintf(pHlp, "\n");
1590 }
1591 else
1592 {
1593 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1594
1595 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1596 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1597 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1598 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1599
1600 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1601 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1602 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1603 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1604 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1605 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1606 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1607 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1608 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1609 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1610 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1611 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1612 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1613 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1614 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1615 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1616 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1617 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1618 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1619 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1620 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1621 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1622 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1623 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1624 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1625 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1626 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1627 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1628 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1629 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1630 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1631 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1632 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1633
1634 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1635 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1636 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1637 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1638 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1639 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1640 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1641 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1642 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1643 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1644 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1645 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1646 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1647 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1648 }
1649 }
1650 if (cStdMax >= 2 && iVerbosity)
1651 {
1652 /** @todo */
1653 }
1654
1655 /*
1656 * Extended.
1657 * Implemented after AMD specs.
1658 */
1659 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1660
1661 pHlp->pfnPrintf(pHlp,
1662 "\n"
1663 " RAW Extended CPUIDs\n"
1664 " Function eax ebx ecx edx\n");
1665 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1666 {
1667 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1668 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1669
1670 pHlp->pfnPrintf(pHlp,
1671 "Gst: %08x %08x %08x %08x %08x%s\n"
1672 "Hst: %08x %08x %08x %08x\n",
1673 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1674 i <= cExtMax ? "" : "*",
1675 Host.eax, Host.ebx, Host.ecx, Host.edx);
1676 }
1677
1678 /*
1679 * Understandable output
1680 */
1681 if (iVerbosity && cExtMax >= 0)
1682 {
1683 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1684 pHlp->pfnPrintf(pHlp,
1685 "Ext Name: %.4s%.4s%.4s\n"
1686 "Ext Supports: 0x80000000-%#010x\n",
1687 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1688 }
1689
1690 if (iVerbosity && cExtMax >= 1)
1691 {
1692 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1693 uint32_t uEAX = Guest.eax;
1694 pHlp->pfnPrintf(pHlp,
1695 "Family: %d \tExtended: %d \tEffective: %d\n"
1696 "Model: %d \tExtended: %d \tEffective: %d\n"
1697 "Stepping: %d\n"
1698 "Brand ID: %#05x\n",
1699 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1700 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1701 ASMGetCpuStepping(uEAX),
1702 Guest.ebx & 0xfff);
1703
1704 if (iVerbosity == 1)
1705 {
1706 uint32_t uEDX = Guest.edx;
1707 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1708 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1709 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1710 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1711 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1712 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1713 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1714 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1715 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1716 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1717 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1718 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1719 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1720 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1721 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1722 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1723 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1724 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1725 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1726 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1727 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1728 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1729 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1730 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1731 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1732 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1733 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1734 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1735 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1736 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1737 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1738 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1739 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1740 pHlp->pfnPrintf(pHlp, "\n");
1741
1742 uint32_t uECX = Guest.ecx;
1743 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1744 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1745 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1746 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1747 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1748 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1749 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1750 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1751 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1752 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1753 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1754 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1755 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1756 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1757 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1758 for (unsigned iBit = 5; iBit < 32; iBit++)
1759 if (uECX & RT_BIT(iBit))
1760 pHlp->pfnPrintf(pHlp, " %d", iBit);
1761 pHlp->pfnPrintf(pHlp, "\n");
1762 }
1763 else
1764 {
1765 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1766
1767 uint32_t uEdxGst = Guest.edx;
1768 uint32_t uEdxHst = Host.edx;
1769 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1770 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1771 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1772 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1773 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1774 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1775 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1776 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1777 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1778 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1779 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1780 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1781 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1782 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1783 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1784 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1785 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1786 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1787 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1788 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1789 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1790 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1791 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1792 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1793 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1794 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1795 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1796 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1797 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1798 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1799 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1800 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1801 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1802
1803 uint32_t uEcxGst = Guest.ecx;
1804 uint32_t uEcxHst = Host.ecx;
1805 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1806 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1807 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1808 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1809 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1810 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1811 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1812 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1813 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1814 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1815 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1816 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1817 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1818 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1819 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1820 }
1821 }
1822
1823 if (iVerbosity && cExtMax >= 2)
1824 {
1825 char szString[4*4*3+1] = {0};
1826 uint32_t *pu32 = (uint32_t *)szString;
1827 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1828 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1829 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1830 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1831 if (cExtMax >= 3)
1832 {
1833 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1834 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1835 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1836 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1837 }
1838 if (cExtMax >= 4)
1839 {
1840 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1841 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1842 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1843 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1844 }
1845 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1846 }
1847
1848 if (iVerbosity && cExtMax >= 5)
1849 {
1850 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1851 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1852 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1853 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1854 char sz1[32];
1855 char sz2[32];
1856
1857 pHlp->pfnPrintf(pHlp,
1858 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1859 "TLB 2/4M Data: %s %3d entries\n",
1860 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1861 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1862 pHlp->pfnPrintf(pHlp,
1863 "TLB 4K Instr/Uni: %s %3d entries\n"
1864 "TLB 4K Data: %s %3d entries\n",
1865 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1866 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1867 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1868 "L1 Instr Cache Lines Per Tag: %d\n"
1869 "L1 Instr Cache Associativity: %s\n"
1870 "L1 Instr Cache Size: %d KB\n",
1871 (uEDX >> 0) & 0xff,
1872 (uEDX >> 8) & 0xff,
1873 getCacheAss((uEDX >> 16) & 0xff, sz1),
1874 (uEDX >> 24) & 0xff);
1875 pHlp->pfnPrintf(pHlp,
1876 "L1 Data Cache Line Size: %d bytes\n"
1877 "L1 Data Cache Lines Per Tag: %d\n"
1878 "L1 Data Cache Associativity: %s\n"
1879 "L1 Data Cache Size: %d KB\n",
1880 (uECX >> 0) & 0xff,
1881 (uECX >> 8) & 0xff,
1882 getCacheAss((uECX >> 16) & 0xff, sz1),
1883 (uECX >> 24) & 0xff);
1884 }
1885
1886 if (iVerbosity && cExtMax >= 6)
1887 {
1888 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1889 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1890 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1891
1892 pHlp->pfnPrintf(pHlp,
1893 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1894 "L2 TLB 2/4M Data: %s %4d entries\n",
1895 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1896 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1897 pHlp->pfnPrintf(pHlp,
1898 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1899 "L2 TLB 4K Data: %s %4d entries\n",
1900 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1901 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1902 pHlp->pfnPrintf(pHlp,
1903 "L2 Cache Line Size: %d bytes\n"
1904 "L2 Cache Lines Per Tag: %d\n"
1905 "L2 Cache Associativity: %s\n"
1906 "L2 Cache Size: %d KB\n",
1907 (uEDX >> 0) & 0xff,
1908 (uEDX >> 8) & 0xf,
1909 getL2CacheAss((uEDX >> 12) & 0xf),
1910 (uEDX >> 16) & 0xffff);
1911 }
1912
1913 if (iVerbosity && cExtMax >= 7)
1914 {
1915 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1916
1917 pHlp->pfnPrintf(pHlp, "APM Features: ");
1918 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1919 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1920 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1921 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1922 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1923 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1924 for (unsigned iBit = 6; iBit < 32; iBit++)
1925 if (uEDX & RT_BIT(iBit))
1926 pHlp->pfnPrintf(pHlp, " %d", iBit);
1927 pHlp->pfnPrintf(pHlp, "\n");
1928 }
1929
1930 if (iVerbosity && cExtMax >= 8)
1931 {
1932 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1933 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1934
1935 pHlp->pfnPrintf(pHlp,
1936 "Physical Address Width: %d bits\n"
1937 "Virtual Address Width: %d bits\n",
1938 (uEAX >> 0) & 0xff,
1939 (uEAX >> 8) & 0xff);
1940 pHlp->pfnPrintf(pHlp,
1941 "Physical Core Count: %d\n",
1942 (uECX >> 0) & 0xff);
1943 }
1944
1945
1946 /*
1947 * Centaur.
1948 */
1949 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1950
1951 pHlp->pfnPrintf(pHlp,
1952 "\n"
1953 " RAW Centaur CPUIDs\n"
1954 " Function eax ebx ecx edx\n");
1955 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1956 {
1957 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1958 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1959
1960 pHlp->pfnPrintf(pHlp,
1961 "Gst: %08x %08x %08x %08x %08x%s\n"
1962 "Hst: %08x %08x %08x %08x\n",
1963 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1964 i <= cCentaurMax ? "" : "*",
1965 Host.eax, Host.ebx, Host.ecx, Host.edx);
1966 }
1967
1968 /*
1969 * Understandable output
1970 */
1971 if (iVerbosity && cCentaurMax >= 0)
1972 {
1973 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1974 pHlp->pfnPrintf(pHlp,
1975 "Centaur Supports: 0xc0000000-%#010x\n",
1976 Guest.eax);
1977 }
1978
1979 if (iVerbosity && cCentaurMax >= 1)
1980 {
1981 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1982 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1983 uint32_t uEdxHst = Host.edx;
1984
1985 if (iVerbosity == 1)
1986 {
1987 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1988 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1989 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1990 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1991 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1992 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1993 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1994 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1995 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1996 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1997 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
1998 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
1999 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2000 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2001 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2002 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2003 for (unsigned iBit = 14; iBit < 32; iBit++)
2004 if (uEdxGst & RT_BIT(iBit))
2005 pHlp->pfnPrintf(pHlp, " %d", iBit);
2006 pHlp->pfnPrintf(pHlp, "\n");
2007 }
2008 else
2009 {
2010 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2011 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2012 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2013 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2014 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2015 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2016 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2017 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2018 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2019 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2020 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2021 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2022 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2023 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2024 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2025 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2026 for (unsigned iBit = 14; iBit < 32; iBit++)
2027 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2028 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2029 pHlp->pfnPrintf(pHlp, "\n");
2030 }
2031 }
2032}
2033
2034
2035/**
2036 * Structure used when disassembling and instructions in DBGF.
2037 * This is used so the reader function can get the stuff it needs.
2038 */
2039typedef struct CPUMDISASSTATE
2040{
2041 /** Pointer to the CPU structure. */
2042 PDISCPUSTATE pCpu;
2043 /** The VM handle. */
2044 PVM pVM;
2045 /** Pointer to the first byte in the segemnt. */
2046 RTGCUINTPTR GCPtrSegBase;
2047 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2048 RTGCUINTPTR GCPtrSegEnd;
2049 /** The size of the segment minus 1. */
2050 RTGCUINTPTR cbSegLimit;
2051 /** Pointer to the current page - HC Ptr. */
2052 void const *pvPageHC;
2053 /** Pointer to the current page - GC Ptr. */
2054 RTGCPTR pvPageGC;
2055 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2056 PGMPAGEMAPLOCK PageMapLock;
2057 /** Whether the PageMapLock is valid or not. */
2058 bool fLocked;
2059 /** 64 bits mode or not. */
2060 bool f64Bits;
2061} CPUMDISASSTATE, *PCPUMDISASSTATE;
2062
2063
2064/**
2065 * Instruction reader.
2066 *
2067 * @returns VBox status code.
2068 * @param PtrSrc Address to read from.
2069 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2070 * @param pu8Dst Where to store the bytes.
2071 * @param cbRead Number of bytes to read.
2072 * @param uDisCpu Pointer to the disassembler cpu state.
2073 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2074 */
2075static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2076{
2077 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2078 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2079 Assert(cbRead > 0);
2080 for (;;)
2081 {
2082 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2083
2084 /* Need to update the page translation? */
2085 if ( !pState->pvPageHC
2086 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2087 {
2088 int rc = VINF_SUCCESS;
2089
2090 /* translate the address */
2091 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2092 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2093 {
2094 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
2095 if (!pState->pvPageHC)
2096 rc = VERR_INVALID_POINTER;
2097 }
2098 else
2099 {
2100 /* Release mapping lock previously acquired. */
2101 if (pState->fLocked)
2102 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2103 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
2104 pState->fLocked = RT_SUCCESS_NP(rc);
2105 }
2106 if (VBOX_FAILURE(rc))
2107 {
2108 pState->pvPageHC = NULL;
2109 return rc;
2110 }
2111 }
2112
2113 /* check the segemnt limit */
2114 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2115 return VERR_OUT_OF_SELECTOR_BOUNDS;
2116
2117 /* calc how much we can read */
2118 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2119 if (!pState->f64Bits)
2120 {
2121 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2122 if (cb > cbSeg && cbSeg)
2123 cb = cbSeg;
2124 }
2125 if (cb > cbRead)
2126 cb = cbRead;
2127
2128 /* read and advance */
2129 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
2130 cbRead -= cb;
2131 if (!cbRead)
2132 return VINF_SUCCESS;
2133 pu8Dst += cb;
2134 PtrSrc += cb;
2135 }
2136}
2137
2138
2139/**
2140 * Disassemble an instruction and return the information in the provided structure.
2141 *
2142 * @returns VBox status code.
2143 * @param pVM VM Handle
2144 * @param pCtx CPU context
2145 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2146 * @param pCpu Disassembly state
2147 * @param pszPrefix String prefix for logging (debug only)
2148 *
2149 */
2150CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2151{
2152 CPUMDISASSTATE State;
2153 int rc;
2154
2155 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2156 State.pCpu = pCpu;
2157 State.pvPageGC = 0;
2158 State.pvPageHC = NULL;
2159 State.pVM = pVM;
2160 State.fLocked = false;
2161 State.f64Bits = false;
2162
2163 /*
2164 * Get selector information.
2165 */
2166 if ( (pCtx->cr0 & X86_CR0_PE)
2167 && pCtx->eflags.Bits.u1VM == 0)
2168 {
2169 if (CPUMAreHiddenSelRegsValid(pVM))
2170 {
2171 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2172 State.GCPtrSegBase = pCtx->csHid.u64Base;
2173 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2174 State.cbSegLimit = pCtx->csHid.u32Limit;
2175 pCpu->mode = (State.f64Bits)
2176 ? CPUMODE_64BIT
2177 : pCtx->csHid.Attr.n.u1DefBig
2178 ? CPUMODE_32BIT
2179 : CPUMODE_16BIT;
2180 }
2181 else
2182 {
2183 SELMSELINFO SelInfo;
2184
2185 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2186 if (!VBOX_SUCCESS(rc))
2187 {
2188 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2189 return rc;
2190 }
2191
2192 /*
2193 * Validate the selector.
2194 */
2195 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2196 if (!VBOX_SUCCESS(rc))
2197 {
2198 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2199 return rc;
2200 }
2201 State.GCPtrSegBase = SelInfo.GCPtrBase;
2202 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2203 State.cbSegLimit = SelInfo.cbLimit;
2204 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2205 }
2206 }
2207 else
2208 {
2209 /* real or V86 mode */
2210 pCpu->mode = CPUMODE_16BIT;
2211 State.GCPtrSegBase = pCtx->cs * 16;
2212 State.GCPtrSegEnd = 0xFFFFFFFF;
2213 State.cbSegLimit = 0xFFFFFFFF;
2214 }
2215
2216 /*
2217 * Disassemble the instruction.
2218 */
2219 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2220 pCpu->apvUserData[0] = &State;
2221
2222 uint32_t cbInstr;
2223#ifndef LOG_ENABLED
2224 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2225 if (VBOX_SUCCESS(rc))
2226 {
2227#else
2228 char szOutput[160];
2229 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2230 if (VBOX_SUCCESS(rc))
2231 {
2232 /* log it */
2233 if (pszPrefix)
2234 Log(("%s: %s", pszPrefix, szOutput));
2235 else
2236 Log(("%s", szOutput));
2237#endif
2238 rc = VINF_SUCCESS;
2239 }
2240 else
2241 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
2242
2243 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2244 if (State.fLocked)
2245 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2246
2247 return rc;
2248}
2249
2250#ifdef DEBUG
2251
2252/**
2253 * Disassemble an instruction and dump it to the log
2254 *
2255 * @returns VBox status code.
2256 * @param pVM VM Handle
2257 * @param pCtx CPU context
2258 * @param pc GC instruction pointer
2259 * @param prefix String prefix for logging
2260 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2261 *
2262 */
2263CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
2264{
2265 DISCPUSTATE cpu;
2266
2267 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2268}
2269
2270/**
2271 * Disassemble an instruction and dump it to the log
2272 *
2273 * @returns VBox status code.
2274 * @param pVM VM Handle
2275 * @param pCtx CPU context
2276 * @param pc GC instruction pointer
2277 * @param prefix String prefix for logging
2278 * @param nrInstructions
2279 *
2280 */
2281CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
2282{
2283 for(int i=0;i<nrInstructions;i++)
2284 {
2285 DISCPUSTATE cpu;
2286
2287 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2288 pc += cpu.opsize;
2289 }
2290}
2291
2292#endif /* DEBUG */
2293
2294#ifdef DEBUG
2295/**
2296 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2297 *
2298 * @internal
2299 */
2300CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2301{
2302 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
2303}
2304#endif /* DEBUG */
2305
2306
2307/**
2308 * API for controlling a few of the CPU features found in CR4.
2309 *
2310 * Currently only X86_CR4_TSD is accepted as input.
2311 *
2312 * @returns VBox status code.
2313 *
2314 * @param pVM The VM handle.
2315 * @param fOr The CR4 OR mask.
2316 * @param fAnd The CR4 AND mask.
2317 */
2318CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2319{
2320 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2321 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2322
2323 pVM->cpum.s.CR4.OrMask &= fAnd;
2324 pVM->cpum.s.CR4.OrMask |= fOr;
2325
2326 return VINF_SUCCESS;
2327}
2328
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