VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 13100

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1/* $Id: CPUM.cpp 13005 2008-10-06 12:35:21Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/ssm.h>
51#include "CPUMInternal.h"
52#include <VBox/vm.h>
53
54#include <VBox/param.h>
55#include <VBox/dis.h>
56#include <VBox/err.h>
57#include <VBox/log.h>
58#include <iprt/assert.h>
59#include <iprt/asm.h>
60#include <iprt/string.h>
61#include <iprt/mp.h>
62#include <iprt/cpuset.h>
63
64
65/*******************************************************************************
66* Defined Constants And Macros *
67*******************************************************************************/
68/** The saved state version. */
69#define CPUM_SAVED_STATE_VERSION 8
70/** The saved state version of 1.6, used for backwards compatability. */
71#define CPUM_SAVED_STATE_VERSION_VER1_6 6
72
73
74/*******************************************************************************
75* Structures and Typedefs *
76*******************************************************************************/
77
78/**
79 * What kind of cpu info dump to perform.
80 */
81typedef enum CPUMDUMPTYPE
82{
83 CPUMDUMPTYPE_TERSE,
84 CPUMDUMPTYPE_DEFAULT,
85 CPUMDUMPTYPE_VERBOSE
86
87} CPUMDUMPTYPE;
88/** Pointer to a cpu info dump type. */
89typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
90
91
92/*******************************************************************************
93* Internal Functions *
94*******************************************************************************/
95static int cpumR3CpuIdInit(PVM pVM);
96static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
97static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
98static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
99static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
100static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104
105
106/**
107 * Initializes the CPUM.
108 *
109 * @returns VBox status code.
110 * @param pVM The VM to operate on.
111 */
112VMMR3DECL(int) CPUMR3Init(PVM pVM)
113{
114 LogFlow(("CPUMR3Init\n"));
115
116 /*
117 * Assert alignment and sizes.
118 */
119 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
120 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
121
122 /*
123 * Setup any fixed pointers and offsets.
124 */
125 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
126 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
127
128 /* Hidden selector registers are invalid by default. */
129 pVM->cpum.s.fValidHiddenSelRegs = false;
130
131 /*
132 * Check that the CPU supports the minimum features we require.
133 */
134 if (!ASMHasCpuId())
135 {
136 Log(("The CPU doesn't support CPUID!\n"));
137 return VERR_UNSUPPORTED_CPU;
138 }
139 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
140 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
141
142 /* Setup the CR4 AND and OR masks used in the switcher */
143 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
144 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
145 {
146 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
147 /* No FXSAVE implies no SSE */
148 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
149 pVM->cpum.s.CR4.OrMask = 0;
150 }
151 else
152 {
153 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
154 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
155 }
156
157 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
158 {
159 Log(("The CPU doesn't support MMX!\n"));
160 return VERR_UNSUPPORTED_CPU;
161 }
162 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
163 {
164 Log(("The CPU doesn't support TSC!\n"));
165 return VERR_UNSUPPORTED_CPU;
166 }
167 /* Bogus on AMD? */
168 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
169 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
170
171 /*
172 * Setup hypervisor startup values.
173 */
174
175 /*
176 * Register saved state data item.
177 */
178 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
179 NULL, cpumR3Save, NULL,
180 NULL, cpumR3Load, NULL);
181 if (VBOX_FAILURE(rc))
182 return rc;
183
184 /* Query the CPU manufacturer. */
185 uint32_t uEAX, uEBX, uECX, uEDX;
186 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
187 if ( uEAX >= 1
188 && uEBX == X86_CPUID_VENDOR_AMD_EBX
189 && uECX == X86_CPUID_VENDOR_AMD_ECX
190 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
191 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
192 else if ( uEAX >= 1
193 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
194 && uECX == X86_CPUID_VENDOR_INTEL_ECX
195 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
196 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
197 else /** @todo Via */
198 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
199
200 /*
201 * Register info handlers.
202 */
203 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
204 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
205 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
206 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
207 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
208 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
209
210 /*
211 * Initialize the Guest CPU state.
212 */
213 rc = cpumR3CpuIdInit(pVM);
214 if (VBOX_FAILURE(rc))
215 return rc;
216 CPUMR3Reset(pVM);
217 return VINF_SUCCESS;
218}
219
220
221/**
222 * Initializes the emulated CPU's cpuid information.
223 *
224 * @returns VBox status code.
225 * @param pVM The VM to operate on.
226 */
227static int cpumR3CpuIdInit(PVM pVM)
228{
229 PCPUM pCPUM = &pVM->cpum.s;
230 uint32_t i;
231
232 /*
233 * Get the host CPUIDs.
234 */
235 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
236 ASMCpuId_Idx_ECX(i, 0,
237 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
238 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
239 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
240 ASMCpuId(0x80000000 + i,
241 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
242 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
243 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
244 ASMCpuId(0xc0000000 + i,
245 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
246 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
247
248
249 /*
250 * Only report features we can support.
251 */
252 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
253 | X86_CPUID_FEATURE_EDX_VME
254 | X86_CPUID_FEATURE_EDX_DE
255 | X86_CPUID_FEATURE_EDX_PSE
256 | X86_CPUID_FEATURE_EDX_TSC
257 | X86_CPUID_FEATURE_EDX_MSR
258 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
259 | X86_CPUID_FEATURE_EDX_MCE
260 | X86_CPUID_FEATURE_EDX_CX8
261 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
262 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
263 //| X86_CPUID_FEATURE_EDX_SEP
264 | X86_CPUID_FEATURE_EDX_MTRR
265 | X86_CPUID_FEATURE_EDX_PGE
266 | X86_CPUID_FEATURE_EDX_MCA
267 | X86_CPUID_FEATURE_EDX_CMOV
268 | X86_CPUID_FEATURE_EDX_PAT
269 | X86_CPUID_FEATURE_EDX_PSE36
270 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
271 | X86_CPUID_FEATURE_EDX_CLFSH
272 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
273 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
274 | X86_CPUID_FEATURE_EDX_MMX
275 | X86_CPUID_FEATURE_EDX_FXSR
276 | X86_CPUID_FEATURE_EDX_SSE
277 | X86_CPUID_FEATURE_EDX_SSE2
278 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
279 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
280 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
281 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
282 | 0;
283 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
284 | X86_CPUID_FEATURE_ECX_MONITOR
285 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
286 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
287 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
288 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
289 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
290 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
291 //| X86_CPUID_FEATURE_ECX_CX16
292 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
293 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
294 /* ECX Bit 21 - x2APIC support - not yet. */
295 // | X86_CPUID_FEATURE_ECX_X2APIC
296 /* ECX Bit 23 - POPCOUNT instruction. */
297 //| X86_CPUID_FEATURE_ECX_POPCOUNT
298 | 0;
299
300 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
301 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
302 | X86_CPUID_AMD_FEATURE_EDX_VME
303 | X86_CPUID_AMD_FEATURE_EDX_DE
304 | X86_CPUID_AMD_FEATURE_EDX_PSE
305 | X86_CPUID_AMD_FEATURE_EDX_TSC
306 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
307 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
308 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
309 | X86_CPUID_AMD_FEATURE_EDX_CX8
310 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
311 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
312 //| X86_CPUID_AMD_FEATURE_EDX_SEP
313 | X86_CPUID_AMD_FEATURE_EDX_MTRR
314 | X86_CPUID_AMD_FEATURE_EDX_PGE
315 | X86_CPUID_AMD_FEATURE_EDX_MCA
316 | X86_CPUID_AMD_FEATURE_EDX_CMOV
317 | X86_CPUID_AMD_FEATURE_EDX_PAT
318 | X86_CPUID_AMD_FEATURE_EDX_PSE36
319 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
320 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
321 | X86_CPUID_AMD_FEATURE_EDX_MMX
322 | X86_CPUID_AMD_FEATURE_EDX_FXSR
323 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
324 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
325 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
326 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
327 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
328 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
329 | 0;
330 pCPUM->aGuestCpuIdExt[1].ecx &= 0
331 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
332 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
333 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
334 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
335 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
336 //| X86_CPUID_AMD_FEATURE_ECX_ABM
337 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
338 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
339 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
340 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
341 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
342 //| X86_CPUID_AMD_FEATURE_ECX_WDT
343 | 0;
344
345 /*
346 * Hide HTT, multicode, SMP, whatever.
347 * (APIC-ID := 0 and #LogCpus := 0)
348 */
349 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
350
351 /* Cpuid 2:
352 * Intel: Cache and TLB information
353 * AMD: Reserved
354 * Safe to expose
355 */
356
357 /* Cpuid 3:
358 * Intel: EAX, EBX - reserved
359 * ECX, EDX - Processor Serial Number if available, otherwise reserved
360 * AMD: Reserved
361 * Safe to expose
362 */
363 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
364 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
365
366 /* Cpuid 4:
367 * Intel: Deterministic Cache Parameters Leaf
368 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
369 * AMD: Reserved
370 * Safe to expose, except for EAX:
371 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
372 * Bits 31-26: Maximum number of processor cores in this physical package**
373 */
374 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
375 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
376
377 /* Cpuid 5: Monitor/mwait Leaf
378 * Intel: ECX, EDX - reserved
379 * EAX, EBX - Smallest and largest monitor line size
380 * AMD: EDX - reserved
381 * EAX, EBX - Smallest and largest monitor line size
382 * ECX - extensions (ignored for now)
383 * Safe to expose
384 */
385 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
386 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
387
388 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
389
390 /*
391 * Determine the default.
392 *
393 * Intel returns values of the highest standard function, while AMD
394 * returns zeros. VIA on the other hand seems to returning nothing or
395 * perhaps some random garbage, we don't try to duplicate this behavior.
396 */
397 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
398 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
399 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
400
401 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
402 * Safe to pass on to the guest.
403 *
404 * Intel: 0x800000005 reserved
405 * 0x800000006 L2 cache information
406 * AMD: 0x800000005 L1 cache information
407 * 0x800000006 L2/L3 cache information
408 */
409
410 /* Cpuid 0x800000007:
411 * AMD: EAX, EBX, ECX - reserved
412 * EDX: Advanced Power Management Information
413 * Intel: Reserved
414 */
415 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
416 {
417 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
418
419 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
420
421 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
422 {
423 /* Only expose the TSC invariant capability bit to the guest. */
424 pCPUM->aGuestCpuIdExt[7].edx &= 0
425 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
426 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
427 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
428 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
429 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
430 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
431 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
432 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
433 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
434 | 0;
435 }
436 else
437 pCPUM->aGuestCpuIdExt[7].edx = 0;
438 }
439
440 /* Cpuid 0x800000008:
441 * AMD: EBX, EDX - reserved
442 * EAX: Virtual/Physical address Size
443 * ECX: Number of cores + APICIdCoreIdSize
444 * Intel: EAX: Virtual/Physical address Size
445 * EBX, ECX, EDX - reserved
446 */
447 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
448 {
449 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
450 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
451 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
452 * NC (0-7) Number of cores; 0 equals 1 core */
453 pCPUM->aGuestCpuIdExt[8].ecx = 0;
454 }
455
456 /*
457 * Limit it the number of entries and fill the remaining with the defaults.
458 *
459 * The limits are masking off stuff about power saving and similar, this
460 * is perhaps a bit crudely done as there is probably some relatively harmless
461 * info too in these leaves (like words about having a constant TSC).
462 */
463#if 0
464 /** @todo NT4 installation regression - investigate */
465 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
466 pCPUM->aGuestCpuIdStd[0].eax = 5;
467#else
468 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
469 pCPUM->aGuestCpuIdStd[0].eax = 2;
470#endif
471 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
472 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
473
474 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
475 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
476 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
477 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
478 : 0;
479 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
480 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
481
482 /*
483 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
484 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
485 * We currently don't support more than 1 processor.
486 */
487 pCPUM->aGuestCpuIdStd[4].eax = 0;
488
489 /*
490 * Centaur stuff (VIA).
491 *
492 * The important part here (we think) is to make sure the 0xc0000000
493 * function returns 0xc0000001. As for the features, we don't currently
494 * let on about any of those... 0xc0000002 seems to be some
495 * temperature/hz/++ stuff, include it as well (static).
496 */
497 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
498 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
499 {
500 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
501 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
502 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
503 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
504 i++)
505 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
506 }
507 else
508 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
509 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
510
511
512 /*
513 * Load CPUID overrides from configuration.
514 */
515 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
516 * Overloads the CPUID leaf values. */
517 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
518 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
519 for (i=0;; )
520 {
521 while (cElements-- > 0)
522 {
523 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
524 if (pNode)
525 {
526 uint32_t u32;
527 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
528 if (VBOX_SUCCESS(rc))
529 pCpuId->eax = u32;
530 else
531 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
532
533 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
534 if (VBOX_SUCCESS(rc))
535 pCpuId->ebx = u32;
536 else
537 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
538
539 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
540 if (VBOX_SUCCESS(rc))
541 pCpuId->ecx = u32;
542 else
543 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
544
545 rc = CFGMR3QueryU32(pNode, "edx", &u32);
546 if (VBOX_SUCCESS(rc))
547 pCpuId->edx = u32;
548 else
549 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
550 }
551 pCpuId++;
552 i++;
553 }
554
555 /* next */
556 if ((i & UINT32_C(0xc0000000)) == 0)
557 {
558 pCpuId = &pCPUM->aGuestCpuIdExt[0];
559 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
560 i = UINT32_C(0x80000000);
561 }
562 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
563 {
564 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
565 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
566 i = UINT32_C(0xc0000000);
567 }
568 else
569 break;
570 }
571
572 /* Check if PAE was explicitely enabled by the user. */
573 bool fEnable = false;
574 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
575 if (VBOX_SUCCESS(rc) && fEnable)
576 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
577
578 /*
579 * Log the cpuid and we're good.
580 */
581 RTCPUSET OnlineSet;
582 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
583 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
584 LogRel(("************************* CPUID dump ************************\n"));
585 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
586 LogRel(("\n"));
587 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
588 LogRel(("******************** End of CPUID dump **********************\n"));
589 return VINF_SUCCESS;
590}
591
592
593
594
595/**
596 * Applies relocations to data and code managed by this
597 * component. This function will be called at init and
598 * whenever the VMM need to relocate it self inside the GC.
599 *
600 * The CPUM will update the addresses used by the switcher.
601 *
602 * @param pVM The VM.
603 */
604VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
605{
606 LogFlow(("CPUMR3Relocate\n"));
607 /*
608 * Switcher pointers.
609 */
610 pVM->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
611 Assert(pVM->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
612}
613
614
615/**
616 * Queries the pointer to the internal CPUMCTX structure
617 *
618 * @returns VBox status code.
619 * @param pVM Handle to the virtual machine.
620 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
621 */
622VMMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
623{
624 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
625 /*
626 * Store the address. (Later we might check how's calling, thus the RC.)
627 */
628 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
629 return VINF_SUCCESS;
630}
631
632
633/**
634 * Terminates the CPUM.
635 *
636 * Termination means cleaning up and freeing all resources,
637 * the VM it self is at this point powered off or suspended.
638 *
639 * @returns VBox status code.
640 * @param pVM The VM to operate on.
641 */
642VMMR3DECL(int) CPUMR3Term(PVM pVM)
643{
644 /** @todo ? */
645 return 0;
646}
647
648
649/**
650 * Resets the CPU.
651 *
652 * @returns VINF_SUCCESS.
653 * @param pVM The VM handle.
654 */
655VMMR3DECL(void) CPUMR3Reset(PVM pVM)
656{
657 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
658
659 /*
660 * Initialize everything to ZERO first.
661 */
662 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
663 memset(pCtx, 0, sizeof(*pCtx));
664 pVM->cpum.s.fUseFlags = fUseFlags;
665
666 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
667 pCtx->eip = 0x0000fff0;
668 pCtx->edx = 0x00000600; /* P6 processor */
669 pCtx->eflags.Bits.u1Reserved0 = 1;
670
671 pCtx->cs = 0xf000;
672 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
673 pCtx->csHid.u32Limit = 0x0000ffff;
674 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
675 pCtx->csHid.Attr.n.u1Present = 1;
676 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
677
678 pCtx->dsHid.u32Limit = 0x0000ffff;
679 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
680 pCtx->dsHid.Attr.n.u1Present = 1;
681 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
682
683 pCtx->esHid.u32Limit = 0x0000ffff;
684 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
685 pCtx->esHid.Attr.n.u1Present = 1;
686 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
687
688 pCtx->fsHid.u32Limit = 0x0000ffff;
689 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
690 pCtx->fsHid.Attr.n.u1Present = 1;
691 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
692
693 pCtx->gsHid.u32Limit = 0x0000ffff;
694 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
695 pCtx->gsHid.Attr.n.u1Present = 1;
696 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
697
698 pCtx->ssHid.u32Limit = 0x0000ffff;
699 pCtx->ssHid.Attr.n.u1Present = 1;
700 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
701 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
702
703 pCtx->idtr.cbIdt = 0xffff;
704 pCtx->gdtr.cbGdt = 0xffff;
705
706 pCtx->ldtrHid.u32Limit = 0xffff;
707 pCtx->ldtrHid.Attr.n.u1Present = 1;
708 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
709
710 pCtx->trHid.u32Limit = 0xffff;
711 pCtx->trHid.Attr.n.u1Present = 1;
712 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
713
714 pCtx->dr[6] = X86_DR6_INIT_VAL;
715 pCtx->dr[7] = X86_DR7_INIT_VAL;
716
717 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
718 pCtx->fpu.FCW = 0x37f;
719
720 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
721 pCtx->fpu.MXCSR = 0x1F80;
722
723 /* Init PAT MSR */
724 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
725
726 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
727 * The Intel docs don't mention it.
728 */
729 pCtx->msrEFER = 0;
730}
731
732
733/**
734 * Execute state save operation.
735 *
736 * @returns VBox status code.
737 * @param pVM VM Handle.
738 * @param pSSM SSM operation handle.
739 */
740static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
741{
742 /* Set the size of RTGCPTR for use of SSMR3Get/PutGCPtr. */
743 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
744
745 /*
746 * Save.
747 */
748 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
749 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
750 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
751 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
752
753 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
754 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
755
756 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
757 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
758
759 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
760 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
761
762 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
763
764 /* Add the cpuid for checking that the cpu is unchanged. */
765 uint32_t au32CpuId[8] = {0};
766 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
767 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
768 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
769}
770
771
772/**
773 * Load a version 1.6 CPUMCTX structure.
774 *
775 * @returns VBox status code.
776 * @param pVM VM Handle.
777 * @param pCpumctx16 Version 1.6 CPUMCTX
778 */
779static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
780{
781#define CPUMCTX16_LOADREG(RegName) \
782 pVM->cpum.s.Guest.RegName = pCpumctx16->RegName;
783
784#define CPUMCTX16_LOADDRXREG(RegName) \
785 pVM->cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
786
787#define CPUMCTX16_LOADHIDREG(RegName) \
788 pVM->cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
789 pVM->cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
790 pVM->cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
791
792#define CPUMCTX16_LOADSEGREG(RegName) \
793 pVM->cpum.s.Guest.RegName = pCpumctx16->RegName; \
794 CPUMCTX16_LOADHIDREG(RegName);
795
796 pVM->cpum.s.Guest.fpu = pCpumctx16->fpu;
797
798 CPUMCTX16_LOADREG(rax);
799 CPUMCTX16_LOADREG(rbx);
800 CPUMCTX16_LOADREG(rcx);
801 CPUMCTX16_LOADREG(rdx);
802 CPUMCTX16_LOADREG(rdi);
803 CPUMCTX16_LOADREG(rsi);
804 CPUMCTX16_LOADREG(rbp);
805 CPUMCTX16_LOADREG(esp);
806 CPUMCTX16_LOADREG(rip);
807 CPUMCTX16_LOADREG(rflags);
808
809 CPUMCTX16_LOADSEGREG(cs);
810 CPUMCTX16_LOADSEGREG(ds);
811 CPUMCTX16_LOADSEGREG(es);
812 CPUMCTX16_LOADSEGREG(fs);
813 CPUMCTX16_LOADSEGREG(gs);
814 CPUMCTX16_LOADSEGREG(ss);
815
816 CPUMCTX16_LOADREG(r8);
817 CPUMCTX16_LOADREG(r9);
818 CPUMCTX16_LOADREG(r10);
819 CPUMCTX16_LOADREG(r11);
820 CPUMCTX16_LOADREG(r12);
821 CPUMCTX16_LOADREG(r13);
822 CPUMCTX16_LOADREG(r14);
823 CPUMCTX16_LOADREG(r15);
824
825 CPUMCTX16_LOADREG(cr0);
826 CPUMCTX16_LOADREG(cr2);
827 CPUMCTX16_LOADREG(cr3);
828 CPUMCTX16_LOADREG(cr4);
829
830 CPUMCTX16_LOADDRXREG(0);
831 CPUMCTX16_LOADDRXREG(1);
832 CPUMCTX16_LOADDRXREG(2);
833 CPUMCTX16_LOADDRXREG(3);
834 CPUMCTX16_LOADDRXREG(4);
835 CPUMCTX16_LOADDRXREG(5);
836 CPUMCTX16_LOADDRXREG(6);
837 CPUMCTX16_LOADDRXREG(7);
838
839 pVM->cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
840 pVM->cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
841 pVM->cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
842 pVM->cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
843
844 CPUMCTX16_LOADREG(ldtr);
845 CPUMCTX16_LOADREG(tr);
846
847 pVM->cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
848
849 CPUMCTX16_LOADREG(msrEFER);
850 CPUMCTX16_LOADREG(msrSTAR);
851 CPUMCTX16_LOADREG(msrPAT);
852 CPUMCTX16_LOADREG(msrLSTAR);
853 CPUMCTX16_LOADREG(msrCSTAR);
854 CPUMCTX16_LOADREG(msrSFMASK);
855 CPUMCTX16_LOADREG(msrKERNELGSBASE);
856
857 CPUMCTX16_LOADHIDREG(ldtr);
858 CPUMCTX16_LOADHIDREG(tr);
859
860#undef CPUMCTX16_LOADSEGREG
861#undef CPUMCTX16_LOADHIDREG
862#undef CPUMCTX16_LOADDRXREG
863#undef CPUMCTX16_LOADREG
864}
865
866
867/**
868 * Execute state load operation.
869 *
870 * @returns VBox status code.
871 * @param pVM VM Handle.
872 * @param pSSM SSM operation handle.
873 * @param u32Version Data layout version.
874 */
875static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
876{
877 /*
878 * Validate version.
879 */
880 if ( u32Version != CPUM_SAVED_STATE_VERSION
881 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
882 {
883 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
884 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
885 }
886
887 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
888 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
889 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
890 else
891 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
892
893 /*
894 * Restore.
895 */
896 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
897 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
898 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
899 pVM->cpum.s.Hyper.cr3 = uCR3;
900 pVM->cpum.s.Hyper.esp = uESP;
901 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
902 {
903 CPUMCTX_VER1_6 cpumctx16;
904 memset(&pVM->cpum.s.Guest, 0, sizeof(pVM->cpum.s.Guest));
905 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
906
907 /* Save the old cpumctx state into the new one. */
908 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
909 }
910 else
911 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
912
913 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
914 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
915
916 uint32_t cElements;
917 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
918 /* Support old saved states with a smaller standard cpuid array. */
919 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
920 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
921 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
922
923 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
924 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
925 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
926 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
927
928 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
929 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
930 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
931 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
932
933 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
934
935 /*
936 * Check that the basic cpuid id information is unchanged.
937 */
938 uint32_t au32CpuId[8] = {0};
939 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
940 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
941 uint32_t au32CpuIdSaved[8];
942 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
943 if (VBOX_SUCCESS(rc))
944 {
945 /* Ignore APIC ID (AMD specs). */
946 au32CpuId[5] &= ~0xff000000;
947 au32CpuIdSaved[5] &= ~0xff000000;
948 /* Ignore the number of Logical CPUs (AMD specs). */
949 au32CpuId[5] &= ~0x00ff0000;
950 au32CpuIdSaved[5] &= ~0x00ff0000;
951
952 /* do the compare */
953 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
954 {
955 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
956 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
957 "Saved=%.*Vhxs\n"
958 "Real =%.*Vhxs\n",
959 sizeof(au32CpuIdSaved), au32CpuIdSaved,
960 sizeof(au32CpuId), au32CpuId));
961 else
962 {
963 LogRel(("cpumR3Load: CpuId mismatch!\n"
964 "Saved=%.*Vhxs\n"
965 "Real =%.*Vhxs\n",
966 sizeof(au32CpuIdSaved), au32CpuIdSaved,
967 sizeof(au32CpuId), au32CpuId));
968 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
969 }
970 }
971 }
972
973 return rc;
974}
975
976
977/**
978 * Formats the EFLAGS value into mnemonics.
979 *
980 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
981 * @param efl The EFLAGS value.
982 */
983static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
984{
985 /*
986 * Format the flags.
987 */
988 static const struct
989 {
990 const char *pszSet; const char *pszClear; uint32_t fFlag;
991 } s_aFlags[] =
992 {
993 { "vip",NULL, X86_EFL_VIP },
994 { "vif",NULL, X86_EFL_VIF },
995 { "ac", NULL, X86_EFL_AC },
996 { "vm", NULL, X86_EFL_VM },
997 { "rf", NULL, X86_EFL_RF },
998 { "nt", NULL, X86_EFL_NT },
999 { "ov", "nv", X86_EFL_OF },
1000 { "dn", "up", X86_EFL_DF },
1001 { "ei", "di", X86_EFL_IF },
1002 { "tf", NULL, X86_EFL_TF },
1003 { "nt", "pl", X86_EFL_SF },
1004 { "nz", "zr", X86_EFL_ZF },
1005 { "ac", "na", X86_EFL_AF },
1006 { "po", "pe", X86_EFL_PF },
1007 { "cy", "nc", X86_EFL_CF },
1008 };
1009 char *psz = pszEFlags;
1010 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1011 {
1012 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1013 if (pszAdd)
1014 {
1015 strcpy(psz, pszAdd);
1016 psz += strlen(pszAdd);
1017 *psz++ = ' ';
1018 }
1019 }
1020 psz[-1] = '\0';
1021}
1022
1023
1024/**
1025 * Formats a full register dump.
1026 *
1027 * @param pVM VM Handle.
1028 * @param pCtx The context to format.
1029 * @param pCtxCore The context core to format.
1030 * @param pHlp Output functions.
1031 * @param enmType The dump type.
1032 * @param pszPrefix Register name prefix.
1033 */
1034static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1035{
1036 /*
1037 * Format the EFLAGS.
1038 */
1039 uint32_t efl = pCtxCore->eflags.u32;
1040 char szEFlags[80];
1041 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1042
1043 /*
1044 * Format the registers.
1045 */
1046 switch (enmType)
1047 {
1048 case CPUMDUMPTYPE_TERSE:
1049 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1050 pHlp->pfnPrintf(pHlp,
1051 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1052 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1053 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1054 "%sr14=%016RX64 %sr15=%016RX64\n"
1055 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1056 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1057 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1058 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1059 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1060 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1061 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1062 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1063 else
1064 pHlp->pfnPrintf(pHlp,
1065 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1066 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1067 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1068 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1069 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1070 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1071 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1072 break;
1073
1074 case CPUMDUMPTYPE_DEFAULT:
1075 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1076 pHlp->pfnPrintf(pHlp,
1077 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1078 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1079 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1080 "%sr14=%016RX64 %sr15=%016RX64\n"
1081 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1082 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1083 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
1084 ,
1085 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1086 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1087 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1088 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1089 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1090 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1091 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1092 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1093 else
1094 pHlp->pfnPrintf(pHlp,
1095 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1096 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1097 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1098 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1099 ,
1100 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1101 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1102 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1103 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1104 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1105 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1106 break;
1107
1108 case CPUMDUMPTYPE_VERBOSE:
1109 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1110 pHlp->pfnPrintf(pHlp,
1111 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1112 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1113 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1114 "%sr14=%016RX64 %sr15=%016RX64\n"
1115 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1116 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1117 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1118 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1119 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1120 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1121 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1122 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1123 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1124 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1125 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1126 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1127 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1128 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1129 ,
1130 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1131 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1132 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1133 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1134 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1135 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1136 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1137 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1138 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1139 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1140 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1141 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1142 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1143 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1144 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1145 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1146 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1147 else
1148 pHlp->pfnPrintf(pHlp,
1149 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1150 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1151 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1152 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1153 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1154 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1155 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1156 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1157 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1158 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1159 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1160 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1161 ,
1162 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1163 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1164 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1165 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1166 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1167 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1168 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1169 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1170 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1171 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1172 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1173 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1174
1175 pHlp->pfnPrintf(pHlp,
1176 "FPU:\n"
1177 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1178 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1179 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1180 ,
1181 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1182 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1183 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1184 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1185
1186 pHlp->pfnPrintf(pHlp,
1187 "MSR:\n"
1188 "%sEFER =%016RX64\n"
1189 "%sPAT =%016RX64\n"
1190 "%sSTAR =%016RX64\n"
1191 "%sCSTAR =%016RX64\n"
1192 "%sLSTAR =%016RX64\n"
1193 "%sSFMASK =%016RX64\n"
1194 "%sKERNELGSBASE =%016RX64\n",
1195 pszPrefix, pCtx->msrEFER,
1196 pszPrefix, pCtx->msrPAT,
1197 pszPrefix, pCtx->msrSTAR,
1198 pszPrefix, pCtx->msrCSTAR,
1199 pszPrefix, pCtx->msrLSTAR,
1200 pszPrefix, pCtx->msrSFMASK,
1201 pszPrefix, pCtx->msrKERNELGSBASE);
1202 break;
1203 }
1204}
1205
1206
1207/**
1208 * Display all cpu states and any other cpum info.
1209 *
1210 * @param pVM VM Handle.
1211 * @param pHlp The info helper functions.
1212 * @param pszArgs Arguments, ignored.
1213 */
1214static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1215{
1216 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1217 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1218 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1219 cpumR3InfoHost(pVM, pHlp, pszArgs);
1220}
1221
1222
1223/**
1224 * Parses the info argument.
1225 *
1226 * The argument starts with 'verbose', 'terse' or 'default' and then
1227 * continues with the comment string.
1228 *
1229 * @param pszArgs The pointer to the argument string.
1230 * @param penmType Where to store the dump type request.
1231 * @param ppszComment Where to store the pointer to the comment string.
1232 */
1233static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1234{
1235 if (!pszArgs)
1236 {
1237 *penmType = CPUMDUMPTYPE_DEFAULT;
1238 *ppszComment = "";
1239 }
1240 else
1241 {
1242 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1243 {
1244 pszArgs += 5;
1245 *penmType = CPUMDUMPTYPE_VERBOSE;
1246 }
1247 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1248 {
1249 pszArgs += 5;
1250 *penmType = CPUMDUMPTYPE_TERSE;
1251 }
1252 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1253 {
1254 pszArgs += 7;
1255 *penmType = CPUMDUMPTYPE_DEFAULT;
1256 }
1257 else
1258 *penmType = CPUMDUMPTYPE_DEFAULT;
1259 *ppszComment = RTStrStripL(pszArgs);
1260 }
1261}
1262
1263
1264/**
1265 * Display the guest cpu state.
1266 *
1267 * @param pVM VM Handle.
1268 * @param pHlp The info helper functions.
1269 * @param pszArgs Arguments, ignored.
1270 */
1271static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1272{
1273 CPUMDUMPTYPE enmType;
1274 const char *pszComment;
1275 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1276 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1277 cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
1278}
1279
1280
1281/**
1282 * Display the current guest instruction
1283 *
1284 * @param pVM VM Handle.
1285 * @param pHlp The info helper functions.
1286 * @param pszArgs Arguments, ignored.
1287 */
1288static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1289{
1290 char szInstruction[256];
1291 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1292 if (VBOX_SUCCESS(rc))
1293 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1294}
1295
1296
1297/**
1298 * Display the hypervisor cpu state.
1299 *
1300 * @param pVM VM Handle.
1301 * @param pHlp The info helper functions.
1302 * @param pszArgs Arguments, ignored.
1303 */
1304static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1305{
1306 CPUMDUMPTYPE enmType;
1307 const char *pszComment;
1308 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1309 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1310 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1311 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1312}
1313
1314
1315/**
1316 * Display the host cpu state.
1317 *
1318 * @param pVM VM Handle.
1319 * @param pHlp The info helper functions.
1320 * @param pszArgs Arguments, ignored.
1321 */
1322static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1323{
1324 CPUMDUMPTYPE enmType;
1325 const char *pszComment;
1326 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1327 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1328
1329 /*
1330 * Format the EFLAGS.
1331 */
1332 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
1333#if HC_ARCH_BITS == 32
1334 uint32_t efl = pCtx->eflags.u32;
1335#else
1336 uint64_t efl = pCtx->rflags;
1337#endif
1338 char szEFlags[80];
1339 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1340
1341 /*
1342 * Format the registers.
1343 */
1344#if HC_ARCH_BITS == 32
1345# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1346 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1347# endif
1348 {
1349 pHlp->pfnPrintf(pHlp,
1350 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1351 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1352 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1353 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1354 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1355 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1356 ,
1357 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1358 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1359 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1360 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1361 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1362 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1363 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1364 }
1365# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1366 else
1367# endif
1368#endif
1369#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1370 {
1371 pHlp->pfnPrintf(pHlp,
1372 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1373 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1374 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1375 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1376 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1377 "r14=%016RX64 r15=%016RX64\n"
1378 "iopl=%d %31s\n"
1379 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1380 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1381 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1382 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1383 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1384 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1385 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1386 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1387 ,
1388 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1389 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1390 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1391 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1392 pCtx->r11, pCtx->r12, pCtx->r13,
1393 pCtx->r14, pCtx->r15,
1394 X86_EFL_GET_IOPL(efl), szEFlags,
1395 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1396 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1397 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1398 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1399 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1400 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1401 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1402 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1403 }
1404#endif
1405}
1406
1407
1408/**
1409 * Get L1 cache / TLS associativity.
1410 */
1411static const char *getCacheAss(unsigned u, char *pszBuf)
1412{
1413 if (u == 0)
1414 return "res0 ";
1415 if (u == 1)
1416 return "direct";
1417 if (u >= 256)
1418 return "???";
1419
1420 RTStrPrintf(pszBuf, 16, "%d way", u);
1421 return pszBuf;
1422}
1423
1424
1425/**
1426 * Get L2 cache soociativity.
1427 */
1428const char *getL2CacheAss(unsigned u)
1429{
1430 switch (u)
1431 {
1432 case 0: return "off ";
1433 case 1: return "direct";
1434 case 2: return "2 way ";
1435 case 3: return "res3 ";
1436 case 4: return "4 way ";
1437 case 5: return "res5 ";
1438 case 6: return "8 way "; case 7: return "res7 ";
1439 case 8: return "16 way";
1440 case 9: return "res9 ";
1441 case 10: return "res10 ";
1442 case 11: return "res11 ";
1443 case 12: return "res12 ";
1444 case 13: return "res13 ";
1445 case 14: return "res14 ";
1446 case 15: return "fully ";
1447 default:
1448 return "????";
1449 }
1450}
1451
1452
1453/**
1454 * Display the guest CpuId leaves.
1455 *
1456 * @param pVM VM Handle.
1457 * @param pHlp The info helper functions.
1458 * @param pszArgs "terse", "default" or "verbose".
1459 */
1460static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1461{
1462 /*
1463 * Parse the argument.
1464 */
1465 unsigned iVerbosity = 1;
1466 if (pszArgs)
1467 {
1468 pszArgs = RTStrStripL(pszArgs);
1469 if (!strcmp(pszArgs, "terse"))
1470 iVerbosity--;
1471 else if (!strcmp(pszArgs, "verbose"))
1472 iVerbosity++;
1473 }
1474
1475 /*
1476 * Start cracking.
1477 */
1478 CPUMCPUID Host;
1479 CPUMCPUID Guest;
1480 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1481
1482 pHlp->pfnPrintf(pHlp,
1483 " RAW Standard CPUIDs\n"
1484 " Function eax ebx ecx edx\n");
1485 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1486 {
1487 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1488 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1489
1490 pHlp->pfnPrintf(pHlp,
1491 "Gst: %08x %08x %08x %08x %08x%s\n"
1492 "Hst: %08x %08x %08x %08x\n",
1493 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1494 i <= cStdMax ? "" : "*",
1495 Host.eax, Host.ebx, Host.ecx, Host.edx);
1496 }
1497
1498 /*
1499 * If verbose, decode it.
1500 */
1501 if (iVerbosity)
1502 {
1503 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1504 pHlp->pfnPrintf(pHlp,
1505 "Name: %.04s%.04s%.04s\n"
1506 "Supports: 0-%x\n",
1507 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1508 }
1509
1510 /*
1511 * Get Features.
1512 */
1513 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1514 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1515 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1516 if (cStdMax >= 1 && iVerbosity)
1517 {
1518 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1519 uint32_t uEAX = Guest.eax;
1520
1521 pHlp->pfnPrintf(pHlp,
1522 "Family: %d \tExtended: %d \tEffective: %d\n"
1523 "Model: %d \tExtended: %d \tEffective: %d\n"
1524 "Stepping: %d\n"
1525 "APIC ID: %#04x\n"
1526 "Logical CPUs: %d\n"
1527 "CLFLUSH Size: %d\n"
1528 "Brand ID: %#04x\n",
1529 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1530 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1531 ASMGetCpuStepping(uEAX),
1532 (Guest.ebx >> 24) & 0xff,
1533 (Guest.ebx >> 16) & 0xff,
1534 (Guest.ebx >> 8) & 0xff,
1535 (Guest.ebx >> 0) & 0xff);
1536 if (iVerbosity == 1)
1537 {
1538 uint32_t uEDX = Guest.edx;
1539 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1540 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1541 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1542 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1543 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1544 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1545 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1546 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1547 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1548 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1549 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1550 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1551 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1552 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1553 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1554 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1555 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1556 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1557 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1558 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1559 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1560 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1561 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1562 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1563 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1564 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1565 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1566 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1567 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1568 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1569 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1570 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1571 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1572 pHlp->pfnPrintf(pHlp, "\n");
1573
1574 uint32_t uECX = Guest.ecx;
1575 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1576 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1577 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1578 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1579 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1580 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1581 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1582 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1583 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1584 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1585 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1586 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1587 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1588 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1589 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1590 for (unsigned iBit = 14; iBit < 32; iBit++)
1591 if (uECX & RT_BIT(iBit))
1592 pHlp->pfnPrintf(pHlp, " %d", iBit);
1593 pHlp->pfnPrintf(pHlp, "\n");
1594 }
1595 else
1596 {
1597 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1598
1599 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1600 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1601 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1602 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1603
1604 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1605 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1606 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1607 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1608 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1609 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1610 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1611 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1612 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1613 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1614 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1615 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1616 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1617 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1618 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1619 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1620 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1621 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1622 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1623 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1624 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1625 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1626 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1627 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1628 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1629 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1630 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1631 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1632 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1633 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1634 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1635 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1636 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1637
1638 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1639 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1640 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1641 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1642 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1643 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1644 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1645 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1646 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1647 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1648 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1649 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1650 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1651 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1652 }
1653 }
1654 if (cStdMax >= 2 && iVerbosity)
1655 {
1656 /** @todo */
1657 }
1658
1659 /*
1660 * Extended.
1661 * Implemented after AMD specs.
1662 */
1663 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1664
1665 pHlp->pfnPrintf(pHlp,
1666 "\n"
1667 " RAW Extended CPUIDs\n"
1668 " Function eax ebx ecx edx\n");
1669 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1670 {
1671 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1672 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1673
1674 pHlp->pfnPrintf(pHlp,
1675 "Gst: %08x %08x %08x %08x %08x%s\n"
1676 "Hst: %08x %08x %08x %08x\n",
1677 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1678 i <= cExtMax ? "" : "*",
1679 Host.eax, Host.ebx, Host.ecx, Host.edx);
1680 }
1681
1682 /*
1683 * Understandable output
1684 */
1685 if (iVerbosity)
1686 {
1687 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1688 pHlp->pfnPrintf(pHlp,
1689 "Ext Name: %.4s%.4s%.4s\n"
1690 "Ext Supports: 0x80000000-%#010x\n",
1691 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1692 }
1693
1694 if (iVerbosity && cExtMax >= 1)
1695 {
1696 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1697 uint32_t uEAX = Guest.eax;
1698 pHlp->pfnPrintf(pHlp,
1699 "Family: %d \tExtended: %d \tEffective: %d\n"
1700 "Model: %d \tExtended: %d \tEffective: %d\n"
1701 "Stepping: %d\n"
1702 "Brand ID: %#05x\n",
1703 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1704 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1705 ASMGetCpuStepping(uEAX),
1706 Guest.ebx & 0xfff);
1707
1708 if (iVerbosity == 1)
1709 {
1710 uint32_t uEDX = Guest.edx;
1711 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1712 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1713 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1714 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1715 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1716 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1717 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1718 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1719 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1720 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1721 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1722 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1723 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1724 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1725 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1726 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1727 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1728 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1729 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1730 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1731 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1732 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1733 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1734 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1735 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1736 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1737 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1738 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1739 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1740 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1741 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1742 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1743 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1744 pHlp->pfnPrintf(pHlp, "\n");
1745
1746 uint32_t uECX = Guest.ecx;
1747 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1748 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1749 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1750 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1751 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1752 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1753 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1754 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1755 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1756 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1757 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1758 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1759 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1760 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1761 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1762 for (unsigned iBit = 5; iBit < 32; iBit++)
1763 if (uECX & RT_BIT(iBit))
1764 pHlp->pfnPrintf(pHlp, " %d", iBit);
1765 pHlp->pfnPrintf(pHlp, "\n");
1766 }
1767 else
1768 {
1769 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1770
1771 uint32_t uEdxGst = Guest.edx;
1772 uint32_t uEdxHst = Host.edx;
1773 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1774 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1775 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1776 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1777 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1778 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1779 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1780 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1781 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1782 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1783 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1784 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1785 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1786 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1787 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1788 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1789 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1790 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1791 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1792 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1793 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1794 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1795 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1796 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1797 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1798 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1799 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1800 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1801 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1802 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1803 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1804 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1805 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1806
1807 uint32_t uEcxGst = Guest.ecx;
1808 uint32_t uEcxHst = Host.ecx;
1809 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1810 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1811 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1812 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1813 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1814 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1815 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1816 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1817 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1818 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1819 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1820 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1821 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1822 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1823 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1824 }
1825 }
1826
1827 if (iVerbosity && cExtMax >= 2)
1828 {
1829 char szString[4*4*3+1] = {0};
1830 uint32_t *pu32 = (uint32_t *)szString;
1831 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1832 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1833 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1834 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1835 if (cExtMax >= 3)
1836 {
1837 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1838 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1839 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1840 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1841 }
1842 if (cExtMax >= 4)
1843 {
1844 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1845 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1846 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1847 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1848 }
1849 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1850 }
1851
1852 if (iVerbosity && cExtMax >= 5)
1853 {
1854 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1855 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1856 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1857 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1858 char sz1[32];
1859 char sz2[32];
1860
1861 pHlp->pfnPrintf(pHlp,
1862 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1863 "TLB 2/4M Data: %s %3d entries\n",
1864 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1865 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1866 pHlp->pfnPrintf(pHlp,
1867 "TLB 4K Instr/Uni: %s %3d entries\n"
1868 "TLB 4K Data: %s %3d entries\n",
1869 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1870 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1871 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1872 "L1 Instr Cache Lines Per Tag: %d\n"
1873 "L1 Instr Cache Associativity: %s\n"
1874 "L1 Instr Cache Size: %d KB\n",
1875 (uEDX >> 0) & 0xff,
1876 (uEDX >> 8) & 0xff,
1877 getCacheAss((uEDX >> 16) & 0xff, sz1),
1878 (uEDX >> 24) & 0xff);
1879 pHlp->pfnPrintf(pHlp,
1880 "L1 Data Cache Line Size: %d bytes\n"
1881 "L1 Data Cache Lines Per Tag: %d\n"
1882 "L1 Data Cache Associativity: %s\n"
1883 "L1 Data Cache Size: %d KB\n",
1884 (uECX >> 0) & 0xff,
1885 (uECX >> 8) & 0xff,
1886 getCacheAss((uECX >> 16) & 0xff, sz1),
1887 (uECX >> 24) & 0xff);
1888 }
1889
1890 if (iVerbosity && cExtMax >= 6)
1891 {
1892 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1893 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1894 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1895
1896 pHlp->pfnPrintf(pHlp,
1897 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1898 "L2 TLB 2/4M Data: %s %4d entries\n",
1899 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1900 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1901 pHlp->pfnPrintf(pHlp,
1902 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1903 "L2 TLB 4K Data: %s %4d entries\n",
1904 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1905 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1906 pHlp->pfnPrintf(pHlp,
1907 "L2 Cache Line Size: %d bytes\n"
1908 "L2 Cache Lines Per Tag: %d\n"
1909 "L2 Cache Associativity: %s\n"
1910 "L2 Cache Size: %d KB\n",
1911 (uEDX >> 0) & 0xff,
1912 (uEDX >> 8) & 0xf,
1913 getL2CacheAss((uEDX >> 12) & 0xf),
1914 (uEDX >> 16) & 0xffff);
1915 }
1916
1917 if (iVerbosity && cExtMax >= 7)
1918 {
1919 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1920
1921 pHlp->pfnPrintf(pHlp, "APM Features: ");
1922 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1923 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1924 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1925 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1926 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1927 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1928 for (unsigned iBit = 6; iBit < 32; iBit++)
1929 if (uEDX & RT_BIT(iBit))
1930 pHlp->pfnPrintf(pHlp, " %d", iBit);
1931 pHlp->pfnPrintf(pHlp, "\n");
1932 }
1933
1934 if (iVerbosity && cExtMax >= 8)
1935 {
1936 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1937 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1938
1939 pHlp->pfnPrintf(pHlp,
1940 "Physical Address Width: %d bits\n"
1941 "Virtual Address Width: %d bits\n",
1942 (uEAX >> 0) & 0xff,
1943 (uEAX >> 8) & 0xff);
1944 pHlp->pfnPrintf(pHlp,
1945 "Physical Core Count: %d\n",
1946 (uECX >> 0) & 0xff);
1947 }
1948
1949
1950 /*
1951 * Centaur.
1952 */
1953 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1954
1955 pHlp->pfnPrintf(pHlp,
1956 "\n"
1957 " RAW Centaur CPUIDs\n"
1958 " Function eax ebx ecx edx\n");
1959 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1960 {
1961 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1962 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1963
1964 pHlp->pfnPrintf(pHlp,
1965 "Gst: %08x %08x %08x %08x %08x%s\n"
1966 "Hst: %08x %08x %08x %08x\n",
1967 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1968 i <= cCentaurMax ? "" : "*",
1969 Host.eax, Host.ebx, Host.ecx, Host.edx);
1970 }
1971
1972 /*
1973 * Understandable output
1974 */
1975 if (iVerbosity)
1976 {
1977 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1978 pHlp->pfnPrintf(pHlp,
1979 "Centaur Supports: 0xc0000000-%#010x\n",
1980 Guest.eax);
1981 }
1982
1983 if (iVerbosity && cCentaurMax >= 1)
1984 {
1985 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1986 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1987 uint32_t uEdxHst = Host.edx;
1988
1989 if (iVerbosity == 1)
1990 {
1991 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1992 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1993 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1994 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1995 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1996 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1997 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1998 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1999 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2000 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2001 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2002 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2003 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2004 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2005 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2006 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2007 for (unsigned iBit = 14; iBit < 32; iBit++)
2008 if (uEdxGst & RT_BIT(iBit))
2009 pHlp->pfnPrintf(pHlp, " %d", iBit);
2010 pHlp->pfnPrintf(pHlp, "\n");
2011 }
2012 else
2013 {
2014 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2015 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2016 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2017 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2018 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2019 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2020 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2021 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2022 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2023 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2024 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2025 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2026 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2027 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2028 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2029 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2030 for (unsigned iBit = 14; iBit < 32; iBit++)
2031 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2032 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2033 pHlp->pfnPrintf(pHlp, "\n");
2034 }
2035 }
2036}
2037
2038
2039/**
2040 * Structure used when disassembling and instructions in DBGF.
2041 * This is used so the reader function can get the stuff it needs.
2042 */
2043typedef struct CPUMDISASSTATE
2044{
2045 /** Pointer to the CPU structure. */
2046 PDISCPUSTATE pCpu;
2047 /** The VM handle. */
2048 PVM pVM;
2049 /** Pointer to the first byte in the segemnt. */
2050 RTGCUINTPTR GCPtrSegBase;
2051 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2052 RTGCUINTPTR GCPtrSegEnd;
2053 /** The size of the segment minus 1. */
2054 RTGCUINTPTR cbSegLimit;
2055 /** Pointer to the current page - HC Ptr. */
2056 void const *pvPageHC;
2057 /** Pointer to the current page - GC Ptr. */
2058 RTGCPTR pvPageGC;
2059 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2060 PGMPAGEMAPLOCK PageMapLock;
2061 /** Whether the PageMapLock is valid or not. */
2062 bool fLocked;
2063 /** 64 bits mode or not. */
2064 bool f64Bits;
2065} CPUMDISASSTATE, *PCPUMDISASSTATE;
2066
2067
2068/**
2069 * Instruction reader.
2070 *
2071 * @returns VBox status code.
2072 * @param PtrSrc Address to read from.
2073 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2074 * @param pu8Dst Where to store the bytes.
2075 * @param cbRead Number of bytes to read.
2076 * @param uDisCpu Pointer to the disassembler cpu state.
2077 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2078 */
2079static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2080{
2081 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2082 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2083 Assert(cbRead > 0);
2084 for (;;)
2085 {
2086 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2087
2088 /* Need to update the page translation? */
2089 if ( !pState->pvPageHC
2090 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2091 {
2092 int rc = VINF_SUCCESS;
2093
2094 /* translate the address */
2095 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2096 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2097 {
2098 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
2099 if (!pState->pvPageHC)
2100 rc = VERR_INVALID_POINTER;
2101 }
2102 else
2103 {
2104 /* Release mapping lock previously acquired. */
2105 if (pState->fLocked)
2106 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2107 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
2108 pState->fLocked = RT_SUCCESS_NP(rc);
2109 }
2110 if (VBOX_FAILURE(rc))
2111 {
2112 pState->pvPageHC = NULL;
2113 return rc;
2114 }
2115 }
2116
2117 /* check the segemnt limit */
2118 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2119 return VERR_OUT_OF_SELECTOR_BOUNDS;
2120
2121 /* calc how much we can read */
2122 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2123 if (!pState->f64Bits)
2124 {
2125 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2126 if (cb > cbSeg && cbSeg)
2127 cb = cbSeg;
2128 }
2129 if (cb > cbRead)
2130 cb = cbRead;
2131
2132 /* read and advance */
2133 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
2134 cbRead -= cb;
2135 if (!cbRead)
2136 return VINF_SUCCESS;
2137 pu8Dst += cb;
2138 PtrSrc += cb;
2139 }
2140}
2141
2142
2143/**
2144 * Disassemble an instruction and return the information in the provided structure.
2145 *
2146 * @returns VBox status code.
2147 * @param pVM VM Handle
2148 * @param pCtx CPU context
2149 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2150 * @param pCpu Disassembly state
2151 * @param pszPrefix String prefix for logging (debug only)
2152 *
2153 */
2154VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2155{
2156 CPUMDISASSTATE State;
2157 int rc;
2158
2159 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2160 State.pCpu = pCpu;
2161 State.pvPageGC = 0;
2162 State.pvPageHC = NULL;
2163 State.pVM = pVM;
2164 State.fLocked = false;
2165 State.f64Bits = false;
2166
2167 /*
2168 * Get selector information.
2169 */
2170 if ( (pCtx->cr0 & X86_CR0_PE)
2171 && pCtx->eflags.Bits.u1VM == 0)
2172 {
2173 if (CPUMAreHiddenSelRegsValid(pVM))
2174 {
2175 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2176 State.GCPtrSegBase = pCtx->csHid.u64Base;
2177 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2178 State.cbSegLimit = pCtx->csHid.u32Limit;
2179 pCpu->mode = (State.f64Bits)
2180 ? CPUMODE_64BIT
2181 : pCtx->csHid.Attr.n.u1DefBig
2182 ? CPUMODE_32BIT
2183 : CPUMODE_16BIT;
2184 }
2185 else
2186 {
2187 SELMSELINFO SelInfo;
2188
2189 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2190 if (!VBOX_SUCCESS(rc))
2191 {
2192 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2193 return rc;
2194 }
2195
2196 /*
2197 * Validate the selector.
2198 */
2199 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2200 if (!VBOX_SUCCESS(rc))
2201 {
2202 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2203 return rc;
2204 }
2205 State.GCPtrSegBase = SelInfo.GCPtrBase;
2206 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2207 State.cbSegLimit = SelInfo.cbLimit;
2208 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2209 }
2210 }
2211 else
2212 {
2213 /* real or V86 mode */
2214 pCpu->mode = CPUMODE_16BIT;
2215 State.GCPtrSegBase = pCtx->cs * 16;
2216 State.GCPtrSegEnd = 0xFFFFFFFF;
2217 State.cbSegLimit = 0xFFFFFFFF;
2218 }
2219
2220 /*
2221 * Disassemble the instruction.
2222 */
2223 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2224 pCpu->apvUserData[0] = &State;
2225
2226 uint32_t cbInstr;
2227#ifndef LOG_ENABLED
2228 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2229 if (VBOX_SUCCESS(rc))
2230 {
2231#else
2232 char szOutput[160];
2233 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2234 if (VBOX_SUCCESS(rc))
2235 {
2236 /* log it */
2237 if (pszPrefix)
2238 Log(("%s: %s", pszPrefix, szOutput));
2239 else
2240 Log(("%s", szOutput));
2241#endif
2242 rc = VINF_SUCCESS;
2243 }
2244 else
2245 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
2246
2247 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2248 if (State.fLocked)
2249 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2250
2251 return rc;
2252}
2253
2254#ifdef DEBUG
2255
2256/**
2257 * Disassemble an instruction and dump it to the log
2258 *
2259 * @returns VBox status code.
2260 * @param pVM VM Handle
2261 * @param pCtx CPU context
2262 * @param pc GC instruction pointer
2263 * @param pszPrefix String prefix for logging
2264 *
2265 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2266 */
2267VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2268{
2269 DISCPUSTATE Cpu;
2270 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &Cpu, pszPrefix);
2271}
2272
2273
2274/**
2275 * Disassemble an instruction and dump it to the log
2276 *
2277 * @returns VBox status code.
2278 * @param pVM VM Handle
2279 * @param pCtx CPU context
2280 * @param pc GC instruction pointer
2281 * @param pszPrefix String prefix for logging
2282 * @param nrInstructions
2283 *
2284 * @deprecated Create new DBGFR3Disas function to do this.
2285 */
2286VMMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix, int nrInstructions)
2287{
2288 for (int i = 0; i < nrInstructions; i++)
2289 {
2290 DISCPUSTATE cpu;
2291
2292 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, pszPrefix);
2293 pc += cpu.opsize;
2294 }
2295}
2296
2297
2298/**
2299 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2300 *
2301 * @internal
2302 */
2303VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2304{
2305 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
2306}
2307
2308#endif /* DEBUG */
2309
2310/**
2311 * API for controlling a few of the CPU features found in CR4.
2312 *
2313 * Currently only X86_CR4_TSD is accepted as input.
2314 *
2315 * @returns VBox status code.
2316 *
2317 * @param pVM The VM handle.
2318 * @param fOr The CR4 OR mask.
2319 * @param fAnd The CR4 AND mask.
2320 */
2321VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2322{
2323 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2324 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2325
2326 pVM->cpum.s.CR4.OrMask &= fAnd;
2327 pVM->cpum.s.CR4.OrMask |= fOr;
2328
2329 return VINF_SUCCESS;
2330}
2331
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