CPUM.cpp@ 13796

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1	/* $Id: CPUM.cpp 13796 2008-11-04 18:37:33Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_cpum CPUM - CPU Monitor / Manager
23	*
24	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
25	* also responsible for lazy FPU handling and some of the context loading
26	* in raw mode.
27	*
28	* There are three CPU contexts, the most important one is the guest one (GC).
29	* When running in raw-mode (RC) there is a special hyper context for the VMM
30	* part that floats around inside the guest address space. When running in
31	* raw-mode, CPUM also maintains a host context for saving and restoring
32	* registers accross world switches. This latter is done in cooperation with the
33	* world switcher (@see pg_vmm).
34	*
35	* @see grp_cpum
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_CPUM
42	#include <VBox/cpum.h>
43	#include <VBox/cpumdis.h>
44	#include <VBox/pgm.h>
45	#include <VBox/pdm.h>
46	#include <VBox/mm.h>
47	#include <VBox/selm.h>
48	#include <VBox/dbgf.h>
49	#include <VBox/patm.h>
50	#include <VBox/ssm.h>
51	#include "CPUMInternal.h"
52	#include <VBox/vm.h>
53
54	#include <VBox/param.h>
55	#include <VBox/dis.h>
56	#include <VBox/err.h>
57	#include <VBox/log.h>
58	#include <iprt/assert.h>
59	#include <iprt/asm.h>
60	#include <iprt/string.h>
61	#include <iprt/mp.h>
62	#include <iprt/cpuset.h>
63
64
65	/*******************************************************************************
66	* Defined Constants And Macros *
67	*******************************************************************************/
68	/** The saved state version. */
69	#define CPUM_SAVED_STATE_VERSION 8
70	/** The saved state version of 1.6, used for backwards compatability. */
71	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
72
73
74	/*******************************************************************************
75	* Structures and Typedefs *
76	*******************************************************************************/
77
78	/**
79	* What kind of cpu info dump to perform.
80	*/
81	typedef enum CPUMDUMPTYPE
82	{
83	CPUMDUMPTYPE_TERSE,
84	CPUMDUMPTYPE_DEFAULT,
85	CPUMDUMPTYPE_VERBOSE
86
87	} CPUMDUMPTYPE;
88	/** Pointer to a cpu info dump type. */
89	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
90
91
92	/*******************************************************************************
93	* Internal Functions *
94	*******************************************************************************/
95	static int cpumR3CpuIdInit(PVM pVM);
96	static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
97	static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
98	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
99	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
100	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104
105
106	/**
107	* Initializes the CPUM.
108	*
109	* @returns VBox status code.
110	* @param pVM The VM to operate on.
111	*/
112	VMMR3DECL(int) CPUMR3Init(PVM pVM)
113	{
114	LogFlow(("CPUMR3Init\n"));
115
116	/*
117	* Assert alignment and sizes.
118	*/
119	AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
120	AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
121
122	/*
123	* Setup any fixed pointers and offsets.
124	*/
125	pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
126	pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
127
128	/* Hidden selector registers are invalid by default. */
129	pVM->cpum.s.fValidHiddenSelRegs = false;
130
131	/*
132	* Check that the CPU supports the minimum features we require.
133	*/
134	if (!ASMHasCpuId())
135	{
136	Log(("The CPU doesn't support CPUID!\n"));
137	return VERR_UNSUPPORTED_CPU;
138	}
139	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
140	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
141
142	/* Setup the CR4 AND and OR masks used in the switcher */
143	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
144	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
145	{
146	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
147	/* No FXSAVE implies no SSE */
148	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
149	pVM->cpum.s.CR4.OrMask = 0;
150	}
151	else
152	{
153	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
154	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
155	}
156
157	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
158	{
159	Log(("The CPU doesn't support MMX!\n"));
160	return VERR_UNSUPPORTED_CPU;
161	}
162	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
163	{
164	Log(("The CPU doesn't support TSC!\n"));
165	return VERR_UNSUPPORTED_CPU;
166	}
167	/* Bogus on AMD? */
168	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
169	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
170
171	/*
172	* Setup hypervisor startup values.
173	*/
174
175	/*
176	* Register saved state data item.
177	*/
178	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
179	NULL, cpumR3Save, NULL,
180	NULL, cpumR3Load, NULL);
181	if (VBOX_FAILURE(rc))
182	return rc;
183
184	/* Query the CPU manufacturer. */
185	uint32_t uEAX, uEBX, uECX, uEDX;
186	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
187	if ( uEAX >= 1
188	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
189	&& uECX == X86_CPUID_VENDOR_AMD_ECX
190	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
191	pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
192	else if ( uEAX >= 1
193	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
194	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
195	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
196	pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
197	else /** @todo Via */
198	pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
199
200	/*
201	* Register info handlers.
202	*/
203	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
204	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
205	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
206	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
207	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
208	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
209
210	/*
211	* Initialize the Guest CPU state.
212	*/
213	rc = cpumR3CpuIdInit(pVM);
214	if (VBOX_FAILURE(rc))
215	return rc;
216	CPUMR3Reset(pVM);
217	return VINF_SUCCESS;
218	}
219
220
221	/**
222	* Initializes the per-VCPU CPUM.
223	*
224	* @returns VBox status code.
225	* @param pVM The VM to operate on.
226	*/
227	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
228	{
229	LogFlow(("CPUMR3InitCPU\n"));
230	return VINF_SUCCESS;
231	}
232
233
234	/**
235	* Initializes the emulated CPU's cpuid information.
236	*
237	* @returns VBox status code.
238	* @param pVM The VM to operate on.
239	*/
240	static int cpumR3CpuIdInit(PVM pVM)
241	{
242	PCPUM pCPUM = &pVM->cpum.s;
243	uint32_t i;
244
245	/*
246	* Get the host CPUIDs.
247	*/
248	for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
249	ASMCpuId_Idx_ECX(i, 0,
250	&pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
251	&pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
252	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
253	ASMCpuId(0x80000000 + i,
254	&pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
255	&pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
256	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
257	ASMCpuId(0xc0000000 + i,
258	&pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
259	&pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
260
261
262	/*
263	* Only report features we can support.
264	*/
265	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
266	\| X86_CPUID_FEATURE_EDX_VME
267	\| X86_CPUID_FEATURE_EDX_DE
268	\| X86_CPUID_FEATURE_EDX_PSE
269	\| X86_CPUID_FEATURE_EDX_TSC
270	\| X86_CPUID_FEATURE_EDX_MSR
271	//\| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
272	\| X86_CPUID_FEATURE_EDX_MCE
273	\| X86_CPUID_FEATURE_EDX_CX8
274	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
275	/** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
276	//\| X86_CPUID_FEATURE_EDX_SEP
277	\| X86_CPUID_FEATURE_EDX_MTRR
278	\| X86_CPUID_FEATURE_EDX_PGE
279	\| X86_CPUID_FEATURE_EDX_MCA
280	\| X86_CPUID_FEATURE_EDX_CMOV
281	\| X86_CPUID_FEATURE_EDX_PAT
282	\| X86_CPUID_FEATURE_EDX_PSE36
283	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
284	\| X86_CPUID_FEATURE_EDX_CLFSH
285	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
286	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
287	\| X86_CPUID_FEATURE_EDX_MMX
288	\| X86_CPUID_FEATURE_EDX_FXSR
289	\| X86_CPUID_FEATURE_EDX_SSE
290	\| X86_CPUID_FEATURE_EDX_SSE2
291	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
292	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
293	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
294	//\| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
295	\| 0;
296	pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
297	\| X86_CPUID_FEATURE_ECX_MONITOR
298	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
299	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
300	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
301	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
302	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
303	/* ECX Bit 13 - CX16 - CMPXCHG16B. */
304	//\| X86_CPUID_FEATURE_ECX_CX16
305	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
306	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
307	/* ECX Bit 21 - x2APIC support - not yet. */
308	// \| X86_CPUID_FEATURE_ECX_X2APIC
309	/* ECX Bit 23 - POPCOUNT instruction. */
310	//\| X86_CPUID_FEATURE_ECX_POPCOUNT
311	\| 0;
312
313	/* ASSUMES that this is ALWAYS the AMD define feature set if present. */
314	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
315	\| X86_CPUID_AMD_FEATURE_EDX_VME
316	\| X86_CPUID_AMD_FEATURE_EDX_DE
317	\| X86_CPUID_AMD_FEATURE_EDX_PSE
318	\| X86_CPUID_AMD_FEATURE_EDX_TSC
319	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
320	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
321	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
322	\| X86_CPUID_AMD_FEATURE_EDX_CX8
323	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
324	/** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
325	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
326	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
327	\| X86_CPUID_AMD_FEATURE_EDX_PGE
328	\| X86_CPUID_AMD_FEATURE_EDX_MCA
329	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
330	\| X86_CPUID_AMD_FEATURE_EDX_PAT
331	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
332	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
333	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
334	\| X86_CPUID_AMD_FEATURE_EDX_MMX
335	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
336	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
337	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
338	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
339	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
340	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
341	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
342	\| 0;
343	pCPUM->aGuestCpuIdExt[1].ecx &= 0
344	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
345	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
346	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
347	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
348	//\| X86_CPUID_AMD_FEATURE_ECX_CR8L
349	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
350	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
351	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
352	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
353	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
354	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
355	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
356	\| 0;
357
358	/*
359	* Hide HTT, multicode, SMP, whatever.
360	* (APIC-ID := 0 and #LogCpus := 0)
361	*/
362	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
363
364	/* Cpuid 2:
365	* Intel: Cache and TLB information
366	* AMD: Reserved
367	* Safe to expose
368	*/
369
370	/* Cpuid 3:
371	* Intel: EAX, EBX - reserved
372	* ECX, EDX - Processor Serial Number if available, otherwise reserved
373	* AMD: Reserved
374	* Safe to expose
375	*/
376	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
377	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
378
379	/* Cpuid 4:
380	* Intel: Deterministic Cache Parameters Leaf
381	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
382	* AMD: Reserved
383	* Safe to expose, except for EAX:
384	* Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
385	* Bits 31-26: Maximum number of processor cores in this physical package**
386	*/
387	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
388	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
389
390	/* Cpuid 5: Monitor/mwait Leaf
391	* Intel: ECX, EDX - reserved
392	* EAX, EBX - Smallest and largest monitor line size
393	* AMD: EDX - reserved
394	* EAX, EBX - Smallest and largest monitor line size
395	* ECX - extensions (ignored for now)
396	* Safe to expose
397	*/
398	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
399	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
400
401	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
402
403	/*
404	* Determine the default.
405	*
406	* Intel returns values of the highest standard function, while AMD
407	* returns zeros. VIA on the other hand seems to returning nothing or
408	* perhaps some random garbage, we don't try to duplicate this behavior.
409	*/
410	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
411	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
412	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
413
414	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
415	* Safe to pass on to the guest.
416	*
417	* Intel: 0x800000005 reserved
418	* 0x800000006 L2 cache information
419	* AMD: 0x800000005 L1 cache information
420	* 0x800000006 L2/L3 cache information
421	*/
422
423	/* Cpuid 0x800000007:
424	* AMD: EAX, EBX, ECX - reserved
425	* EDX: Advanced Power Management Information
426	* Intel: Reserved
427	*/
428	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
429	{
430	Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
431
432	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
433
434	if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
435	{
436	/* Only expose the TSC invariant capability bit to the guest. */
437	pCPUM->aGuestCpuIdExt[7].edx &= 0
438	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
439	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
440	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
441	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
442	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
443	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
444	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
445	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
446	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
447	\| 0;
448	}
449	else
450	pCPUM->aGuestCpuIdExt[7].edx = 0;
451	}
452
453	/* Cpuid 0x800000008:
454	* AMD: EBX, EDX - reserved
455	* EAX: Virtual/Physical address Size
456	* ECX: Number of cores + APICIdCoreIdSize
457	* Intel: EAX: Virtual/Physical address Size
458	* EBX, ECX, EDX - reserved
459	*/
460	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
461	{
462	/* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
463	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
464	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
465	* NC (0-7) Number of cores; 0 equals 1 core */
466	pCPUM->aGuestCpuIdExt[8].ecx = 0;
467	}
468
469	/*
470	* Limit it the number of entries and fill the remaining with the defaults.
471	*
472	* The limits are masking off stuff about power saving and similar, this
473	* is perhaps a bit crudely done as there is probably some relatively harmless
474	* info too in these leaves (like words about having a constant TSC).
475	*/
476	#if 0
477	/** @todo NT4 installation regression - investigate */
478	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
479	pCPUM->aGuestCpuIdStd[0].eax = 5;
480	#else
481	if (pCPUM->aGuestCpuIdStd[0].eax > 2)
482	pCPUM->aGuestCpuIdStd[0].eax = 2;
483	#endif
484	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
485	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
486
487	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
488	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
489	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
490	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
491	: 0;
492	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
493	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
494
495	/*
496	* Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
497	* Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
498	* We currently don't support more than 1 processor.
499	*/
500	pCPUM->aGuestCpuIdStd[4].eax = 0;
501
502	/*
503	* Centaur stuff (VIA).
504	*
505	* The important part here (we think) is to make sure the 0xc0000000
506	* function returns 0xc0000001. As for the features, we don't currently
507	* let on about any of those... 0xc0000002 seems to be some
508	* temperature/hz/++ stuff, include it as well (static).
509	*/
510	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
511	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
512	{
513	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
514	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
515	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
516	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
517	i++)
518	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
519	}
520	else
521	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
522	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
523
524
525	/*
526	* Load CPUID overrides from configuration.
527	*/
528	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
529	* Overloads the CPUID leaf values. */
530	PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
531	uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
532	for (i=0;; )
533	{
534	while (cElements-- > 0)
535	{
536	PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
537	if (pNode)
538	{
539	uint32_t u32;
540	int rc = CFGMR3QueryU32(pNode, "eax", &u32);
541	if (VBOX_SUCCESS(rc))
542	pCpuId->eax = u32;
543	else
544	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
545
546	rc = CFGMR3QueryU32(pNode, "ebx", &u32);
547	if (VBOX_SUCCESS(rc))
548	pCpuId->ebx = u32;
549	else
550	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
551
552	rc = CFGMR3QueryU32(pNode, "ecx", &u32);
553	if (VBOX_SUCCESS(rc))
554	pCpuId->ecx = u32;
555	else
556	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
557
558	rc = CFGMR3QueryU32(pNode, "edx", &u32);
559	if (VBOX_SUCCESS(rc))
560	pCpuId->edx = u32;
561	else
562	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
563	}
564	pCpuId++;
565	i++;
566	}
567
568	/* next */
569	if ((i & UINT32_C(0xc0000000)) == 0)
570	{
571	pCpuId = &pCPUM->aGuestCpuIdExt[0];
572	cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
573	i = UINT32_C(0x80000000);
574	}
575	else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
576	{
577	pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
578	cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
579	i = UINT32_C(0xc0000000);
580	}
581	else
582	break;
583	}
584
585	/* Check if PAE was explicitely enabled by the user. */
586	bool fEnable = false;
587	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
588	if (VBOX_SUCCESS(rc) && fEnable)
589	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
590
591	/*
592	* Log the cpuid and we're good.
593	*/
594	RTCPUSET OnlineSet;
595	LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
596	(int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
597	LogRel(("*********************** CPUID dump **********************\n"));
598	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
599	LogRel(("\n"));
600	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
601	LogRel(("****************** End of CPUID dump ********************\n"));
602	return VINF_SUCCESS;
603	}
604
605
606
607
608	/**
609	* Applies relocations to data and code managed by this
610	* component. This function will be called at init and
611	* whenever the VMM need to relocate it self inside the GC.
612	*
613	* The CPUM will update the addresses used by the switcher.
614	*
615	* @param pVM The VM.
616	*/
617	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
618	{
619	LogFlow(("CPUMR3Relocate\n"));
620	/*
621	* Switcher pointers.
622	*/
623	pVM->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
624	Assert(pVM->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
625	}
626
627
628	/**
629	* Queries the pointer to the internal CPUMCTX structure
630	*
631	* @returns VBox status code.
632	* @param pVM Handle to the virtual machine.
633	* @param ppCtx Receives the CPUMCTX GC pointer when successful.
634	*/
635	VMMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
636	{
637	LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
638	/*
639	* Store the address. (Later we might check how's calling, thus the RC.)
640	*/
641	*ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
642	return VINF_SUCCESS;
643	}
644
645
646	/**
647	* Terminates the CPUM.
648	*
649	* Termination means cleaning up and freeing all resources,
650	* the VM it self is at this point powered off or suspended.
651	*
652	* @returns VBox status code.
653	* @param pVM The VM to operate on.
654	*/
655	VMMR3DECL(int) CPUMR3Term(PVM pVM)
656	{
657	/** @todo ? */
658	return 0;
659	}
660
661
662	/**
663	* Terminates the per-VCPU CPUM.
664	*
665	* Termination means cleaning up and freeing all resources,
666	* the VM it self is at this point powered off or suspended.
667	*
668	* @returns VBox status code.
669	* @param pVM The VM to operate on.
670	*/
671	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
672	{
673	return 0;
674	}
675
676
677	/**
678	* Resets the CPU.
679	*
680	* @returns VINF_SUCCESS.
681	* @param pVM The VM handle.
682	*/
683	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
684	{
685	PCPUMCTX pCtx = &pVM->cpum.s.Guest;
686
687	/*
688	* Initialize everything to ZERO first.
689	*/
690	uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
691	memset(pCtx, 0, sizeof(*pCtx));
692	pVM->cpum.s.fUseFlags = fUseFlags;
693
694	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
695	pCtx->eip = 0x0000fff0;
696	pCtx->edx = 0x00000600; /* P6 processor */
697	pCtx->eflags.Bits.u1Reserved0 = 1;
698
699	pCtx->cs = 0xf000;
700	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
701	pCtx->csHid.u32Limit = 0x0000ffff;
702	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
703	pCtx->csHid.Attr.n.u1Present = 1;
704	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
705
706	pCtx->dsHid.u32Limit = 0x0000ffff;
707	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
708	pCtx->dsHid.Attr.n.u1Present = 1;
709	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
710
711	pCtx->esHid.u32Limit = 0x0000ffff;
712	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
713	pCtx->esHid.Attr.n.u1Present = 1;
714	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
715
716	pCtx->fsHid.u32Limit = 0x0000ffff;
717	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
718	pCtx->fsHid.Attr.n.u1Present = 1;
719	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
720
721	pCtx->gsHid.u32Limit = 0x0000ffff;
722	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
723	pCtx->gsHid.Attr.n.u1Present = 1;
724	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
725
726	pCtx->ssHid.u32Limit = 0x0000ffff;
727	pCtx->ssHid.Attr.n.u1Present = 1;
728	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
729	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
730
731	pCtx->idtr.cbIdt = 0xffff;
732	pCtx->gdtr.cbGdt = 0xffff;
733
734	pCtx->ldtrHid.u32Limit = 0xffff;
735	pCtx->ldtrHid.Attr.n.u1Present = 1;
736	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
737
738	pCtx->trHid.u32Limit = 0xffff;
739	pCtx->trHid.Attr.n.u1Present = 1;
740	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
741
742	pCtx->dr[6] = X86_DR6_INIT_VAL;
743	pCtx->dr[7] = X86_DR7_INIT_VAL;
744
745	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
746	pCtx->fpu.FCW = 0x37f;
747
748	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
749	pCtx->fpu.MXCSR = 0x1F80;
750
751	/* Init PAT MSR */
752	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
753
754	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
755	* The Intel docs don't mention it.
756	*/
757	pCtx->msrEFER = 0;
758	}
759
760
761	/**
762	* Execute state save operation.
763	*
764	* @returns VBox status code.
765	* @param pVM VM Handle.
766	* @param pSSM SSM operation handle.
767	*/
768	static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
769	{
770	/* Set the size of RTGCPTR for use of SSMR3Get/PutGCPtr. */
771	SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
772
773	/*
774	* Save.
775	*/
776	SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
777	SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
778	SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
779	SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
780
781	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
782	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
783
784	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
785	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
786
787	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
788	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
789
790	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
791
792	/* Add the cpuid for checking that the cpu is unchanged. */
793	uint32_t au32CpuId[8] = {0};
794	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
795	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
796	return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
797	}
798
799
800	/**
801	* Load a version 1.6 CPUMCTX structure.
802	*
803	* @returns VBox status code.
804	* @param pVM VM Handle.
805	* @param pCpumctx16 Version 1.6 CPUMCTX
806	*/
807	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
808	{
809	#define CPUMCTX16_LOADREG(RegName) \
810	pVM->cpum.s.Guest.RegName = pCpumctx16->RegName;
811
812	#define CPUMCTX16_LOADDRXREG(RegName) \
813	pVM->cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
814
815	#define CPUMCTX16_LOADHIDREG(RegName) \
816	pVM->cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
817	pVM->cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
818	pVM->cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
819
820	#define CPUMCTX16_LOADSEGREG(RegName) \
821	pVM->cpum.s.Guest.RegName = pCpumctx16->RegName; \
822	CPUMCTX16_LOADHIDREG(RegName);
823
824	pVM->cpum.s.Guest.fpu = pCpumctx16->fpu;
825
826	CPUMCTX16_LOADREG(rax);
827	CPUMCTX16_LOADREG(rbx);
828	CPUMCTX16_LOADREG(rcx);
829	CPUMCTX16_LOADREG(rdx);
830	CPUMCTX16_LOADREG(rdi);
831	CPUMCTX16_LOADREG(rsi);
832	CPUMCTX16_LOADREG(rbp);
833	CPUMCTX16_LOADREG(esp);
834	CPUMCTX16_LOADREG(rip);
835	CPUMCTX16_LOADREG(rflags);
836
837	CPUMCTX16_LOADSEGREG(cs);
838	CPUMCTX16_LOADSEGREG(ds);
839	CPUMCTX16_LOADSEGREG(es);
840	CPUMCTX16_LOADSEGREG(fs);
841	CPUMCTX16_LOADSEGREG(gs);
842	CPUMCTX16_LOADSEGREG(ss);
843
844	CPUMCTX16_LOADREG(r8);
845	CPUMCTX16_LOADREG(r9);
846	CPUMCTX16_LOADREG(r10);
847	CPUMCTX16_LOADREG(r11);
848	CPUMCTX16_LOADREG(r12);
849	CPUMCTX16_LOADREG(r13);
850	CPUMCTX16_LOADREG(r14);
851	CPUMCTX16_LOADREG(r15);
852
853	CPUMCTX16_LOADREG(cr0);
854	CPUMCTX16_LOADREG(cr2);
855	CPUMCTX16_LOADREG(cr3);
856	CPUMCTX16_LOADREG(cr4);
857
858	CPUMCTX16_LOADDRXREG(0);
859	CPUMCTX16_LOADDRXREG(1);
860	CPUMCTX16_LOADDRXREG(2);
861	CPUMCTX16_LOADDRXREG(3);
862	CPUMCTX16_LOADDRXREG(4);
863	CPUMCTX16_LOADDRXREG(5);
864	CPUMCTX16_LOADDRXREG(6);
865	CPUMCTX16_LOADDRXREG(7);
866
867	pVM->cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
868	pVM->cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
869	pVM->cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
870	pVM->cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
871
872	CPUMCTX16_LOADREG(ldtr);
873	CPUMCTX16_LOADREG(tr);
874
875	pVM->cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
876
877	CPUMCTX16_LOADREG(msrEFER);
878	CPUMCTX16_LOADREG(msrSTAR);
879	CPUMCTX16_LOADREG(msrPAT);
880	CPUMCTX16_LOADREG(msrLSTAR);
881	CPUMCTX16_LOADREG(msrCSTAR);
882	CPUMCTX16_LOADREG(msrSFMASK);
883	CPUMCTX16_LOADREG(msrKERNELGSBASE);
884
885	CPUMCTX16_LOADHIDREG(ldtr);
886	CPUMCTX16_LOADHIDREG(tr);
887
888	#undef CPUMCTX16_LOADSEGREG
889	#undef CPUMCTX16_LOADHIDREG
890	#undef CPUMCTX16_LOADDRXREG
891	#undef CPUMCTX16_LOADREG
892	}
893
894
895	/**
896	* Execute state load operation.
897	*
898	* @returns VBox status code.
899	* @param pVM VM Handle.
900	* @param pSSM SSM operation handle.
901	* @param u32Version Data layout version.
902	*/
903	static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
904	{
905	/*
906	* Validate version.
907	*/
908	if ( u32Version != CPUM_SAVED_STATE_VERSION
909	&& u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
910	{
911	AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
912	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
913	}
914
915	/* Set the size of RTGCPTR for SSMR3GetGCPtr. */
916	if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
917	SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
918	else
919	SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
920
921	/*
922	* Restore.
923	*/
924	uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
925	uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
926	SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
927	pVM->cpum.s.Hyper.cr3 = uCR3;
928	pVM->cpum.s.Hyper.esp = uESP;
929	if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
930	{
931	CPUMCTX_VER1_6 cpumctx16;
932	memset(&pVM->cpum.s.Guest, 0, sizeof(pVM->cpum.s.Guest));
933	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
934
935	/* Save the old cpumctx state into the new one. */
936	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
937	}
938	else
939	SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
940
941	SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
942	SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
943
944	uint32_t cElements;
945	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
946	/* Support old saved states with a smaller standard cpuid array. */
947	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
948	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
949	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
950
951	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
952	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
953	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
954	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
955
956	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
957	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
958	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
959	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
960
961	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
962
963	/*
964	* Check that the basic cpuid id information is unchanged.
965	*/
966	uint32_t au32CpuId[8] = {0};
967	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
968	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
969	uint32_t au32CpuIdSaved[8];
970	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
971	if (VBOX_SUCCESS(rc))
972	{
973	/* Ignore APIC ID (AMD specs). */
974	au32CpuId[5] &= ~0xff000000;
975	au32CpuIdSaved[5] &= ~0xff000000;
976	/* Ignore the number of Logical CPUs (AMD specs). */
977	au32CpuId[5] &= ~0x00ff0000;
978	au32CpuIdSaved[5] &= ~0x00ff0000;
979
980	/* do the compare */
981	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
982	{
983	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
984	LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
985	"Saved=%.*Vhxs\n"
986	"Real =%.*Vhxs\n",
987	sizeof(au32CpuIdSaved), au32CpuIdSaved,
988	sizeof(au32CpuId), au32CpuId));
989	else
990	{
991	LogRel(("cpumR3Load: CpuId mismatch!\n"
992	"Saved=%.*Vhxs\n"
993	"Real =%.*Vhxs\n",
994	sizeof(au32CpuIdSaved), au32CpuIdSaved,
995	sizeof(au32CpuId), au32CpuId));
996	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
997	}
998	}
999	}
1000
1001	return rc;
1002	}
1003
1004
1005	/**
1006	* Formats the EFLAGS value into mnemonics.
1007	*
1008	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1009	* @param efl The EFLAGS value.
1010	*/
1011	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1012	{
1013	/*
1014	* Format the flags.
1015	*/
1016	static const struct
1017	{
1018	const char pszSet; const char pszClear; uint32_t fFlag;
1019	} s_aFlags[] =
1020	{
1021	{ "vip",NULL, X86_EFL_VIP },
1022	{ "vif",NULL, X86_EFL_VIF },
1023	{ "ac", NULL, X86_EFL_AC },
1024	{ "vm", NULL, X86_EFL_VM },
1025	{ "rf", NULL, X86_EFL_RF },
1026	{ "nt", NULL, X86_EFL_NT },
1027	{ "ov", "nv", X86_EFL_OF },
1028	{ "dn", "up", X86_EFL_DF },
1029	{ "ei", "di", X86_EFL_IF },
1030	{ "tf", NULL, X86_EFL_TF },
1031	{ "nt", "pl", X86_EFL_SF },
1032	{ "nz", "zr", X86_EFL_ZF },
1033	{ "ac", "na", X86_EFL_AF },
1034	{ "po", "pe", X86_EFL_PF },
1035	{ "cy", "nc", X86_EFL_CF },
1036	};
1037	char *psz = pszEFlags;
1038	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1039	{
1040	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1041	if (pszAdd)
1042	{
1043	strcpy(psz, pszAdd);
1044	psz += strlen(pszAdd);
1045	*psz++ = ' ';
1046	}
1047	}
1048	psz[-1] = '\0';
1049	}
1050
1051
1052	/**
1053	* Formats a full register dump.
1054	*
1055	* @param pVM VM Handle.
1056	* @param pCtx The context to format.
1057	* @param pCtxCore The context core to format.
1058	* @param pHlp Output functions.
1059	* @param enmType The dump type.
1060	* @param pszPrefix Register name prefix.
1061	*/
1062	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1063	{
1064	/*
1065	* Format the EFLAGS.
1066	*/
1067	uint32_t efl = pCtxCore->eflags.u32;
1068	char szEFlags[80];
1069	cpumR3InfoFormatFlags(&szEFlags[0], efl);
1070
1071	/*
1072	* Format the registers.
1073	*/
1074	switch (enmType)
1075	{
1076	case CPUMDUMPTYPE_TERSE:
1077	if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1078	pHlp->pfnPrintf(pHlp,
1079	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1080	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1081	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1082	"%sr14=%016RX64 %sr15=%016RX64\n"
1083	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1084	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1085	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1086	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1087	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1088	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1089	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1090	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1091	else
1092	pHlp->pfnPrintf(pHlp,
1093	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1094	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1095	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1096	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1097	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1098	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1099	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1100	break;
1101
1102	case CPUMDUMPTYPE_DEFAULT:
1103	if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1104	pHlp->pfnPrintf(pHlp,
1105	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1106	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1107	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1108	"%sr14=%016RX64 %sr15=%016RX64\n"
1109	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1110	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1111	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
1112	,
1113	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1114	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1115	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1116	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1117	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1118	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1119	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1120	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1121	else
1122	pHlp->pfnPrintf(pHlp,
1123	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1124	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1125	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1126	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1127	,
1128	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1129	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1130	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1131	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1132	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1133	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1134	break;
1135
1136	case CPUMDUMPTYPE_VERBOSE:
1137	if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1138	pHlp->pfnPrintf(pHlp,
1139	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1140	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1141	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1142	"%sr14=%016RX64 %sr15=%016RX64\n"
1143	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1144	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1145	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1146	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1147	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1148	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1149	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1150	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1151	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1152	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1153	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1154	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1155	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1156	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1157	,
1158	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1159	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1160	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1161	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1162	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1163	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1164	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1165	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1166	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1167	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1168	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1169	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1170	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1171	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1172	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1173	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1174	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1175	else
1176	pHlp->pfnPrintf(pHlp,
1177	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1178	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1179	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1180	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1181	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1182	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1183	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1184	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1185	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1186	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1187	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1188	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1189	,
1190	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1191	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1192	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1193	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1194	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1195	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1196	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1197	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1198	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1199	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1200	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1201	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1202
1203	pHlp->pfnPrintf(pHlp,
1204	"FPU:\n"
1205	"%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1206	"%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1207	"%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1208	,
1209	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1210	pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1211	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1212	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1213
1214	pHlp->pfnPrintf(pHlp,
1215	"MSR:\n"
1216	"%sEFER =%016RX64\n"
1217	"%sPAT =%016RX64\n"
1218	"%sSTAR =%016RX64\n"
1219	"%sCSTAR =%016RX64\n"
1220	"%sLSTAR =%016RX64\n"
1221	"%sSFMASK =%016RX64\n"
1222	"%sKERNELGSBASE =%016RX64\n",
1223	pszPrefix, pCtx->msrEFER,
1224	pszPrefix, pCtx->msrPAT,
1225	pszPrefix, pCtx->msrSTAR,
1226	pszPrefix, pCtx->msrCSTAR,
1227	pszPrefix, pCtx->msrLSTAR,
1228	pszPrefix, pCtx->msrSFMASK,
1229	pszPrefix, pCtx->msrKERNELGSBASE);
1230	break;
1231	}
1232	}
1233
1234
1235	/**
1236	* Display all cpu states and any other cpum info.
1237	*
1238	* @param pVM VM Handle.
1239	* @param pHlp The info helper functions.
1240	* @param pszArgs Arguments, ignored.
1241	*/
1242	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1243	{
1244	cpumR3InfoGuest(pVM, pHlp, pszArgs);
1245	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1246	cpumR3InfoHyper(pVM, pHlp, pszArgs);
1247	cpumR3InfoHost(pVM, pHlp, pszArgs);
1248	}
1249
1250
1251	/**
1252	* Parses the info argument.
1253	*
1254	* The argument starts with 'verbose', 'terse' or 'default' and then
1255	* continues with the comment string.
1256	*
1257	* @param pszArgs The pointer to the argument string.
1258	* @param penmType Where to store the dump type request.
1259	* @param ppszComment Where to store the pointer to the comment string.
1260	*/
1261	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
1262	{
1263	if (!pszArgs)
1264	{
1265	*penmType = CPUMDUMPTYPE_DEFAULT;
1266	*ppszComment = "";
1267	}
1268	else
1269	{
1270	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1271	{
1272	pszArgs += 5;
1273	*penmType = CPUMDUMPTYPE_VERBOSE;
1274	}
1275	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1276	{
1277	pszArgs += 5;
1278	*penmType = CPUMDUMPTYPE_TERSE;
1279	}
1280	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1281	{
1282	pszArgs += 7;
1283	*penmType = CPUMDUMPTYPE_DEFAULT;
1284	}
1285	else
1286	*penmType = CPUMDUMPTYPE_DEFAULT;
1287	*ppszComment = RTStrStripL(pszArgs);
1288	}
1289	}
1290
1291
1292	/**
1293	* Display the guest cpu state.
1294	*
1295	* @param pVM VM Handle.
1296	* @param pHlp The info helper functions.
1297	* @param pszArgs Arguments, ignored.
1298	*/
1299	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1300	{
1301	CPUMDUMPTYPE enmType;
1302	const char *pszComment;
1303	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1304	pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1305	cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
1306	}
1307
1308
1309	/**
1310	* Display the current guest instruction
1311	*
1312	* @param pVM VM Handle.
1313	* @param pHlp The info helper functions.
1314	* @param pszArgs Arguments, ignored.
1315	*/
1316	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1317	{
1318	char szInstruction[256];
1319	int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1320	if (VBOX_SUCCESS(rc))
1321	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1322	}
1323
1324
1325	/**
1326	* Display the hypervisor cpu state.
1327	*
1328	* @param pVM VM Handle.
1329	* @param pHlp The info helper functions.
1330	* @param pszArgs Arguments, ignored.
1331	*/
1332	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1333	{
1334	CPUMDUMPTYPE enmType;
1335	const char *pszComment;
1336	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1337	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1338	cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1339	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1340	}
1341
1342
1343	/**
1344	* Display the host cpu state.
1345	*
1346	* @param pVM VM Handle.
1347	* @param pHlp The info helper functions.
1348	* @param pszArgs Arguments, ignored.
1349	*/
1350	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1351	{
1352	CPUMDUMPTYPE enmType;
1353	const char *pszComment;
1354	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1355	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1356
1357	/*
1358	* Format the EFLAGS.
1359	*/
1360	PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
1361	#if HC_ARCH_BITS == 32
1362	uint32_t efl = pCtx->eflags.u32;
1363	#else
1364	uint64_t efl = pCtx->rflags;
1365	#endif
1366	char szEFlags[80];
1367	cpumR3InfoFormatFlags(&szEFlags[0], efl);
1368
1369	/*
1370	* Format the registers.
1371	*/
1372	#if HC_ARCH_BITS == 32
1373	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1374	if (!(pCtx->efer & MSR_K6_EFER_LMA))
1375	# endif
1376	{
1377	pHlp->pfnPrintf(pHlp,
1378	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1379	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1380	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1381	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1382	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1383	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1384	,
1385	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
1386	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1387	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1388	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
1389	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1390	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1391	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1392	}
1393	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1394	else
1395	# endif
1396	#endif
1397	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1398	{
1399	pHlp->pfnPrintf(pHlp,
1400	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1401	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1402	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1403	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1404	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1405	"r14=%016RX64 r15=%016RX64\n"
1406	"iopl=%d %31s\n"
1407	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1408	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1409	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
1410	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1411	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1412	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1413	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1414	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1415	,
1416	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
1417	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1418	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
1419	/pCtx->r8, pCtx->r9,/ pCtx->r10,
1420	pCtx->r11, pCtx->r12, pCtx->r13,
1421	pCtx->r14, pCtx->r15,
1422	X86_EFL_GET_IOPL(efl), szEFlags,
1423	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1424	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
1425	pCtx->cr4, pCtx->ldtr, pCtx->tr,
1426	pCtx->dr0, pCtx->dr1, pCtx->dr2,
1427	pCtx->dr3, pCtx->dr6, pCtx->dr7,
1428	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1429	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1430	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1431	}
1432	#endif
1433	}
1434
1435
1436	/**
1437	* Get L1 cache / TLS associativity.
1438	*/
1439	static const char getCacheAss(unsigned u, char pszBuf)
1440	{
1441	if (u == 0)
1442	return "res0 ";
1443	if (u == 1)
1444	return "direct";
1445	if (u >= 256)
1446	return "???";
1447
1448	RTStrPrintf(pszBuf, 16, "%d way", u);
1449	return pszBuf;
1450	}
1451
1452
1453	/**
1454	* Get L2 cache soociativity.
1455	*/
1456	const char *getL2CacheAss(unsigned u)
1457	{
1458	switch (u)
1459	{
1460	case 0: return "off ";
1461	case 1: return "direct";
1462	case 2: return "2 way ";
1463	case 3: return "res3 ";
1464	case 4: return "4 way ";
1465	case 5: return "res5 ";
1466	case 6: return "8 way "; case 7: return "res7 ";
1467	case 8: return "16 way";
1468	case 9: return "res9 ";
1469	case 10: return "res10 ";
1470	case 11: return "res11 ";
1471	case 12: return "res12 ";
1472	case 13: return "res13 ";
1473	case 14: return "res14 ";
1474	case 15: return "fully ";
1475	default:
1476	return "????";
1477	}
1478	}
1479
1480
1481	/**
1482	* Display the guest CpuId leaves.
1483	*
1484	* @param pVM VM Handle.
1485	* @param pHlp The info helper functions.
1486	* @param pszArgs "terse", "default" or "verbose".
1487	*/
1488	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1489	{
1490	/*
1491	* Parse the argument.
1492	*/
1493	unsigned iVerbosity = 1;
1494	if (pszArgs)
1495	{
1496	pszArgs = RTStrStripL(pszArgs);
1497	if (!strcmp(pszArgs, "terse"))
1498	iVerbosity--;
1499	else if (!strcmp(pszArgs, "verbose"))
1500	iVerbosity++;
1501	}
1502
1503	/*
1504	* Start cracking.
1505	*/
1506	CPUMCPUID Host;
1507	CPUMCPUID Guest;
1508	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1509
1510	pHlp->pfnPrintf(pHlp,
1511	" RAW Standard CPUIDs\n"
1512	" Function eax ebx ecx edx\n");
1513	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1514	{
1515	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1516	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1517
1518	pHlp->pfnPrintf(pHlp,
1519	"Gst: %08x %08x %08x %08x %08x%s\n"
1520	"Hst: %08x %08x %08x %08x\n",
1521	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1522	i <= cStdMax ? "" : "*",
1523	Host.eax, Host.ebx, Host.ecx, Host.edx);
1524	}
1525
1526	/*
1527	* If verbose, decode it.
1528	*/
1529	if (iVerbosity)
1530	{
1531	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1532	pHlp->pfnPrintf(pHlp,
1533	"Name: %.04s%.04s%.04s\n"
1534	"Supports: 0-%x\n",
1535	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1536	}
1537
1538	/*
1539	* Get Features.
1540	*/
1541	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1542	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1543	pVM->cpum.s.aGuestCpuIdStd[0].edx);
1544	if (cStdMax >= 1 && iVerbosity)
1545	{
1546	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1547	uint32_t uEAX = Guest.eax;
1548
1549	pHlp->pfnPrintf(pHlp,
1550	"Family: %d \tExtended: %d \tEffective: %d\n"
1551	"Model: %d \tExtended: %d \tEffective: %d\n"
1552	"Stepping: %d\n"
1553	"APIC ID: %#04x\n"
1554	"Logical CPUs: %d\n"
1555	"CLFLUSH Size: %d\n"
1556	"Brand ID: %#04x\n",
1557	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1558	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1559	ASMGetCpuStepping(uEAX),
1560	(Guest.ebx >> 24) & 0xff,
1561	(Guest.ebx >> 16) & 0xff,
1562	(Guest.ebx >> 8) & 0xff,
1563	(Guest.ebx >> 0) & 0xff);
1564	if (iVerbosity == 1)
1565	{
1566	uint32_t uEDX = Guest.edx;
1567	pHlp->pfnPrintf(pHlp, "Features EDX: ");
1568	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1569	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1570	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1571	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1572	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1573	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1574	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1575	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1576	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1577	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1578	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1579	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1580	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1581	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1582	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1583	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1584	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1585	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1586	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1587	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1588	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1589	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1590	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1591	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1592	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1593	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1594	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1595	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1596	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1597	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1598	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1599	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1600	pHlp->pfnPrintf(pHlp, "\n");
1601
1602	uint32_t uECX = Guest.ecx;
1603	pHlp->pfnPrintf(pHlp, "Features ECX: ");
1604	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1605	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1606	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1607	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1608	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1609	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1610	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1611	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1612	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1613	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1614	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1615	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1616	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1617	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1618	for (unsigned iBit = 14; iBit < 32; iBit++)
1619	if (uECX & RT_BIT(iBit))
1620	pHlp->pfnPrintf(pHlp, " %d", iBit);
1621	pHlp->pfnPrintf(pHlp, "\n");
1622	}
1623	else
1624	{
1625	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1626
1627	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1628	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1629	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1630	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1631
1632	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1633	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1634	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1635	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1636	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1637	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1638	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1639	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1640	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1641	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1642	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1643	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1644	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1645	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1646	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1647	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1648	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1649	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1650	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1651	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1652	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1653	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1654	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1655	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1656	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1657	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1658	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1659	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1660	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1661	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1662	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1663	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1664	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1665
1666	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1667	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1668	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1669	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1670	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1671	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1672	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1673	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1674	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1675	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1676	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1677	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1678	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1679	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1680	}
1681	}
1682	if (cStdMax >= 2 && iVerbosity)
1683	{
1684	/** @todo */
1685	}
1686
1687	/*
1688	* Extended.
1689	* Implemented after AMD specs.
1690	*/
1691	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1692
1693	pHlp->pfnPrintf(pHlp,
1694	"\n"
1695	" RAW Extended CPUIDs\n"
1696	" Function eax ebx ecx edx\n");
1697	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1698	{
1699	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1700	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1701
1702	pHlp->pfnPrintf(pHlp,
1703	"Gst: %08x %08x %08x %08x %08x%s\n"
1704	"Hst: %08x %08x %08x %08x\n",
1705	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1706	i <= cExtMax ? "" : "*",
1707	Host.eax, Host.ebx, Host.ecx, Host.edx);
1708	}
1709
1710	/*
1711	* Understandable output
1712	*/
1713	if (iVerbosity)
1714	{
1715	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1716	pHlp->pfnPrintf(pHlp,
1717	"Ext Name: %.4s%.4s%.4s\n"
1718	"Ext Supports: 0x80000000-%#010x\n",
1719	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1720	}
1721
1722	if (iVerbosity && cExtMax >= 1)
1723	{
1724	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1725	uint32_t uEAX = Guest.eax;
1726	pHlp->pfnPrintf(pHlp,
1727	"Family: %d \tExtended: %d \tEffective: %d\n"
1728	"Model: %d \tExtended: %d \tEffective: %d\n"
1729	"Stepping: %d\n"
1730	"Brand ID: %#05x\n",
1731	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1732	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1733	ASMGetCpuStepping(uEAX),
1734	Guest.ebx & 0xfff);
1735
1736	if (iVerbosity == 1)
1737	{
1738	uint32_t uEDX = Guest.edx;
1739	pHlp->pfnPrintf(pHlp, "Features EDX: ");
1740	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1741	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1742	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1743	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1744	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1745	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1746	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1747	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1748	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1749	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1750	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1751	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1752	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1753	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1754	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1755	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1756	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1757	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1758	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1759	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1760	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1761	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1762	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1763	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1764	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1765	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1766	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1767	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1768	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1769	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1770	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1771	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1772	pHlp->pfnPrintf(pHlp, "\n");
1773
1774	uint32_t uECX = Guest.ecx;
1775	pHlp->pfnPrintf(pHlp, "Features ECX: ");
1776	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1777	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1778	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1779	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1780	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1781	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1782	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1783	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1784	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1785	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1786	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1787	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1788	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1789	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1790	for (unsigned iBit = 5; iBit < 32; iBit++)
1791	if (uECX & RT_BIT(iBit))
1792	pHlp->pfnPrintf(pHlp, " %d", iBit);
1793	pHlp->pfnPrintf(pHlp, "\n");
1794	}
1795	else
1796	{
1797	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1798
1799	uint32_t uEdxGst = Guest.edx;
1800	uint32_t uEdxHst = Host.edx;
1801	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1802	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1803	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1804	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1805	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1806	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1807	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1808	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1809	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1810	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1811	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1812	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1813	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1814	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1815	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1816	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1817	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1818	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1819	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1820	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1821	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1822	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1823	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1824	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1825	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1826	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1827	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1828	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1829	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1830	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1831	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1832	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1833	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1834
1835	uint32_t uEcxGst = Guest.ecx;
1836	uint32_t uEcxHst = Host.ecx;
1837	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1838	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1839	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1840	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1841	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1842	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1843	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1844	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1845	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1846	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1847	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1848	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1849	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1850	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1851	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1852	}
1853	}
1854
1855	if (iVerbosity && cExtMax >= 2)
1856	{
1857	char szString[443+1] = {0};
1858	uint32_t pu32 = (uint32_t )szString;
1859	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1860	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1861	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1862	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1863	if (cExtMax >= 3)
1864	{
1865	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1866	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1867	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1868	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1869	}
1870	if (cExtMax >= 4)
1871	{
1872	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1873	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1874	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1875	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1876	}
1877	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1878	}
1879
1880	if (iVerbosity && cExtMax >= 5)
1881	{
1882	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1883	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1884	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1885	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1886	char sz1[32];
1887	char sz2[32];
1888
1889	pHlp->pfnPrintf(pHlp,
1890	"TLB 2/4M Instr/Uni: %s %3d entries\n"
1891	"TLB 2/4M Data: %s %3d entries\n",
1892	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1893	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1894	pHlp->pfnPrintf(pHlp,
1895	"TLB 4K Instr/Uni: %s %3d entries\n"
1896	"TLB 4K Data: %s %3d entries\n",
1897	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1898	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1899	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1900	"L1 Instr Cache Lines Per Tag: %d\n"
1901	"L1 Instr Cache Associativity: %s\n"
1902	"L1 Instr Cache Size: %d KB\n",
1903	(uEDX >> 0) & 0xff,
1904	(uEDX >> 8) & 0xff,
1905	getCacheAss((uEDX >> 16) & 0xff, sz1),
1906	(uEDX >> 24) & 0xff);
1907	pHlp->pfnPrintf(pHlp,
1908	"L1 Data Cache Line Size: %d bytes\n"
1909	"L1 Data Cache Lines Per Tag: %d\n"
1910	"L1 Data Cache Associativity: %s\n"
1911	"L1 Data Cache Size: %d KB\n",
1912	(uECX >> 0) & 0xff,
1913	(uECX >> 8) & 0xff,
1914	getCacheAss((uECX >> 16) & 0xff, sz1),
1915	(uECX >> 24) & 0xff);
1916	}
1917
1918	if (iVerbosity && cExtMax >= 6)
1919	{
1920	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1921	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1922	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1923
1924	pHlp->pfnPrintf(pHlp,
1925	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1926	"L2 TLB 2/4M Data: %s %4d entries\n",
1927	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1928	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1929	pHlp->pfnPrintf(pHlp,
1930	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
1931	"L2 TLB 4K Data: %s %4d entries\n",
1932	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1933	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1934	pHlp->pfnPrintf(pHlp,
1935	"L2 Cache Line Size: %d bytes\n"
1936	"L2 Cache Lines Per Tag: %d\n"
1937	"L2 Cache Associativity: %s\n"
1938	"L2 Cache Size: %d KB\n",
1939	(uEDX >> 0) & 0xff,
1940	(uEDX >> 8) & 0xf,
1941	getL2CacheAss((uEDX >> 12) & 0xf),
1942	(uEDX >> 16) & 0xffff);
1943	}
1944
1945	if (iVerbosity && cExtMax >= 7)
1946	{
1947	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1948
1949	pHlp->pfnPrintf(pHlp, "APM Features: ");
1950	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1951	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1952	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1953	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1954	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1955	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1956	for (unsigned iBit = 6; iBit < 32; iBit++)
1957	if (uEDX & RT_BIT(iBit))
1958	pHlp->pfnPrintf(pHlp, " %d", iBit);
1959	pHlp->pfnPrintf(pHlp, "\n");
1960	}
1961
1962	if (iVerbosity && cExtMax >= 8)
1963	{
1964	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1965	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1966
1967	pHlp->pfnPrintf(pHlp,
1968	"Physical Address Width: %d bits\n"
1969	"Virtual Address Width: %d bits\n",
1970	(uEAX >> 0) & 0xff,
1971	(uEAX >> 8) & 0xff);
1972	pHlp->pfnPrintf(pHlp,
1973	"Physical Core Count: %d\n",
1974	(uECX >> 0) & 0xff);
1975	}
1976
1977
1978	/*
1979	* Centaur.
1980	*/
1981	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1982
1983	pHlp->pfnPrintf(pHlp,
1984	"\n"
1985	" RAW Centaur CPUIDs\n"
1986	" Function eax ebx ecx edx\n");
1987	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1988	{
1989	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1990	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1991
1992	pHlp->pfnPrintf(pHlp,
1993	"Gst: %08x %08x %08x %08x %08x%s\n"
1994	"Hst: %08x %08x %08x %08x\n",
1995	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1996	i <= cCentaurMax ? "" : "*",
1997	Host.eax, Host.ebx, Host.ecx, Host.edx);
1998	}
1999
2000	/*
2001	* Understandable output
2002	*/
2003	if (iVerbosity)
2004	{
2005	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2006	pHlp->pfnPrintf(pHlp,
2007	"Centaur Supports: 0xc0000000-%#010x\n",
2008	Guest.eax);
2009	}
2010
2011	if (iVerbosity && cCentaurMax >= 1)
2012	{
2013	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2014	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2015	uint32_t uEdxHst = Host.edx;
2016
2017	if (iVerbosity == 1)
2018	{
2019	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2020	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2021	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2022	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2023	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2024	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2025	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2026	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2027	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2028	/* possibly indicating MM/HE and MM/HE-E on older chips... */
2029	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2030	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2031	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2032	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2033	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2034	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2035	for (unsigned iBit = 14; iBit < 32; iBit++)
2036	if (uEdxGst & RT_BIT(iBit))
2037	pHlp->pfnPrintf(pHlp, " %d", iBit);
2038	pHlp->pfnPrintf(pHlp, "\n");
2039	}
2040	else
2041	{
2042	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2043	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2044	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2045	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2046	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2047	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2048	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2049	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2050	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2051	/* possibly indicating MM/HE and MM/HE-E on older chips... */
2052	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2053	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2054	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2055	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2056	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2057	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2058	for (unsigned iBit = 14; iBit < 32; iBit++)
2059	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
2060	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2061	pHlp->pfnPrintf(pHlp, "\n");
2062	}
2063	}
2064	}
2065
2066
2067	/**
2068	* Structure used when disassembling and instructions in DBGF.
2069	* This is used so the reader function can get the stuff it needs.
2070	*/
2071	typedef struct CPUMDISASSTATE
2072	{
2073	/** Pointer to the CPU structure. */
2074	PDISCPUSTATE pCpu;
2075	/** The VM handle. */
2076	PVM pVM;
2077	/** Pointer to the first byte in the segemnt. */
2078	RTGCUINTPTR GCPtrSegBase;
2079	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
2080	RTGCUINTPTR GCPtrSegEnd;
2081	/** The size of the segment minus 1. */
2082	RTGCUINTPTR cbSegLimit;
2083	/** Pointer to the current page - HC Ptr. */
2084	void const *pvPageHC;
2085	/** Pointer to the current page - GC Ptr. */
2086	RTGCPTR pvPageGC;
2087	/** The lock information that PGMPhysReleasePageMappingLock needs. */
2088	PGMPAGEMAPLOCK PageMapLock;
2089	/** Whether the PageMapLock is valid or not. */
2090	bool fLocked;
2091	/** 64 bits mode or not. */
2092	bool f64Bits;
2093	} CPUMDISASSTATE, *PCPUMDISASSTATE;
2094
2095
2096	/**
2097	* Instruction reader.
2098	*
2099	* @returns VBox status code.
2100	* @param PtrSrc Address to read from.
2101	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2102	* @param pu8Dst Where to store the bytes.
2103	* @param cbRead Number of bytes to read.
2104	* @param uDisCpu Pointer to the disassembler cpu state.
2105	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
2106	*/
2107	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
2108	{
2109	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2110	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2111	Assert(cbRead > 0);
2112	for (;;)
2113	{
2114	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2115
2116	/* Need to update the page translation? */
2117	if ( !pState->pvPageHC
2118	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2119	{
2120	int rc = VINF_SUCCESS;
2121
2122	/* translate the address */
2123	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2124	if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2125	{
2126	pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
2127	if (!pState->pvPageHC)
2128	rc = VERR_INVALID_POINTER;
2129	}
2130	else
2131	{
2132	/* Release mapping lock previously acquired. */
2133	if (pState->fLocked)
2134	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2135	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
2136	pState->fLocked = RT_SUCCESS_NP(rc);
2137	}
2138	if (VBOX_FAILURE(rc))
2139	{
2140	pState->pvPageHC = NULL;
2141	return rc;
2142	}
2143	}
2144
2145	/* check the segemnt limit */
2146	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2147	return VERR_OUT_OF_SELECTOR_BOUNDS;
2148
2149	/* calc how much we can read */
2150	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2151	if (!pState->f64Bits)
2152	{
2153	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2154	if (cb > cbSeg && cbSeg)
2155	cb = cbSeg;
2156	}
2157	if (cb > cbRead)
2158	cb = cbRead;
2159
2160	/* read and advance */
2161	memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
2162	cbRead -= cb;
2163	if (!cbRead)
2164	return VINF_SUCCESS;
2165	pu8Dst += cb;
2166	PtrSrc += cb;
2167	}
2168	}
2169
2170
2171	/**
2172	* Disassemble an instruction and return the information in the provided structure.
2173	*
2174	* @returns VBox status code.
2175	* @param pVM VM Handle
2176	* @param pCtx CPU context
2177	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
2178	* @param pCpu Disassembly state
2179	* @param pszPrefix String prefix for logging (debug only)
2180	*
2181	*/
2182	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2183	{
2184	CPUMDISASSTATE State;
2185	int rc;
2186
2187	const PGMMODE enmMode = PGMGetGuestMode(pVM);
2188	State.pCpu = pCpu;
2189	State.pvPageGC = 0;
2190	State.pvPageHC = NULL;
2191	State.pVM = pVM;
2192	State.fLocked = false;
2193	State.f64Bits = false;
2194
2195	/*
2196	* Get selector information.
2197	*/
2198	if ( (pCtx->cr0 & X86_CR0_PE)
2199	&& pCtx->eflags.Bits.u1VM == 0)
2200	{
2201	if (CPUMAreHiddenSelRegsValid(pVM))
2202	{
2203	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2204	State.GCPtrSegBase = pCtx->csHid.u64Base;
2205	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2206	State.cbSegLimit = pCtx->csHid.u32Limit;
2207	pCpu->mode = (State.f64Bits)
2208	? CPUMODE_64BIT
2209	: pCtx->csHid.Attr.n.u1DefBig
2210	? CPUMODE_32BIT
2211	: CPUMODE_16BIT;
2212	}
2213	else
2214	{
2215	SELMSELINFO SelInfo;
2216
2217	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2218	if (!VBOX_SUCCESS(rc))
2219	{
2220	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2221	return rc;
2222	}
2223
2224	/*
2225	* Validate the selector.
2226	*/
2227	rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2228	if (!VBOX_SUCCESS(rc))
2229	{
2230	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2231	return rc;
2232	}
2233	State.GCPtrSegBase = SelInfo.GCPtrBase;
2234	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2235	State.cbSegLimit = SelInfo.cbLimit;
2236	pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2237	}
2238	}
2239	else
2240	{
2241	/* real or V86 mode */
2242	pCpu->mode = CPUMODE_16BIT;
2243	State.GCPtrSegBase = pCtx->cs * 16;
2244	State.GCPtrSegEnd = 0xFFFFFFFF;
2245	State.cbSegLimit = 0xFFFFFFFF;
2246	}
2247
2248	/*
2249	* Disassemble the instruction.
2250	*/
2251	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2252	pCpu->apvUserData[0] = &State;
2253
2254	uint32_t cbInstr;
2255	#ifndef LOG_ENABLED
2256	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2257	if (VBOX_SUCCESS(rc))
2258	{
2259	#else
2260	char szOutput[160];
2261	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2262	if (VBOX_SUCCESS(rc))
2263	{
2264	/* log it */
2265	if (pszPrefix)
2266	Log(("%s: %s", pszPrefix, szOutput));
2267	else
2268	Log(("%s", szOutput));
2269	#endif
2270	rc = VINF_SUCCESS;
2271	}
2272	else
2273	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
2274
2275	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
2276	if (State.fLocked)
2277	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2278
2279	return rc;
2280	}
2281
2282	#ifdef DEBUG
2283
2284	/**
2285	* Disassemble an instruction and dump it to the log
2286	*
2287	* @returns VBox status code.
2288	* @param pVM VM Handle
2289	* @param pCtx CPU context
2290	* @param pc GC instruction pointer
2291	* @param pszPrefix String prefix for logging
2292	*
2293	* @deprecated Use DBGFR3DisasInstrCurrentLog().
2294	*/
2295	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2296	{
2297	DISCPUSTATE Cpu;
2298	CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &Cpu, pszPrefix);
2299	}
2300
2301
2302	/**
2303	* Disassemble an instruction and dump it to the log
2304	*
2305	* @returns VBox status code.
2306	* @param pVM VM Handle
2307	* @param pCtx CPU context
2308	* @param pc GC instruction pointer
2309	* @param pszPrefix String prefix for logging
2310	* @param nrInstructions
2311	*
2312	* @deprecated Create new DBGFR3Disas function to do this.
2313	*/
2314	VMMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix, int nrInstructions)
2315	{
2316	for (int i = 0; i < nrInstructions; i++)
2317	{
2318	DISCPUSTATE cpu;
2319
2320	CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, pszPrefix);
2321	pc += cpu.opsize;
2322	}
2323	}
2324
2325
2326	/**
2327	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
2328	*
2329	* @internal
2330	*/
2331	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2332	{
2333	pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
2334	}
2335
2336	#endif /* DEBUG */
2337
2338	/**
2339	* API for controlling a few of the CPU features found in CR4.
2340	*
2341	* Currently only X86_CR4_TSD is accepted as input.
2342	*
2343	* @returns VBox status code.
2344	*
2345	* @param pVM The VM handle.
2346	* @param fOr The CR4 OR mask.
2347	* @param fAnd The CR4 AND mask.
2348	*/
2349	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2350	{
2351	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2352	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2353
2354	pVM->cpum.s.CR4.OrMask &= fAnd;
2355	pVM->cpum.s.CR4.OrMask \|= fOr;
2356
2357	return VINF_SUCCESS;
2358	}
2359

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 13796

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