VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 13883

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1/* $Id: CPUM.cpp 13840 2008-11-05 03:31:46Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 8
71/** The saved state version of 1.6, used for backwards compatability. */
72#define CPUM_SAVED_STATE_VERSION_VER1_6 6
73
74
75/*******************************************************************************
76* Structures and Typedefs *
77*******************************************************************************/
78
79/**
80 * What kind of cpu info dump to perform.
81 */
82typedef enum CPUMDUMPTYPE
83{
84 CPUMDUMPTYPE_TERSE,
85 CPUMDUMPTYPE_DEFAULT,
86 CPUMDUMPTYPE_VERBOSE
87
88} CPUMDUMPTYPE;
89/** Pointer to a cpu info dump type. */
90typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
91
92
93/*******************************************************************************
94* Internal Functions *
95*******************************************************************************/
96static int cpumR3CpuIdInit(PVM pVM);
97static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
98static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
99static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
100static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105
106
107/**
108 * Initializes the CPUM.
109 *
110 * @returns VBox status code.
111 * @param pVM The VM to operate on.
112 */
113VMMR3DECL(int) CPUMR3Init(PVM pVM)
114{
115 LogFlow(("CPUMR3Init\n"));
116
117 /*
118 * Assert alignment and sizes.
119 */
120 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
121 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
122
123 /*
124 * Setup any fixed pointers and offsets.
125 */
126 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
127 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
128
129 /* Hidden selector registers are invalid by default. */
130 pVM->cpum.s.fValidHiddenSelRegs = false;
131
132 /*
133 * Check that the CPU supports the minimum features we require.
134 */
135 if (!ASMHasCpuId())
136 {
137 Log(("The CPU doesn't support CPUID!\n"));
138 return VERR_UNSUPPORTED_CPU;
139 }
140 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
141 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
142
143 /* Setup the CR4 AND and OR masks used in the switcher */
144 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
145 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
146 {
147 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
148 /* No FXSAVE implies no SSE */
149 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
150 pVM->cpum.s.CR4.OrMask = 0;
151 }
152 else
153 {
154 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
155 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
156 }
157
158 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
159 {
160 Log(("The CPU doesn't support MMX!\n"));
161 return VERR_UNSUPPORTED_CPU;
162 }
163 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
164 {
165 Log(("The CPU doesn't support TSC!\n"));
166 return VERR_UNSUPPORTED_CPU;
167 }
168 /* Bogus on AMD? */
169 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
170 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
171
172 /*
173 * Setup hypervisor startup values.
174 */
175
176 /*
177 * Register saved state data item.
178 */
179 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
180 NULL, cpumR3Save, NULL,
181 NULL, cpumR3Load, NULL);
182 if (RT_FAILURE(rc))
183 return rc;
184
185 /* Query the CPU manufacturer. */
186 uint32_t uEAX, uEBX, uECX, uEDX;
187 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
188 if ( uEAX >= 1
189 && uEBX == X86_CPUID_VENDOR_AMD_EBX
190 && uECX == X86_CPUID_VENDOR_AMD_ECX
191 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
192 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
193 else if ( uEAX >= 1
194 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
195 && uECX == X86_CPUID_VENDOR_INTEL_ECX
196 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
197 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
198 else /** @todo Via */
199 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
200
201 /*
202 * Register info handlers.
203 */
204 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
205 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
206 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
207 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
208 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
209 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
210
211 /*
212 * Initialize the Guest CPU state.
213 */
214 rc = cpumR3CpuIdInit(pVM);
215 if (RT_FAILURE(rc))
216 return rc;
217 CPUMR3Reset(pVM);
218 return VINF_SUCCESS;
219}
220
221
222/**
223 * Initializes the per-VCPU CPUM.
224 *
225 * @returns VBox status code.
226 * @param pVM The VM to operate on.
227 */
228VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
229{
230 LogFlow(("CPUMR3InitCPU\n"));
231 return VINF_SUCCESS;
232}
233
234
235/**
236 * Initializes the emulated CPU's cpuid information.
237 *
238 * @returns VBox status code.
239 * @param pVM The VM to operate on.
240 */
241static int cpumR3CpuIdInit(PVM pVM)
242{
243 PCPUM pCPUM = &pVM->cpum.s;
244 uint32_t i;
245
246 /*
247 * Get the host CPUIDs.
248 */
249 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
250 ASMCpuId_Idx_ECX(i, 0,
251 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
252 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
253 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
254 ASMCpuId(0x80000000 + i,
255 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
256 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
257 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
258 ASMCpuId(0xc0000000 + i,
259 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
260 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
261
262
263 /*
264 * Only report features we can support.
265 */
266 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
267 | X86_CPUID_FEATURE_EDX_VME
268 | X86_CPUID_FEATURE_EDX_DE
269 | X86_CPUID_FEATURE_EDX_PSE
270 | X86_CPUID_FEATURE_EDX_TSC
271 | X86_CPUID_FEATURE_EDX_MSR
272 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
273 | X86_CPUID_FEATURE_EDX_MCE
274 | X86_CPUID_FEATURE_EDX_CX8
275 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
276 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
277 //| X86_CPUID_FEATURE_EDX_SEP
278 | X86_CPUID_FEATURE_EDX_MTRR
279 | X86_CPUID_FEATURE_EDX_PGE
280 | X86_CPUID_FEATURE_EDX_MCA
281 | X86_CPUID_FEATURE_EDX_CMOV
282 | X86_CPUID_FEATURE_EDX_PAT
283 | X86_CPUID_FEATURE_EDX_PSE36
284 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
285 | X86_CPUID_FEATURE_EDX_CLFSH
286 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
287 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
288 | X86_CPUID_FEATURE_EDX_MMX
289 | X86_CPUID_FEATURE_EDX_FXSR
290 | X86_CPUID_FEATURE_EDX_SSE
291 | X86_CPUID_FEATURE_EDX_SSE2
292 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
293 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
294 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
295 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
296 | 0;
297 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
298 | X86_CPUID_FEATURE_ECX_MONITOR
299 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
300 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
301 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
302 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
303 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
304 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
305 //| X86_CPUID_FEATURE_ECX_CX16
306 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
307 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
308 /* ECX Bit 21 - x2APIC support - not yet. */
309 // | X86_CPUID_FEATURE_ECX_X2APIC
310 /* ECX Bit 23 - POPCOUNT instruction. */
311 //| X86_CPUID_FEATURE_ECX_POPCOUNT
312 | 0;
313
314 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
315 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
316 | X86_CPUID_AMD_FEATURE_EDX_VME
317 | X86_CPUID_AMD_FEATURE_EDX_DE
318 | X86_CPUID_AMD_FEATURE_EDX_PSE
319 | X86_CPUID_AMD_FEATURE_EDX_TSC
320 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
321 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
322 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
323 | X86_CPUID_AMD_FEATURE_EDX_CX8
324 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
325 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
326 //| X86_CPUID_AMD_FEATURE_EDX_SEP
327 | X86_CPUID_AMD_FEATURE_EDX_MTRR
328 | X86_CPUID_AMD_FEATURE_EDX_PGE
329 | X86_CPUID_AMD_FEATURE_EDX_MCA
330 | X86_CPUID_AMD_FEATURE_EDX_CMOV
331 | X86_CPUID_AMD_FEATURE_EDX_PAT
332 | X86_CPUID_AMD_FEATURE_EDX_PSE36
333 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
334 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
335 | X86_CPUID_AMD_FEATURE_EDX_MMX
336 | X86_CPUID_AMD_FEATURE_EDX_FXSR
337 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
338 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
339 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
340 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
341 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
342 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
343 | 0;
344 pCPUM->aGuestCpuIdExt[1].ecx &= 0
345 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
346 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
347 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
348 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
349 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
350 //| X86_CPUID_AMD_FEATURE_ECX_ABM
351 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
352 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
353 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
354 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
355 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
356 //| X86_CPUID_AMD_FEATURE_ECX_WDT
357 | 0;
358
359 /*
360 * Hide HTT, multicode, SMP, whatever.
361 * (APIC-ID := 0 and #LogCpus := 0)
362 */
363 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
364
365 /* Cpuid 2:
366 * Intel: Cache and TLB information
367 * AMD: Reserved
368 * Safe to expose
369 */
370
371 /* Cpuid 3:
372 * Intel: EAX, EBX - reserved
373 * ECX, EDX - Processor Serial Number if available, otherwise reserved
374 * AMD: Reserved
375 * Safe to expose
376 */
377 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
378 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
379
380 /* Cpuid 4:
381 * Intel: Deterministic Cache Parameters Leaf
382 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
383 * AMD: Reserved
384 * Safe to expose, except for EAX:
385 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
386 * Bits 31-26: Maximum number of processor cores in this physical package**
387 */
388 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
389 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
390
391 /* Cpuid 5: Monitor/mwait Leaf
392 * Intel: ECX, EDX - reserved
393 * EAX, EBX - Smallest and largest monitor line size
394 * AMD: EDX - reserved
395 * EAX, EBX - Smallest and largest monitor line size
396 * ECX - extensions (ignored for now)
397 * Safe to expose
398 */
399 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
400 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
401
402 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
403
404 /*
405 * Determine the default.
406 *
407 * Intel returns values of the highest standard function, while AMD
408 * returns zeros. VIA on the other hand seems to returning nothing or
409 * perhaps some random garbage, we don't try to duplicate this behavior.
410 */
411 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
412 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
413 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
414
415 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
416 * Safe to pass on to the guest.
417 *
418 * Intel: 0x800000005 reserved
419 * 0x800000006 L2 cache information
420 * AMD: 0x800000005 L1 cache information
421 * 0x800000006 L2/L3 cache information
422 */
423
424 /* Cpuid 0x800000007:
425 * AMD: EAX, EBX, ECX - reserved
426 * EDX: Advanced Power Management Information
427 * Intel: Reserved
428 */
429 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
430 {
431 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
432
433 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
434
435 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
436 {
437 /* Only expose the TSC invariant capability bit to the guest. */
438 pCPUM->aGuestCpuIdExt[7].edx &= 0
439 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
440 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
441 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
442 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
443 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
444 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
445 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
446 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
447 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
448 | 0;
449 }
450 else
451 pCPUM->aGuestCpuIdExt[7].edx = 0;
452 }
453
454 /* Cpuid 0x800000008:
455 * AMD: EBX, EDX - reserved
456 * EAX: Virtual/Physical address Size
457 * ECX: Number of cores + APICIdCoreIdSize
458 * Intel: EAX: Virtual/Physical address Size
459 * EBX, ECX, EDX - reserved
460 */
461 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
462 {
463 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
464 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
465 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
466 * NC (0-7) Number of cores; 0 equals 1 core */
467 pCPUM->aGuestCpuIdExt[8].ecx = 0;
468 }
469
470 /*
471 * Limit it the number of entries and fill the remaining with the defaults.
472 *
473 * The limits are masking off stuff about power saving and similar, this
474 * is perhaps a bit crudely done as there is probably some relatively harmless
475 * info too in these leaves (like words about having a constant TSC).
476 */
477#if 0
478 /** @todo NT4 installation regression - investigate */
479 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
480 pCPUM->aGuestCpuIdStd[0].eax = 5;
481#else
482 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
483 pCPUM->aGuestCpuIdStd[0].eax = 2;
484#endif
485 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
486 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
487
488 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
489 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
490 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
491 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
492 : 0;
493 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
494 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
495
496 /*
497 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
498 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
499 * We currently don't support more than 1 processor.
500 */
501 pCPUM->aGuestCpuIdStd[4].eax = 0;
502
503 /*
504 * Centaur stuff (VIA).
505 *
506 * The important part here (we think) is to make sure the 0xc0000000
507 * function returns 0xc0000001. As for the features, we don't currently
508 * let on about any of those... 0xc0000002 seems to be some
509 * temperature/hz/++ stuff, include it as well (static).
510 */
511 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
512 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
513 {
514 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
515 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
516 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
517 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
518 i++)
519 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
520 }
521 else
522 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
523 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
524
525
526 /*
527 * Load CPUID overrides from configuration.
528 */
529 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
530 * Overloads the CPUID leaf values. */
531 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
532 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
533 for (i=0;; )
534 {
535 while (cElements-- > 0)
536 {
537 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
538 if (pNode)
539 {
540 uint32_t u32;
541 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
542 if (RT_SUCCESS(rc))
543 pCpuId->eax = u32;
544 else
545 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
546
547 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
548 if (RT_SUCCESS(rc))
549 pCpuId->ebx = u32;
550 else
551 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
552
553 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
554 if (RT_SUCCESS(rc))
555 pCpuId->ecx = u32;
556 else
557 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
558
559 rc = CFGMR3QueryU32(pNode, "edx", &u32);
560 if (RT_SUCCESS(rc))
561 pCpuId->edx = u32;
562 else
563 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
564 }
565 pCpuId++;
566 i++;
567 }
568
569 /* next */
570 if ((i & UINT32_C(0xc0000000)) == 0)
571 {
572 pCpuId = &pCPUM->aGuestCpuIdExt[0];
573 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
574 i = UINT32_C(0x80000000);
575 }
576 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
577 {
578 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
579 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
580 i = UINT32_C(0xc0000000);
581 }
582 else
583 break;
584 }
585
586 /* Check if PAE was explicitely enabled by the user. */
587 bool fEnable = false;
588 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
589 if (RT_SUCCESS(rc) && fEnable)
590 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
591
592 /*
593 * Log the cpuid and we're good.
594 */
595 RTCPUSET OnlineSet;
596 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
597 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
598 LogRel(("************************* CPUID dump ************************\n"));
599 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
600 LogRel(("\n"));
601 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
602 LogRel(("******************** End of CPUID dump **********************\n"));
603 return VINF_SUCCESS;
604}
605
606
607
608
609/**
610 * Applies relocations to data and code managed by this
611 * component. This function will be called at init and
612 * whenever the VMM need to relocate it self inside the GC.
613 *
614 * The CPUM will update the addresses used by the switcher.
615 *
616 * @param pVM The VM.
617 */
618VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
619{
620 LogFlow(("CPUMR3Relocate\n"));
621 /*
622 * Switcher pointers.
623 */
624 pVM->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
625 Assert(pVM->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
626}
627
628
629/**
630 * Queries the pointer to the internal CPUMCTX structure
631 *
632 * @returns VBox status code.
633 * @param pVM Handle to the virtual machine.
634 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
635 */
636VMMR3DECL(int) CPUMR3QueryGuestCtxRCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
637{
638 LogFlow(("CPUMR3QueryGuestCtxRCPtr\n"));
639 /*
640 * Store the address. (Later we might check how's calling, thus the RC.)
641 */
642 *ppCtx = VM_RC_ADDR(pVM, &pVM->cpum.s.Guest);
643 return VINF_SUCCESS;
644}
645
646
647/**
648 * Terminates the CPUM.
649 *
650 * Termination means cleaning up and freeing all resources,
651 * the VM it self is at this point powered off or suspended.
652 *
653 * @returns VBox status code.
654 * @param pVM The VM to operate on.
655 */
656VMMR3DECL(int) CPUMR3Term(PVM pVM)
657{
658 /** @todo ? */
659 return 0;
660}
661
662
663/**
664 * Terminates the per-VCPU CPUM.
665 *
666 * Termination means cleaning up and freeing all resources,
667 * the VM it self is at this point powered off or suspended.
668 *
669 * @returns VBox status code.
670 * @param pVM The VM to operate on.
671 */
672VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
673{
674 return 0;
675}
676
677
678/**
679 * Resets the CPU.
680 *
681 * @returns VINF_SUCCESS.
682 * @param pVM The VM handle.
683 */
684VMMR3DECL(void) CPUMR3Reset(PVM pVM)
685{
686 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
687
688 /*
689 * Initialize everything to ZERO first.
690 */
691 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
692 memset(pCtx, 0, sizeof(*pCtx));
693 pVM->cpum.s.fUseFlags = fUseFlags;
694
695 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
696 pCtx->eip = 0x0000fff0;
697 pCtx->edx = 0x00000600; /* P6 processor */
698 pCtx->eflags.Bits.u1Reserved0 = 1;
699
700 pCtx->cs = 0xf000;
701 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
702 pCtx->csHid.u32Limit = 0x0000ffff;
703 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
704 pCtx->csHid.Attr.n.u1Present = 1;
705 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
706
707 pCtx->dsHid.u32Limit = 0x0000ffff;
708 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
709 pCtx->dsHid.Attr.n.u1Present = 1;
710 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
711
712 pCtx->esHid.u32Limit = 0x0000ffff;
713 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
714 pCtx->esHid.Attr.n.u1Present = 1;
715 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
716
717 pCtx->fsHid.u32Limit = 0x0000ffff;
718 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
719 pCtx->fsHid.Attr.n.u1Present = 1;
720 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
721
722 pCtx->gsHid.u32Limit = 0x0000ffff;
723 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
724 pCtx->gsHid.Attr.n.u1Present = 1;
725 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
726
727 pCtx->ssHid.u32Limit = 0x0000ffff;
728 pCtx->ssHid.Attr.n.u1Present = 1;
729 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
730 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
731
732 pCtx->idtr.cbIdt = 0xffff;
733 pCtx->gdtr.cbGdt = 0xffff;
734
735 pCtx->ldtrHid.u32Limit = 0xffff;
736 pCtx->ldtrHid.Attr.n.u1Present = 1;
737 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
738
739 pCtx->trHid.u32Limit = 0xffff;
740 pCtx->trHid.Attr.n.u1Present = 1;
741 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
742
743 pCtx->dr[6] = X86_DR6_INIT_VAL;
744 pCtx->dr[7] = X86_DR7_INIT_VAL;
745
746 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
747 pCtx->fpu.FCW = 0x37f;
748
749 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
750 pCtx->fpu.MXCSR = 0x1F80;
751
752 /* Init PAT MSR */
753 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
754
755 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
756 * The Intel docs don't mention it.
757 */
758 pCtx->msrEFER = 0;
759}
760
761
762/**
763 * Execute state save operation.
764 *
765 * @returns VBox status code.
766 * @param pVM VM Handle.
767 * @param pSSM SSM operation handle.
768 */
769static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
770{
771 /* Set the size of RTGCPTR for use of SSMR3Get/PutGCPtr. */
772 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
773
774 /*
775 * Save.
776 */
777 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
778 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
779 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
780 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
781
782 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
783 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
784
785 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
786 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
787
788 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
789 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
790
791 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
792
793 /* Add the cpuid for checking that the cpu is unchanged. */
794 uint32_t au32CpuId[8] = {0};
795 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
796 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
797 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
798}
799
800
801/**
802 * Load a version 1.6 CPUMCTX structure.
803 *
804 * @returns VBox status code.
805 * @param pVM VM Handle.
806 * @param pCpumctx16 Version 1.6 CPUMCTX
807 */
808static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
809{
810#define CPUMCTX16_LOADREG(RegName) \
811 pVM->cpum.s.Guest.RegName = pCpumctx16->RegName;
812
813#define CPUMCTX16_LOADDRXREG(RegName) \
814 pVM->cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
815
816#define CPUMCTX16_LOADHIDREG(RegName) \
817 pVM->cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
818 pVM->cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
819 pVM->cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
820
821#define CPUMCTX16_LOADSEGREG(RegName) \
822 pVM->cpum.s.Guest.RegName = pCpumctx16->RegName; \
823 CPUMCTX16_LOADHIDREG(RegName);
824
825 pVM->cpum.s.Guest.fpu = pCpumctx16->fpu;
826
827 CPUMCTX16_LOADREG(rax);
828 CPUMCTX16_LOADREG(rbx);
829 CPUMCTX16_LOADREG(rcx);
830 CPUMCTX16_LOADREG(rdx);
831 CPUMCTX16_LOADREG(rdi);
832 CPUMCTX16_LOADREG(rsi);
833 CPUMCTX16_LOADREG(rbp);
834 CPUMCTX16_LOADREG(esp);
835 CPUMCTX16_LOADREG(rip);
836 CPUMCTX16_LOADREG(rflags);
837
838 CPUMCTX16_LOADSEGREG(cs);
839 CPUMCTX16_LOADSEGREG(ds);
840 CPUMCTX16_LOADSEGREG(es);
841 CPUMCTX16_LOADSEGREG(fs);
842 CPUMCTX16_LOADSEGREG(gs);
843 CPUMCTX16_LOADSEGREG(ss);
844
845 CPUMCTX16_LOADREG(r8);
846 CPUMCTX16_LOADREG(r9);
847 CPUMCTX16_LOADREG(r10);
848 CPUMCTX16_LOADREG(r11);
849 CPUMCTX16_LOADREG(r12);
850 CPUMCTX16_LOADREG(r13);
851 CPUMCTX16_LOADREG(r14);
852 CPUMCTX16_LOADREG(r15);
853
854 CPUMCTX16_LOADREG(cr0);
855 CPUMCTX16_LOADREG(cr2);
856 CPUMCTX16_LOADREG(cr3);
857 CPUMCTX16_LOADREG(cr4);
858
859 CPUMCTX16_LOADDRXREG(0);
860 CPUMCTX16_LOADDRXREG(1);
861 CPUMCTX16_LOADDRXREG(2);
862 CPUMCTX16_LOADDRXREG(3);
863 CPUMCTX16_LOADDRXREG(4);
864 CPUMCTX16_LOADDRXREG(5);
865 CPUMCTX16_LOADDRXREG(6);
866 CPUMCTX16_LOADDRXREG(7);
867
868 pVM->cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
869 pVM->cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
870 pVM->cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
871 pVM->cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
872
873 CPUMCTX16_LOADREG(ldtr);
874 CPUMCTX16_LOADREG(tr);
875
876 pVM->cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
877
878 CPUMCTX16_LOADREG(msrEFER);
879 CPUMCTX16_LOADREG(msrSTAR);
880 CPUMCTX16_LOADREG(msrPAT);
881 CPUMCTX16_LOADREG(msrLSTAR);
882 CPUMCTX16_LOADREG(msrCSTAR);
883 CPUMCTX16_LOADREG(msrSFMASK);
884 CPUMCTX16_LOADREG(msrKERNELGSBASE);
885
886 CPUMCTX16_LOADHIDREG(ldtr);
887 CPUMCTX16_LOADHIDREG(tr);
888
889#undef CPUMCTX16_LOADSEGREG
890#undef CPUMCTX16_LOADHIDREG
891#undef CPUMCTX16_LOADDRXREG
892#undef CPUMCTX16_LOADREG
893}
894
895
896/**
897 * Execute state load operation.
898 *
899 * @returns VBox status code.
900 * @param pVM VM Handle.
901 * @param pSSM SSM operation handle.
902 * @param u32Version Data layout version.
903 */
904static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
905{
906 /*
907 * Validate version.
908 */
909 if ( u32Version != CPUM_SAVED_STATE_VERSION
910 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
911 {
912 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
913 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
914 }
915
916 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
917 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
918 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
919 else
920 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
921
922 /*
923 * Restore.
924 */
925 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
926 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
927 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
928 pVM->cpum.s.Hyper.cr3 = uCR3;
929 pVM->cpum.s.Hyper.esp = uESP;
930 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
931 {
932 CPUMCTX_VER1_6 cpumctx16;
933 memset(&pVM->cpum.s.Guest, 0, sizeof(pVM->cpum.s.Guest));
934 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
935
936 /* Save the old cpumctx state into the new one. */
937 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
938 }
939 else
940 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
941
942 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
943 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
944
945 uint32_t cElements;
946 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
947 /* Support old saved states with a smaller standard cpuid array. */
948 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
949 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
950 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
951
952 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
953 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
954 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
955 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
956
957 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
958 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
959 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
960 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
961
962 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
963
964 /*
965 * Check that the basic cpuid id information is unchanged.
966 */
967 uint32_t au32CpuId[8] = {0};
968 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
969 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
970 uint32_t au32CpuIdSaved[8];
971 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
972 if (RT_SUCCESS(rc))
973 {
974 /* Ignore APIC ID (AMD specs). */
975 au32CpuId[5] &= ~0xff000000;
976 au32CpuIdSaved[5] &= ~0xff000000;
977 /* Ignore the number of Logical CPUs (AMD specs). */
978 au32CpuId[5] &= ~0x00ff0000;
979 au32CpuIdSaved[5] &= ~0x00ff0000;
980
981 /* do the compare */
982 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
983 {
984 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
985 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
986 "Saved=%.*Rhxs\n"
987 "Real =%.*Rhxs\n",
988 sizeof(au32CpuIdSaved), au32CpuIdSaved,
989 sizeof(au32CpuId), au32CpuId));
990 else
991 {
992 LogRel(("cpumR3Load: CpuId mismatch!\n"
993 "Saved=%.*Rhxs\n"
994 "Real =%.*Rhxs\n",
995 sizeof(au32CpuIdSaved), au32CpuIdSaved,
996 sizeof(au32CpuId), au32CpuId));
997 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
998 }
999 }
1000 }
1001
1002 return rc;
1003}
1004
1005
1006/**
1007 * Formats the EFLAGS value into mnemonics.
1008 *
1009 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1010 * @param efl The EFLAGS value.
1011 */
1012static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1013{
1014 /*
1015 * Format the flags.
1016 */
1017 static const struct
1018 {
1019 const char *pszSet; const char *pszClear; uint32_t fFlag;
1020 } s_aFlags[] =
1021 {
1022 { "vip",NULL, X86_EFL_VIP },
1023 { "vif",NULL, X86_EFL_VIF },
1024 { "ac", NULL, X86_EFL_AC },
1025 { "vm", NULL, X86_EFL_VM },
1026 { "rf", NULL, X86_EFL_RF },
1027 { "nt", NULL, X86_EFL_NT },
1028 { "ov", "nv", X86_EFL_OF },
1029 { "dn", "up", X86_EFL_DF },
1030 { "ei", "di", X86_EFL_IF },
1031 { "tf", NULL, X86_EFL_TF },
1032 { "nt", "pl", X86_EFL_SF },
1033 { "nz", "zr", X86_EFL_ZF },
1034 { "ac", "na", X86_EFL_AF },
1035 { "po", "pe", X86_EFL_PF },
1036 { "cy", "nc", X86_EFL_CF },
1037 };
1038 char *psz = pszEFlags;
1039 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1040 {
1041 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1042 if (pszAdd)
1043 {
1044 strcpy(psz, pszAdd);
1045 psz += strlen(pszAdd);
1046 *psz++ = ' ';
1047 }
1048 }
1049 psz[-1] = '\0';
1050}
1051
1052
1053/**
1054 * Formats a full register dump.
1055 *
1056 * @param pVM VM Handle.
1057 * @param pCtx The context to format.
1058 * @param pCtxCore The context core to format.
1059 * @param pHlp Output functions.
1060 * @param enmType The dump type.
1061 * @param pszPrefix Register name prefix.
1062 */
1063static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1064{
1065 /*
1066 * Format the EFLAGS.
1067 */
1068 uint32_t efl = pCtxCore->eflags.u32;
1069 char szEFlags[80];
1070 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1071
1072 /*
1073 * Format the registers.
1074 */
1075 switch (enmType)
1076 {
1077 case CPUMDUMPTYPE_TERSE:
1078 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1079 pHlp->pfnPrintf(pHlp,
1080 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1081 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1082 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1083 "%sr14=%016RX64 %sr15=%016RX64\n"
1084 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1085 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1086 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1087 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1088 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1089 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1090 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1091 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1092 else
1093 pHlp->pfnPrintf(pHlp,
1094 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1095 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1096 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1097 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1098 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1099 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1100 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1101 break;
1102
1103 case CPUMDUMPTYPE_DEFAULT:
1104 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1105 pHlp->pfnPrintf(pHlp,
1106 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1107 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1108 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1109 "%sr14=%016RX64 %sr15=%016RX64\n"
1110 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1111 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1112 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1113 ,
1114 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1115 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1116 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1117 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1118 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1119 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1120 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1121 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1122 else
1123 pHlp->pfnPrintf(pHlp,
1124 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1125 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1126 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1127 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1128 ,
1129 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1130 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1131 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1132 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1133 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1134 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1135 break;
1136
1137 case CPUMDUMPTYPE_VERBOSE:
1138 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1139 pHlp->pfnPrintf(pHlp,
1140 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1141 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1142 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1143 "%sr14=%016RX64 %sr15=%016RX64\n"
1144 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1145 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1146 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1147 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1148 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1149 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1150 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1151 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1152 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1153 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1154 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1155 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1156 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1157 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1158 ,
1159 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1160 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1161 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1162 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1163 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1164 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1165 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1166 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1167 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1168 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1169 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1170 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1171 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1172 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1173 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1174 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1175 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1176 else
1177 pHlp->pfnPrintf(pHlp,
1178 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1179 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1180 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1181 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1182 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1183 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1184 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1185 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1186 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1187 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1188 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1189 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1190 ,
1191 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1192 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1193 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1194 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1195 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1196 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1197 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1198 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1199 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1200 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1201 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1202 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1203
1204 pHlp->pfnPrintf(pHlp,
1205 "FPU:\n"
1206 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1207 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1208 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1209 ,
1210 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1211 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1212 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1213 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1214
1215 pHlp->pfnPrintf(pHlp,
1216 "MSR:\n"
1217 "%sEFER =%016RX64\n"
1218 "%sPAT =%016RX64\n"
1219 "%sSTAR =%016RX64\n"
1220 "%sCSTAR =%016RX64\n"
1221 "%sLSTAR =%016RX64\n"
1222 "%sSFMASK =%016RX64\n"
1223 "%sKERNELGSBASE =%016RX64\n",
1224 pszPrefix, pCtx->msrEFER,
1225 pszPrefix, pCtx->msrPAT,
1226 pszPrefix, pCtx->msrSTAR,
1227 pszPrefix, pCtx->msrCSTAR,
1228 pszPrefix, pCtx->msrLSTAR,
1229 pszPrefix, pCtx->msrSFMASK,
1230 pszPrefix, pCtx->msrKERNELGSBASE);
1231 break;
1232 }
1233}
1234
1235
1236/**
1237 * Display all cpu states and any other cpum info.
1238 *
1239 * @param pVM VM Handle.
1240 * @param pHlp The info helper functions.
1241 * @param pszArgs Arguments, ignored.
1242 */
1243static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1244{
1245 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1246 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1247 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1248 cpumR3InfoHost(pVM, pHlp, pszArgs);
1249}
1250
1251
1252/**
1253 * Parses the info argument.
1254 *
1255 * The argument starts with 'verbose', 'terse' or 'default' and then
1256 * continues with the comment string.
1257 *
1258 * @param pszArgs The pointer to the argument string.
1259 * @param penmType Where to store the dump type request.
1260 * @param ppszComment Where to store the pointer to the comment string.
1261 */
1262static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1263{
1264 if (!pszArgs)
1265 {
1266 *penmType = CPUMDUMPTYPE_DEFAULT;
1267 *ppszComment = "";
1268 }
1269 else
1270 {
1271 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1272 {
1273 pszArgs += 5;
1274 *penmType = CPUMDUMPTYPE_VERBOSE;
1275 }
1276 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1277 {
1278 pszArgs += 5;
1279 *penmType = CPUMDUMPTYPE_TERSE;
1280 }
1281 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1282 {
1283 pszArgs += 7;
1284 *penmType = CPUMDUMPTYPE_DEFAULT;
1285 }
1286 else
1287 *penmType = CPUMDUMPTYPE_DEFAULT;
1288 *ppszComment = RTStrStripL(pszArgs);
1289 }
1290}
1291
1292
1293/**
1294 * Display the guest cpu state.
1295 *
1296 * @param pVM VM Handle.
1297 * @param pHlp The info helper functions.
1298 * @param pszArgs Arguments, ignored.
1299 */
1300static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1301{
1302 CPUMDUMPTYPE enmType;
1303 const char *pszComment;
1304 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1305 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1306 cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
1307}
1308
1309
1310/**
1311 * Display the current guest instruction
1312 *
1313 * @param pVM VM Handle.
1314 * @param pHlp The info helper functions.
1315 * @param pszArgs Arguments, ignored.
1316 */
1317static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1318{
1319 char szInstruction[256];
1320 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1321 if (RT_SUCCESS(rc))
1322 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1323}
1324
1325
1326/**
1327 * Display the hypervisor cpu state.
1328 *
1329 * @param pVM VM Handle.
1330 * @param pHlp The info helper functions.
1331 * @param pszArgs Arguments, ignored.
1332 */
1333static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1334{
1335 CPUMDUMPTYPE enmType;
1336 const char *pszComment;
1337 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1338 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1339 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1340 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1341}
1342
1343
1344/**
1345 * Display the host cpu state.
1346 *
1347 * @param pVM VM Handle.
1348 * @param pHlp The info helper functions.
1349 * @param pszArgs Arguments, ignored.
1350 */
1351static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1352{
1353 CPUMDUMPTYPE enmType;
1354 const char *pszComment;
1355 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1356 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1357
1358 /*
1359 * Format the EFLAGS.
1360 */
1361 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
1362#if HC_ARCH_BITS == 32
1363 uint32_t efl = pCtx->eflags.u32;
1364#else
1365 uint64_t efl = pCtx->rflags;
1366#endif
1367 char szEFlags[80];
1368 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1369
1370 /*
1371 * Format the registers.
1372 */
1373#if HC_ARCH_BITS == 32
1374# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1375 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1376# endif
1377 {
1378 pHlp->pfnPrintf(pHlp,
1379 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1380 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1381 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1382 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1383 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1384 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1385 ,
1386 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1387 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1388 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1389 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1390 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1391 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1392 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1393 }
1394# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1395 else
1396# endif
1397#endif
1398#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1399 {
1400 pHlp->pfnPrintf(pHlp,
1401 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1402 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1403 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1404 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1405 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1406 "r14=%016RX64 r15=%016RX64\n"
1407 "iopl=%d %31s\n"
1408 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1409 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1410 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1411 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1412 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1413 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1414 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1415 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1416 ,
1417 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1418 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1419 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1420 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1421 pCtx->r11, pCtx->r12, pCtx->r13,
1422 pCtx->r14, pCtx->r15,
1423 X86_EFL_GET_IOPL(efl), szEFlags,
1424 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1425 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1426 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1427 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1428 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1429 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1430 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1431 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1432 }
1433#endif
1434}
1435
1436
1437/**
1438 * Get L1 cache / TLS associativity.
1439 */
1440static const char *getCacheAss(unsigned u, char *pszBuf)
1441{
1442 if (u == 0)
1443 return "res0 ";
1444 if (u == 1)
1445 return "direct";
1446 if (u >= 256)
1447 return "???";
1448
1449 RTStrPrintf(pszBuf, 16, "%d way", u);
1450 return pszBuf;
1451}
1452
1453
1454/**
1455 * Get L2 cache soociativity.
1456 */
1457const char *getL2CacheAss(unsigned u)
1458{
1459 switch (u)
1460 {
1461 case 0: return "off ";
1462 case 1: return "direct";
1463 case 2: return "2 way ";
1464 case 3: return "res3 ";
1465 case 4: return "4 way ";
1466 case 5: return "res5 ";
1467 case 6: return "8 way "; case 7: return "res7 ";
1468 case 8: return "16 way";
1469 case 9: return "res9 ";
1470 case 10: return "res10 ";
1471 case 11: return "res11 ";
1472 case 12: return "res12 ";
1473 case 13: return "res13 ";
1474 case 14: return "res14 ";
1475 case 15: return "fully ";
1476 default:
1477 return "????";
1478 }
1479}
1480
1481
1482/**
1483 * Display the guest CpuId leaves.
1484 *
1485 * @param pVM VM Handle.
1486 * @param pHlp The info helper functions.
1487 * @param pszArgs "terse", "default" or "verbose".
1488 */
1489static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1490{
1491 /*
1492 * Parse the argument.
1493 */
1494 unsigned iVerbosity = 1;
1495 if (pszArgs)
1496 {
1497 pszArgs = RTStrStripL(pszArgs);
1498 if (!strcmp(pszArgs, "terse"))
1499 iVerbosity--;
1500 else if (!strcmp(pszArgs, "verbose"))
1501 iVerbosity++;
1502 }
1503
1504 /*
1505 * Start cracking.
1506 */
1507 CPUMCPUID Host;
1508 CPUMCPUID Guest;
1509 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1510
1511 pHlp->pfnPrintf(pHlp,
1512 " RAW Standard CPUIDs\n"
1513 " Function eax ebx ecx edx\n");
1514 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1515 {
1516 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1517 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1518
1519 pHlp->pfnPrintf(pHlp,
1520 "Gst: %08x %08x %08x %08x %08x%s\n"
1521 "Hst: %08x %08x %08x %08x\n",
1522 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1523 i <= cStdMax ? "" : "*",
1524 Host.eax, Host.ebx, Host.ecx, Host.edx);
1525 }
1526
1527 /*
1528 * If verbose, decode it.
1529 */
1530 if (iVerbosity)
1531 {
1532 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1533 pHlp->pfnPrintf(pHlp,
1534 "Name: %.04s%.04s%.04s\n"
1535 "Supports: 0-%x\n",
1536 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1537 }
1538
1539 /*
1540 * Get Features.
1541 */
1542 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1543 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1544 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1545 if (cStdMax >= 1 && iVerbosity)
1546 {
1547 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1548 uint32_t uEAX = Guest.eax;
1549
1550 pHlp->pfnPrintf(pHlp,
1551 "Family: %d \tExtended: %d \tEffective: %d\n"
1552 "Model: %d \tExtended: %d \tEffective: %d\n"
1553 "Stepping: %d\n"
1554 "APIC ID: %#04x\n"
1555 "Logical CPUs: %d\n"
1556 "CLFLUSH Size: %d\n"
1557 "Brand ID: %#04x\n",
1558 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1559 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1560 ASMGetCpuStepping(uEAX),
1561 (Guest.ebx >> 24) & 0xff,
1562 (Guest.ebx >> 16) & 0xff,
1563 (Guest.ebx >> 8) & 0xff,
1564 (Guest.ebx >> 0) & 0xff);
1565 if (iVerbosity == 1)
1566 {
1567 uint32_t uEDX = Guest.edx;
1568 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1569 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1570 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1571 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1572 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1573 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1574 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1575 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1576 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1577 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1578 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1579 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1580 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1581 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1582 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1583 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1584 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1585 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1586 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1587 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1588 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1589 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1590 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1591 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1592 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1593 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1594 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1595 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1596 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1597 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1598 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1599 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1600 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1601 pHlp->pfnPrintf(pHlp, "\n");
1602
1603 uint32_t uECX = Guest.ecx;
1604 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1605 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1606 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1607 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1608 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1609 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1610 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1611 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1612 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1613 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1614 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1615 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1616 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1617 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1618 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1619 for (unsigned iBit = 14; iBit < 32; iBit++)
1620 if (uECX & RT_BIT(iBit))
1621 pHlp->pfnPrintf(pHlp, " %d", iBit);
1622 pHlp->pfnPrintf(pHlp, "\n");
1623 }
1624 else
1625 {
1626 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1627
1628 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1629 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1630 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1631 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1632
1633 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1634 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1635 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1636 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1637 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1638 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1639 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1640 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1641 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1642 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1643 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1644 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1645 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1646 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1647 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1648 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1649 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1650 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1651 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1652 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1653 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1654 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1655 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1656 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1657 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1658 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1659 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1660 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1661 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1662 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1663 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1664 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1665 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1666
1667 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1668 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1669 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1670 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1671 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1672 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1673 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1674 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1675 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1676 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1677 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1678 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1679 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1680 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1681 }
1682 }
1683 if (cStdMax >= 2 && iVerbosity)
1684 {
1685 /** @todo */
1686 }
1687
1688 /*
1689 * Extended.
1690 * Implemented after AMD specs.
1691 */
1692 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1693
1694 pHlp->pfnPrintf(pHlp,
1695 "\n"
1696 " RAW Extended CPUIDs\n"
1697 " Function eax ebx ecx edx\n");
1698 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1699 {
1700 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1701 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1702
1703 pHlp->pfnPrintf(pHlp,
1704 "Gst: %08x %08x %08x %08x %08x%s\n"
1705 "Hst: %08x %08x %08x %08x\n",
1706 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1707 i <= cExtMax ? "" : "*",
1708 Host.eax, Host.ebx, Host.ecx, Host.edx);
1709 }
1710
1711 /*
1712 * Understandable output
1713 */
1714 if (iVerbosity)
1715 {
1716 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1717 pHlp->pfnPrintf(pHlp,
1718 "Ext Name: %.4s%.4s%.4s\n"
1719 "Ext Supports: 0x80000000-%#010x\n",
1720 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1721 }
1722
1723 if (iVerbosity && cExtMax >= 1)
1724 {
1725 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1726 uint32_t uEAX = Guest.eax;
1727 pHlp->pfnPrintf(pHlp,
1728 "Family: %d \tExtended: %d \tEffective: %d\n"
1729 "Model: %d \tExtended: %d \tEffective: %d\n"
1730 "Stepping: %d\n"
1731 "Brand ID: %#05x\n",
1732 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1733 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1734 ASMGetCpuStepping(uEAX),
1735 Guest.ebx & 0xfff);
1736
1737 if (iVerbosity == 1)
1738 {
1739 uint32_t uEDX = Guest.edx;
1740 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1741 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1742 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1743 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1744 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1745 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1746 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1747 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1748 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1749 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1750 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1751 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1752 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1753 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1754 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1755 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1756 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1757 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1758 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1759 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1760 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1761 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1762 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1763 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1764 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1765 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1766 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1767 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1768 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1769 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1770 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1771 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1772 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1773 pHlp->pfnPrintf(pHlp, "\n");
1774
1775 uint32_t uECX = Guest.ecx;
1776 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1777 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1778 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1779 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1780 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1781 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1782 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1783 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1784 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1785 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1786 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1787 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1788 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1789 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1790 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1791 for (unsigned iBit = 5; iBit < 32; iBit++)
1792 if (uECX & RT_BIT(iBit))
1793 pHlp->pfnPrintf(pHlp, " %d", iBit);
1794 pHlp->pfnPrintf(pHlp, "\n");
1795 }
1796 else
1797 {
1798 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1799
1800 uint32_t uEdxGst = Guest.edx;
1801 uint32_t uEdxHst = Host.edx;
1802 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1803 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1804 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1805 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1806 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1807 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1808 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1809 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1810 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1811 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1812 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1813 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1814 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1815 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1816 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1817 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1818 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1819 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1820 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1821 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1822 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1823 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1824 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1825 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1826 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1827 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1828 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1829 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1830 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1831 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1832 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1833 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1834 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1835
1836 uint32_t uEcxGst = Guest.ecx;
1837 uint32_t uEcxHst = Host.ecx;
1838 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1839 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1840 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1841 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1842 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1843 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1844 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1845 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1846 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1847 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1848 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1849 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1850 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1851 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1852 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1853 }
1854 }
1855
1856 if (iVerbosity && cExtMax >= 2)
1857 {
1858 char szString[4*4*3+1] = {0};
1859 uint32_t *pu32 = (uint32_t *)szString;
1860 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1861 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1862 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1863 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1864 if (cExtMax >= 3)
1865 {
1866 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1867 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1868 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1869 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1870 }
1871 if (cExtMax >= 4)
1872 {
1873 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1874 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1875 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1876 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1877 }
1878 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1879 }
1880
1881 if (iVerbosity && cExtMax >= 5)
1882 {
1883 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1884 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1885 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1886 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1887 char sz1[32];
1888 char sz2[32];
1889
1890 pHlp->pfnPrintf(pHlp,
1891 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1892 "TLB 2/4M Data: %s %3d entries\n",
1893 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1894 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1895 pHlp->pfnPrintf(pHlp,
1896 "TLB 4K Instr/Uni: %s %3d entries\n"
1897 "TLB 4K Data: %s %3d entries\n",
1898 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1899 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1900 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1901 "L1 Instr Cache Lines Per Tag: %d\n"
1902 "L1 Instr Cache Associativity: %s\n"
1903 "L1 Instr Cache Size: %d KB\n",
1904 (uEDX >> 0) & 0xff,
1905 (uEDX >> 8) & 0xff,
1906 getCacheAss((uEDX >> 16) & 0xff, sz1),
1907 (uEDX >> 24) & 0xff);
1908 pHlp->pfnPrintf(pHlp,
1909 "L1 Data Cache Line Size: %d bytes\n"
1910 "L1 Data Cache Lines Per Tag: %d\n"
1911 "L1 Data Cache Associativity: %s\n"
1912 "L1 Data Cache Size: %d KB\n",
1913 (uECX >> 0) & 0xff,
1914 (uECX >> 8) & 0xff,
1915 getCacheAss((uECX >> 16) & 0xff, sz1),
1916 (uECX >> 24) & 0xff);
1917 }
1918
1919 if (iVerbosity && cExtMax >= 6)
1920 {
1921 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1922 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1923 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1924
1925 pHlp->pfnPrintf(pHlp,
1926 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1927 "L2 TLB 2/4M Data: %s %4d entries\n",
1928 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1929 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1930 pHlp->pfnPrintf(pHlp,
1931 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1932 "L2 TLB 4K Data: %s %4d entries\n",
1933 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1934 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1935 pHlp->pfnPrintf(pHlp,
1936 "L2 Cache Line Size: %d bytes\n"
1937 "L2 Cache Lines Per Tag: %d\n"
1938 "L2 Cache Associativity: %s\n"
1939 "L2 Cache Size: %d KB\n",
1940 (uEDX >> 0) & 0xff,
1941 (uEDX >> 8) & 0xf,
1942 getL2CacheAss((uEDX >> 12) & 0xf),
1943 (uEDX >> 16) & 0xffff);
1944 }
1945
1946 if (iVerbosity && cExtMax >= 7)
1947 {
1948 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1949
1950 pHlp->pfnPrintf(pHlp, "APM Features: ");
1951 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1952 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1953 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1954 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1955 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1956 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1957 for (unsigned iBit = 6; iBit < 32; iBit++)
1958 if (uEDX & RT_BIT(iBit))
1959 pHlp->pfnPrintf(pHlp, " %d", iBit);
1960 pHlp->pfnPrintf(pHlp, "\n");
1961 }
1962
1963 if (iVerbosity && cExtMax >= 8)
1964 {
1965 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1966 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1967
1968 pHlp->pfnPrintf(pHlp,
1969 "Physical Address Width: %d bits\n"
1970 "Virtual Address Width: %d bits\n",
1971 (uEAX >> 0) & 0xff,
1972 (uEAX >> 8) & 0xff);
1973 pHlp->pfnPrintf(pHlp,
1974 "Physical Core Count: %d\n",
1975 (uECX >> 0) & 0xff);
1976 }
1977
1978
1979 /*
1980 * Centaur.
1981 */
1982 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1983
1984 pHlp->pfnPrintf(pHlp,
1985 "\n"
1986 " RAW Centaur CPUIDs\n"
1987 " Function eax ebx ecx edx\n");
1988 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1989 {
1990 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1991 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1992
1993 pHlp->pfnPrintf(pHlp,
1994 "Gst: %08x %08x %08x %08x %08x%s\n"
1995 "Hst: %08x %08x %08x %08x\n",
1996 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1997 i <= cCentaurMax ? "" : "*",
1998 Host.eax, Host.ebx, Host.ecx, Host.edx);
1999 }
2000
2001 /*
2002 * Understandable output
2003 */
2004 if (iVerbosity)
2005 {
2006 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2007 pHlp->pfnPrintf(pHlp,
2008 "Centaur Supports: 0xc0000000-%#010x\n",
2009 Guest.eax);
2010 }
2011
2012 if (iVerbosity && cCentaurMax >= 1)
2013 {
2014 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2015 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2016 uint32_t uEdxHst = Host.edx;
2017
2018 if (iVerbosity == 1)
2019 {
2020 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2021 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2022 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2023 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2024 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2025 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2026 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2027 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2028 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2029 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2030 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2031 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2032 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2033 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2034 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2035 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2036 for (unsigned iBit = 14; iBit < 32; iBit++)
2037 if (uEdxGst & RT_BIT(iBit))
2038 pHlp->pfnPrintf(pHlp, " %d", iBit);
2039 pHlp->pfnPrintf(pHlp, "\n");
2040 }
2041 else
2042 {
2043 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2044 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2045 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2046 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2047 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2048 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2049 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2050 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2051 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2052 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2053 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2054 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2055 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2056 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2057 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2058 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2059 for (unsigned iBit = 14; iBit < 32; iBit++)
2060 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2061 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2062 pHlp->pfnPrintf(pHlp, "\n");
2063 }
2064 }
2065}
2066
2067
2068/**
2069 * Structure used when disassembling and instructions in DBGF.
2070 * This is used so the reader function can get the stuff it needs.
2071 */
2072typedef struct CPUMDISASSTATE
2073{
2074 /** Pointer to the CPU structure. */
2075 PDISCPUSTATE pCpu;
2076 /** The VM handle. */
2077 PVM pVM;
2078 /** Pointer to the first byte in the segemnt. */
2079 RTGCUINTPTR GCPtrSegBase;
2080 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2081 RTGCUINTPTR GCPtrSegEnd;
2082 /** The size of the segment minus 1. */
2083 RTGCUINTPTR cbSegLimit;
2084 /** Pointer to the current page - R3 Ptr. */
2085 void const *pvPageR3;
2086 /** Pointer to the current page - GC Ptr. */
2087 RTGCPTR pvPageGC;
2088 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2089 PGMPAGEMAPLOCK PageMapLock;
2090 /** Whether the PageMapLock is valid or not. */
2091 bool fLocked;
2092 /** 64 bits mode or not. */
2093 bool f64Bits;
2094} CPUMDISASSTATE, *PCPUMDISASSTATE;
2095
2096
2097/**
2098 * Instruction reader.
2099 *
2100 * @returns VBox status code.
2101 * @param PtrSrc Address to read from.
2102 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2103 * @param pu8Dst Where to store the bytes.
2104 * @param cbRead Number of bytes to read.
2105 * @param uDisCpu Pointer to the disassembler cpu state.
2106 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2107 */
2108static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2109{
2110 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2111 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2112 Assert(cbRead > 0);
2113 for (;;)
2114 {
2115 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2116
2117 /* Need to update the page translation? */
2118 if ( !pState->pvPageR3
2119 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2120 {
2121 int rc = VINF_SUCCESS;
2122
2123 /* translate the address */
2124 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2125 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2126 && !HWACCMIsEnabled(pState->pVM))
2127 {
2128 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2129 if (!pState->pvPageR3)
2130 rc = VERR_INVALID_POINTER;
2131 }
2132 else
2133 {
2134 /* Release mapping lock previously acquired. */
2135 if (pState->fLocked)
2136 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2137 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2138 pState->fLocked = RT_SUCCESS_NP(rc);
2139 }
2140 if (RT_FAILURE(rc))
2141 {
2142 pState->pvPageR3 = NULL;
2143 return rc;
2144 }
2145 }
2146
2147 /* check the segemnt limit */
2148 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2149 return VERR_OUT_OF_SELECTOR_BOUNDS;
2150
2151 /* calc how much we can read */
2152 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2153 if (!pState->f64Bits)
2154 {
2155 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2156 if (cb > cbSeg && cbSeg)
2157 cb = cbSeg;
2158 }
2159 if (cb > cbRead)
2160 cb = cbRead;
2161
2162 /* read and advance */
2163 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2164 cbRead -= cb;
2165 if (!cbRead)
2166 return VINF_SUCCESS;
2167 pu8Dst += cb;
2168 PtrSrc += cb;
2169 }
2170}
2171
2172
2173/**
2174 * Disassemble an instruction and return the information in the provided structure.
2175 *
2176 * @returns VBox status code.
2177 * @param pVM VM Handle
2178 * @param pCtx CPU context
2179 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2180 * @param pCpu Disassembly state
2181 * @param pszPrefix String prefix for logging (debug only)
2182 *
2183 */
2184VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2185{
2186 CPUMDISASSTATE State;
2187 int rc;
2188
2189 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2190 State.pCpu = pCpu;
2191 State.pvPageGC = 0;
2192 State.pvPageR3 = NULL;
2193 State.pVM = pVM;
2194 State.fLocked = false;
2195 State.f64Bits = false;
2196
2197 /*
2198 * Get selector information.
2199 */
2200 if ( (pCtx->cr0 & X86_CR0_PE)
2201 && pCtx->eflags.Bits.u1VM == 0)
2202 {
2203 if (CPUMAreHiddenSelRegsValid(pVM))
2204 {
2205 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2206 State.GCPtrSegBase = pCtx->csHid.u64Base;
2207 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2208 State.cbSegLimit = pCtx->csHid.u32Limit;
2209 pCpu->mode = (State.f64Bits)
2210 ? CPUMODE_64BIT
2211 : pCtx->csHid.Attr.n.u1DefBig
2212 ? CPUMODE_32BIT
2213 : CPUMODE_16BIT;
2214 }
2215 else
2216 {
2217 SELMSELINFO SelInfo;
2218
2219 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2220 if (!RT_SUCCESS(rc))
2221 {
2222 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2223 return rc;
2224 }
2225
2226 /*
2227 * Validate the selector.
2228 */
2229 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2230 if (!RT_SUCCESS(rc))
2231 {
2232 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2233 return rc;
2234 }
2235 State.GCPtrSegBase = SelInfo.GCPtrBase;
2236 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2237 State.cbSegLimit = SelInfo.cbLimit;
2238 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2239 }
2240 }
2241 else
2242 {
2243 /* real or V86 mode */
2244 pCpu->mode = CPUMODE_16BIT;
2245 State.GCPtrSegBase = pCtx->cs * 16;
2246 State.GCPtrSegEnd = 0xFFFFFFFF;
2247 State.cbSegLimit = 0xFFFFFFFF;
2248 }
2249
2250 /*
2251 * Disassemble the instruction.
2252 */
2253 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2254 pCpu->apvUserData[0] = &State;
2255
2256 uint32_t cbInstr;
2257#ifndef LOG_ENABLED
2258 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2259 if (RT_SUCCESS(rc))
2260 {
2261#else
2262 char szOutput[160];
2263 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2264 if (RT_SUCCESS(rc))
2265 {
2266 /* log it */
2267 if (pszPrefix)
2268 Log(("%s: %s", pszPrefix, szOutput));
2269 else
2270 Log(("%s", szOutput));
2271#endif
2272 rc = VINF_SUCCESS;
2273 }
2274 else
2275 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2276
2277 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2278 if (State.fLocked)
2279 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2280
2281 return rc;
2282}
2283
2284#ifdef DEBUG
2285
2286/**
2287 * Disassemble an instruction and dump it to the log
2288 *
2289 * @returns VBox status code.
2290 * @param pVM VM Handle
2291 * @param pCtx CPU context
2292 * @param pc GC instruction pointer
2293 * @param pszPrefix String prefix for logging
2294 *
2295 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2296 */
2297VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2298{
2299 DISCPUSTATE Cpu;
2300 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &Cpu, pszPrefix);
2301}
2302
2303
2304/**
2305 * Disassemble an instruction and dump it to the log
2306 *
2307 * @returns VBox status code.
2308 * @param pVM VM Handle
2309 * @param pCtx CPU context
2310 * @param pc GC instruction pointer
2311 * @param pszPrefix String prefix for logging
2312 * @param nrInstructions
2313 *
2314 * @deprecated Create new DBGFR3Disas function to do this.
2315 */
2316VMMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix, int nrInstructions)
2317{
2318 for (int i = 0; i < nrInstructions; i++)
2319 {
2320 DISCPUSTATE cpu;
2321
2322 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, pszPrefix);
2323 pc += cpu.opsize;
2324 }
2325}
2326
2327
2328/**
2329 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2330 *
2331 * @internal
2332 */
2333VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2334{
2335 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
2336}
2337
2338#endif /* DEBUG */
2339
2340/**
2341 * API for controlling a few of the CPU features found in CR4.
2342 *
2343 * Currently only X86_CR4_TSD is accepted as input.
2344 *
2345 * @returns VBox status code.
2346 *
2347 * @param pVM The VM handle.
2348 * @param fOr The CR4 OR mask.
2349 * @param fAnd The CR4 AND mask.
2350 */
2351VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2352{
2353 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2354 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2355
2356 pVM->cpum.s.CR4.OrMask &= fAnd;
2357 pVM->cpum.s.CR4.OrMask |= fOr;
2358
2359 return VINF_SUCCESS;
2360}
2361
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