VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 13960

Last change on this file since 13960 was 13960, checked in by vboxsync, 16 years ago

Moved guest and host CPU contexts into per-VCPU array.
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File size: 108.2 KB
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1/* $Id: CPUM.cpp 13960 2008-11-07 13:04:45Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 8
71/** The saved state version of 1.6, used for backwards compatability. */
72#define CPUM_SAVED_STATE_VERSION_VER1_6 6
73
74
75/*******************************************************************************
76* Structures and Typedefs *
77*******************************************************************************/
78
79/**
80 * What kind of cpu info dump to perform.
81 */
82typedef enum CPUMDUMPTYPE
83{
84 CPUMDUMPTYPE_TERSE,
85 CPUMDUMPTYPE_DEFAULT,
86 CPUMDUMPTYPE_VERBOSE
87
88} CPUMDUMPTYPE;
89/** Pointer to a cpu info dump type. */
90typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
91
92
93/*******************************************************************************
94* Internal Functions *
95*******************************************************************************/
96static int cpumR3CpuIdInit(PVM pVM);
97static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
98static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
99static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
100static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105
106
107/**
108 * Initializes the CPUM.
109 *
110 * @returns VBox status code.
111 * @param pVM The VM to operate on.
112 */
113VMMR3DECL(int) CPUMR3Init(PVM pVM)
114{
115 LogFlow(("CPUMR3Init\n"));
116
117 /*
118 * Assert alignment and sizes.
119 */
120 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
121 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
122
123 /*
124 * Setup any fixed pointers and offsets.
125 */
126 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
127 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
128
129 /* Hidden selector registers are invalid by default. */
130 pVM->cpum.s.fValidHiddenSelRegs = false;
131
132 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
133 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
134 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
135
136 /* Calculate the offset from CPUMCPU to CPUM. */
137 for (unsigned i=0;i<pVM->cCPUs;i++)
138 {
139 pVM->aCpus[i].cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
140 Assert((uintptr_t)&pVM->aCpus[i].cpum - pVM->aCpus[i].cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
141 }
142
143 /*
144 * Check that the CPU supports the minimum features we require.
145 */
146 if (!ASMHasCpuId())
147 {
148 Log(("The CPU doesn't support CPUID!\n"));
149 return VERR_UNSUPPORTED_CPU;
150 }
151 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
152 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
153
154 /* Setup the CR4 AND and OR masks used in the switcher */
155 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
156 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
157 {
158 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
159 /* No FXSAVE implies no SSE */
160 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
161 pVM->cpum.s.CR4.OrMask = 0;
162 }
163 else
164 {
165 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
166 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
167 }
168
169 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
170 {
171 Log(("The CPU doesn't support MMX!\n"));
172 return VERR_UNSUPPORTED_CPU;
173 }
174 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
175 {
176 Log(("The CPU doesn't support TSC!\n"));
177 return VERR_UNSUPPORTED_CPU;
178 }
179 /* Bogus on AMD? */
180 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
181 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
182
183 /*
184 * Setup hypervisor startup values.
185 */
186
187 /*
188 * Register saved state data item.
189 */
190 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
191 NULL, cpumR3Save, NULL,
192 NULL, cpumR3Load, NULL);
193 if (RT_FAILURE(rc))
194 return rc;
195
196 /* Query the CPU manufacturer. */
197 uint32_t uEAX, uEBX, uECX, uEDX;
198 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
199 if ( uEAX >= 1
200 && uEBX == X86_CPUID_VENDOR_AMD_EBX
201 && uECX == X86_CPUID_VENDOR_AMD_ECX
202 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
203 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
204 else if ( uEAX >= 1
205 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
206 && uECX == X86_CPUID_VENDOR_INTEL_ECX
207 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
208 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
209 else /** @todo Via */
210 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
211
212 /*
213 * Register info handlers.
214 */
215 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
216 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
217 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
218 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
219 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
220 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
221
222 /*
223 * Initialize the Guest CPU state.
224 */
225 rc = cpumR3CpuIdInit(pVM);
226 if (RT_FAILURE(rc))
227 return rc;
228 CPUMR3Reset(pVM);
229 return VINF_SUCCESS;
230}
231
232
233/**
234 * Initializes the per-VCPU CPUM.
235 *
236 * @returns VBox status code.
237 * @param pVM The VM to operate on.
238 */
239VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
240{
241 LogFlow(("CPUMR3InitCPU\n"));
242 return VINF_SUCCESS;
243}
244
245
246/**
247 * Initializes the emulated CPU's cpuid information.
248 *
249 * @returns VBox status code.
250 * @param pVM The VM to operate on.
251 */
252static int cpumR3CpuIdInit(PVM pVM)
253{
254 PCPUM pCPUM = &pVM->cpum.s;
255 uint32_t i;
256
257 /*
258 * Get the host CPUIDs.
259 */
260 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
261 ASMCpuId_Idx_ECX(i, 0,
262 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
263 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
264 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
265 ASMCpuId(0x80000000 + i,
266 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
267 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
268 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
269 ASMCpuId(0xc0000000 + i,
270 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
271 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
272
273
274 /*
275 * Only report features we can support.
276 */
277 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
278 | X86_CPUID_FEATURE_EDX_VME
279 | X86_CPUID_FEATURE_EDX_DE
280 | X86_CPUID_FEATURE_EDX_PSE
281 | X86_CPUID_FEATURE_EDX_TSC
282 | X86_CPUID_FEATURE_EDX_MSR
283 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
284 | X86_CPUID_FEATURE_EDX_MCE
285 | X86_CPUID_FEATURE_EDX_CX8
286 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
287 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
288 //| X86_CPUID_FEATURE_EDX_SEP
289 | X86_CPUID_FEATURE_EDX_MTRR
290 | X86_CPUID_FEATURE_EDX_PGE
291 | X86_CPUID_FEATURE_EDX_MCA
292 | X86_CPUID_FEATURE_EDX_CMOV
293 | X86_CPUID_FEATURE_EDX_PAT
294 | X86_CPUID_FEATURE_EDX_PSE36
295 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
296 | X86_CPUID_FEATURE_EDX_CLFSH
297 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
298 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
299 | X86_CPUID_FEATURE_EDX_MMX
300 | X86_CPUID_FEATURE_EDX_FXSR
301 | X86_CPUID_FEATURE_EDX_SSE
302 | X86_CPUID_FEATURE_EDX_SSE2
303 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
304 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
305 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
306 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
307 | 0;
308 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
309 | X86_CPUID_FEATURE_ECX_MONITOR
310 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
311 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
312 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
313 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
314 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
315 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
316 //| X86_CPUID_FEATURE_ECX_CX16
317 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
318 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
319 /* ECX Bit 21 - x2APIC support - not yet. */
320 // | X86_CPUID_FEATURE_ECX_X2APIC
321 /* ECX Bit 23 - POPCOUNT instruction. */
322 //| X86_CPUID_FEATURE_ECX_POPCOUNT
323 | 0;
324
325 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
326 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
327 | X86_CPUID_AMD_FEATURE_EDX_VME
328 | X86_CPUID_AMD_FEATURE_EDX_DE
329 | X86_CPUID_AMD_FEATURE_EDX_PSE
330 | X86_CPUID_AMD_FEATURE_EDX_TSC
331 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
332 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
333 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
334 | X86_CPUID_AMD_FEATURE_EDX_CX8
335 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
336 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
337 //| X86_CPUID_AMD_FEATURE_EDX_SEP
338 | X86_CPUID_AMD_FEATURE_EDX_MTRR
339 | X86_CPUID_AMD_FEATURE_EDX_PGE
340 | X86_CPUID_AMD_FEATURE_EDX_MCA
341 | X86_CPUID_AMD_FEATURE_EDX_CMOV
342 | X86_CPUID_AMD_FEATURE_EDX_PAT
343 | X86_CPUID_AMD_FEATURE_EDX_PSE36
344 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
345 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
346 | X86_CPUID_AMD_FEATURE_EDX_MMX
347 | X86_CPUID_AMD_FEATURE_EDX_FXSR
348 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
349 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
350 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
351 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
352 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
353 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
354 | 0;
355 pCPUM->aGuestCpuIdExt[1].ecx &= 0
356 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
357 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
358 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
359 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
360 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
361 //| X86_CPUID_AMD_FEATURE_ECX_ABM
362 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
363 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
364 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
365 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
366 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
367 //| X86_CPUID_AMD_FEATURE_ECX_WDT
368 | 0;
369
370 /*
371 * Hide HTT, multicode, SMP, whatever.
372 * (APIC-ID := 0 and #LogCpus := 0)
373 */
374 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
375
376 /* Cpuid 2:
377 * Intel: Cache and TLB information
378 * AMD: Reserved
379 * Safe to expose
380 */
381
382 /* Cpuid 3:
383 * Intel: EAX, EBX - reserved
384 * ECX, EDX - Processor Serial Number if available, otherwise reserved
385 * AMD: Reserved
386 * Safe to expose
387 */
388 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
389 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
390
391 /* Cpuid 4:
392 * Intel: Deterministic Cache Parameters Leaf
393 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
394 * AMD: Reserved
395 * Safe to expose, except for EAX:
396 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
397 * Bits 31-26: Maximum number of processor cores in this physical package**
398 */
399 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
400 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
401
402 /* Cpuid 5: Monitor/mwait Leaf
403 * Intel: ECX, EDX - reserved
404 * EAX, EBX - Smallest and largest monitor line size
405 * AMD: EDX - reserved
406 * EAX, EBX - Smallest and largest monitor line size
407 * ECX - extensions (ignored for now)
408 * Safe to expose
409 */
410 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
411 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
412
413 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
414
415 /*
416 * Determine the default.
417 *
418 * Intel returns values of the highest standard function, while AMD
419 * returns zeros. VIA on the other hand seems to returning nothing or
420 * perhaps some random garbage, we don't try to duplicate this behavior.
421 */
422 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
423 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
424 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
425
426 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
427 * Safe to pass on to the guest.
428 *
429 * Intel: 0x800000005 reserved
430 * 0x800000006 L2 cache information
431 * AMD: 0x800000005 L1 cache information
432 * 0x800000006 L2/L3 cache information
433 */
434
435 /* Cpuid 0x800000007:
436 * AMD: EAX, EBX, ECX - reserved
437 * EDX: Advanced Power Management Information
438 * Intel: Reserved
439 */
440 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
441 {
442 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
443
444 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
445
446 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
447 {
448 /* Only expose the TSC invariant capability bit to the guest. */
449 pCPUM->aGuestCpuIdExt[7].edx &= 0
450 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
451 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
452 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
453 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
454 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
455 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
456 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
457 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
458 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
459 | 0;
460 }
461 else
462 pCPUM->aGuestCpuIdExt[7].edx = 0;
463 }
464
465 /* Cpuid 0x800000008:
466 * AMD: EBX, EDX - reserved
467 * EAX: Virtual/Physical address Size
468 * ECX: Number of cores + APICIdCoreIdSize
469 * Intel: EAX: Virtual/Physical address Size
470 * EBX, ECX, EDX - reserved
471 */
472 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
473 {
474 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
475 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
476 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
477 * NC (0-7) Number of cores; 0 equals 1 core */
478 pCPUM->aGuestCpuIdExt[8].ecx = 0;
479 }
480
481 /*
482 * Limit it the number of entries and fill the remaining with the defaults.
483 *
484 * The limits are masking off stuff about power saving and similar, this
485 * is perhaps a bit crudely done as there is probably some relatively harmless
486 * info too in these leaves (like words about having a constant TSC).
487 */
488#if 0
489 /** @todo NT4 installation regression - investigate */
490 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
491 pCPUM->aGuestCpuIdStd[0].eax = 5;
492#else
493 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
494 pCPUM->aGuestCpuIdStd[0].eax = 2;
495#endif
496 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
497 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
498
499 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
500 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
501 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
502 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
503 : 0;
504 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
505 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
506
507 /*
508 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
509 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
510 * We currently don't support more than 1 processor.
511 */
512 pCPUM->aGuestCpuIdStd[4].eax = 0;
513
514 /*
515 * Centaur stuff (VIA).
516 *
517 * The important part here (we think) is to make sure the 0xc0000000
518 * function returns 0xc0000001. As for the features, we don't currently
519 * let on about any of those... 0xc0000002 seems to be some
520 * temperature/hz/++ stuff, include it as well (static).
521 */
522 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
523 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
524 {
525 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
526 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
527 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
528 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
529 i++)
530 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
531 }
532 else
533 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
534 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
535
536
537 /*
538 * Load CPUID overrides from configuration.
539 */
540 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
541 * Overloads the CPUID leaf values. */
542 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
543 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
544 for (i=0;; )
545 {
546 while (cElements-- > 0)
547 {
548 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
549 if (pNode)
550 {
551 uint32_t u32;
552 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
553 if (RT_SUCCESS(rc))
554 pCpuId->eax = u32;
555 else
556 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
557
558 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
559 if (RT_SUCCESS(rc))
560 pCpuId->ebx = u32;
561 else
562 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
563
564 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
565 if (RT_SUCCESS(rc))
566 pCpuId->ecx = u32;
567 else
568 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
569
570 rc = CFGMR3QueryU32(pNode, "edx", &u32);
571 if (RT_SUCCESS(rc))
572 pCpuId->edx = u32;
573 else
574 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
575 }
576 pCpuId++;
577 i++;
578 }
579
580 /* next */
581 if ((i & UINT32_C(0xc0000000)) == 0)
582 {
583 pCpuId = &pCPUM->aGuestCpuIdExt[0];
584 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
585 i = UINT32_C(0x80000000);
586 }
587 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
588 {
589 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
590 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
591 i = UINT32_C(0xc0000000);
592 }
593 else
594 break;
595 }
596
597 /* Check if PAE was explicitely enabled by the user. */
598 bool fEnable = false;
599 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
600 if (RT_SUCCESS(rc) && fEnable)
601 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
602
603 /*
604 * Log the cpuid and we're good.
605 */
606 RTCPUSET OnlineSet;
607 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
608 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
609 LogRel(("************************* CPUID dump ************************\n"));
610 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
611 LogRel(("\n"));
612 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
613 LogRel(("******************** End of CPUID dump **********************\n"));
614 return VINF_SUCCESS;
615}
616
617
618
619
620/**
621 * Applies relocations to data and code managed by this
622 * component. This function will be called at init and
623 * whenever the VMM need to relocate it self inside the GC.
624 *
625 * The CPUM will update the addresses used by the switcher.
626 *
627 * @param pVM The VM.
628 */
629VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
630{
631 LogFlow(("CPUMR3Relocate\n"));
632 /*
633 * Switcher pointers.
634 */
635 pVM->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
636 Assert(pVM->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
637}
638
639
640/**
641 * Terminates the CPUM.
642 *
643 * Termination means cleaning up and freeing all resources,
644 * the VM it self is at this point powered off or suspended.
645 *
646 * @returns VBox status code.
647 * @param pVM The VM to operate on.
648 */
649VMMR3DECL(int) CPUMR3Term(PVM pVM)
650{
651 /** @todo ? */
652 return 0;
653}
654
655
656/**
657 * Terminates the per-VCPU CPUM.
658 *
659 * Termination means cleaning up and freeing all resources,
660 * the VM it self is at this point powered off or suspended.
661 *
662 * @returns VBox status code.
663 * @param pVM The VM to operate on.
664 */
665VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
666{
667 return 0;
668}
669
670
671/**
672 * Resets the CPU.
673 *
674 * @returns VINF_SUCCESS.
675 * @param pVM The VM handle.
676 */
677VMMR3DECL(void) CPUMR3Reset(PVM pVM)
678{
679 /* @todo anything different for VCPU > 0? */
680 for (unsigned i=0;i<pVM->cCPUs;i++)
681 {
682 PCPUMCTX pCtx = CPUMQueryGuestCtxPtrEx(pVM, &pVM->aCpus[i]);
683
684 /*
685 * Initialize everything to ZERO first.
686 */
687 uint32_t fUseFlags = pVM->aCpus[i].cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
688 memset(pCtx, 0, sizeof(*pCtx));
689 pVM->aCpus[i].cpum.s.fUseFlags = fUseFlags;
690
691 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
692 pCtx->eip = 0x0000fff0;
693 pCtx->edx = 0x00000600; /* P6 processor */
694 pCtx->eflags.Bits.u1Reserved0 = 1;
695
696 pCtx->cs = 0xf000;
697 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
698 pCtx->csHid.u32Limit = 0x0000ffff;
699 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
700 pCtx->csHid.Attr.n.u1Present = 1;
701 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
702
703 pCtx->dsHid.u32Limit = 0x0000ffff;
704 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
705 pCtx->dsHid.Attr.n.u1Present = 1;
706 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
707
708 pCtx->esHid.u32Limit = 0x0000ffff;
709 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
710 pCtx->esHid.Attr.n.u1Present = 1;
711 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
712
713 pCtx->fsHid.u32Limit = 0x0000ffff;
714 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
715 pCtx->fsHid.Attr.n.u1Present = 1;
716 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
717
718 pCtx->gsHid.u32Limit = 0x0000ffff;
719 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
720 pCtx->gsHid.Attr.n.u1Present = 1;
721 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
722
723 pCtx->ssHid.u32Limit = 0x0000ffff;
724 pCtx->ssHid.Attr.n.u1Present = 1;
725 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
726 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
727
728 pCtx->idtr.cbIdt = 0xffff;
729 pCtx->gdtr.cbGdt = 0xffff;
730
731 pCtx->ldtrHid.u32Limit = 0xffff;
732 pCtx->ldtrHid.Attr.n.u1Present = 1;
733 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
734
735 pCtx->trHid.u32Limit = 0xffff;
736 pCtx->trHid.Attr.n.u1Present = 1;
737 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
738
739 pCtx->dr[6] = X86_DR6_INIT_VAL;
740 pCtx->dr[7] = X86_DR7_INIT_VAL;
741
742 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
743 pCtx->fpu.FCW = 0x37f;
744
745 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
746 pCtx->fpu.MXCSR = 0x1F80;
747
748 /* Init PAT MSR */
749 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
750
751 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
752 * The Intel docs don't mention it.
753 */
754 pCtx->msrEFER = 0;
755 }
756}
757
758
759/**
760 * Execute state save operation.
761 *
762 * @returns VBox status code.
763 * @param pVM VM Handle.
764 * @param pSSM SSM operation handle.
765 */
766static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
767{
768 /* Set the size of RTGCPTR for use of SSMR3Get/PutGCPtr. */
769 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
770
771 /*
772 * Save.
773 */
774 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
775
776 for (unsigned i=0;i<pVM->cCPUs;i++)
777 {
778 SSMR3PutMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
779 SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fUseFlags);
780 SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fChanged);
781 }
782
783 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
784 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
785
786 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
787 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
788
789 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
790 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
791
792 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
793
794 /* Add the cpuid for checking that the cpu is unchanged. */
795 uint32_t au32CpuId[8] = {0};
796 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
797 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
798 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
799}
800
801
802/**
803 * Load a version 1.6 CPUMCTX structure.
804 *
805 * @returns VBox status code.
806 * @param pVM VM Handle.
807 * @param pCpumctx16 Version 1.6 CPUMCTX
808 */
809static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
810{
811#define CPUMCTX16_LOADREG(RegName) \
812 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
813
814#define CPUMCTX16_LOADDRXREG(RegName) \
815 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
816
817#define CPUMCTX16_LOADHIDREG(RegName) \
818 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
819 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
820 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
821
822#define CPUMCTX16_LOADSEGREG(RegName) \
823 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
824 CPUMCTX16_LOADHIDREG(RegName);
825
826 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
827
828 CPUMCTX16_LOADREG(rax);
829 CPUMCTX16_LOADREG(rbx);
830 CPUMCTX16_LOADREG(rcx);
831 CPUMCTX16_LOADREG(rdx);
832 CPUMCTX16_LOADREG(rdi);
833 CPUMCTX16_LOADREG(rsi);
834 CPUMCTX16_LOADREG(rbp);
835 CPUMCTX16_LOADREG(esp);
836 CPUMCTX16_LOADREG(rip);
837 CPUMCTX16_LOADREG(rflags);
838
839 CPUMCTX16_LOADSEGREG(cs);
840 CPUMCTX16_LOADSEGREG(ds);
841 CPUMCTX16_LOADSEGREG(es);
842 CPUMCTX16_LOADSEGREG(fs);
843 CPUMCTX16_LOADSEGREG(gs);
844 CPUMCTX16_LOADSEGREG(ss);
845
846 CPUMCTX16_LOADREG(r8);
847 CPUMCTX16_LOADREG(r9);
848 CPUMCTX16_LOADREG(r10);
849 CPUMCTX16_LOADREG(r11);
850 CPUMCTX16_LOADREG(r12);
851 CPUMCTX16_LOADREG(r13);
852 CPUMCTX16_LOADREG(r14);
853 CPUMCTX16_LOADREG(r15);
854
855 CPUMCTX16_LOADREG(cr0);
856 CPUMCTX16_LOADREG(cr2);
857 CPUMCTX16_LOADREG(cr3);
858 CPUMCTX16_LOADREG(cr4);
859
860 CPUMCTX16_LOADDRXREG(0);
861 CPUMCTX16_LOADDRXREG(1);
862 CPUMCTX16_LOADDRXREG(2);
863 CPUMCTX16_LOADDRXREG(3);
864 CPUMCTX16_LOADDRXREG(4);
865 CPUMCTX16_LOADDRXREG(5);
866 CPUMCTX16_LOADDRXREG(6);
867 CPUMCTX16_LOADDRXREG(7);
868
869 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
870 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
871 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
872 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
873
874 CPUMCTX16_LOADREG(ldtr);
875 CPUMCTX16_LOADREG(tr);
876
877 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
878
879 CPUMCTX16_LOADREG(msrEFER);
880 CPUMCTX16_LOADREG(msrSTAR);
881 CPUMCTX16_LOADREG(msrPAT);
882 CPUMCTX16_LOADREG(msrLSTAR);
883 CPUMCTX16_LOADREG(msrCSTAR);
884 CPUMCTX16_LOADREG(msrSFMASK);
885 CPUMCTX16_LOADREG(msrKERNELGSBASE);
886
887 CPUMCTX16_LOADHIDREG(ldtr);
888 CPUMCTX16_LOADHIDREG(tr);
889
890#undef CPUMCTX16_LOADSEGREG
891#undef CPUMCTX16_LOADHIDREG
892#undef CPUMCTX16_LOADDRXREG
893#undef CPUMCTX16_LOADREG
894}
895
896
897/**
898 * Execute state load operation.
899 *
900 * @returns VBox status code.
901 * @param pVM VM Handle.
902 * @param pSSM SSM operation handle.
903 * @param u32Version Data layout version.
904 */
905static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
906{
907 /*
908 * Validate version.
909 */
910 if ( u32Version != CPUM_SAVED_STATE_VERSION
911 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
912 {
913 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
914 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
915 }
916
917 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
918 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
919 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
920 else
921 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
922
923 /*
924 * Restore.
925 */
926 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
927 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
928 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
929 pVM->cpum.s.Hyper.cr3 = uCR3;
930 pVM->cpum.s.Hyper.esp = uESP;
931 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
932 {
933 CPUMCTX_VER1_6 cpumctx16;
934 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
935 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
936
937 /* Save the old cpumctx state into the new one. */
938 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
939
940 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
941 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
942 }
943 else
944 {
945 for (unsigned i=0;i<pVM->cCPUs;i++)
946 {
947 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
948 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
949 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
950 }
951 }
952
953
954 uint32_t cElements;
955 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
956 /* Support old saved states with a smaller standard cpuid array. */
957 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
958 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
959 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
960
961 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
962 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
963 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
964 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
965
966 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
967 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
968 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
969 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
970
971 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
972
973 /*
974 * Check that the basic cpuid id information is unchanged.
975 */
976 uint32_t au32CpuId[8] = {0};
977 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
978 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
979 uint32_t au32CpuIdSaved[8];
980 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
981 if (RT_SUCCESS(rc))
982 {
983 /* Ignore APIC ID (AMD specs). */
984 au32CpuId[5] &= ~0xff000000;
985 au32CpuIdSaved[5] &= ~0xff000000;
986 /* Ignore the number of Logical CPUs (AMD specs). */
987 au32CpuId[5] &= ~0x00ff0000;
988 au32CpuIdSaved[5] &= ~0x00ff0000;
989
990 /* do the compare */
991 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
992 {
993 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
994 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
995 "Saved=%.*Rhxs\n"
996 "Real =%.*Rhxs\n",
997 sizeof(au32CpuIdSaved), au32CpuIdSaved,
998 sizeof(au32CpuId), au32CpuId));
999 else
1000 {
1001 LogRel(("cpumR3Load: CpuId mismatch!\n"
1002 "Saved=%.*Rhxs\n"
1003 "Real =%.*Rhxs\n",
1004 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1005 sizeof(au32CpuId), au32CpuId));
1006 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1007 }
1008 }
1009 }
1010
1011 return rc;
1012}
1013
1014
1015/**
1016 * Formats the EFLAGS value into mnemonics.
1017 *
1018 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1019 * @param efl The EFLAGS value.
1020 */
1021static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1022{
1023 /*
1024 * Format the flags.
1025 */
1026 static const struct
1027 {
1028 const char *pszSet; const char *pszClear; uint32_t fFlag;
1029 } s_aFlags[] =
1030 {
1031 { "vip",NULL, X86_EFL_VIP },
1032 { "vif",NULL, X86_EFL_VIF },
1033 { "ac", NULL, X86_EFL_AC },
1034 { "vm", NULL, X86_EFL_VM },
1035 { "rf", NULL, X86_EFL_RF },
1036 { "nt", NULL, X86_EFL_NT },
1037 { "ov", "nv", X86_EFL_OF },
1038 { "dn", "up", X86_EFL_DF },
1039 { "ei", "di", X86_EFL_IF },
1040 { "tf", NULL, X86_EFL_TF },
1041 { "nt", "pl", X86_EFL_SF },
1042 { "nz", "zr", X86_EFL_ZF },
1043 { "ac", "na", X86_EFL_AF },
1044 { "po", "pe", X86_EFL_PF },
1045 { "cy", "nc", X86_EFL_CF },
1046 };
1047 char *psz = pszEFlags;
1048 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1049 {
1050 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1051 if (pszAdd)
1052 {
1053 strcpy(psz, pszAdd);
1054 psz += strlen(pszAdd);
1055 *psz++ = ' ';
1056 }
1057 }
1058 psz[-1] = '\0';
1059}
1060
1061
1062/**
1063 * Formats a full register dump.
1064 *
1065 * @param pVM VM Handle.
1066 * @param pCtx The context to format.
1067 * @param pCtxCore The context core to format.
1068 * @param pHlp Output functions.
1069 * @param enmType The dump type.
1070 * @param pszPrefix Register name prefix.
1071 */
1072static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1073{
1074 /*
1075 * Format the EFLAGS.
1076 */
1077 uint32_t efl = pCtxCore->eflags.u32;
1078 char szEFlags[80];
1079 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1080
1081 /*
1082 * Format the registers.
1083 */
1084 switch (enmType)
1085 {
1086 case CPUMDUMPTYPE_TERSE:
1087 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1088 pHlp->pfnPrintf(pHlp,
1089 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1090 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1091 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1092 "%sr14=%016RX64 %sr15=%016RX64\n"
1093 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1094 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1095 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1096 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1097 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1098 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1099 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1100 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1101 else
1102 pHlp->pfnPrintf(pHlp,
1103 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1104 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1105 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1106 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1107 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1108 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1109 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1110 break;
1111
1112 case CPUMDUMPTYPE_DEFAULT:
1113 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1114 pHlp->pfnPrintf(pHlp,
1115 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1116 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1117 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1118 "%sr14=%016RX64 %sr15=%016RX64\n"
1119 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1120 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1121 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1122 ,
1123 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1124 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1125 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1126 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1127 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1128 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1129 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1130 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1131 else
1132 pHlp->pfnPrintf(pHlp,
1133 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1134 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1135 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1136 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1137 ,
1138 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1139 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1140 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1141 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1142 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1143 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1144 break;
1145
1146 case CPUMDUMPTYPE_VERBOSE:
1147 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1148 pHlp->pfnPrintf(pHlp,
1149 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1150 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1151 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1152 "%sr14=%016RX64 %sr15=%016RX64\n"
1153 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1154 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1155 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1156 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1157 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1158 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1159 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1160 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1161 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1162 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1163 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1164 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1165 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1166 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1167 ,
1168 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1169 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1170 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1171 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1172 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1173 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1174 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1175 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1176 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1177 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1178 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1179 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1180 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1181 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1182 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1183 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1184 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1185 else
1186 pHlp->pfnPrintf(pHlp,
1187 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1188 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1189 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1190 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1191 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1192 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1193 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1194 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1195 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1196 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1197 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1198 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1199 ,
1200 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1201 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1202 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1203 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1204 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1205 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1206 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1207 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1208 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1209 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1210 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1211 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1212
1213 pHlp->pfnPrintf(pHlp,
1214 "FPU:\n"
1215 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1216 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1217 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1218 ,
1219 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1220 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1221 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1222 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1223
1224 pHlp->pfnPrintf(pHlp,
1225 "MSR:\n"
1226 "%sEFER =%016RX64\n"
1227 "%sPAT =%016RX64\n"
1228 "%sSTAR =%016RX64\n"
1229 "%sCSTAR =%016RX64\n"
1230 "%sLSTAR =%016RX64\n"
1231 "%sSFMASK =%016RX64\n"
1232 "%sKERNELGSBASE =%016RX64\n",
1233 pszPrefix, pCtx->msrEFER,
1234 pszPrefix, pCtx->msrPAT,
1235 pszPrefix, pCtx->msrSTAR,
1236 pszPrefix, pCtx->msrCSTAR,
1237 pszPrefix, pCtx->msrLSTAR,
1238 pszPrefix, pCtx->msrSFMASK,
1239 pszPrefix, pCtx->msrKERNELGSBASE);
1240 break;
1241 }
1242}
1243
1244
1245/**
1246 * Display all cpu states and any other cpum info.
1247 *
1248 * @param pVM VM Handle.
1249 * @param pHlp The info helper functions.
1250 * @param pszArgs Arguments, ignored.
1251 */
1252static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1253{
1254 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1255 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1256 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1257 cpumR3InfoHost(pVM, pHlp, pszArgs);
1258}
1259
1260
1261/**
1262 * Parses the info argument.
1263 *
1264 * The argument starts with 'verbose', 'terse' or 'default' and then
1265 * continues with the comment string.
1266 *
1267 * @param pszArgs The pointer to the argument string.
1268 * @param penmType Where to store the dump type request.
1269 * @param ppszComment Where to store the pointer to the comment string.
1270 */
1271static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1272{
1273 if (!pszArgs)
1274 {
1275 *penmType = CPUMDUMPTYPE_DEFAULT;
1276 *ppszComment = "";
1277 }
1278 else
1279 {
1280 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1281 {
1282 pszArgs += 5;
1283 *penmType = CPUMDUMPTYPE_VERBOSE;
1284 }
1285 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1286 {
1287 pszArgs += 5;
1288 *penmType = CPUMDUMPTYPE_TERSE;
1289 }
1290 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1291 {
1292 pszArgs += 7;
1293 *penmType = CPUMDUMPTYPE_DEFAULT;
1294 }
1295 else
1296 *penmType = CPUMDUMPTYPE_DEFAULT;
1297 *ppszComment = RTStrStripL(pszArgs);
1298 }
1299}
1300
1301
1302/**
1303 * Display the guest cpu state.
1304 *
1305 * @param pVM VM Handle.
1306 * @param pHlp The info helper functions.
1307 * @param pszArgs Arguments, ignored.
1308 */
1309static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1310{
1311 CPUMDUMPTYPE enmType;
1312 const char *pszComment;
1313 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1314 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1315 /* @todo SMP */
1316 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVM);
1317 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1318}
1319
1320
1321/**
1322 * Display the current guest instruction
1323 *
1324 * @param pVM VM Handle.
1325 * @param pHlp The info helper functions.
1326 * @param pszArgs Arguments, ignored.
1327 */
1328static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1329{
1330 char szInstruction[256];
1331 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1332 if (RT_SUCCESS(rc))
1333 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1334}
1335
1336
1337/**
1338 * Display the hypervisor cpu state.
1339 *
1340 * @param pVM VM Handle.
1341 * @param pHlp The info helper functions.
1342 * @param pszArgs Arguments, ignored.
1343 */
1344static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1345{
1346 CPUMDUMPTYPE enmType;
1347 const char *pszComment;
1348 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1349 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1350 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1351 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1352}
1353
1354
1355/**
1356 * Display the host cpu state.
1357 *
1358 * @param pVM VM Handle.
1359 * @param pHlp The info helper functions.
1360 * @param pszArgs Arguments, ignored.
1361 */
1362static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1363{
1364 CPUMDUMPTYPE enmType;
1365 const char *pszComment;
1366 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1367 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1368
1369 /*
1370 * Format the EFLAGS.
1371 */
1372 /* @todo SMP */
1373 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1374#if HC_ARCH_BITS == 32
1375 uint32_t efl = pCtx->eflags.u32;
1376#else
1377 uint64_t efl = pCtx->rflags;
1378#endif
1379 char szEFlags[80];
1380 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1381
1382 /*
1383 * Format the registers.
1384 */
1385#if HC_ARCH_BITS == 32
1386# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1387 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1388# endif
1389 {
1390 pHlp->pfnPrintf(pHlp,
1391 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1392 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1393 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1394 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1395 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1396 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1397 ,
1398 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1399 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1400 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1401 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1402 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1403 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1404 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1405 }
1406# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1407 else
1408# endif
1409#endif
1410#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1411 {
1412 pHlp->pfnPrintf(pHlp,
1413 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1414 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1415 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1416 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1417 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1418 "r14=%016RX64 r15=%016RX64\n"
1419 "iopl=%d %31s\n"
1420 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1421 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1422 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1423 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1424 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1425 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1426 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1427 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1428 ,
1429 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1430 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1431 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1432 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1433 pCtx->r11, pCtx->r12, pCtx->r13,
1434 pCtx->r14, pCtx->r15,
1435 X86_EFL_GET_IOPL(efl), szEFlags,
1436 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1437 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1438 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1439 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1440 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1441 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1442 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1443 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1444 }
1445#endif
1446}
1447
1448
1449/**
1450 * Get L1 cache / TLS associativity.
1451 */
1452static const char *getCacheAss(unsigned u, char *pszBuf)
1453{
1454 if (u == 0)
1455 return "res0 ";
1456 if (u == 1)
1457 return "direct";
1458 if (u >= 256)
1459 return "???";
1460
1461 RTStrPrintf(pszBuf, 16, "%d way", u);
1462 return pszBuf;
1463}
1464
1465
1466/**
1467 * Get L2 cache soociativity.
1468 */
1469const char *getL2CacheAss(unsigned u)
1470{
1471 switch (u)
1472 {
1473 case 0: return "off ";
1474 case 1: return "direct";
1475 case 2: return "2 way ";
1476 case 3: return "res3 ";
1477 case 4: return "4 way ";
1478 case 5: return "res5 ";
1479 case 6: return "8 way "; case 7: return "res7 ";
1480 case 8: return "16 way";
1481 case 9: return "res9 ";
1482 case 10: return "res10 ";
1483 case 11: return "res11 ";
1484 case 12: return "res12 ";
1485 case 13: return "res13 ";
1486 case 14: return "res14 ";
1487 case 15: return "fully ";
1488 default:
1489 return "????";
1490 }
1491}
1492
1493
1494/**
1495 * Display the guest CpuId leaves.
1496 *
1497 * @param pVM VM Handle.
1498 * @param pHlp The info helper functions.
1499 * @param pszArgs "terse", "default" or "verbose".
1500 */
1501static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1502{
1503 /*
1504 * Parse the argument.
1505 */
1506 unsigned iVerbosity = 1;
1507 if (pszArgs)
1508 {
1509 pszArgs = RTStrStripL(pszArgs);
1510 if (!strcmp(pszArgs, "terse"))
1511 iVerbosity--;
1512 else if (!strcmp(pszArgs, "verbose"))
1513 iVerbosity++;
1514 }
1515
1516 /*
1517 * Start cracking.
1518 */
1519 CPUMCPUID Host;
1520 CPUMCPUID Guest;
1521 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1522
1523 pHlp->pfnPrintf(pHlp,
1524 " RAW Standard CPUIDs\n"
1525 " Function eax ebx ecx edx\n");
1526 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1527 {
1528 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1529 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1530
1531 pHlp->pfnPrintf(pHlp,
1532 "Gst: %08x %08x %08x %08x %08x%s\n"
1533 "Hst: %08x %08x %08x %08x\n",
1534 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1535 i <= cStdMax ? "" : "*",
1536 Host.eax, Host.ebx, Host.ecx, Host.edx);
1537 }
1538
1539 /*
1540 * If verbose, decode it.
1541 */
1542 if (iVerbosity)
1543 {
1544 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1545 pHlp->pfnPrintf(pHlp,
1546 "Name: %.04s%.04s%.04s\n"
1547 "Supports: 0-%x\n",
1548 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1549 }
1550
1551 /*
1552 * Get Features.
1553 */
1554 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1555 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1556 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1557 if (cStdMax >= 1 && iVerbosity)
1558 {
1559 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1560 uint32_t uEAX = Guest.eax;
1561
1562 pHlp->pfnPrintf(pHlp,
1563 "Family: %d \tExtended: %d \tEffective: %d\n"
1564 "Model: %d \tExtended: %d \tEffective: %d\n"
1565 "Stepping: %d\n"
1566 "APIC ID: %#04x\n"
1567 "Logical CPUs: %d\n"
1568 "CLFLUSH Size: %d\n"
1569 "Brand ID: %#04x\n",
1570 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1571 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1572 ASMGetCpuStepping(uEAX),
1573 (Guest.ebx >> 24) & 0xff,
1574 (Guest.ebx >> 16) & 0xff,
1575 (Guest.ebx >> 8) & 0xff,
1576 (Guest.ebx >> 0) & 0xff);
1577 if (iVerbosity == 1)
1578 {
1579 uint32_t uEDX = Guest.edx;
1580 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1581 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1582 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1583 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1584 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1585 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1586 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1587 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1588 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1589 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1590 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1591 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1592 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1593 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1594 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1595 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1596 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1597 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1598 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1599 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1600 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1601 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1602 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1603 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1604 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1605 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1606 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1607 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1608 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1609 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1610 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1611 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1612 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1613 pHlp->pfnPrintf(pHlp, "\n");
1614
1615 uint32_t uECX = Guest.ecx;
1616 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1617 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1618 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1619 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1620 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1621 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1622 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1623 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1624 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1625 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1626 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1627 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1628 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1629 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1630 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1631 for (unsigned iBit = 14; iBit < 32; iBit++)
1632 if (uECX & RT_BIT(iBit))
1633 pHlp->pfnPrintf(pHlp, " %d", iBit);
1634 pHlp->pfnPrintf(pHlp, "\n");
1635 }
1636 else
1637 {
1638 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1639
1640 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1641 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1642 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1643 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1644
1645 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1646 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1647 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1648 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1649 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1650 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1651 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1652 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1653 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1654 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1655 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1656 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1657 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1658 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1659 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1660 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1661 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1662 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1663 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1664 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1665 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1666 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1667 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1668 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1669 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1670 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1671 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1672 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1673 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1674 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1675 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1676 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1677 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1678
1679 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1680 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1681 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1682 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1683 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1684 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1685 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1686 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1687 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1688 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1689 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1690 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1691 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1692 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1693 }
1694 }
1695 if (cStdMax >= 2 && iVerbosity)
1696 {
1697 /** @todo */
1698 }
1699
1700 /*
1701 * Extended.
1702 * Implemented after AMD specs.
1703 */
1704 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1705
1706 pHlp->pfnPrintf(pHlp,
1707 "\n"
1708 " RAW Extended CPUIDs\n"
1709 " Function eax ebx ecx edx\n");
1710 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1711 {
1712 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1713 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1714
1715 pHlp->pfnPrintf(pHlp,
1716 "Gst: %08x %08x %08x %08x %08x%s\n"
1717 "Hst: %08x %08x %08x %08x\n",
1718 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1719 i <= cExtMax ? "" : "*",
1720 Host.eax, Host.ebx, Host.ecx, Host.edx);
1721 }
1722
1723 /*
1724 * Understandable output
1725 */
1726 if (iVerbosity)
1727 {
1728 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1729 pHlp->pfnPrintf(pHlp,
1730 "Ext Name: %.4s%.4s%.4s\n"
1731 "Ext Supports: 0x80000000-%#010x\n",
1732 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1733 }
1734
1735 if (iVerbosity && cExtMax >= 1)
1736 {
1737 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1738 uint32_t uEAX = Guest.eax;
1739 pHlp->pfnPrintf(pHlp,
1740 "Family: %d \tExtended: %d \tEffective: %d\n"
1741 "Model: %d \tExtended: %d \tEffective: %d\n"
1742 "Stepping: %d\n"
1743 "Brand ID: %#05x\n",
1744 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1745 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1746 ASMGetCpuStepping(uEAX),
1747 Guest.ebx & 0xfff);
1748
1749 if (iVerbosity == 1)
1750 {
1751 uint32_t uEDX = Guest.edx;
1752 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1753 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1754 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1755 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1756 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1757 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1758 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1759 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1760 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1761 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1762 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1763 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1764 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1765 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1766 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1767 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1768 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1769 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1770 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1771 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1772 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1773 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1774 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1775 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1776 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1777 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1778 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1779 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1780 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1781 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1782 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1783 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1784 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1785 pHlp->pfnPrintf(pHlp, "\n");
1786
1787 uint32_t uECX = Guest.ecx;
1788 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1789 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1790 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1791 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1792 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1793 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1794 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1795 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1796 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1797 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1798 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1799 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1800 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1801 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1802 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1803 for (unsigned iBit = 5; iBit < 32; iBit++)
1804 if (uECX & RT_BIT(iBit))
1805 pHlp->pfnPrintf(pHlp, " %d", iBit);
1806 pHlp->pfnPrintf(pHlp, "\n");
1807 }
1808 else
1809 {
1810 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1811
1812 uint32_t uEdxGst = Guest.edx;
1813 uint32_t uEdxHst = Host.edx;
1814 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1815 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1816 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1817 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1818 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1819 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1820 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1821 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1822 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1823 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1824 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1825 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1826 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1827 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1828 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1829 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1830 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1831 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1832 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1833 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1834 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1835 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1836 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1837 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1838 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1839 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1840 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1841 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1842 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1843 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1844 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1845 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1846 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1847
1848 uint32_t uEcxGst = Guest.ecx;
1849 uint32_t uEcxHst = Host.ecx;
1850 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1851 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1852 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1853 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1854 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1855 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1856 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1857 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1858 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1859 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1860 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1861 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1862 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1863 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1864 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1865 }
1866 }
1867
1868 if (iVerbosity && cExtMax >= 2)
1869 {
1870 char szString[4*4*3+1] = {0};
1871 uint32_t *pu32 = (uint32_t *)szString;
1872 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1873 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1874 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1875 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1876 if (cExtMax >= 3)
1877 {
1878 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1879 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1880 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1881 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1882 }
1883 if (cExtMax >= 4)
1884 {
1885 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1886 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1887 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1888 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1889 }
1890 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1891 }
1892
1893 if (iVerbosity && cExtMax >= 5)
1894 {
1895 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1896 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1897 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1898 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1899 char sz1[32];
1900 char sz2[32];
1901
1902 pHlp->pfnPrintf(pHlp,
1903 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1904 "TLB 2/4M Data: %s %3d entries\n",
1905 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1906 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1907 pHlp->pfnPrintf(pHlp,
1908 "TLB 4K Instr/Uni: %s %3d entries\n"
1909 "TLB 4K Data: %s %3d entries\n",
1910 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1911 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1912 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1913 "L1 Instr Cache Lines Per Tag: %d\n"
1914 "L1 Instr Cache Associativity: %s\n"
1915 "L1 Instr Cache Size: %d KB\n",
1916 (uEDX >> 0) & 0xff,
1917 (uEDX >> 8) & 0xff,
1918 getCacheAss((uEDX >> 16) & 0xff, sz1),
1919 (uEDX >> 24) & 0xff);
1920 pHlp->pfnPrintf(pHlp,
1921 "L1 Data Cache Line Size: %d bytes\n"
1922 "L1 Data Cache Lines Per Tag: %d\n"
1923 "L1 Data Cache Associativity: %s\n"
1924 "L1 Data Cache Size: %d KB\n",
1925 (uECX >> 0) & 0xff,
1926 (uECX >> 8) & 0xff,
1927 getCacheAss((uECX >> 16) & 0xff, sz1),
1928 (uECX >> 24) & 0xff);
1929 }
1930
1931 if (iVerbosity && cExtMax >= 6)
1932 {
1933 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1934 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1935 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1936
1937 pHlp->pfnPrintf(pHlp,
1938 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1939 "L2 TLB 2/4M Data: %s %4d entries\n",
1940 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1941 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1942 pHlp->pfnPrintf(pHlp,
1943 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1944 "L2 TLB 4K Data: %s %4d entries\n",
1945 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1946 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1947 pHlp->pfnPrintf(pHlp,
1948 "L2 Cache Line Size: %d bytes\n"
1949 "L2 Cache Lines Per Tag: %d\n"
1950 "L2 Cache Associativity: %s\n"
1951 "L2 Cache Size: %d KB\n",
1952 (uEDX >> 0) & 0xff,
1953 (uEDX >> 8) & 0xf,
1954 getL2CacheAss((uEDX >> 12) & 0xf),
1955 (uEDX >> 16) & 0xffff);
1956 }
1957
1958 if (iVerbosity && cExtMax >= 7)
1959 {
1960 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1961
1962 pHlp->pfnPrintf(pHlp, "APM Features: ");
1963 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1964 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1965 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1966 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1967 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1968 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1969 for (unsigned iBit = 6; iBit < 32; iBit++)
1970 if (uEDX & RT_BIT(iBit))
1971 pHlp->pfnPrintf(pHlp, " %d", iBit);
1972 pHlp->pfnPrintf(pHlp, "\n");
1973 }
1974
1975 if (iVerbosity && cExtMax >= 8)
1976 {
1977 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1978 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1979
1980 pHlp->pfnPrintf(pHlp,
1981 "Physical Address Width: %d bits\n"
1982 "Virtual Address Width: %d bits\n",
1983 (uEAX >> 0) & 0xff,
1984 (uEAX >> 8) & 0xff);
1985 pHlp->pfnPrintf(pHlp,
1986 "Physical Core Count: %d\n",
1987 (uECX >> 0) & 0xff);
1988 }
1989
1990
1991 /*
1992 * Centaur.
1993 */
1994 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1995
1996 pHlp->pfnPrintf(pHlp,
1997 "\n"
1998 " RAW Centaur CPUIDs\n"
1999 " Function eax ebx ecx edx\n");
2000 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2001 {
2002 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2003 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2004
2005 pHlp->pfnPrintf(pHlp,
2006 "Gst: %08x %08x %08x %08x %08x%s\n"
2007 "Hst: %08x %08x %08x %08x\n",
2008 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2009 i <= cCentaurMax ? "" : "*",
2010 Host.eax, Host.ebx, Host.ecx, Host.edx);
2011 }
2012
2013 /*
2014 * Understandable output
2015 */
2016 if (iVerbosity)
2017 {
2018 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2019 pHlp->pfnPrintf(pHlp,
2020 "Centaur Supports: 0xc0000000-%#010x\n",
2021 Guest.eax);
2022 }
2023
2024 if (iVerbosity && cCentaurMax >= 1)
2025 {
2026 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2027 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2028 uint32_t uEdxHst = Host.edx;
2029
2030 if (iVerbosity == 1)
2031 {
2032 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2033 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2034 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2035 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2036 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2037 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2038 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2039 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2040 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2041 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2042 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2043 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2044 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2045 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2046 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2047 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2048 for (unsigned iBit = 14; iBit < 32; iBit++)
2049 if (uEdxGst & RT_BIT(iBit))
2050 pHlp->pfnPrintf(pHlp, " %d", iBit);
2051 pHlp->pfnPrintf(pHlp, "\n");
2052 }
2053 else
2054 {
2055 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2056 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2057 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2058 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2059 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2060 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2061 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2062 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2063 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2064 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2065 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2066 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2067 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2068 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2069 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2070 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2071 for (unsigned iBit = 14; iBit < 32; iBit++)
2072 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2073 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2074 pHlp->pfnPrintf(pHlp, "\n");
2075 }
2076 }
2077}
2078
2079
2080/**
2081 * Structure used when disassembling and instructions in DBGF.
2082 * This is used so the reader function can get the stuff it needs.
2083 */
2084typedef struct CPUMDISASSTATE
2085{
2086 /** Pointer to the CPU structure. */
2087 PDISCPUSTATE pCpu;
2088 /** The VM handle. */
2089 PVM pVM;
2090 /** Pointer to the first byte in the segemnt. */
2091 RTGCUINTPTR GCPtrSegBase;
2092 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2093 RTGCUINTPTR GCPtrSegEnd;
2094 /** The size of the segment minus 1. */
2095 RTGCUINTPTR cbSegLimit;
2096 /** Pointer to the current page - R3 Ptr. */
2097 void const *pvPageR3;
2098 /** Pointer to the current page - GC Ptr. */
2099 RTGCPTR pvPageGC;
2100 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2101 PGMPAGEMAPLOCK PageMapLock;
2102 /** Whether the PageMapLock is valid or not. */
2103 bool fLocked;
2104 /** 64 bits mode or not. */
2105 bool f64Bits;
2106} CPUMDISASSTATE, *PCPUMDISASSTATE;
2107
2108
2109/**
2110 * Instruction reader.
2111 *
2112 * @returns VBox status code.
2113 * @param PtrSrc Address to read from.
2114 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2115 * @param pu8Dst Where to store the bytes.
2116 * @param cbRead Number of bytes to read.
2117 * @param uDisCpu Pointer to the disassembler cpu state.
2118 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2119 */
2120static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2121{
2122 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2123 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2124 Assert(cbRead > 0);
2125 for (;;)
2126 {
2127 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2128
2129 /* Need to update the page translation? */
2130 if ( !pState->pvPageR3
2131 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2132 {
2133 int rc = VINF_SUCCESS;
2134
2135 /* translate the address */
2136 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2137 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2138 && !HWACCMIsEnabled(pState->pVM))
2139 {
2140 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2141 if (!pState->pvPageR3)
2142 rc = VERR_INVALID_POINTER;
2143 }
2144 else
2145 {
2146 /* Release mapping lock previously acquired. */
2147 if (pState->fLocked)
2148 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2149 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2150 pState->fLocked = RT_SUCCESS_NP(rc);
2151 }
2152 if (RT_FAILURE(rc))
2153 {
2154 pState->pvPageR3 = NULL;
2155 return rc;
2156 }
2157 }
2158
2159 /* check the segemnt limit */
2160 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2161 return VERR_OUT_OF_SELECTOR_BOUNDS;
2162
2163 /* calc how much we can read */
2164 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2165 if (!pState->f64Bits)
2166 {
2167 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2168 if (cb > cbSeg && cbSeg)
2169 cb = cbSeg;
2170 }
2171 if (cb > cbRead)
2172 cb = cbRead;
2173
2174 /* read and advance */
2175 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2176 cbRead -= cb;
2177 if (!cbRead)
2178 return VINF_SUCCESS;
2179 pu8Dst += cb;
2180 PtrSrc += cb;
2181 }
2182}
2183
2184
2185/**
2186 * Disassemble an instruction and return the information in the provided structure.
2187 *
2188 * @returns VBox status code.
2189 * @param pVM VM Handle
2190 * @param pCtx CPU context
2191 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2192 * @param pCpu Disassembly state
2193 * @param pszPrefix String prefix for logging (debug only)
2194 *
2195 */
2196VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2197{
2198 CPUMDISASSTATE State;
2199 int rc;
2200
2201 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2202 State.pCpu = pCpu;
2203 State.pvPageGC = 0;
2204 State.pvPageR3 = NULL;
2205 State.pVM = pVM;
2206 State.fLocked = false;
2207 State.f64Bits = false;
2208
2209 /*
2210 * Get selector information.
2211 */
2212 if ( (pCtx->cr0 & X86_CR0_PE)
2213 && pCtx->eflags.Bits.u1VM == 0)
2214 {
2215 if (CPUMAreHiddenSelRegsValid(pVM))
2216 {
2217 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2218 State.GCPtrSegBase = pCtx->csHid.u64Base;
2219 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2220 State.cbSegLimit = pCtx->csHid.u32Limit;
2221 pCpu->mode = (State.f64Bits)
2222 ? CPUMODE_64BIT
2223 : pCtx->csHid.Attr.n.u1DefBig
2224 ? CPUMODE_32BIT
2225 : CPUMODE_16BIT;
2226 }
2227 else
2228 {
2229 SELMSELINFO SelInfo;
2230
2231 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2232 if (!RT_SUCCESS(rc))
2233 {
2234 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2235 return rc;
2236 }
2237
2238 /*
2239 * Validate the selector.
2240 */
2241 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2242 if (!RT_SUCCESS(rc))
2243 {
2244 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2245 return rc;
2246 }
2247 State.GCPtrSegBase = SelInfo.GCPtrBase;
2248 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2249 State.cbSegLimit = SelInfo.cbLimit;
2250 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2251 }
2252 }
2253 else
2254 {
2255 /* real or V86 mode */
2256 pCpu->mode = CPUMODE_16BIT;
2257 State.GCPtrSegBase = pCtx->cs * 16;
2258 State.GCPtrSegEnd = 0xFFFFFFFF;
2259 State.cbSegLimit = 0xFFFFFFFF;
2260 }
2261
2262 /*
2263 * Disassemble the instruction.
2264 */
2265 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2266 pCpu->apvUserData[0] = &State;
2267
2268 uint32_t cbInstr;
2269#ifndef LOG_ENABLED
2270 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2271 if (RT_SUCCESS(rc))
2272 {
2273#else
2274 char szOutput[160];
2275 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2276 if (RT_SUCCESS(rc))
2277 {
2278 /* log it */
2279 if (pszPrefix)
2280 Log(("%s: %s", pszPrefix, szOutput));
2281 else
2282 Log(("%s", szOutput));
2283#endif
2284 rc = VINF_SUCCESS;
2285 }
2286 else
2287 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2288
2289 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2290 if (State.fLocked)
2291 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2292
2293 return rc;
2294}
2295
2296#ifdef DEBUG
2297
2298/**
2299 * Disassemble an instruction and dump it to the log
2300 *
2301 * @returns VBox status code.
2302 * @param pVM VM Handle
2303 * @param pCtx CPU context
2304 * @param pc GC instruction pointer
2305 * @param pszPrefix String prefix for logging
2306 *
2307 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2308 */
2309VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2310{
2311 DISCPUSTATE Cpu;
2312 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &Cpu, pszPrefix);
2313}
2314
2315
2316/**
2317 * Disassemble an instruction and dump it to the log
2318 *
2319 * @returns VBox status code.
2320 * @param pVM VM Handle
2321 * @param pCtx CPU context
2322 * @param pc GC instruction pointer
2323 * @param pszPrefix String prefix for logging
2324 * @param nrInstructions
2325 *
2326 * @deprecated Create new DBGFR3Disas function to do this.
2327 */
2328VMMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix, int nrInstructions)
2329{
2330 for (int i = 0; i < nrInstructions; i++)
2331 {
2332 DISCPUSTATE cpu;
2333
2334 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, pszPrefix);
2335 pc += cpu.opsize;
2336 }
2337}
2338
2339
2340/**
2341 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2342 *
2343 * @internal
2344 */
2345VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2346{
2347 /* @todo SMP */
2348 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(pVM);
2349}
2350
2351#endif /* DEBUG */
2352
2353/**
2354 * API for controlling a few of the CPU features found in CR4.
2355 *
2356 * Currently only X86_CR4_TSD is accepted as input.
2357 *
2358 * @returns VBox status code.
2359 *
2360 * @param pVM The VM handle.
2361 * @param fOr The CR4 OR mask.
2362 * @param fAnd The CR4 AND mask.
2363 */
2364VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2365{
2366 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2367 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2368
2369 pVM->cpum.s.CR4.OrMask &= fAnd;
2370 pVM->cpum.s.CR4.OrMask |= fOr;
2371
2372 return VINF_SUCCESS;
2373}
2374
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