VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 14091

Last change on this file since 14091 was 14091, checked in by vboxsync, 16 years ago

Minor cleanup
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1/* $Id: CPUM.cpp 14091 2008-11-11 13:31:09Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 9
71/** The saved state version of 2.0, used for backwards compatibility. */
72#define CPUM_SAVED_STATE_VERSION_VER2_0 8
73/** The saved state version of 1.6, used for backwards compatability. */
74#define CPUM_SAVED_STATE_VERSION_VER1_6 6
75
76
77/*******************************************************************************
78* Structures and Typedefs *
79*******************************************************************************/
80
81/**
82 * What kind of cpu info dump to perform.
83 */
84typedef enum CPUMDUMPTYPE
85{
86 CPUMDUMPTYPE_TERSE,
87 CPUMDUMPTYPE_DEFAULT,
88 CPUMDUMPTYPE_VERBOSE
89
90} CPUMDUMPTYPE;
91/** Pointer to a cpu info dump type. */
92typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
93
94
95/*******************************************************************************
96* Internal Functions *
97*******************************************************************************/
98static int cpumR3CpuIdInit(PVM pVM);
99static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
100static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
101static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107
108
109/**
110 * Initializes the CPUM.
111 *
112 * @returns VBox status code.
113 * @param pVM The VM to operate on.
114 */
115VMMR3DECL(int) CPUMR3Init(PVM pVM)
116{
117 LogFlow(("CPUMR3Init\n"));
118
119 /*
120 * Assert alignment and sizes.
121 */
122 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
123 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
124
125 /*
126 * Setup any fixed pointers and offsets.
127 */
128 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
129 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
130
131 /* Hidden selector registers are invalid by default. */
132 pVM->cpum.s.fValidHiddenSelRegs = false;
133
134 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
135 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
136 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
137
138 /* Calculate the offset from CPUMCPU to CPUM. */
139 for (unsigned i=0;i<pVM->cCPUs;i++)
140 {
141 pVM->aCpus[i].cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
142 Assert((uintptr_t)&pVM->aCpus[i].cpum - pVM->aCpus[i].cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
143 }
144
145 /*
146 * Check that the CPU supports the minimum features we require.
147 */
148 if (!ASMHasCpuId())
149 {
150 Log(("The CPU doesn't support CPUID!\n"));
151 return VERR_UNSUPPORTED_CPU;
152 }
153 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
154 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
155
156 /* Setup the CR4 AND and OR masks used in the switcher */
157 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
158 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
159 {
160 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
161 /* No FXSAVE implies no SSE */
162 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
163 pVM->cpum.s.CR4.OrMask = 0;
164 }
165 else
166 {
167 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
168 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
169 }
170
171 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
172 {
173 Log(("The CPU doesn't support MMX!\n"));
174 return VERR_UNSUPPORTED_CPU;
175 }
176 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
177 {
178 Log(("The CPU doesn't support TSC!\n"));
179 return VERR_UNSUPPORTED_CPU;
180 }
181 /* Bogus on AMD? */
182 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
183 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
184
185 /*
186 * Setup hypervisor startup values.
187 */
188
189 /*
190 * Register saved state data item.
191 */
192 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
193 NULL, cpumR3Save, NULL,
194 NULL, cpumR3Load, NULL);
195 if (RT_FAILURE(rc))
196 return rc;
197
198 /* Query the CPU manufacturer. */
199 uint32_t uEAX, uEBX, uECX, uEDX;
200 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
201 if ( uEAX >= 1
202 && uEBX == X86_CPUID_VENDOR_AMD_EBX
203 && uECX == X86_CPUID_VENDOR_AMD_ECX
204 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
205 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
206 else if ( uEAX >= 1
207 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
208 && uECX == X86_CPUID_VENDOR_INTEL_ECX
209 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
210 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
211 else /** @todo Via */
212 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
213
214 /*
215 * Register info handlers.
216 */
217 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
218 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
219 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
220 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
221 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
222 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
223
224 /*
225 * Initialize the Guest CPU state.
226 */
227 rc = cpumR3CpuIdInit(pVM);
228 if (RT_FAILURE(rc))
229 return rc;
230 CPUMR3Reset(pVM);
231 return VINF_SUCCESS;
232}
233
234
235/**
236 * Initializes the per-VCPU CPUM.
237 *
238 * @returns VBox status code.
239 * @param pVM The VM to operate on.
240 */
241VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
242{
243 LogFlow(("CPUMR3InitCPU\n"));
244 return VINF_SUCCESS;
245}
246
247
248/**
249 * Initializes the emulated CPU's cpuid information.
250 *
251 * @returns VBox status code.
252 * @param pVM The VM to operate on.
253 */
254static int cpumR3CpuIdInit(PVM pVM)
255{
256 PCPUM pCPUM = &pVM->cpum.s;
257 uint32_t i;
258
259 /*
260 * Get the host CPUIDs.
261 */
262 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
263 ASMCpuId_Idx_ECX(i, 0,
264 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
265 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
266 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
267 ASMCpuId(0x80000000 + i,
268 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
269 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
270 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
271 ASMCpuId(0xc0000000 + i,
272 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
273 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
274
275
276 /*
277 * Only report features we can support.
278 */
279 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
280 | X86_CPUID_FEATURE_EDX_VME
281 | X86_CPUID_FEATURE_EDX_DE
282 | X86_CPUID_FEATURE_EDX_PSE
283 | X86_CPUID_FEATURE_EDX_TSC
284 | X86_CPUID_FEATURE_EDX_MSR
285 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
286 | X86_CPUID_FEATURE_EDX_MCE
287 | X86_CPUID_FEATURE_EDX_CX8
288 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
289 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
290 //| X86_CPUID_FEATURE_EDX_SEP
291 | X86_CPUID_FEATURE_EDX_MTRR
292 | X86_CPUID_FEATURE_EDX_PGE
293 | X86_CPUID_FEATURE_EDX_MCA
294 | X86_CPUID_FEATURE_EDX_CMOV
295 | X86_CPUID_FEATURE_EDX_PAT
296 | X86_CPUID_FEATURE_EDX_PSE36
297 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
298 | X86_CPUID_FEATURE_EDX_CLFSH
299 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
300 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
301 | X86_CPUID_FEATURE_EDX_MMX
302 | X86_CPUID_FEATURE_EDX_FXSR
303 | X86_CPUID_FEATURE_EDX_SSE
304 | X86_CPUID_FEATURE_EDX_SSE2
305 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
306 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
307 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
308 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
309 | 0;
310 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
311 | X86_CPUID_FEATURE_ECX_MONITOR
312 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
313 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
314 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
315 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
316 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
317 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
318 //| X86_CPUID_FEATURE_ECX_CX16
319 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
320 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
321 /* ECX Bit 21 - x2APIC support - not yet. */
322 // | X86_CPUID_FEATURE_ECX_X2APIC
323 /* ECX Bit 23 - POPCOUNT instruction. */
324 //| X86_CPUID_FEATURE_ECX_POPCOUNT
325 | 0;
326
327 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
328 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
329 | X86_CPUID_AMD_FEATURE_EDX_VME
330 | X86_CPUID_AMD_FEATURE_EDX_DE
331 | X86_CPUID_AMD_FEATURE_EDX_PSE
332 | X86_CPUID_AMD_FEATURE_EDX_TSC
333 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
334 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
335 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
336 | X86_CPUID_AMD_FEATURE_EDX_CX8
337 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
338 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
339 //| X86_CPUID_AMD_FEATURE_EDX_SEP
340 | X86_CPUID_AMD_FEATURE_EDX_MTRR
341 | X86_CPUID_AMD_FEATURE_EDX_PGE
342 | X86_CPUID_AMD_FEATURE_EDX_MCA
343 | X86_CPUID_AMD_FEATURE_EDX_CMOV
344 | X86_CPUID_AMD_FEATURE_EDX_PAT
345 | X86_CPUID_AMD_FEATURE_EDX_PSE36
346 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
347 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
348 | X86_CPUID_AMD_FEATURE_EDX_MMX
349 | X86_CPUID_AMD_FEATURE_EDX_FXSR
350 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
351 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
352 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
353 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
354 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
355 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
356 | 0;
357 pCPUM->aGuestCpuIdExt[1].ecx &= 0
358 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
359 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
360 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
361 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
362 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
363 //| X86_CPUID_AMD_FEATURE_ECX_ABM
364 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
365 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
366 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
367 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
368 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
369 //| X86_CPUID_AMD_FEATURE_ECX_WDT
370 | 0;
371
372 /*
373 * Hide HTT, multicode, SMP, whatever.
374 * (APIC-ID := 0 and #LogCpus := 0)
375 */
376 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
377
378 /* Cpuid 2:
379 * Intel: Cache and TLB information
380 * AMD: Reserved
381 * Safe to expose
382 */
383
384 /* Cpuid 3:
385 * Intel: EAX, EBX - reserved
386 * ECX, EDX - Processor Serial Number if available, otherwise reserved
387 * AMD: Reserved
388 * Safe to expose
389 */
390 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
391 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
392
393 /* Cpuid 4:
394 * Intel: Deterministic Cache Parameters Leaf
395 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
396 * AMD: Reserved
397 * Safe to expose, except for EAX:
398 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
399 * Bits 31-26: Maximum number of processor cores in this physical package**
400 */
401 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
402 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
403
404 /* Cpuid 5: Monitor/mwait Leaf
405 * Intel: ECX, EDX - reserved
406 * EAX, EBX - Smallest and largest monitor line size
407 * AMD: EDX - reserved
408 * EAX, EBX - Smallest and largest monitor line size
409 * ECX - extensions (ignored for now)
410 * Safe to expose
411 */
412 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
413 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
414
415 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
416
417 /*
418 * Determine the default.
419 *
420 * Intel returns values of the highest standard function, while AMD
421 * returns zeros. VIA on the other hand seems to returning nothing or
422 * perhaps some random garbage, we don't try to duplicate this behavior.
423 */
424 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
425 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
426 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
427
428 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
429 * Safe to pass on to the guest.
430 *
431 * Intel: 0x800000005 reserved
432 * 0x800000006 L2 cache information
433 * AMD: 0x800000005 L1 cache information
434 * 0x800000006 L2/L3 cache information
435 */
436
437 /* Cpuid 0x800000007:
438 * AMD: EAX, EBX, ECX - reserved
439 * EDX: Advanced Power Management Information
440 * Intel: Reserved
441 */
442 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
443 {
444 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
445
446 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
447
448 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
449 {
450 /* Only expose the TSC invariant capability bit to the guest. */
451 pCPUM->aGuestCpuIdExt[7].edx &= 0
452 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
453 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
454 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
455 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
456 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
457 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
458 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
459 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
460 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
461 | 0;
462 }
463 else
464 pCPUM->aGuestCpuIdExt[7].edx = 0;
465 }
466
467 /* Cpuid 0x800000008:
468 * AMD: EBX, EDX - reserved
469 * EAX: Virtual/Physical address Size
470 * ECX: Number of cores + APICIdCoreIdSize
471 * Intel: EAX: Virtual/Physical address Size
472 * EBX, ECX, EDX - reserved
473 */
474 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
475 {
476 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
477 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
478 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
479 * NC (0-7) Number of cores; 0 equals 1 core */
480 pCPUM->aGuestCpuIdExt[8].ecx = 0;
481 }
482
483 /*
484 * Limit it the number of entries and fill the remaining with the defaults.
485 *
486 * The limits are masking off stuff about power saving and similar, this
487 * is perhaps a bit crudely done as there is probably some relatively harmless
488 * info too in these leaves (like words about having a constant TSC).
489 */
490#if 0
491 /** @todo NT4 installation regression - investigate */
492 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
493 pCPUM->aGuestCpuIdStd[0].eax = 5;
494#else
495 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
496 pCPUM->aGuestCpuIdStd[0].eax = 2;
497#endif
498 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
499 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
500
501 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
502 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
503 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
504 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
505 : 0;
506 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
507 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
508
509 /*
510 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
511 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
512 * We currently don't support more than 1 processor.
513 */
514 pCPUM->aGuestCpuIdStd[4].eax = 0;
515
516 /*
517 * Centaur stuff (VIA).
518 *
519 * The important part here (we think) is to make sure the 0xc0000000
520 * function returns 0xc0000001. As for the features, we don't currently
521 * let on about any of those... 0xc0000002 seems to be some
522 * temperature/hz/++ stuff, include it as well (static).
523 */
524 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
525 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
526 {
527 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
528 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
529 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
530 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
531 i++)
532 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
533 }
534 else
535 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
536 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
537
538
539 /*
540 * Load CPUID overrides from configuration.
541 */
542 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
543 * Overloads the CPUID leaf values. */
544 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
545 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
546 for (i=0;; )
547 {
548 while (cElements-- > 0)
549 {
550 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
551 if (pNode)
552 {
553 uint32_t u32;
554 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
555 if (RT_SUCCESS(rc))
556 pCpuId->eax = u32;
557 else
558 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
559
560 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
561 if (RT_SUCCESS(rc))
562 pCpuId->ebx = u32;
563 else
564 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
565
566 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
567 if (RT_SUCCESS(rc))
568 pCpuId->ecx = u32;
569 else
570 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
571
572 rc = CFGMR3QueryU32(pNode, "edx", &u32);
573 if (RT_SUCCESS(rc))
574 pCpuId->edx = u32;
575 else
576 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
577 }
578 pCpuId++;
579 i++;
580 }
581
582 /* next */
583 if ((i & UINT32_C(0xc0000000)) == 0)
584 {
585 pCpuId = &pCPUM->aGuestCpuIdExt[0];
586 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
587 i = UINT32_C(0x80000000);
588 }
589 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
590 {
591 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
592 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
593 i = UINT32_C(0xc0000000);
594 }
595 else
596 break;
597 }
598
599 /* Check if PAE was explicitely enabled by the user. */
600 bool fEnable = false;
601 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
602 if (RT_SUCCESS(rc) && fEnable)
603 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
604
605 /*
606 * Log the cpuid and we're good.
607 */
608 RTCPUSET OnlineSet;
609 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
610 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
611 LogRel(("************************* CPUID dump ************************\n"));
612 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
613 LogRel(("\n"));
614 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
615 LogRel(("******************** End of CPUID dump **********************\n"));
616 return VINF_SUCCESS;
617}
618
619
620
621
622/**
623 * Applies relocations to data and code managed by this
624 * component. This function will be called at init and
625 * whenever the VMM need to relocate it self inside the GC.
626 *
627 * The CPUM will update the addresses used by the switcher.
628 *
629 * @param pVM The VM.
630 */
631VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
632{
633 LogFlow(("CPUMR3Relocate\n"));
634 /*
635 * Switcher pointers.
636 */
637 pVM->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
638 Assert(pVM->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
639}
640
641
642/**
643 * Terminates the CPUM.
644 *
645 * Termination means cleaning up and freeing all resources,
646 * the VM it self is at this point powered off or suspended.
647 *
648 * @returns VBox status code.
649 * @param pVM The VM to operate on.
650 */
651VMMR3DECL(int) CPUMR3Term(PVM pVM)
652{
653 /** @todo ? */
654 return 0;
655}
656
657
658/**
659 * Terminates the per-VCPU CPUM.
660 *
661 * Termination means cleaning up and freeing all resources,
662 * the VM it self is at this point powered off or suspended.
663 *
664 * @returns VBox status code.
665 * @param pVM The VM to operate on.
666 */
667VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
668{
669 return 0;
670}
671
672
673/**
674 * Resets the CPU.
675 *
676 * @returns VINF_SUCCESS.
677 * @param pVM The VM handle.
678 */
679VMMR3DECL(void) CPUMR3Reset(PVM pVM)
680{
681 /* @todo anything different for VCPU > 0? */
682 for (unsigned i=0;i<pVM->cCPUs;i++)
683 {
684 PCPUMCTX pCtx = CPUMQueryGuestCtxPtrEx(pVM, &pVM->aCpus[i]);
685
686 /*
687 * Initialize everything to ZERO first.
688 */
689 uint32_t fUseFlags = pVM->aCpus[i].cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
690 memset(pCtx, 0, sizeof(*pCtx));
691 pVM->aCpus[i].cpum.s.fUseFlags = fUseFlags;
692
693 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
694 pCtx->eip = 0x0000fff0;
695 pCtx->edx = 0x00000600; /* P6 processor */
696 pCtx->eflags.Bits.u1Reserved0 = 1;
697
698 pCtx->cs = 0xf000;
699 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
700 pCtx->csHid.u32Limit = 0x0000ffff;
701 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
702 pCtx->csHid.Attr.n.u1Present = 1;
703 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
704
705 pCtx->dsHid.u32Limit = 0x0000ffff;
706 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
707 pCtx->dsHid.Attr.n.u1Present = 1;
708 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
709
710 pCtx->esHid.u32Limit = 0x0000ffff;
711 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
712 pCtx->esHid.Attr.n.u1Present = 1;
713 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
714
715 pCtx->fsHid.u32Limit = 0x0000ffff;
716 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
717 pCtx->fsHid.Attr.n.u1Present = 1;
718 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
719
720 pCtx->gsHid.u32Limit = 0x0000ffff;
721 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
722 pCtx->gsHid.Attr.n.u1Present = 1;
723 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
724
725 pCtx->ssHid.u32Limit = 0x0000ffff;
726 pCtx->ssHid.Attr.n.u1Present = 1;
727 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
728 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
729
730 pCtx->idtr.cbIdt = 0xffff;
731 pCtx->gdtr.cbGdt = 0xffff;
732
733 pCtx->ldtrHid.u32Limit = 0xffff;
734 pCtx->ldtrHid.Attr.n.u1Present = 1;
735 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
736
737 pCtx->trHid.u32Limit = 0xffff;
738 pCtx->trHid.Attr.n.u1Present = 1;
739 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
740
741 pCtx->dr[6] = X86_DR6_INIT_VAL;
742 pCtx->dr[7] = X86_DR7_INIT_VAL;
743
744 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
745 pCtx->fpu.FCW = 0x37f;
746
747 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
748 pCtx->fpu.MXCSR = 0x1F80;
749
750 /* Init PAT MSR */
751 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
752
753 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
754 * The Intel docs don't mention it.
755 */
756 pCtx->msrEFER = 0;
757 }
758}
759
760
761/**
762 * Execute state save operation.
763 *
764 * @returns VBox status code.
765 * @param pVM VM Handle.
766 * @param pSSM SSM operation handle.
767 */
768static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
769{
770 /* Set the size of RTGCPTR for use of SSMR3Get/PutGCPtr. */
771 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
772
773 /*
774 * Save.
775 */
776 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
777
778 SSMR3PutU32(pSSM, pVM->cCPUs);
779 for (unsigned i=0;i<pVM->cCPUs;i++)
780 {
781 SSMR3PutMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
782 SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fUseFlags);
783 SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fChanged);
784 }
785
786 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
787 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
788
789 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
790 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
791
792 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
793 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
794
795 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
796
797 /* Add the cpuid for checking that the cpu is unchanged. */
798 uint32_t au32CpuId[8] = {0};
799 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
800 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
801 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
802}
803
804
805/**
806 * Load a version 1.6 CPUMCTX structure.
807 *
808 * @returns VBox status code.
809 * @param pVM VM Handle.
810 * @param pCpumctx16 Version 1.6 CPUMCTX
811 */
812static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
813{
814#define CPUMCTX16_LOADREG(RegName) \
815 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
816
817#define CPUMCTX16_LOADDRXREG(RegName) \
818 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
819
820#define CPUMCTX16_LOADHIDREG(RegName) \
821 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
822 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
823 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
824
825#define CPUMCTX16_LOADSEGREG(RegName) \
826 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
827 CPUMCTX16_LOADHIDREG(RegName);
828
829 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
830
831 CPUMCTX16_LOADREG(rax);
832 CPUMCTX16_LOADREG(rbx);
833 CPUMCTX16_LOADREG(rcx);
834 CPUMCTX16_LOADREG(rdx);
835 CPUMCTX16_LOADREG(rdi);
836 CPUMCTX16_LOADREG(rsi);
837 CPUMCTX16_LOADREG(rbp);
838 CPUMCTX16_LOADREG(esp);
839 CPUMCTX16_LOADREG(rip);
840 CPUMCTX16_LOADREG(rflags);
841
842 CPUMCTX16_LOADSEGREG(cs);
843 CPUMCTX16_LOADSEGREG(ds);
844 CPUMCTX16_LOADSEGREG(es);
845 CPUMCTX16_LOADSEGREG(fs);
846 CPUMCTX16_LOADSEGREG(gs);
847 CPUMCTX16_LOADSEGREG(ss);
848
849 CPUMCTX16_LOADREG(r8);
850 CPUMCTX16_LOADREG(r9);
851 CPUMCTX16_LOADREG(r10);
852 CPUMCTX16_LOADREG(r11);
853 CPUMCTX16_LOADREG(r12);
854 CPUMCTX16_LOADREG(r13);
855 CPUMCTX16_LOADREG(r14);
856 CPUMCTX16_LOADREG(r15);
857
858 CPUMCTX16_LOADREG(cr0);
859 CPUMCTX16_LOADREG(cr2);
860 CPUMCTX16_LOADREG(cr3);
861 CPUMCTX16_LOADREG(cr4);
862
863 CPUMCTX16_LOADDRXREG(0);
864 CPUMCTX16_LOADDRXREG(1);
865 CPUMCTX16_LOADDRXREG(2);
866 CPUMCTX16_LOADDRXREG(3);
867 CPUMCTX16_LOADDRXREG(4);
868 CPUMCTX16_LOADDRXREG(5);
869 CPUMCTX16_LOADDRXREG(6);
870 CPUMCTX16_LOADDRXREG(7);
871
872 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
873 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
874 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
875 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
876
877 CPUMCTX16_LOADREG(ldtr);
878 CPUMCTX16_LOADREG(tr);
879
880 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
881
882 CPUMCTX16_LOADREG(msrEFER);
883 CPUMCTX16_LOADREG(msrSTAR);
884 CPUMCTX16_LOADREG(msrPAT);
885 CPUMCTX16_LOADREG(msrLSTAR);
886 CPUMCTX16_LOADREG(msrCSTAR);
887 CPUMCTX16_LOADREG(msrSFMASK);
888 CPUMCTX16_LOADREG(msrKERNELGSBASE);
889
890 CPUMCTX16_LOADHIDREG(ldtr);
891 CPUMCTX16_LOADHIDREG(tr);
892
893#undef CPUMCTX16_LOADSEGREG
894#undef CPUMCTX16_LOADHIDREG
895#undef CPUMCTX16_LOADDRXREG
896#undef CPUMCTX16_LOADREG
897}
898
899
900/**
901 * Execute state load operation.
902 *
903 * @returns VBox status code.
904 * @param pVM VM Handle.
905 * @param pSSM SSM operation handle.
906 * @param u32Version Data layout version.
907 */
908static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
909{
910 /*
911 * Validate version.
912 */
913 if ( u32Version != CPUM_SAVED_STATE_VERSION
914 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
915 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
916 {
917 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
918 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
919 }
920
921 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
922 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
923 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
924 else
925 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
926
927 /*
928 * Restore.
929 */
930 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
931 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
932 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
933 pVM->cpum.s.Hyper.cr3 = uCR3;
934 pVM->cpum.s.Hyper.esp = uESP;
935 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
936 {
937 CPUMCTX_VER1_6 cpumctx16;
938 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
939 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
940
941 /* Save the old cpumctx state into the new one. */
942 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
943
944 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
945 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
946 }
947 else
948 {
949 if (u32Version == CPUM_SAVED_STATE_VERSION)
950 {
951 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
952 AssertRCReturn(rc, rc);
953 }
954
955 if ( !pVM->cCPUs
956 || pVM->cCPUs > VMCPU_MAX_CPU_COUNT
957 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
958 && pVM->cCPUs != 1))
959 {
960 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
961 return VERR_SSM_UNEXPECTED_DATA;
962 }
963
964 for (unsigned i=0;i<pVM->cCPUs;i++)
965 {
966 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
967 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
968 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
969 }
970 }
971
972
973 uint32_t cElements;
974 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
975 /* Support old saved states with a smaller standard cpuid array. */
976 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
977 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
978 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
979
980 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
981 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
982 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
983 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
984
985 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
986 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
987 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
988 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
989
990 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
991
992 /*
993 * Check that the basic cpuid id information is unchanged.
994 */
995 uint32_t au32CpuId[8] = {0};
996 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
997 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
998 uint32_t au32CpuIdSaved[8];
999 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1000 if (RT_SUCCESS(rc))
1001 {
1002 /* Ignore APIC ID (AMD specs). */
1003 au32CpuId[5] &= ~0xff000000;
1004 au32CpuIdSaved[5] &= ~0xff000000;
1005 /* Ignore the number of Logical CPUs (AMD specs). */
1006 au32CpuId[5] &= ~0x00ff0000;
1007 au32CpuIdSaved[5] &= ~0x00ff0000;
1008
1009 /* do the compare */
1010 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1011 {
1012 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1013 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1014 "Saved=%.*Rhxs\n"
1015 "Real =%.*Rhxs\n",
1016 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1017 sizeof(au32CpuId), au32CpuId));
1018 else
1019 {
1020 LogRel(("cpumR3Load: CpuId mismatch!\n"
1021 "Saved=%.*Rhxs\n"
1022 "Real =%.*Rhxs\n",
1023 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1024 sizeof(au32CpuId), au32CpuId));
1025 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1026 }
1027 }
1028 }
1029
1030 return rc;
1031}
1032
1033
1034/**
1035 * Formats the EFLAGS value into mnemonics.
1036 *
1037 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1038 * @param efl The EFLAGS value.
1039 */
1040static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1041{
1042 /*
1043 * Format the flags.
1044 */
1045 static const struct
1046 {
1047 const char *pszSet; const char *pszClear; uint32_t fFlag;
1048 } s_aFlags[] =
1049 {
1050 { "vip",NULL, X86_EFL_VIP },
1051 { "vif",NULL, X86_EFL_VIF },
1052 { "ac", NULL, X86_EFL_AC },
1053 { "vm", NULL, X86_EFL_VM },
1054 { "rf", NULL, X86_EFL_RF },
1055 { "nt", NULL, X86_EFL_NT },
1056 { "ov", "nv", X86_EFL_OF },
1057 { "dn", "up", X86_EFL_DF },
1058 { "ei", "di", X86_EFL_IF },
1059 { "tf", NULL, X86_EFL_TF },
1060 { "nt", "pl", X86_EFL_SF },
1061 { "nz", "zr", X86_EFL_ZF },
1062 { "ac", "na", X86_EFL_AF },
1063 { "po", "pe", X86_EFL_PF },
1064 { "cy", "nc", X86_EFL_CF },
1065 };
1066 char *psz = pszEFlags;
1067 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1068 {
1069 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1070 if (pszAdd)
1071 {
1072 strcpy(psz, pszAdd);
1073 psz += strlen(pszAdd);
1074 *psz++ = ' ';
1075 }
1076 }
1077 psz[-1] = '\0';
1078}
1079
1080
1081/**
1082 * Formats a full register dump.
1083 *
1084 * @param pVM VM Handle.
1085 * @param pCtx The context to format.
1086 * @param pCtxCore The context core to format.
1087 * @param pHlp Output functions.
1088 * @param enmType The dump type.
1089 * @param pszPrefix Register name prefix.
1090 */
1091static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1092{
1093 /*
1094 * Format the EFLAGS.
1095 */
1096 uint32_t efl = pCtxCore->eflags.u32;
1097 char szEFlags[80];
1098 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1099
1100 /*
1101 * Format the registers.
1102 */
1103 switch (enmType)
1104 {
1105 case CPUMDUMPTYPE_TERSE:
1106 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1107 pHlp->pfnPrintf(pHlp,
1108 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1109 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1110 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1111 "%sr14=%016RX64 %sr15=%016RX64\n"
1112 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1113 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1114 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1115 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1116 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1117 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1118 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1119 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1120 else
1121 pHlp->pfnPrintf(pHlp,
1122 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1123 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1124 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1125 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1126 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1127 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1128 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1129 break;
1130
1131 case CPUMDUMPTYPE_DEFAULT:
1132 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1133 pHlp->pfnPrintf(pHlp,
1134 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1135 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1136 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1137 "%sr14=%016RX64 %sr15=%016RX64\n"
1138 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1139 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1140 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1141 ,
1142 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1143 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1144 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1145 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1146 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1147 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1148 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1149 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1150 else
1151 pHlp->pfnPrintf(pHlp,
1152 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1153 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1154 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1155 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1156 ,
1157 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1158 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1159 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1160 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1161 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1162 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1163 break;
1164
1165 case CPUMDUMPTYPE_VERBOSE:
1166 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1167 pHlp->pfnPrintf(pHlp,
1168 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1169 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1170 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1171 "%sr14=%016RX64 %sr15=%016RX64\n"
1172 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1173 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1174 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1175 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1176 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1177 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1178 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1179 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1180 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1181 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1182 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1183 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1184 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1185 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1186 ,
1187 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1188 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1189 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1190 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1191 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1192 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1193 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1194 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1195 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1196 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1197 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1198 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1199 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1200 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1201 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1202 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1203 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1204 else
1205 pHlp->pfnPrintf(pHlp,
1206 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1207 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1208 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1209 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1210 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1211 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1212 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1213 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1214 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1215 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1216 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1217 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1218 ,
1219 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1220 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1221 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1222 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1223 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1224 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1225 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1226 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1227 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1228 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1229 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1230 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1231
1232 pHlp->pfnPrintf(pHlp,
1233 "FPU:\n"
1234 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1235 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1236 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1237 ,
1238 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1239 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1240 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1241 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1242
1243 pHlp->pfnPrintf(pHlp,
1244 "MSR:\n"
1245 "%sEFER =%016RX64\n"
1246 "%sPAT =%016RX64\n"
1247 "%sSTAR =%016RX64\n"
1248 "%sCSTAR =%016RX64\n"
1249 "%sLSTAR =%016RX64\n"
1250 "%sSFMASK =%016RX64\n"
1251 "%sKERNELGSBASE =%016RX64\n",
1252 pszPrefix, pCtx->msrEFER,
1253 pszPrefix, pCtx->msrPAT,
1254 pszPrefix, pCtx->msrSTAR,
1255 pszPrefix, pCtx->msrCSTAR,
1256 pszPrefix, pCtx->msrLSTAR,
1257 pszPrefix, pCtx->msrSFMASK,
1258 pszPrefix, pCtx->msrKERNELGSBASE);
1259 break;
1260 }
1261}
1262
1263
1264/**
1265 * Display all cpu states and any other cpum info.
1266 *
1267 * @param pVM VM Handle.
1268 * @param pHlp The info helper functions.
1269 * @param pszArgs Arguments, ignored.
1270 */
1271static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1272{
1273 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1274 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1275 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1276 cpumR3InfoHost(pVM, pHlp, pszArgs);
1277}
1278
1279
1280/**
1281 * Parses the info argument.
1282 *
1283 * The argument starts with 'verbose', 'terse' or 'default' and then
1284 * continues with the comment string.
1285 *
1286 * @param pszArgs The pointer to the argument string.
1287 * @param penmType Where to store the dump type request.
1288 * @param ppszComment Where to store the pointer to the comment string.
1289 */
1290static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1291{
1292 if (!pszArgs)
1293 {
1294 *penmType = CPUMDUMPTYPE_DEFAULT;
1295 *ppszComment = "";
1296 }
1297 else
1298 {
1299 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1300 {
1301 pszArgs += 5;
1302 *penmType = CPUMDUMPTYPE_VERBOSE;
1303 }
1304 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1305 {
1306 pszArgs += 5;
1307 *penmType = CPUMDUMPTYPE_TERSE;
1308 }
1309 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1310 {
1311 pszArgs += 7;
1312 *penmType = CPUMDUMPTYPE_DEFAULT;
1313 }
1314 else
1315 *penmType = CPUMDUMPTYPE_DEFAULT;
1316 *ppszComment = RTStrStripL(pszArgs);
1317 }
1318}
1319
1320
1321/**
1322 * Display the guest cpu state.
1323 *
1324 * @param pVM VM Handle.
1325 * @param pHlp The info helper functions.
1326 * @param pszArgs Arguments, ignored.
1327 */
1328static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1329{
1330 CPUMDUMPTYPE enmType;
1331 const char *pszComment;
1332 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1333 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1334 /* @todo SMP */
1335 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVM);
1336 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1337}
1338
1339
1340/**
1341 * Display the current guest instruction
1342 *
1343 * @param pVM VM Handle.
1344 * @param pHlp The info helper functions.
1345 * @param pszArgs Arguments, ignored.
1346 */
1347static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1348{
1349 char szInstruction[256];
1350 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1351 if (RT_SUCCESS(rc))
1352 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1353}
1354
1355
1356/**
1357 * Display the hypervisor cpu state.
1358 *
1359 * @param pVM VM Handle.
1360 * @param pHlp The info helper functions.
1361 * @param pszArgs Arguments, ignored.
1362 */
1363static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1364{
1365 CPUMDUMPTYPE enmType;
1366 const char *pszComment;
1367 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1368 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1369 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1370 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1371}
1372
1373
1374/**
1375 * Display the host cpu state.
1376 *
1377 * @param pVM VM Handle.
1378 * @param pHlp The info helper functions.
1379 * @param pszArgs Arguments, ignored.
1380 */
1381static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1382{
1383 CPUMDUMPTYPE enmType;
1384 const char *pszComment;
1385 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1386 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1387
1388 /*
1389 * Format the EFLAGS.
1390 */
1391 /* @todo SMP */
1392 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1393#if HC_ARCH_BITS == 32
1394 uint32_t efl = pCtx->eflags.u32;
1395#else
1396 uint64_t efl = pCtx->rflags;
1397#endif
1398 char szEFlags[80];
1399 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1400
1401 /*
1402 * Format the registers.
1403 */
1404#if HC_ARCH_BITS == 32
1405# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1406 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1407# endif
1408 {
1409 pHlp->pfnPrintf(pHlp,
1410 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1411 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1412 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1413 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1414 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1415 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1416 ,
1417 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1418 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1419 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1420 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1421 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1422 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1423 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1424 }
1425# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1426 else
1427# endif
1428#endif
1429#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1430 {
1431 pHlp->pfnPrintf(pHlp,
1432 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1433 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1434 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1435 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1436 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1437 "r14=%016RX64 r15=%016RX64\n"
1438 "iopl=%d %31s\n"
1439 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1440 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1441 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1442 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1443 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1444 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1445 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1446 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1447 ,
1448 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1449 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1450 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1451 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1452 pCtx->r11, pCtx->r12, pCtx->r13,
1453 pCtx->r14, pCtx->r15,
1454 X86_EFL_GET_IOPL(efl), szEFlags,
1455 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1456 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1457 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1458 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1459 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1460 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1461 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1462 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1463 }
1464#endif
1465}
1466
1467
1468/**
1469 * Get L1 cache / TLS associativity.
1470 */
1471static const char *getCacheAss(unsigned u, char *pszBuf)
1472{
1473 if (u == 0)
1474 return "res0 ";
1475 if (u == 1)
1476 return "direct";
1477 if (u >= 256)
1478 return "???";
1479
1480 RTStrPrintf(pszBuf, 16, "%d way", u);
1481 return pszBuf;
1482}
1483
1484
1485/**
1486 * Get L2 cache soociativity.
1487 */
1488const char *getL2CacheAss(unsigned u)
1489{
1490 switch (u)
1491 {
1492 case 0: return "off ";
1493 case 1: return "direct";
1494 case 2: return "2 way ";
1495 case 3: return "res3 ";
1496 case 4: return "4 way ";
1497 case 5: return "res5 ";
1498 case 6: return "8 way "; case 7: return "res7 ";
1499 case 8: return "16 way";
1500 case 9: return "res9 ";
1501 case 10: return "res10 ";
1502 case 11: return "res11 ";
1503 case 12: return "res12 ";
1504 case 13: return "res13 ";
1505 case 14: return "res14 ";
1506 case 15: return "fully ";
1507 default:
1508 return "????";
1509 }
1510}
1511
1512
1513/**
1514 * Display the guest CpuId leaves.
1515 *
1516 * @param pVM VM Handle.
1517 * @param pHlp The info helper functions.
1518 * @param pszArgs "terse", "default" or "verbose".
1519 */
1520static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1521{
1522 /*
1523 * Parse the argument.
1524 */
1525 unsigned iVerbosity = 1;
1526 if (pszArgs)
1527 {
1528 pszArgs = RTStrStripL(pszArgs);
1529 if (!strcmp(pszArgs, "terse"))
1530 iVerbosity--;
1531 else if (!strcmp(pszArgs, "verbose"))
1532 iVerbosity++;
1533 }
1534
1535 /*
1536 * Start cracking.
1537 */
1538 CPUMCPUID Host;
1539 CPUMCPUID Guest;
1540 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1541
1542 pHlp->pfnPrintf(pHlp,
1543 " RAW Standard CPUIDs\n"
1544 " Function eax ebx ecx edx\n");
1545 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1546 {
1547 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1548 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1549
1550 pHlp->pfnPrintf(pHlp,
1551 "Gst: %08x %08x %08x %08x %08x%s\n"
1552 "Hst: %08x %08x %08x %08x\n",
1553 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1554 i <= cStdMax ? "" : "*",
1555 Host.eax, Host.ebx, Host.ecx, Host.edx);
1556 }
1557
1558 /*
1559 * If verbose, decode it.
1560 */
1561 if (iVerbosity)
1562 {
1563 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1564 pHlp->pfnPrintf(pHlp,
1565 "Name: %.04s%.04s%.04s\n"
1566 "Supports: 0-%x\n",
1567 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1568 }
1569
1570 /*
1571 * Get Features.
1572 */
1573 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1574 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1575 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1576 if (cStdMax >= 1 && iVerbosity)
1577 {
1578 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1579 uint32_t uEAX = Guest.eax;
1580
1581 pHlp->pfnPrintf(pHlp,
1582 "Family: %d \tExtended: %d \tEffective: %d\n"
1583 "Model: %d \tExtended: %d \tEffective: %d\n"
1584 "Stepping: %d\n"
1585 "APIC ID: %#04x\n"
1586 "Logical CPUs: %d\n"
1587 "CLFLUSH Size: %d\n"
1588 "Brand ID: %#04x\n",
1589 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1590 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1591 ASMGetCpuStepping(uEAX),
1592 (Guest.ebx >> 24) & 0xff,
1593 (Guest.ebx >> 16) & 0xff,
1594 (Guest.ebx >> 8) & 0xff,
1595 (Guest.ebx >> 0) & 0xff);
1596 if (iVerbosity == 1)
1597 {
1598 uint32_t uEDX = Guest.edx;
1599 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1600 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1601 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1602 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1603 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1604 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1605 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1606 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1607 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1608 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1609 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1610 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1611 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1612 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1613 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1614 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1615 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1616 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1617 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1618 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1619 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1620 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1621 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1622 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1623 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1624 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1625 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1626 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1627 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1628 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1629 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1630 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1631 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1632 pHlp->pfnPrintf(pHlp, "\n");
1633
1634 uint32_t uECX = Guest.ecx;
1635 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1636 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1637 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1638 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1639 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1640 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1641 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1642 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1643 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1644 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1645 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1646 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1647 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1648 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1649 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1650 for (unsigned iBit = 14; iBit < 32; iBit++)
1651 if (uECX & RT_BIT(iBit))
1652 pHlp->pfnPrintf(pHlp, " %d", iBit);
1653 pHlp->pfnPrintf(pHlp, "\n");
1654 }
1655 else
1656 {
1657 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1658
1659 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1660 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1661 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1662 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1663
1664 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1665 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1666 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1667 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1668 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1669 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1670 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1671 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1672 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1673 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1674 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1675 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1676 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1677 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1678 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1679 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1680 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1681 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1682 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1683 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1684 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1685 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1686 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1687 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1688 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1689 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1690 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1691 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1692 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1693 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1694 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1695 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1696 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1697
1698 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1699 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1700 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1701 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1702 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1703 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1704 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1705 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1706 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1707 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1708 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1709 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1710 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1711 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1712 }
1713 }
1714 if (cStdMax >= 2 && iVerbosity)
1715 {
1716 /** @todo */
1717 }
1718
1719 /*
1720 * Extended.
1721 * Implemented after AMD specs.
1722 */
1723 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1724
1725 pHlp->pfnPrintf(pHlp,
1726 "\n"
1727 " RAW Extended CPUIDs\n"
1728 " Function eax ebx ecx edx\n");
1729 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1730 {
1731 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1732 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1733
1734 pHlp->pfnPrintf(pHlp,
1735 "Gst: %08x %08x %08x %08x %08x%s\n"
1736 "Hst: %08x %08x %08x %08x\n",
1737 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1738 i <= cExtMax ? "" : "*",
1739 Host.eax, Host.ebx, Host.ecx, Host.edx);
1740 }
1741
1742 /*
1743 * Understandable output
1744 */
1745 if (iVerbosity)
1746 {
1747 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1748 pHlp->pfnPrintf(pHlp,
1749 "Ext Name: %.4s%.4s%.4s\n"
1750 "Ext Supports: 0x80000000-%#010x\n",
1751 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1752 }
1753
1754 if (iVerbosity && cExtMax >= 1)
1755 {
1756 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1757 uint32_t uEAX = Guest.eax;
1758 pHlp->pfnPrintf(pHlp,
1759 "Family: %d \tExtended: %d \tEffective: %d\n"
1760 "Model: %d \tExtended: %d \tEffective: %d\n"
1761 "Stepping: %d\n"
1762 "Brand ID: %#05x\n",
1763 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1764 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1765 ASMGetCpuStepping(uEAX),
1766 Guest.ebx & 0xfff);
1767
1768 if (iVerbosity == 1)
1769 {
1770 uint32_t uEDX = Guest.edx;
1771 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1772 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1773 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1774 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1775 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1776 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1777 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1778 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1779 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1780 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1781 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1782 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1783 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1784 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1785 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1786 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1787 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1788 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1789 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1790 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1791 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1792 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1793 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1794 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1795 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1796 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1797 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1798 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1799 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1800 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1801 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1802 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1803 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1804 pHlp->pfnPrintf(pHlp, "\n");
1805
1806 uint32_t uECX = Guest.ecx;
1807 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1808 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1809 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1810 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1811 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1812 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1813 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1814 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1815 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1816 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1817 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1818 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1819 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1820 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1821 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1822 for (unsigned iBit = 5; iBit < 32; iBit++)
1823 if (uECX & RT_BIT(iBit))
1824 pHlp->pfnPrintf(pHlp, " %d", iBit);
1825 pHlp->pfnPrintf(pHlp, "\n");
1826 }
1827 else
1828 {
1829 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1830
1831 uint32_t uEdxGst = Guest.edx;
1832 uint32_t uEdxHst = Host.edx;
1833 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1834 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1835 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1836 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1837 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1838 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1839 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1840 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1841 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1842 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1843 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1844 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1845 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1846 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1847 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1848 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1849 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1850 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1851 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1852 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1853 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1854 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1855 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1856 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1857 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1858 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1859 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1860 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1861 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1862 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1863 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1864 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1865 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1866
1867 uint32_t uEcxGst = Guest.ecx;
1868 uint32_t uEcxHst = Host.ecx;
1869 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1870 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1871 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1872 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1873 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1874 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1875 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1876 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1877 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1878 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1879 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1880 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1881 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1882 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1883 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1884 }
1885 }
1886
1887 if (iVerbosity && cExtMax >= 2)
1888 {
1889 char szString[4*4*3+1] = {0};
1890 uint32_t *pu32 = (uint32_t *)szString;
1891 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1892 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1893 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1894 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1895 if (cExtMax >= 3)
1896 {
1897 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1898 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1899 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1900 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1901 }
1902 if (cExtMax >= 4)
1903 {
1904 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1905 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1906 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1907 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1908 }
1909 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1910 }
1911
1912 if (iVerbosity && cExtMax >= 5)
1913 {
1914 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1915 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1916 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1917 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1918 char sz1[32];
1919 char sz2[32];
1920
1921 pHlp->pfnPrintf(pHlp,
1922 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1923 "TLB 2/4M Data: %s %3d entries\n",
1924 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1925 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1926 pHlp->pfnPrintf(pHlp,
1927 "TLB 4K Instr/Uni: %s %3d entries\n"
1928 "TLB 4K Data: %s %3d entries\n",
1929 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1930 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1931 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1932 "L1 Instr Cache Lines Per Tag: %d\n"
1933 "L1 Instr Cache Associativity: %s\n"
1934 "L1 Instr Cache Size: %d KB\n",
1935 (uEDX >> 0) & 0xff,
1936 (uEDX >> 8) & 0xff,
1937 getCacheAss((uEDX >> 16) & 0xff, sz1),
1938 (uEDX >> 24) & 0xff);
1939 pHlp->pfnPrintf(pHlp,
1940 "L1 Data Cache Line Size: %d bytes\n"
1941 "L1 Data Cache Lines Per Tag: %d\n"
1942 "L1 Data Cache Associativity: %s\n"
1943 "L1 Data Cache Size: %d KB\n",
1944 (uECX >> 0) & 0xff,
1945 (uECX >> 8) & 0xff,
1946 getCacheAss((uECX >> 16) & 0xff, sz1),
1947 (uECX >> 24) & 0xff);
1948 }
1949
1950 if (iVerbosity && cExtMax >= 6)
1951 {
1952 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1953 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1954 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1955
1956 pHlp->pfnPrintf(pHlp,
1957 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1958 "L2 TLB 2/4M Data: %s %4d entries\n",
1959 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1960 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1961 pHlp->pfnPrintf(pHlp,
1962 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1963 "L2 TLB 4K Data: %s %4d entries\n",
1964 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1965 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1966 pHlp->pfnPrintf(pHlp,
1967 "L2 Cache Line Size: %d bytes\n"
1968 "L2 Cache Lines Per Tag: %d\n"
1969 "L2 Cache Associativity: %s\n"
1970 "L2 Cache Size: %d KB\n",
1971 (uEDX >> 0) & 0xff,
1972 (uEDX >> 8) & 0xf,
1973 getL2CacheAss((uEDX >> 12) & 0xf),
1974 (uEDX >> 16) & 0xffff);
1975 }
1976
1977 if (iVerbosity && cExtMax >= 7)
1978 {
1979 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1980
1981 pHlp->pfnPrintf(pHlp, "APM Features: ");
1982 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1983 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1984 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1985 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1986 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1987 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1988 for (unsigned iBit = 6; iBit < 32; iBit++)
1989 if (uEDX & RT_BIT(iBit))
1990 pHlp->pfnPrintf(pHlp, " %d", iBit);
1991 pHlp->pfnPrintf(pHlp, "\n");
1992 }
1993
1994 if (iVerbosity && cExtMax >= 8)
1995 {
1996 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1997 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1998
1999 pHlp->pfnPrintf(pHlp,
2000 "Physical Address Width: %d bits\n"
2001 "Virtual Address Width: %d bits\n",
2002 (uEAX >> 0) & 0xff,
2003 (uEAX >> 8) & 0xff);
2004 pHlp->pfnPrintf(pHlp,
2005 "Physical Core Count: %d\n",
2006 (uECX >> 0) & 0xff);
2007 }
2008
2009
2010 /*
2011 * Centaur.
2012 */
2013 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2014
2015 pHlp->pfnPrintf(pHlp,
2016 "\n"
2017 " RAW Centaur CPUIDs\n"
2018 " Function eax ebx ecx edx\n");
2019 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2020 {
2021 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2022 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2023
2024 pHlp->pfnPrintf(pHlp,
2025 "Gst: %08x %08x %08x %08x %08x%s\n"
2026 "Hst: %08x %08x %08x %08x\n",
2027 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2028 i <= cCentaurMax ? "" : "*",
2029 Host.eax, Host.ebx, Host.ecx, Host.edx);
2030 }
2031
2032 /*
2033 * Understandable output
2034 */
2035 if (iVerbosity)
2036 {
2037 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2038 pHlp->pfnPrintf(pHlp,
2039 "Centaur Supports: 0xc0000000-%#010x\n",
2040 Guest.eax);
2041 }
2042
2043 if (iVerbosity && cCentaurMax >= 1)
2044 {
2045 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2046 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2047 uint32_t uEdxHst = Host.edx;
2048
2049 if (iVerbosity == 1)
2050 {
2051 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2052 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2053 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2054 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2055 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2056 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2057 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2058 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2059 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2060 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2061 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2062 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2063 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2064 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2065 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2066 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2067 for (unsigned iBit = 14; iBit < 32; iBit++)
2068 if (uEdxGst & RT_BIT(iBit))
2069 pHlp->pfnPrintf(pHlp, " %d", iBit);
2070 pHlp->pfnPrintf(pHlp, "\n");
2071 }
2072 else
2073 {
2074 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2075 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2076 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2077 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2078 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2079 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2080 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2081 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2082 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2083 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2084 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2085 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2086 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2087 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2088 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2089 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2090 for (unsigned iBit = 14; iBit < 32; iBit++)
2091 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2092 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2093 pHlp->pfnPrintf(pHlp, "\n");
2094 }
2095 }
2096}
2097
2098
2099/**
2100 * Structure used when disassembling and instructions in DBGF.
2101 * This is used so the reader function can get the stuff it needs.
2102 */
2103typedef struct CPUMDISASSTATE
2104{
2105 /** Pointer to the CPU structure. */
2106 PDISCPUSTATE pCpu;
2107 /** The VM handle. */
2108 PVM pVM;
2109 /** Pointer to the first byte in the segemnt. */
2110 RTGCUINTPTR GCPtrSegBase;
2111 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2112 RTGCUINTPTR GCPtrSegEnd;
2113 /** The size of the segment minus 1. */
2114 RTGCUINTPTR cbSegLimit;
2115 /** Pointer to the current page - R3 Ptr. */
2116 void const *pvPageR3;
2117 /** Pointer to the current page - GC Ptr. */
2118 RTGCPTR pvPageGC;
2119 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2120 PGMPAGEMAPLOCK PageMapLock;
2121 /** Whether the PageMapLock is valid or not. */
2122 bool fLocked;
2123 /** 64 bits mode or not. */
2124 bool f64Bits;
2125} CPUMDISASSTATE, *PCPUMDISASSTATE;
2126
2127
2128/**
2129 * Instruction reader.
2130 *
2131 * @returns VBox status code.
2132 * @param PtrSrc Address to read from.
2133 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2134 * @param pu8Dst Where to store the bytes.
2135 * @param cbRead Number of bytes to read.
2136 * @param uDisCpu Pointer to the disassembler cpu state.
2137 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2138 */
2139static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2140{
2141 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2142 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2143 Assert(cbRead > 0);
2144 for (;;)
2145 {
2146 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2147
2148 /* Need to update the page translation? */
2149 if ( !pState->pvPageR3
2150 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2151 {
2152 int rc = VINF_SUCCESS;
2153
2154 /* translate the address */
2155 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2156 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2157 && !HWACCMIsEnabled(pState->pVM))
2158 {
2159 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2160 if (!pState->pvPageR3)
2161 rc = VERR_INVALID_POINTER;
2162 }
2163 else
2164 {
2165 /* Release mapping lock previously acquired. */
2166 if (pState->fLocked)
2167 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2168 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2169 pState->fLocked = RT_SUCCESS_NP(rc);
2170 }
2171 if (RT_FAILURE(rc))
2172 {
2173 pState->pvPageR3 = NULL;
2174 return rc;
2175 }
2176 }
2177
2178 /* check the segemnt limit */
2179 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2180 return VERR_OUT_OF_SELECTOR_BOUNDS;
2181
2182 /* calc how much we can read */
2183 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2184 if (!pState->f64Bits)
2185 {
2186 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2187 if (cb > cbSeg && cbSeg)
2188 cb = cbSeg;
2189 }
2190 if (cb > cbRead)
2191 cb = cbRead;
2192
2193 /* read and advance */
2194 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2195 cbRead -= cb;
2196 if (!cbRead)
2197 return VINF_SUCCESS;
2198 pu8Dst += cb;
2199 PtrSrc += cb;
2200 }
2201}
2202
2203
2204/**
2205 * Disassemble an instruction and return the information in the provided structure.
2206 *
2207 * @returns VBox status code.
2208 * @param pVM VM Handle
2209 * @param pCtx CPU context
2210 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2211 * @param pCpu Disassembly state
2212 * @param pszPrefix String prefix for logging (debug only)
2213 *
2214 */
2215VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2216{
2217 CPUMDISASSTATE State;
2218 int rc;
2219
2220 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2221 State.pCpu = pCpu;
2222 State.pvPageGC = 0;
2223 State.pvPageR3 = NULL;
2224 State.pVM = pVM;
2225 State.fLocked = false;
2226 State.f64Bits = false;
2227
2228 /*
2229 * Get selector information.
2230 */
2231 if ( (pCtx->cr0 & X86_CR0_PE)
2232 && pCtx->eflags.Bits.u1VM == 0)
2233 {
2234 if (CPUMAreHiddenSelRegsValid(pVM))
2235 {
2236 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2237 State.GCPtrSegBase = pCtx->csHid.u64Base;
2238 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2239 State.cbSegLimit = pCtx->csHid.u32Limit;
2240 pCpu->mode = (State.f64Bits)
2241 ? CPUMODE_64BIT
2242 : pCtx->csHid.Attr.n.u1DefBig
2243 ? CPUMODE_32BIT
2244 : CPUMODE_16BIT;
2245 }
2246 else
2247 {
2248 SELMSELINFO SelInfo;
2249
2250 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2251 if (!RT_SUCCESS(rc))
2252 {
2253 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2254 return rc;
2255 }
2256
2257 /*
2258 * Validate the selector.
2259 */
2260 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2261 if (!RT_SUCCESS(rc))
2262 {
2263 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2264 return rc;
2265 }
2266 State.GCPtrSegBase = SelInfo.GCPtrBase;
2267 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2268 State.cbSegLimit = SelInfo.cbLimit;
2269 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2270 }
2271 }
2272 else
2273 {
2274 /* real or V86 mode */
2275 pCpu->mode = CPUMODE_16BIT;
2276 State.GCPtrSegBase = pCtx->cs * 16;
2277 State.GCPtrSegEnd = 0xFFFFFFFF;
2278 State.cbSegLimit = 0xFFFFFFFF;
2279 }
2280
2281 /*
2282 * Disassemble the instruction.
2283 */
2284 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2285 pCpu->apvUserData[0] = &State;
2286
2287 uint32_t cbInstr;
2288#ifndef LOG_ENABLED
2289 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2290 if (RT_SUCCESS(rc))
2291 {
2292#else
2293 char szOutput[160];
2294 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2295 if (RT_SUCCESS(rc))
2296 {
2297 /* log it */
2298 if (pszPrefix)
2299 Log(("%s: %s", pszPrefix, szOutput));
2300 else
2301 Log(("%s", szOutput));
2302#endif
2303 rc = VINF_SUCCESS;
2304 }
2305 else
2306 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2307
2308 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2309 if (State.fLocked)
2310 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2311
2312 return rc;
2313}
2314
2315#ifdef DEBUG
2316
2317/**
2318 * Disassemble an instruction and dump it to the log
2319 *
2320 * @returns VBox status code.
2321 * @param pVM VM Handle
2322 * @param pCtx CPU context
2323 * @param pc GC instruction pointer
2324 * @param pszPrefix String prefix for logging
2325 *
2326 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2327 */
2328VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2329{
2330 DISCPUSTATE Cpu;
2331 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &Cpu, pszPrefix);
2332}
2333
2334
2335/**
2336 * Disassemble an instruction and dump it to the log
2337 *
2338 * @returns VBox status code.
2339 * @param pVM VM Handle
2340 * @param pCtx CPU context
2341 * @param pc GC instruction pointer
2342 * @param pszPrefix String prefix for logging
2343 * @param nrInstructions
2344 *
2345 * @deprecated Create new DBGFR3Disas function to do this.
2346 */
2347VMMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix, int nrInstructions)
2348{
2349 for (int i = 0; i < nrInstructions; i++)
2350 {
2351 DISCPUSTATE cpu;
2352
2353 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, pszPrefix);
2354 pc += cpu.opsize;
2355 }
2356}
2357
2358
2359/**
2360 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2361 *
2362 * @internal
2363 */
2364VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2365{
2366 /* @todo SMP */
2367 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(pVM);
2368}
2369
2370#endif /* DEBUG */
2371
2372/**
2373 * API for controlling a few of the CPU features found in CR4.
2374 *
2375 * Currently only X86_CR4_TSD is accepted as input.
2376 *
2377 * @returns VBox status code.
2378 *
2379 * @param pVM The VM handle.
2380 * @param fOr The CR4 OR mask.
2381 * @param fAnd The CR4 AND mask.
2382 */
2383VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2384{
2385 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2386 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2387
2388 pVM->cpum.s.CR4.OrMask &= fAnd;
2389 pVM->cpum.s.CR4.OrMask |= fOr;
2390
2391 return VINF_SUCCESS;
2392}
2393
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