VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 14792

Last change on this file since 14792 was 14762, checked in by vboxsync, 16 years ago

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1/* $Id: CPUM.cpp 14762 2008-11-28 09:32:12Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 10
71/** The saved state version for the 2.1 trunk before the MSR changes. */
72#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
73/** The saved state version of 2.0, used for backwards compatibility. */
74#define CPUM_SAVED_STATE_VERSION_VER2_0 8
75/** The saved state version of 1.6, used for backwards compatability. */
76#define CPUM_SAVED_STATE_VERSION_VER1_6 6
77
78
79/*******************************************************************************
80* Structures and Typedefs *
81*******************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91
92} CPUMDUMPTYPE;
93/** Pointer to a cpu info dump type. */
94typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97/*******************************************************************************
98* Internal Functions *
99*******************************************************************************/
100static int cpumR3CpuIdInit(PVM pVM);
101static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/**
112 * Initializes the CPUM.
113 *
114 * @returns VBox status code.
115 * @param pVM The VM to operate on.
116 */
117VMMR3DECL(int) CPUMR3Init(PVM pVM)
118{
119 LogFlow(("CPUMR3Init\n"));
120
121 /*
122 * Assert alignment and sizes.
123 */
124 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
125 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
126
127 /*
128 * Setup any fixed pointers and offsets.
129 */
130 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
131 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
132
133 /* Hidden selector registers are invalid by default. */
134 pVM->cpum.s.fValidHiddenSelRegs = false;
135
136 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
137 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
138 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
139
140 /* Calculate the offset from CPUMCPU to CPUM. */
141 for (unsigned i=0;i<pVM->cCPUs;i++)
142 {
143 pVM->aCpus[i].cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
144 Assert((uintptr_t)&pVM->aCpus[i].cpum - pVM->aCpus[i].cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
145 }
146
147 /*
148 * Check that the CPU supports the minimum features we require.
149 */
150 if (!ASMHasCpuId())
151 {
152 Log(("The CPU doesn't support CPUID!\n"));
153 return VERR_UNSUPPORTED_CPU;
154 }
155 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
156 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
157
158 /* Setup the CR4 AND and OR masks used in the switcher */
159 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
160 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
161 {
162 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
163 /* No FXSAVE implies no SSE */
164 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
165 pVM->cpum.s.CR4.OrMask = 0;
166 }
167 else
168 {
169 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
170 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
171 }
172
173 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
174 {
175 Log(("The CPU doesn't support MMX!\n"));
176 return VERR_UNSUPPORTED_CPU;
177 }
178 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
179 {
180 Log(("The CPU doesn't support TSC!\n"));
181 return VERR_UNSUPPORTED_CPU;
182 }
183 /* Bogus on AMD? */
184 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
185 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
186
187 /*
188 * Setup hypervisor startup values.
189 */
190
191 /*
192 * Register saved state data item.
193 */
194 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
195 NULL, cpumR3Save, NULL,
196 NULL, cpumR3Load, NULL);
197 if (RT_FAILURE(rc))
198 return rc;
199
200 /* Query the CPU manufacturer. */
201 uint32_t uEAX, uEBX, uECX, uEDX;
202 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
203 if ( uEAX >= 1
204 && uEBX == X86_CPUID_VENDOR_AMD_EBX
205 && uECX == X86_CPUID_VENDOR_AMD_ECX
206 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
207 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
208 else if ( uEAX >= 1
209 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
210 && uECX == X86_CPUID_VENDOR_INTEL_ECX
211 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
212 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
213 else /** @todo Via */
214 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
215
216 /*
217 * Register info handlers.
218 */
219 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
220 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
221 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
222 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
223 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
224 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
225
226 /*
227 * Initialize the Guest CPU state.
228 */
229 rc = cpumR3CpuIdInit(pVM);
230 if (RT_FAILURE(rc))
231 return rc;
232 CPUMR3Reset(pVM);
233 return VINF_SUCCESS;
234}
235
236
237/**
238 * Initializes the per-VCPU CPUM.
239 *
240 * @returns VBox status code.
241 * @param pVM The VM to operate on.
242 */
243VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
244{
245 LogFlow(("CPUMR3InitCPU\n"));
246 return VINF_SUCCESS;
247}
248
249
250/**
251 * Initializes the emulated CPU's cpuid information.
252 *
253 * @returns VBox status code.
254 * @param pVM The VM to operate on.
255 */
256static int cpumR3CpuIdInit(PVM pVM)
257{
258 PCPUM pCPUM = &pVM->cpum.s;
259 uint32_t i;
260
261 /*
262 * Get the host CPUIDs.
263 */
264 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
265 ASMCpuId_Idx_ECX(i, 0,
266 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
267 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
268 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
269 ASMCpuId(0x80000000 + i,
270 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
271 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
272 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
273 ASMCpuId(0xc0000000 + i,
274 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
275 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
276
277
278 /*
279 * Only report features we can support.
280 */
281 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
282 | X86_CPUID_FEATURE_EDX_VME
283 | X86_CPUID_FEATURE_EDX_DE
284 | X86_CPUID_FEATURE_EDX_PSE
285 | X86_CPUID_FEATURE_EDX_TSC
286 | X86_CPUID_FEATURE_EDX_MSR
287 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
288 | X86_CPUID_FEATURE_EDX_MCE
289 | X86_CPUID_FEATURE_EDX_CX8
290 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
291 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
292 //| X86_CPUID_FEATURE_EDX_SEP
293 | X86_CPUID_FEATURE_EDX_MTRR
294 | X86_CPUID_FEATURE_EDX_PGE
295 | X86_CPUID_FEATURE_EDX_MCA
296 | X86_CPUID_FEATURE_EDX_CMOV
297 | X86_CPUID_FEATURE_EDX_PAT
298 | X86_CPUID_FEATURE_EDX_PSE36
299 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
300 | X86_CPUID_FEATURE_EDX_CLFSH
301 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
302 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
303 | X86_CPUID_FEATURE_EDX_MMX
304 | X86_CPUID_FEATURE_EDX_FXSR
305 | X86_CPUID_FEATURE_EDX_SSE
306 | X86_CPUID_FEATURE_EDX_SSE2
307 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
308 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
309 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
310 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
311 | 0;
312 pCPUM->aGuestCpuIdStd[1].ecx &= 0
313#ifdef VBOX_WITH_NEW_RECOMPILER
314 | X86_CPUID_FEATURE_ECX_SSE3
315#endif
316 | X86_CPUID_FEATURE_ECX_MONITOR
317 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
318 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
319 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
320 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
321 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
322 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
323 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
324 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
325 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
326 /* ECX Bit 21 - x2APIC support - not yet. */
327 // | X86_CPUID_FEATURE_ECX_X2APIC
328 /* ECX Bit 23 - POPCOUNT instruction. */
329 //| X86_CPUID_FEATURE_ECX_POPCOUNT
330 | 0;
331
332 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
333 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
334 | X86_CPUID_AMD_FEATURE_EDX_VME
335 | X86_CPUID_AMD_FEATURE_EDX_DE
336 | X86_CPUID_AMD_FEATURE_EDX_PSE
337 | X86_CPUID_AMD_FEATURE_EDX_TSC
338 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
339 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
340 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
341 | X86_CPUID_AMD_FEATURE_EDX_CX8
342 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
343 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
344 //| X86_CPUID_AMD_FEATURE_EDX_SEP
345 | X86_CPUID_AMD_FEATURE_EDX_MTRR
346 | X86_CPUID_AMD_FEATURE_EDX_PGE
347 | X86_CPUID_AMD_FEATURE_EDX_MCA
348 | X86_CPUID_AMD_FEATURE_EDX_CMOV
349 | X86_CPUID_AMD_FEATURE_EDX_PAT
350 | X86_CPUID_AMD_FEATURE_EDX_PSE36
351 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
352 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
353 | X86_CPUID_AMD_FEATURE_EDX_MMX
354 | X86_CPUID_AMD_FEATURE_EDX_FXSR
355 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
356 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
357 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
358 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
359 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
360 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
361 | 0;
362 pCPUM->aGuestCpuIdExt[1].ecx &= 0
363 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
364 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
365 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
366 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
367 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
368 //| X86_CPUID_AMD_FEATURE_ECX_ABM
369 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
370 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
371 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
372 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
373 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
374 //| X86_CPUID_AMD_FEATURE_ECX_WDT
375 | 0;
376
377 /*
378 * Hide HTT, multicode, SMP, whatever.
379 * (APIC-ID := 0 and #LogCpus := 0)
380 */
381 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
382
383 /* Cpuid 2:
384 * Intel: Cache and TLB information
385 * AMD: Reserved
386 * Safe to expose
387 */
388
389 /* Cpuid 3:
390 * Intel: EAX, EBX - reserved
391 * ECX, EDX - Processor Serial Number if available, otherwise reserved
392 * AMD: Reserved
393 * Safe to expose
394 */
395 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
396 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
397
398 /* Cpuid 4:
399 * Intel: Deterministic Cache Parameters Leaf
400 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
401 * AMD: Reserved
402 * Safe to expose, except for EAX:
403 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
404 * Bits 31-26: Maximum number of processor cores in this physical package**
405 */
406 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
407 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
408
409 /* Cpuid 5: Monitor/mwait Leaf
410 * Intel: ECX, EDX - reserved
411 * EAX, EBX - Smallest and largest monitor line size
412 * AMD: EDX - reserved
413 * EAX, EBX - Smallest and largest monitor line size
414 * ECX - extensions (ignored for now)
415 * Safe to expose
416 */
417 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
418 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
419
420 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
421
422 /*
423 * Determine the default.
424 *
425 * Intel returns values of the highest standard function, while AMD
426 * returns zeros. VIA on the other hand seems to returning nothing or
427 * perhaps some random garbage, we don't try to duplicate this behavior.
428 */
429 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
430 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
431 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
432
433 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
434 * Safe to pass on to the guest.
435 *
436 * Intel: 0x800000005 reserved
437 * 0x800000006 L2 cache information
438 * AMD: 0x800000005 L1 cache information
439 * 0x800000006 L2/L3 cache information
440 */
441
442 /* Cpuid 0x800000007:
443 * AMD: EAX, EBX, ECX - reserved
444 * EDX: Advanced Power Management Information
445 * Intel: Reserved
446 */
447 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
448 {
449 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
450
451 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
452
453 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
454 {
455 /* Only expose the TSC invariant capability bit to the guest. */
456 pCPUM->aGuestCpuIdExt[7].edx &= 0
457 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
458 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
459 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
460 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
461 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
462 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
463 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
464 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
465 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
466 | 0;
467 }
468 else
469 pCPUM->aGuestCpuIdExt[7].edx = 0;
470 }
471
472 /* Cpuid 0x800000008:
473 * AMD: EBX, EDX - reserved
474 * EAX: Virtual/Physical address Size
475 * ECX: Number of cores + APICIdCoreIdSize
476 * Intel: EAX: Virtual/Physical address Size
477 * EBX, ECX, EDX - reserved
478 */
479 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
480 {
481 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
482 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
483 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
484 * NC (0-7) Number of cores; 0 equals 1 core */
485 pCPUM->aGuestCpuIdExt[8].ecx = 0;
486 }
487
488 /*
489 * Limit it the number of entries and fill the remaining with the defaults.
490 *
491 * The limits are masking off stuff about power saving and similar, this
492 * is perhaps a bit crudely done as there is probably some relatively harmless
493 * info too in these leaves (like words about having a constant TSC).
494 */
495#if 0
496 /** @todo NT4 installation regression - investigate */
497 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
498 pCPUM->aGuestCpuIdStd[0].eax = 5;
499#else
500 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
501 pCPUM->aGuestCpuIdStd[0].eax = 2;
502#endif
503 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
504 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
505
506 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
507 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
508 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
509 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
510 : 0;
511 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
512 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
513
514 /*
515 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
516 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
517 * We currently don't support more than 1 processor.
518 */
519 pCPUM->aGuestCpuIdStd[4].eax = 0;
520
521 /*
522 * Centaur stuff (VIA).
523 *
524 * The important part here (we think) is to make sure the 0xc0000000
525 * function returns 0xc0000001. As for the features, we don't currently
526 * let on about any of those... 0xc0000002 seems to be some
527 * temperature/hz/++ stuff, include it as well (static).
528 */
529 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
530 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
531 {
532 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
533 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
534 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
535 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
536 i++)
537 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
538 }
539 else
540 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
541 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
542
543
544 /*
545 * Load CPUID overrides from configuration.
546 */
547 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
548 * Overloads the CPUID leaf values. */
549 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
550 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
551 for (i=0;; )
552 {
553 while (cElements-- > 0)
554 {
555 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
556 if (pNode)
557 {
558 uint32_t u32;
559 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
560 if (RT_SUCCESS(rc))
561 pCpuId->eax = u32;
562 else
563 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
564
565 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
566 if (RT_SUCCESS(rc))
567 pCpuId->ebx = u32;
568 else
569 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
570
571 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
572 if (RT_SUCCESS(rc))
573 pCpuId->ecx = u32;
574 else
575 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
576
577 rc = CFGMR3QueryU32(pNode, "edx", &u32);
578 if (RT_SUCCESS(rc))
579 pCpuId->edx = u32;
580 else
581 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
582 }
583 pCpuId++;
584 i++;
585 }
586
587 /* next */
588 if ((i & UINT32_C(0xc0000000)) == 0)
589 {
590 pCpuId = &pCPUM->aGuestCpuIdExt[0];
591 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
592 i = UINT32_C(0x80000000);
593 }
594 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
595 {
596 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
597 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
598 i = UINT32_C(0xc0000000);
599 }
600 else
601 break;
602 }
603
604 /* Check if PAE was explicitely enabled by the user. */
605 bool fEnable = false;
606 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
607 if (RT_SUCCESS(rc) && fEnable)
608 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
609
610 /*
611 * Log the cpuid and we're good.
612 */
613 RTCPUSET OnlineSet;
614 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
615 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
616 LogRel(("************************* CPUID dump ************************\n"));
617 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
618 LogRel(("\n"));
619 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
620 LogRel(("******************** End of CPUID dump **********************\n"));
621 return VINF_SUCCESS;
622}
623
624
625
626
627/**
628 * Applies relocations to data and code managed by this
629 * component. This function will be called at init and
630 * whenever the VMM need to relocate it self inside the GC.
631 *
632 * The CPUM will update the addresses used by the switcher.
633 *
634 * @param pVM The VM.
635 */
636VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
637{
638 LogFlow(("CPUMR3Relocate\n"));
639 /*
640 * Switcher pointers.
641 */
642 pVM->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
643 Assert(pVM->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
644}
645
646
647/**
648 * Terminates the CPUM.
649 *
650 * Termination means cleaning up and freeing all resources,
651 * the VM it self is at this point powered off or suspended.
652 *
653 * @returns VBox status code.
654 * @param pVM The VM to operate on.
655 */
656VMMR3DECL(int) CPUMR3Term(PVM pVM)
657{
658 /** @todo ? */
659 return 0;
660}
661
662
663/**
664 * Terminates the per-VCPU CPUM.
665 *
666 * Termination means cleaning up and freeing all resources,
667 * the VM it self is at this point powered off or suspended.
668 *
669 * @returns VBox status code.
670 * @param pVM The VM to operate on.
671 */
672VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
673{
674 return 0;
675}
676
677
678/**
679 * Resets the CPU.
680 *
681 * @returns VINF_SUCCESS.
682 * @param pVM The VM handle.
683 */
684VMMR3DECL(void) CPUMR3Reset(PVM pVM)
685{
686 /* @todo anything different for VCPU > 0? */
687 for (unsigned i=0;i<pVM->cCPUs;i++)
688 {
689 PCPUMCTX pCtx = CPUMQueryGuestCtxPtrEx(pVM, &pVM->aCpus[i]);
690
691 /*
692 * Initialize everything to ZERO first.
693 */
694 uint32_t fUseFlags = pVM->aCpus[i].cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
695 memset(pCtx, 0, sizeof(*pCtx));
696 pVM->aCpus[i].cpum.s.fUseFlags = fUseFlags;
697
698 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
699 pCtx->eip = 0x0000fff0;
700 pCtx->edx = 0x00000600; /* P6 processor */
701 pCtx->eflags.Bits.u1Reserved0 = 1;
702
703 pCtx->cs = 0xf000;
704 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
705 pCtx->csHid.u32Limit = 0x0000ffff;
706 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
707 pCtx->csHid.Attr.n.u1Present = 1;
708 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
709
710 pCtx->dsHid.u32Limit = 0x0000ffff;
711 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
712 pCtx->dsHid.Attr.n.u1Present = 1;
713 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
714
715 pCtx->esHid.u32Limit = 0x0000ffff;
716 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
717 pCtx->esHid.Attr.n.u1Present = 1;
718 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
719
720 pCtx->fsHid.u32Limit = 0x0000ffff;
721 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
722 pCtx->fsHid.Attr.n.u1Present = 1;
723 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
724
725 pCtx->gsHid.u32Limit = 0x0000ffff;
726 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
727 pCtx->gsHid.Attr.n.u1Present = 1;
728 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
729
730 pCtx->ssHid.u32Limit = 0x0000ffff;
731 pCtx->ssHid.Attr.n.u1Present = 1;
732 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
733 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
734
735 pCtx->idtr.cbIdt = 0xffff;
736 pCtx->gdtr.cbGdt = 0xffff;
737
738 pCtx->ldtrHid.u32Limit = 0xffff;
739 pCtx->ldtrHid.Attr.n.u1Present = 1;
740 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
741
742 pCtx->trHid.u32Limit = 0xffff;
743 pCtx->trHid.Attr.n.u1Present = 1;
744 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
745
746 pCtx->dr[6] = X86_DR6_INIT_VAL;
747 pCtx->dr[7] = X86_DR7_INIT_VAL;
748
749 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
750 pCtx->fpu.FCW = 0x37f;
751
752 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
753 pCtx->fpu.MXCSR = 0x1F80;
754
755 /* Init PAT MSR */
756 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
757
758 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
759 * The Intel docs don't mention it.
760 */
761 pCtx->msrEFER = 0;
762 }
763}
764
765
766/**
767 * Execute state save operation.
768 *
769 * @returns VBox status code.
770 * @param pVM VM Handle.
771 * @param pSSM SSM operation handle.
772 */
773static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
774{
775 /* Set the size of RTGCPTR for use of SSMR3Get/PutGCPtr. */
776 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
777
778 /*
779 * Save.
780 */
781 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
782
783 SSMR3PutU32(pSSM, pVM->cCPUs);
784 for (unsigned i=0;i<pVM->cCPUs;i++)
785 {
786 SSMR3PutMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
787 SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fUseFlags);
788 SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fChanged);
789 SSMR3PutMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
790 }
791
792 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
793 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
794
795 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
796 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
797
798 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
799 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
800
801 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
802
803 /* Add the cpuid for checking that the cpu is unchanged. */
804 uint32_t au32CpuId[8] = {0};
805 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
806 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
807 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
808}
809
810
811/**
812 * Load a version 1.6 CPUMCTX structure.
813 *
814 * @returns VBox status code.
815 * @param pVM VM Handle.
816 * @param pCpumctx16 Version 1.6 CPUMCTX
817 */
818static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
819{
820#define CPUMCTX16_LOADREG(RegName) \
821 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
822
823#define CPUMCTX16_LOADDRXREG(RegName) \
824 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
825
826#define CPUMCTX16_LOADHIDREG(RegName) \
827 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
828 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
829 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
830
831#define CPUMCTX16_LOADSEGREG(RegName) \
832 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
833 CPUMCTX16_LOADHIDREG(RegName);
834
835 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
836
837 CPUMCTX16_LOADREG(rax);
838 CPUMCTX16_LOADREG(rbx);
839 CPUMCTX16_LOADREG(rcx);
840 CPUMCTX16_LOADREG(rdx);
841 CPUMCTX16_LOADREG(rdi);
842 CPUMCTX16_LOADREG(rsi);
843 CPUMCTX16_LOADREG(rbp);
844 CPUMCTX16_LOADREG(esp);
845 CPUMCTX16_LOADREG(rip);
846 CPUMCTX16_LOADREG(rflags);
847
848 CPUMCTX16_LOADSEGREG(cs);
849 CPUMCTX16_LOADSEGREG(ds);
850 CPUMCTX16_LOADSEGREG(es);
851 CPUMCTX16_LOADSEGREG(fs);
852 CPUMCTX16_LOADSEGREG(gs);
853 CPUMCTX16_LOADSEGREG(ss);
854
855 CPUMCTX16_LOADREG(r8);
856 CPUMCTX16_LOADREG(r9);
857 CPUMCTX16_LOADREG(r10);
858 CPUMCTX16_LOADREG(r11);
859 CPUMCTX16_LOADREG(r12);
860 CPUMCTX16_LOADREG(r13);
861 CPUMCTX16_LOADREG(r14);
862 CPUMCTX16_LOADREG(r15);
863
864 CPUMCTX16_LOADREG(cr0);
865 CPUMCTX16_LOADREG(cr2);
866 CPUMCTX16_LOADREG(cr3);
867 CPUMCTX16_LOADREG(cr4);
868
869 CPUMCTX16_LOADDRXREG(0);
870 CPUMCTX16_LOADDRXREG(1);
871 CPUMCTX16_LOADDRXREG(2);
872 CPUMCTX16_LOADDRXREG(3);
873 CPUMCTX16_LOADDRXREG(4);
874 CPUMCTX16_LOADDRXREG(5);
875 CPUMCTX16_LOADDRXREG(6);
876 CPUMCTX16_LOADDRXREG(7);
877
878 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
879 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
880 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
881 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
882
883 CPUMCTX16_LOADREG(ldtr);
884 CPUMCTX16_LOADREG(tr);
885
886 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
887
888 CPUMCTX16_LOADREG(msrEFER);
889 CPUMCTX16_LOADREG(msrSTAR);
890 CPUMCTX16_LOADREG(msrPAT);
891 CPUMCTX16_LOADREG(msrLSTAR);
892 CPUMCTX16_LOADREG(msrCSTAR);
893 CPUMCTX16_LOADREG(msrSFMASK);
894 CPUMCTX16_LOADREG(msrKERNELGSBASE);
895
896 CPUMCTX16_LOADHIDREG(ldtr);
897 CPUMCTX16_LOADHIDREG(tr);
898
899#undef CPUMCTX16_LOADSEGREG
900#undef CPUMCTX16_LOADHIDREG
901#undef CPUMCTX16_LOADDRXREG
902#undef CPUMCTX16_LOADREG
903}
904
905
906/**
907 * Execute state load operation.
908 *
909 * @returns VBox status code.
910 * @param pVM VM Handle.
911 * @param pSSM SSM operation handle.
912 * @param u32Version Data layout version.
913 */
914static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
915{
916 /*
917 * Validate version.
918 */
919 if ( u32Version != CPUM_SAVED_STATE_VERSION
920 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
921 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
922 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
923 {
924 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
925 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
926 }
927
928 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
929 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
930 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
931 else
932 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
933
934 /*
935 * Restore.
936 */
937 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
938 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
939 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
940 pVM->cpum.s.Hyper.cr3 = uCR3;
941 pVM->cpum.s.Hyper.esp = uESP;
942 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
943 {
944 CPUMCTX_VER1_6 cpumctx16;
945 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
946 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
947
948 /* Save the old cpumctx state into the new one. */
949 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
950
951 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
952 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
953 }
954 else
955 {
956 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
957 {
958 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
959 AssertRCReturn(rc, rc);
960 }
961
962 if ( !pVM->cCPUs
963 || pVM->cCPUs > VMCPU_MAX_CPU_COUNT
964 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
965 && pVM->cCPUs != 1))
966 {
967 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
968 return VERR_SSM_UNEXPECTED_DATA;
969 }
970
971 for (unsigned i=0;i<pVM->cCPUs;i++)
972 {
973 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
974 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
975 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
976 if (u32Version == CPUM_SAVED_STATE_VERSION)
977 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
978 }
979 }
980
981
982 uint32_t cElements;
983 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
984 /* Support old saved states with a smaller standard cpuid array. */
985 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
986 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
987 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
988
989 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
990 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
991 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
992 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
993
994 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
995 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
996 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
997 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
998
999 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1000
1001 /*
1002 * Check that the basic cpuid id information is unchanged.
1003 */
1004 uint32_t au32CpuId[8] = {0};
1005 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1006 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1007 uint32_t au32CpuIdSaved[8];
1008 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1009 if (RT_SUCCESS(rc))
1010 {
1011 /* Ignore APIC ID (AMD specs). */
1012 au32CpuId[5] &= ~0xff000000;
1013 au32CpuIdSaved[5] &= ~0xff000000;
1014 /* Ignore the number of Logical CPUs (AMD specs). */
1015 au32CpuId[5] &= ~0x00ff0000;
1016 au32CpuIdSaved[5] &= ~0x00ff0000;
1017
1018 /* do the compare */
1019 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1020 {
1021 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1022 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1023 "Saved=%.*Rhxs\n"
1024 "Real =%.*Rhxs\n",
1025 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1026 sizeof(au32CpuId), au32CpuId));
1027 else
1028 {
1029 LogRel(("cpumR3Load: CpuId mismatch!\n"
1030 "Saved=%.*Rhxs\n"
1031 "Real =%.*Rhxs\n",
1032 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1033 sizeof(au32CpuId), au32CpuId));
1034 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1035 }
1036 }
1037 }
1038
1039 return rc;
1040}
1041
1042
1043/**
1044 * Formats the EFLAGS value into mnemonics.
1045 *
1046 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1047 * @param efl The EFLAGS value.
1048 */
1049static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1050{
1051 /*
1052 * Format the flags.
1053 */
1054 static const struct
1055 {
1056 const char *pszSet; const char *pszClear; uint32_t fFlag;
1057 } s_aFlags[] =
1058 {
1059 { "vip",NULL, X86_EFL_VIP },
1060 { "vif",NULL, X86_EFL_VIF },
1061 { "ac", NULL, X86_EFL_AC },
1062 { "vm", NULL, X86_EFL_VM },
1063 { "rf", NULL, X86_EFL_RF },
1064 { "nt", NULL, X86_EFL_NT },
1065 { "ov", "nv", X86_EFL_OF },
1066 { "dn", "up", X86_EFL_DF },
1067 { "ei", "di", X86_EFL_IF },
1068 { "tf", NULL, X86_EFL_TF },
1069 { "nt", "pl", X86_EFL_SF },
1070 { "nz", "zr", X86_EFL_ZF },
1071 { "ac", "na", X86_EFL_AF },
1072 { "po", "pe", X86_EFL_PF },
1073 { "cy", "nc", X86_EFL_CF },
1074 };
1075 char *psz = pszEFlags;
1076 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1077 {
1078 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1079 if (pszAdd)
1080 {
1081 strcpy(psz, pszAdd);
1082 psz += strlen(pszAdd);
1083 *psz++ = ' ';
1084 }
1085 }
1086 psz[-1] = '\0';
1087}
1088
1089
1090/**
1091 * Formats a full register dump.
1092 *
1093 * @param pVM VM Handle.
1094 * @param pCtx The context to format.
1095 * @param pCtxCore The context core to format.
1096 * @param pHlp Output functions.
1097 * @param enmType The dump type.
1098 * @param pszPrefix Register name prefix.
1099 */
1100static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1101{
1102 /*
1103 * Format the EFLAGS.
1104 */
1105 uint32_t efl = pCtxCore->eflags.u32;
1106 char szEFlags[80];
1107 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1108
1109 /*
1110 * Format the registers.
1111 */
1112 switch (enmType)
1113 {
1114 case CPUMDUMPTYPE_TERSE:
1115 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1116 pHlp->pfnPrintf(pHlp,
1117 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1118 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1119 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1120 "%sr14=%016RX64 %sr15=%016RX64\n"
1121 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1122 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1123 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1124 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1125 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1126 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1127 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1128 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1129 else
1130 pHlp->pfnPrintf(pHlp,
1131 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1132 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1133 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1134 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1135 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1136 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1137 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1138 break;
1139
1140 case CPUMDUMPTYPE_DEFAULT:
1141 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1142 pHlp->pfnPrintf(pHlp,
1143 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1144 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1145 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1146 "%sr14=%016RX64 %sr15=%016RX64\n"
1147 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1148 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1149 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1150 ,
1151 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1152 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1153 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1154 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1155 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1156 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1157 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1158 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1159 else
1160 pHlp->pfnPrintf(pHlp,
1161 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1162 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1163 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1164 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1165 ,
1166 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1167 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1168 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1169 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1170 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1171 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1172 break;
1173
1174 case CPUMDUMPTYPE_VERBOSE:
1175 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1176 pHlp->pfnPrintf(pHlp,
1177 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1178 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1179 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1180 "%sr14=%016RX64 %sr15=%016RX64\n"
1181 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1182 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1183 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1184 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1185 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1186 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1187 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1188 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1189 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1190 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1191 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1192 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1193 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1194 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1195 ,
1196 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1197 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1198 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1199 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1200 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1201 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1202 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1203 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1204 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1205 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1206 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1207 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1208 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1209 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1210 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1211 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1212 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1213 else
1214 pHlp->pfnPrintf(pHlp,
1215 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1216 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1217 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1218 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1219 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1220 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1221 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1222 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1223 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1224 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1225 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1226 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1227 ,
1228 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1229 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1230 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1231 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1232 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1233 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1234 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1235 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1236 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1237 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1238 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1239 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1240
1241 pHlp->pfnPrintf(pHlp,
1242 "FPU:\n"
1243 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1244 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1245 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1246 ,
1247 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1248 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1249 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1250 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1251
1252 pHlp->pfnPrintf(pHlp,
1253 "MSR:\n"
1254 "%sEFER =%016RX64\n"
1255 "%sPAT =%016RX64\n"
1256 "%sSTAR =%016RX64\n"
1257 "%sCSTAR =%016RX64\n"
1258 "%sLSTAR =%016RX64\n"
1259 "%sSFMASK =%016RX64\n"
1260 "%sKERNELGSBASE =%016RX64\n",
1261 pszPrefix, pCtx->msrEFER,
1262 pszPrefix, pCtx->msrPAT,
1263 pszPrefix, pCtx->msrSTAR,
1264 pszPrefix, pCtx->msrCSTAR,
1265 pszPrefix, pCtx->msrLSTAR,
1266 pszPrefix, pCtx->msrSFMASK,
1267 pszPrefix, pCtx->msrKERNELGSBASE);
1268 break;
1269 }
1270}
1271
1272
1273/**
1274 * Display all cpu states and any other cpum info.
1275 *
1276 * @param pVM VM Handle.
1277 * @param pHlp The info helper functions.
1278 * @param pszArgs Arguments, ignored.
1279 */
1280static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1281{
1282 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1283 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1284 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1285 cpumR3InfoHost(pVM, pHlp, pszArgs);
1286}
1287
1288
1289/**
1290 * Parses the info argument.
1291 *
1292 * The argument starts with 'verbose', 'terse' or 'default' and then
1293 * continues with the comment string.
1294 *
1295 * @param pszArgs The pointer to the argument string.
1296 * @param penmType Where to store the dump type request.
1297 * @param ppszComment Where to store the pointer to the comment string.
1298 */
1299static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1300{
1301 if (!pszArgs)
1302 {
1303 *penmType = CPUMDUMPTYPE_DEFAULT;
1304 *ppszComment = "";
1305 }
1306 else
1307 {
1308 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1309 {
1310 pszArgs += 5;
1311 *penmType = CPUMDUMPTYPE_VERBOSE;
1312 }
1313 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1314 {
1315 pszArgs += 5;
1316 *penmType = CPUMDUMPTYPE_TERSE;
1317 }
1318 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1319 {
1320 pszArgs += 7;
1321 *penmType = CPUMDUMPTYPE_DEFAULT;
1322 }
1323 else
1324 *penmType = CPUMDUMPTYPE_DEFAULT;
1325 *ppszComment = RTStrStripL(pszArgs);
1326 }
1327}
1328
1329
1330/**
1331 * Display the guest cpu state.
1332 *
1333 * @param pVM VM Handle.
1334 * @param pHlp The info helper functions.
1335 * @param pszArgs Arguments, ignored.
1336 */
1337static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1338{
1339 CPUMDUMPTYPE enmType;
1340 const char *pszComment;
1341 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1342 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1343 /* @todo SMP */
1344 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVM);
1345 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1346}
1347
1348
1349/**
1350 * Display the current guest instruction
1351 *
1352 * @param pVM VM Handle.
1353 * @param pHlp The info helper functions.
1354 * @param pszArgs Arguments, ignored.
1355 */
1356static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1357{
1358 char szInstruction[256];
1359 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1360 if (RT_SUCCESS(rc))
1361 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1362}
1363
1364
1365/**
1366 * Display the hypervisor cpu state.
1367 *
1368 * @param pVM VM Handle.
1369 * @param pHlp The info helper functions.
1370 * @param pszArgs Arguments, ignored.
1371 */
1372static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1373{
1374 CPUMDUMPTYPE enmType;
1375 const char *pszComment;
1376 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1377 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1378 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1379 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1380}
1381
1382
1383/**
1384 * Display the host cpu state.
1385 *
1386 * @param pVM VM Handle.
1387 * @param pHlp The info helper functions.
1388 * @param pszArgs Arguments, ignored.
1389 */
1390static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1391{
1392 CPUMDUMPTYPE enmType;
1393 const char *pszComment;
1394 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1395 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1396
1397 /*
1398 * Format the EFLAGS.
1399 */
1400 /* @todo SMP */
1401 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1402#if HC_ARCH_BITS == 32
1403 uint32_t efl = pCtx->eflags.u32;
1404#else
1405 uint64_t efl = pCtx->rflags;
1406#endif
1407 char szEFlags[80];
1408 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1409
1410 /*
1411 * Format the registers.
1412 */
1413#if HC_ARCH_BITS == 32
1414# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1415 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1416# endif
1417 {
1418 pHlp->pfnPrintf(pHlp,
1419 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1420 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1421 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1422 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1423 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1424 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1425 ,
1426 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1427 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1428 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1429 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1430 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1431 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1432 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1433 }
1434# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1435 else
1436# endif
1437#endif
1438#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1439 {
1440 pHlp->pfnPrintf(pHlp,
1441 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1442 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1443 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1444 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1445 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1446 "r14=%016RX64 r15=%016RX64\n"
1447 "iopl=%d %31s\n"
1448 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1449 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1450 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1451 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1452 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1453 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1454 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1455 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1456 ,
1457 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1458 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1459 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1460 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1461 pCtx->r11, pCtx->r12, pCtx->r13,
1462 pCtx->r14, pCtx->r15,
1463 X86_EFL_GET_IOPL(efl), szEFlags,
1464 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1465 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1466 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1467 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1468 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1469 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1470 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1471 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1472 }
1473#endif
1474}
1475
1476
1477/**
1478 * Get L1 cache / TLS associativity.
1479 */
1480static const char *getCacheAss(unsigned u, char *pszBuf)
1481{
1482 if (u == 0)
1483 return "res0 ";
1484 if (u == 1)
1485 return "direct";
1486 if (u >= 256)
1487 return "???";
1488
1489 RTStrPrintf(pszBuf, 16, "%d way", u);
1490 return pszBuf;
1491}
1492
1493
1494/**
1495 * Get L2 cache soociativity.
1496 */
1497const char *getL2CacheAss(unsigned u)
1498{
1499 switch (u)
1500 {
1501 case 0: return "off ";
1502 case 1: return "direct";
1503 case 2: return "2 way ";
1504 case 3: return "res3 ";
1505 case 4: return "4 way ";
1506 case 5: return "res5 ";
1507 case 6: return "8 way "; case 7: return "res7 ";
1508 case 8: return "16 way";
1509 case 9: return "res9 ";
1510 case 10: return "res10 ";
1511 case 11: return "res11 ";
1512 case 12: return "res12 ";
1513 case 13: return "res13 ";
1514 case 14: return "res14 ";
1515 case 15: return "fully ";
1516 default:
1517 return "????";
1518 }
1519}
1520
1521
1522/**
1523 * Display the guest CpuId leaves.
1524 *
1525 * @param pVM VM Handle.
1526 * @param pHlp The info helper functions.
1527 * @param pszArgs "terse", "default" or "verbose".
1528 */
1529static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1530{
1531 /*
1532 * Parse the argument.
1533 */
1534 unsigned iVerbosity = 1;
1535 if (pszArgs)
1536 {
1537 pszArgs = RTStrStripL(pszArgs);
1538 if (!strcmp(pszArgs, "terse"))
1539 iVerbosity--;
1540 else if (!strcmp(pszArgs, "verbose"))
1541 iVerbosity++;
1542 }
1543
1544 /*
1545 * Start cracking.
1546 */
1547 CPUMCPUID Host;
1548 CPUMCPUID Guest;
1549 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1550
1551 pHlp->pfnPrintf(pHlp,
1552 " RAW Standard CPUIDs\n"
1553 " Function eax ebx ecx edx\n");
1554 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1555 {
1556 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1557 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1558
1559 pHlp->pfnPrintf(pHlp,
1560 "Gst: %08x %08x %08x %08x %08x%s\n"
1561 "Hst: %08x %08x %08x %08x\n",
1562 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1563 i <= cStdMax ? "" : "*",
1564 Host.eax, Host.ebx, Host.ecx, Host.edx);
1565 }
1566
1567 /*
1568 * If verbose, decode it.
1569 */
1570 if (iVerbosity)
1571 {
1572 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1573 pHlp->pfnPrintf(pHlp,
1574 "Name: %.04s%.04s%.04s\n"
1575 "Supports: 0-%x\n",
1576 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1577 }
1578
1579 /*
1580 * Get Features.
1581 */
1582 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1583 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1584 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1585 if (cStdMax >= 1 && iVerbosity)
1586 {
1587 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1588 uint32_t uEAX = Guest.eax;
1589
1590 pHlp->pfnPrintf(pHlp,
1591 "Family: %d \tExtended: %d \tEffective: %d\n"
1592 "Model: %d \tExtended: %d \tEffective: %d\n"
1593 "Stepping: %d\n"
1594 "APIC ID: %#04x\n"
1595 "Logical CPUs: %d\n"
1596 "CLFLUSH Size: %d\n"
1597 "Brand ID: %#04x\n",
1598 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1599 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1600 ASMGetCpuStepping(uEAX),
1601 (Guest.ebx >> 24) & 0xff,
1602 (Guest.ebx >> 16) & 0xff,
1603 (Guest.ebx >> 8) & 0xff,
1604 (Guest.ebx >> 0) & 0xff);
1605 if (iVerbosity == 1)
1606 {
1607 uint32_t uEDX = Guest.edx;
1608 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1609 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1610 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1611 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1612 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1613 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1614 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1615 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1616 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1617 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1618 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1619 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1620 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1621 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1622 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1623 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1624 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1625 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1626 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1627 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1628 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1629 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1630 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1631 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1632 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1633 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1634 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1635 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1636 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1637 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1638 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1639 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1640 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1641 pHlp->pfnPrintf(pHlp, "\n");
1642
1643 uint32_t uECX = Guest.ecx;
1644 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1645 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1646 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1647 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1648 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1649 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1650 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1651 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1652 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1653 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1654 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1655 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1656 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1657 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1658 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1659 for (unsigned iBit = 14; iBit < 32; iBit++)
1660 if (uECX & RT_BIT(iBit))
1661 pHlp->pfnPrintf(pHlp, " %d", iBit);
1662 pHlp->pfnPrintf(pHlp, "\n");
1663 }
1664 else
1665 {
1666 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1667
1668 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1669 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1670 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1671 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1672
1673 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1674 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1675 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1676 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1677 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1678 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1679 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1680 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1681 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1682 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1683 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1684 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1685 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1686 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1687 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1688 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1689 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1690 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1691 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1692 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1693 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1694 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1695 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1696 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1697 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1698 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1699 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1700 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1701 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1702 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1703 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1704 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1705 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1706
1707 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1708 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1709 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1710 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1711 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1712 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1713 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1714 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1715 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1716 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1717 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1718 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1719 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1720 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1721 }
1722 }
1723 if (cStdMax >= 2 && iVerbosity)
1724 {
1725 /** @todo */
1726 }
1727
1728 /*
1729 * Extended.
1730 * Implemented after AMD specs.
1731 */
1732 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1733
1734 pHlp->pfnPrintf(pHlp,
1735 "\n"
1736 " RAW Extended CPUIDs\n"
1737 " Function eax ebx ecx edx\n");
1738 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1739 {
1740 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1741 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1742
1743 pHlp->pfnPrintf(pHlp,
1744 "Gst: %08x %08x %08x %08x %08x%s\n"
1745 "Hst: %08x %08x %08x %08x\n",
1746 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1747 i <= cExtMax ? "" : "*",
1748 Host.eax, Host.ebx, Host.ecx, Host.edx);
1749 }
1750
1751 /*
1752 * Understandable output
1753 */
1754 if (iVerbosity)
1755 {
1756 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1757 pHlp->pfnPrintf(pHlp,
1758 "Ext Name: %.4s%.4s%.4s\n"
1759 "Ext Supports: 0x80000000-%#010x\n",
1760 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1761 }
1762
1763 if (iVerbosity && cExtMax >= 1)
1764 {
1765 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1766 uint32_t uEAX = Guest.eax;
1767 pHlp->pfnPrintf(pHlp,
1768 "Family: %d \tExtended: %d \tEffective: %d\n"
1769 "Model: %d \tExtended: %d \tEffective: %d\n"
1770 "Stepping: %d\n"
1771 "Brand ID: %#05x\n",
1772 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1773 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1774 ASMGetCpuStepping(uEAX),
1775 Guest.ebx & 0xfff);
1776
1777 if (iVerbosity == 1)
1778 {
1779 uint32_t uEDX = Guest.edx;
1780 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1781 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1782 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1783 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1784 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1785 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1786 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1787 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1788 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1789 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1790 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1791 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1792 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1793 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1794 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1795 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1796 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1797 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1798 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1799 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1800 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1801 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1802 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1803 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1804 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1805 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1806 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1807 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1808 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1809 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1810 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1811 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1812 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1813 pHlp->pfnPrintf(pHlp, "\n");
1814
1815 uint32_t uECX = Guest.ecx;
1816 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1817 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1818 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1819 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1820 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1821 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1822 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1823 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1824 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1825 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1826 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1827 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1828 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1829 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1830 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1831 for (unsigned iBit = 5; iBit < 32; iBit++)
1832 if (uECX & RT_BIT(iBit))
1833 pHlp->pfnPrintf(pHlp, " %d", iBit);
1834 pHlp->pfnPrintf(pHlp, "\n");
1835 }
1836 else
1837 {
1838 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1839
1840 uint32_t uEdxGst = Guest.edx;
1841 uint32_t uEdxHst = Host.edx;
1842 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1843 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1844 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1845 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1846 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1847 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1848 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1849 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1850 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1851 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1852 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1853 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1854 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1855 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1856 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1857 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1858 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1859 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1860 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1861 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1862 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1863 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1864 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1865 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1866 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1867 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1868 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1869 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1870 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1871 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1872 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1873 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1874 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1875
1876 uint32_t uEcxGst = Guest.ecx;
1877 uint32_t uEcxHst = Host.ecx;
1878 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1879 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1880 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1881 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1882 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1883 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1884 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1885 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1886 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1887 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1888 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1889 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1890 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1891 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1892 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1893 }
1894 }
1895
1896 if (iVerbosity && cExtMax >= 2)
1897 {
1898 char szString[4*4*3+1] = {0};
1899 uint32_t *pu32 = (uint32_t *)szString;
1900 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1901 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1902 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1903 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1904 if (cExtMax >= 3)
1905 {
1906 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1907 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1908 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1909 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1910 }
1911 if (cExtMax >= 4)
1912 {
1913 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1914 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1915 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1916 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1917 }
1918 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1919 }
1920
1921 if (iVerbosity && cExtMax >= 5)
1922 {
1923 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1924 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1925 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1926 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1927 char sz1[32];
1928 char sz2[32];
1929
1930 pHlp->pfnPrintf(pHlp,
1931 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1932 "TLB 2/4M Data: %s %3d entries\n",
1933 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1934 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1935 pHlp->pfnPrintf(pHlp,
1936 "TLB 4K Instr/Uni: %s %3d entries\n"
1937 "TLB 4K Data: %s %3d entries\n",
1938 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1939 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1940 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1941 "L1 Instr Cache Lines Per Tag: %d\n"
1942 "L1 Instr Cache Associativity: %s\n"
1943 "L1 Instr Cache Size: %d KB\n",
1944 (uEDX >> 0) & 0xff,
1945 (uEDX >> 8) & 0xff,
1946 getCacheAss((uEDX >> 16) & 0xff, sz1),
1947 (uEDX >> 24) & 0xff);
1948 pHlp->pfnPrintf(pHlp,
1949 "L1 Data Cache Line Size: %d bytes\n"
1950 "L1 Data Cache Lines Per Tag: %d\n"
1951 "L1 Data Cache Associativity: %s\n"
1952 "L1 Data Cache Size: %d KB\n",
1953 (uECX >> 0) & 0xff,
1954 (uECX >> 8) & 0xff,
1955 getCacheAss((uECX >> 16) & 0xff, sz1),
1956 (uECX >> 24) & 0xff);
1957 }
1958
1959 if (iVerbosity && cExtMax >= 6)
1960 {
1961 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1962 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1963 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1964
1965 pHlp->pfnPrintf(pHlp,
1966 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1967 "L2 TLB 2/4M Data: %s %4d entries\n",
1968 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1969 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1970 pHlp->pfnPrintf(pHlp,
1971 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1972 "L2 TLB 4K Data: %s %4d entries\n",
1973 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1974 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1975 pHlp->pfnPrintf(pHlp,
1976 "L2 Cache Line Size: %d bytes\n"
1977 "L2 Cache Lines Per Tag: %d\n"
1978 "L2 Cache Associativity: %s\n"
1979 "L2 Cache Size: %d KB\n",
1980 (uEDX >> 0) & 0xff,
1981 (uEDX >> 8) & 0xf,
1982 getL2CacheAss((uEDX >> 12) & 0xf),
1983 (uEDX >> 16) & 0xffff);
1984 }
1985
1986 if (iVerbosity && cExtMax >= 7)
1987 {
1988 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1989
1990 pHlp->pfnPrintf(pHlp, "APM Features: ");
1991 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1992 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1993 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1994 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1995 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1996 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1997 for (unsigned iBit = 6; iBit < 32; iBit++)
1998 if (uEDX & RT_BIT(iBit))
1999 pHlp->pfnPrintf(pHlp, " %d", iBit);
2000 pHlp->pfnPrintf(pHlp, "\n");
2001 }
2002
2003 if (iVerbosity && cExtMax >= 8)
2004 {
2005 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2006 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2007
2008 pHlp->pfnPrintf(pHlp,
2009 "Physical Address Width: %d bits\n"
2010 "Virtual Address Width: %d bits\n",
2011 (uEAX >> 0) & 0xff,
2012 (uEAX >> 8) & 0xff);
2013 pHlp->pfnPrintf(pHlp,
2014 "Physical Core Count: %d\n",
2015 (uECX >> 0) & 0xff);
2016 }
2017
2018
2019 /*
2020 * Centaur.
2021 */
2022 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2023
2024 pHlp->pfnPrintf(pHlp,
2025 "\n"
2026 " RAW Centaur CPUIDs\n"
2027 " Function eax ebx ecx edx\n");
2028 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2029 {
2030 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2031 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2032
2033 pHlp->pfnPrintf(pHlp,
2034 "Gst: %08x %08x %08x %08x %08x%s\n"
2035 "Hst: %08x %08x %08x %08x\n",
2036 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2037 i <= cCentaurMax ? "" : "*",
2038 Host.eax, Host.ebx, Host.ecx, Host.edx);
2039 }
2040
2041 /*
2042 * Understandable output
2043 */
2044 if (iVerbosity)
2045 {
2046 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2047 pHlp->pfnPrintf(pHlp,
2048 "Centaur Supports: 0xc0000000-%#010x\n",
2049 Guest.eax);
2050 }
2051
2052 if (iVerbosity && cCentaurMax >= 1)
2053 {
2054 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2055 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2056 uint32_t uEdxHst = Host.edx;
2057
2058 if (iVerbosity == 1)
2059 {
2060 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2061 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2062 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2063 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2064 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2065 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2066 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2067 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2068 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2069 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2070 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2071 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2072 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2073 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2074 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2075 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2076 for (unsigned iBit = 14; iBit < 32; iBit++)
2077 if (uEdxGst & RT_BIT(iBit))
2078 pHlp->pfnPrintf(pHlp, " %d", iBit);
2079 pHlp->pfnPrintf(pHlp, "\n");
2080 }
2081 else
2082 {
2083 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2084 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2085 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2086 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2087 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2088 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2089 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2090 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2091 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2092 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2093 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2094 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2095 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2096 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2097 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2098 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2099 for (unsigned iBit = 14; iBit < 32; iBit++)
2100 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2101 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2102 pHlp->pfnPrintf(pHlp, "\n");
2103 }
2104 }
2105}
2106
2107
2108/**
2109 * Structure used when disassembling and instructions in DBGF.
2110 * This is used so the reader function can get the stuff it needs.
2111 */
2112typedef struct CPUMDISASSTATE
2113{
2114 /** Pointer to the CPU structure. */
2115 PDISCPUSTATE pCpu;
2116 /** The VM handle. */
2117 PVM pVM;
2118 /** Pointer to the first byte in the segemnt. */
2119 RTGCUINTPTR GCPtrSegBase;
2120 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2121 RTGCUINTPTR GCPtrSegEnd;
2122 /** The size of the segment minus 1. */
2123 RTGCUINTPTR cbSegLimit;
2124 /** Pointer to the current page - R3 Ptr. */
2125 void const *pvPageR3;
2126 /** Pointer to the current page - GC Ptr. */
2127 RTGCPTR pvPageGC;
2128 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2129 PGMPAGEMAPLOCK PageMapLock;
2130 /** Whether the PageMapLock is valid or not. */
2131 bool fLocked;
2132 /** 64 bits mode or not. */
2133 bool f64Bits;
2134} CPUMDISASSTATE, *PCPUMDISASSTATE;
2135
2136
2137/**
2138 * Instruction reader.
2139 *
2140 * @returns VBox status code.
2141 * @param PtrSrc Address to read from.
2142 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2143 * @param pu8Dst Where to store the bytes.
2144 * @param cbRead Number of bytes to read.
2145 * @param uDisCpu Pointer to the disassembler cpu state.
2146 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2147 */
2148static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2149{
2150 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2151 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2152 Assert(cbRead > 0);
2153 for (;;)
2154 {
2155 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2156
2157 /* Need to update the page translation? */
2158 if ( !pState->pvPageR3
2159 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2160 {
2161 int rc = VINF_SUCCESS;
2162
2163 /* translate the address */
2164 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2165 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2166 && !HWACCMIsEnabled(pState->pVM))
2167 {
2168 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2169 if (!pState->pvPageR3)
2170 rc = VERR_INVALID_POINTER;
2171 }
2172 else
2173 {
2174 /* Release mapping lock previously acquired. */
2175 if (pState->fLocked)
2176 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2177 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2178 pState->fLocked = RT_SUCCESS_NP(rc);
2179 }
2180 if (RT_FAILURE(rc))
2181 {
2182 pState->pvPageR3 = NULL;
2183 return rc;
2184 }
2185 }
2186
2187 /* check the segemnt limit */
2188 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2189 return VERR_OUT_OF_SELECTOR_BOUNDS;
2190
2191 /* calc how much we can read */
2192 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2193 if (!pState->f64Bits)
2194 {
2195 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2196 if (cb > cbSeg && cbSeg)
2197 cb = cbSeg;
2198 }
2199 if (cb > cbRead)
2200 cb = cbRead;
2201
2202 /* read and advance */
2203 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2204 cbRead -= cb;
2205 if (!cbRead)
2206 return VINF_SUCCESS;
2207 pu8Dst += cb;
2208 PtrSrc += cb;
2209 }
2210}
2211
2212
2213/**
2214 * Disassemble an instruction and return the information in the provided structure.
2215 *
2216 * @returns VBox status code.
2217 * @param pVM VM Handle
2218 * @param pCtx CPU context
2219 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2220 * @param pCpu Disassembly state
2221 * @param pszPrefix String prefix for logging (debug only)
2222 *
2223 */
2224VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2225{
2226 CPUMDISASSTATE State;
2227 int rc;
2228
2229 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2230 State.pCpu = pCpu;
2231 State.pvPageGC = 0;
2232 State.pvPageR3 = NULL;
2233 State.pVM = pVM;
2234 State.fLocked = false;
2235 State.f64Bits = false;
2236
2237 /*
2238 * Get selector information.
2239 */
2240 if ( (pCtx->cr0 & X86_CR0_PE)
2241 && pCtx->eflags.Bits.u1VM == 0)
2242 {
2243 if (CPUMAreHiddenSelRegsValid(pVM))
2244 {
2245 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2246 State.GCPtrSegBase = pCtx->csHid.u64Base;
2247 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2248 State.cbSegLimit = pCtx->csHid.u32Limit;
2249 pCpu->mode = (State.f64Bits)
2250 ? CPUMODE_64BIT
2251 : pCtx->csHid.Attr.n.u1DefBig
2252 ? CPUMODE_32BIT
2253 : CPUMODE_16BIT;
2254 }
2255 else
2256 {
2257 SELMSELINFO SelInfo;
2258
2259 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2260 if (!RT_SUCCESS(rc))
2261 {
2262 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2263 return rc;
2264 }
2265
2266 /*
2267 * Validate the selector.
2268 */
2269 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2270 if (!RT_SUCCESS(rc))
2271 {
2272 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2273 return rc;
2274 }
2275 State.GCPtrSegBase = SelInfo.GCPtrBase;
2276 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2277 State.cbSegLimit = SelInfo.cbLimit;
2278 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2279 }
2280 }
2281 else
2282 {
2283 /* real or V86 mode */
2284 pCpu->mode = CPUMODE_16BIT;
2285 State.GCPtrSegBase = pCtx->cs * 16;
2286 State.GCPtrSegEnd = 0xFFFFFFFF;
2287 State.cbSegLimit = 0xFFFFFFFF;
2288 }
2289
2290 /*
2291 * Disassemble the instruction.
2292 */
2293 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2294 pCpu->apvUserData[0] = &State;
2295
2296 uint32_t cbInstr;
2297#ifndef LOG_ENABLED
2298 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2299 if (RT_SUCCESS(rc))
2300 {
2301#else
2302 char szOutput[160];
2303 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2304 if (RT_SUCCESS(rc))
2305 {
2306 /* log it */
2307 if (pszPrefix)
2308 Log(("%s: %s", pszPrefix, szOutput));
2309 else
2310 Log(("%s", szOutput));
2311#endif
2312 rc = VINF_SUCCESS;
2313 }
2314 else
2315 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2316
2317 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2318 if (State.fLocked)
2319 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2320
2321 return rc;
2322}
2323
2324#ifdef DEBUG
2325
2326/**
2327 * Disassemble an instruction and dump it to the log
2328 *
2329 * @returns VBox status code.
2330 * @param pVM VM Handle
2331 * @param pCtx CPU context
2332 * @param pc GC instruction pointer
2333 * @param pszPrefix String prefix for logging
2334 *
2335 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2336 */
2337VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2338{
2339 DISCPUSTATE Cpu;
2340 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &Cpu, pszPrefix);
2341}
2342
2343
2344/**
2345 * Disassemble an instruction and dump it to the log
2346 *
2347 * @returns VBox status code.
2348 * @param pVM VM Handle
2349 * @param pCtx CPU context
2350 * @param pc GC instruction pointer
2351 * @param pszPrefix String prefix for logging
2352 * @param nrInstructions
2353 *
2354 * @deprecated Create new DBGFR3Disas function to do this.
2355 */
2356VMMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix, int nrInstructions)
2357{
2358 for (int i = 0; i < nrInstructions; i++)
2359 {
2360 DISCPUSTATE cpu;
2361
2362 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, pszPrefix);
2363 pc += cpu.opsize;
2364 }
2365}
2366
2367
2368/**
2369 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2370 *
2371 * @internal
2372 */
2373VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2374{
2375 /* @todo SMP */
2376 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(pVM);
2377}
2378
2379#endif /* DEBUG */
2380
2381/**
2382 * API for controlling a few of the CPU features found in CR4.
2383 *
2384 * Currently only X86_CR4_TSD is accepted as input.
2385 *
2386 * @returns VBox status code.
2387 *
2388 * @param pVM The VM handle.
2389 * @param fOr The CR4 OR mask.
2390 * @param fAnd The CR4 AND mask.
2391 */
2392VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2393{
2394 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2395 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2396
2397 pVM->cpum.s.CR4.OrMask &= fAnd;
2398 pVM->cpum.s.CR4.OrMask |= fOr;
2399
2400 return VINF_SUCCESS;
2401}
2402
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