VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 18927

Last change on this file since 18927 was 18927, checked in by vboxsync, 16 years ago

Big step to separate VMM data structures for guest SMP. (pgm, em)
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File size: 110.6 KB
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1/* $Id: CPUM.cpp 18927 2009-04-16 11:41:38Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 10
71/** The saved state version for the 2.1 trunk before the MSR changes. */
72#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
73/** The saved state version of 2.0, used for backwards compatibility. */
74#define CPUM_SAVED_STATE_VERSION_VER2_0 8
75/** The saved state version of 1.6, used for backwards compatability. */
76#define CPUM_SAVED_STATE_VERSION_VER1_6 6
77
78
79/*******************************************************************************
80* Structures and Typedefs *
81*******************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91
92} CPUMDUMPTYPE;
93/** Pointer to a cpu info dump type. */
94typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97/*******************************************************************************
98* Internal Functions *
99*******************************************************************************/
100static int cpumR3CpuIdInit(PVM pVM);
101static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/**
112 * Initializes the CPUM.
113 *
114 * @returns VBox status code.
115 * @param pVM The VM to operate on.
116 */
117VMMR3DECL(int) CPUMR3Init(PVM pVM)
118{
119 LogFlow(("CPUMR3Init\n"));
120
121 /*
122 * Assert alignment and sizes.
123 */
124 AssertCompile(!(RT_OFFSETOF(VM, cpum.s) & 31));
125 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
126 AssertCompile(!(sizeof(CPUMCTX) & 63));
127 AssertCompile(!(sizeof(CPUMCTXMSR) & 63));
128 AssertCompile(!(sizeof(CPUMHOSTCTX) & 63));
129 AssertCompile(!(RT_OFFSETOF(VM, cpum) & 63));
130 AssertCompile(!(RT_OFFSETOF(VM, aCpus) & 63));
131 AssertCompile(!(RT_OFFSETOF(VMCPU, cpum.s) & 63));
132 AssertCompile(!(sizeof(pVM->aCpus[0].cpum.s) & 63));
133
134 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
135 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
136 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
137
138 /* Calculate the offset from CPUMCPU to CPUM. */
139 for (unsigned i=0;i<pVM->cCPUs;i++)
140 {
141 PVMCPU pVCpu = &pVM->aCpus[i];
142
143 /*
144 * Setup any fixed pointers and offsets.
145 */
146 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
147 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
148
149 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
150 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
151 }
152
153 /*
154 * Check that the CPU supports the minimum features we require.
155 */
156 if (!ASMHasCpuId())
157 {
158 Log(("The CPU doesn't support CPUID!\n"));
159 return VERR_UNSUPPORTED_CPU;
160 }
161 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
162 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
163
164 /* Setup the CR4 AND and OR masks used in the switcher */
165 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
166 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
167 {
168 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
169 /* No FXSAVE implies no SSE */
170 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
171 pVM->cpum.s.CR4.OrMask = 0;
172 }
173 else
174 {
175 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
176 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
177 }
178
179 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
180 {
181 Log(("The CPU doesn't support MMX!\n"));
182 return VERR_UNSUPPORTED_CPU;
183 }
184 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
185 {
186 Log(("The CPU doesn't support TSC!\n"));
187 return VERR_UNSUPPORTED_CPU;
188 }
189 /* Bogus on AMD? */
190 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
191 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
192
193 /*
194 * Setup hypervisor startup values.
195 */
196
197 /*
198 * Register saved state data item.
199 */
200 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
201 NULL, cpumR3Save, NULL,
202 NULL, cpumR3Load, NULL);
203 if (RT_FAILURE(rc))
204 return rc;
205
206 /* Query the CPU manufacturer. */
207 uint32_t uEAX, uEBX, uECX, uEDX;
208 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
209 if ( uEAX >= 1
210 && uEBX == X86_CPUID_VENDOR_AMD_EBX
211 && uECX == X86_CPUID_VENDOR_AMD_ECX
212 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
213 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
214 else if ( uEAX >= 1
215 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
216 && uECX == X86_CPUID_VENDOR_INTEL_ECX
217 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
218 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
219 else /** @todo Via */
220 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
221
222 /*
223 * Register info handlers.
224 */
225 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
226 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
227 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
228 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
229 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
230 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
231
232 /*
233 * Initialize the Guest CPU state.
234 */
235 rc = cpumR3CpuIdInit(pVM);
236 if (RT_FAILURE(rc))
237 return rc;
238 CPUMR3Reset(pVM);
239 return VINF_SUCCESS;
240}
241
242
243/**
244 * Initializes the per-VCPU CPUM.
245 *
246 * @returns VBox status code.
247 * @param pVM The VM to operate on.
248 */
249VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
250{
251 LogFlow(("CPUMR3InitCPU\n"));
252 return VINF_SUCCESS;
253}
254
255
256/**
257 * Initializes the emulated CPU's cpuid information.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262static int cpumR3CpuIdInit(PVM pVM)
263{
264 PCPUM pCPUM = &pVM->cpum.s;
265 uint32_t i;
266
267 /*
268 * Get the host CPUIDs.
269 */
270 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
271 ASMCpuId_Idx_ECX(i, 0,
272 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
273 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
274 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
275 ASMCpuId(0x80000000 + i,
276 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
277 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
278 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
279 ASMCpuId(0xc0000000 + i,
280 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
281 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
282
283
284 /*
285 * Only report features we can support.
286 */
287 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
288 | X86_CPUID_FEATURE_EDX_VME
289 | X86_CPUID_FEATURE_EDX_DE
290 | X86_CPUID_FEATURE_EDX_PSE
291 | X86_CPUID_FEATURE_EDX_TSC
292 | X86_CPUID_FEATURE_EDX_MSR
293 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
294 | X86_CPUID_FEATURE_EDX_MCE
295 | X86_CPUID_FEATURE_EDX_CX8
296 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
297 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
298 //| X86_CPUID_FEATURE_EDX_SEP
299 | X86_CPUID_FEATURE_EDX_MTRR
300 | X86_CPUID_FEATURE_EDX_PGE
301 | X86_CPUID_FEATURE_EDX_MCA
302 | X86_CPUID_FEATURE_EDX_CMOV
303 | X86_CPUID_FEATURE_EDX_PAT
304 | X86_CPUID_FEATURE_EDX_PSE36
305 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
306 | X86_CPUID_FEATURE_EDX_CLFSH
307 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
308 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
309 | X86_CPUID_FEATURE_EDX_MMX
310 | X86_CPUID_FEATURE_EDX_FXSR
311 | X86_CPUID_FEATURE_EDX_SSE
312 | X86_CPUID_FEATURE_EDX_SSE2
313 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
314 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
315 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
316 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
317 | 0;
318 pCPUM->aGuestCpuIdStd[1].ecx &= 0
319#ifdef VBOX_WITH_NEW_RECOMPILER
320 | X86_CPUID_FEATURE_ECX_SSE3
321#endif
322 | X86_CPUID_FEATURE_ECX_MONITOR
323 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
324 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
325 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
326 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
327 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
328 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
329 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
330 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
331 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
332 /* ECX Bit 21 - x2APIC support - not yet. */
333 // | X86_CPUID_FEATURE_ECX_X2APIC
334 /* ECX Bit 23 - POPCOUNT instruction. */
335 //| X86_CPUID_FEATURE_ECX_POPCOUNT
336 | 0;
337
338 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
339 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
340 | X86_CPUID_AMD_FEATURE_EDX_VME
341 | X86_CPUID_AMD_FEATURE_EDX_DE
342 | X86_CPUID_AMD_FEATURE_EDX_PSE
343 | X86_CPUID_AMD_FEATURE_EDX_TSC
344 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
345 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
346 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
347 | X86_CPUID_AMD_FEATURE_EDX_CX8
348 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
349 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
350 //| X86_CPUID_AMD_FEATURE_EDX_SEP
351 | X86_CPUID_AMD_FEATURE_EDX_MTRR
352 | X86_CPUID_AMD_FEATURE_EDX_PGE
353 | X86_CPUID_AMD_FEATURE_EDX_MCA
354 | X86_CPUID_AMD_FEATURE_EDX_CMOV
355 | X86_CPUID_AMD_FEATURE_EDX_PAT
356 | X86_CPUID_AMD_FEATURE_EDX_PSE36
357 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
358 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
359 | X86_CPUID_AMD_FEATURE_EDX_MMX
360 | X86_CPUID_AMD_FEATURE_EDX_FXSR
361 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
362 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
363 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
364 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
365 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
366 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
367 | 0;
368 pCPUM->aGuestCpuIdExt[1].ecx &= 0
369 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
370 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
371 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
372 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
373 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
374 //| X86_CPUID_AMD_FEATURE_ECX_ABM
375 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
376 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
377 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
378 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
379 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
380 //| X86_CPUID_AMD_FEATURE_ECX_WDT
381 | 0;
382
383 /*
384 * Hide HTT, multicode, SMP, whatever.
385 * (APIC-ID := 0 and #LogCpus := 0)
386 */
387 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
388
389 /* Cpuid 2:
390 * Intel: Cache and TLB information
391 * AMD: Reserved
392 * Safe to expose
393 */
394
395 /* Cpuid 3:
396 * Intel: EAX, EBX - reserved
397 * ECX, EDX - Processor Serial Number if available, otherwise reserved
398 * AMD: Reserved
399 * Safe to expose
400 */
401 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
402 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
403
404 /* Cpuid 4:
405 * Intel: Deterministic Cache Parameters Leaf
406 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
407 * AMD: Reserved
408 * Safe to expose, except for EAX:
409 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
410 * Bits 31-26: Maximum number of processor cores in this physical package**
411 */
412 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
413 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
414
415 /* Cpuid 5: Monitor/mwait Leaf
416 * Intel: ECX, EDX - reserved
417 * EAX, EBX - Smallest and largest monitor line size
418 * AMD: EDX - reserved
419 * EAX, EBX - Smallest and largest monitor line size
420 * ECX - extensions (ignored for now)
421 * Safe to expose
422 */
423 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
424 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
425
426 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
427
428 /*
429 * Determine the default.
430 *
431 * Intel returns values of the highest standard function, while AMD
432 * returns zeros. VIA on the other hand seems to returning nothing or
433 * perhaps some random garbage, we don't try to duplicate this behavior.
434 */
435 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
436 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
437 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
438
439 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
440 * Safe to pass on to the guest.
441 *
442 * Intel: 0x800000005 reserved
443 * 0x800000006 L2 cache information
444 * AMD: 0x800000005 L1 cache information
445 * 0x800000006 L2/L3 cache information
446 */
447
448 /* Cpuid 0x800000007:
449 * AMD: EAX, EBX, ECX - reserved
450 * EDX: Advanced Power Management Information
451 * Intel: Reserved
452 */
453 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
454 {
455 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
456
457 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
458
459 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
460 {
461 /* Only expose the TSC invariant capability bit to the guest. */
462 pCPUM->aGuestCpuIdExt[7].edx &= 0
463 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
464 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
465 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
466 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
467 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
468 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
469 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
470 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
471 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
472 | 0;
473 }
474 else
475 pCPUM->aGuestCpuIdExt[7].edx = 0;
476 }
477
478 /* Cpuid 0x800000008:
479 * AMD: EBX, EDX - reserved
480 * EAX: Virtual/Physical address Size
481 * ECX: Number of cores + APICIdCoreIdSize
482 * Intel: EAX: Virtual/Physical address Size
483 * EBX, ECX, EDX - reserved
484 */
485 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
486 {
487 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
488 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
489 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
490 * NC (0-7) Number of cores; 0 equals 1 core */
491 pCPUM->aGuestCpuIdExt[8].ecx = 0;
492 }
493
494 /*
495 * Limit it the number of entries and fill the remaining with the defaults.
496 *
497 * The limits are masking off stuff about power saving and similar, this
498 * is perhaps a bit crudely done as there is probably some relatively harmless
499 * info too in these leaves (like words about having a constant TSC).
500 */
501#if 0
502 /** @todo NT4 installation regression - investigate */
503 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
504 pCPUM->aGuestCpuIdStd[0].eax = 5;
505#else
506 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
507 pCPUM->aGuestCpuIdStd[0].eax = 2;
508#endif
509 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
510 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
511
512 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
513 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
514 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
515 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
516 : 0;
517 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
518 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
519
520 /*
521 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
522 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
523 * We currently don't support more than 1 processor.
524 */
525 pCPUM->aGuestCpuIdStd[4].eax = 0;
526
527 /*
528 * Centaur stuff (VIA).
529 *
530 * The important part here (we think) is to make sure the 0xc0000000
531 * function returns 0xc0000001. As for the features, we don't currently
532 * let on about any of those... 0xc0000002 seems to be some
533 * temperature/hz/++ stuff, include it as well (static).
534 */
535 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
536 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
537 {
538 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
539 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
540 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
541 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
542 i++)
543 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
544 }
545 else
546 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
547 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
548
549
550 /*
551 * Load CPUID overrides from configuration.
552 */
553 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
554 * Overloads the CPUID leaf values. */
555 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
556 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
557 for (i=0;; )
558 {
559 while (cElements-- > 0)
560 {
561 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
562 if (pNode)
563 {
564 uint32_t u32;
565 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
566 if (RT_SUCCESS(rc))
567 pCpuId->eax = u32;
568 else
569 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
570
571 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
572 if (RT_SUCCESS(rc))
573 pCpuId->ebx = u32;
574 else
575 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
576
577 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
578 if (RT_SUCCESS(rc))
579 pCpuId->ecx = u32;
580 else
581 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
582
583 rc = CFGMR3QueryU32(pNode, "edx", &u32);
584 if (RT_SUCCESS(rc))
585 pCpuId->edx = u32;
586 else
587 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
588 }
589 pCpuId++;
590 i++;
591 }
592
593 /* next */
594 if ((i & UINT32_C(0xc0000000)) == 0)
595 {
596 pCpuId = &pCPUM->aGuestCpuIdExt[0];
597 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
598 i = UINT32_C(0x80000000);
599 }
600 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
601 {
602 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
603 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
604 i = UINT32_C(0xc0000000);
605 }
606 else
607 break;
608 }
609
610 /* Check if PAE was explicitely enabled by the user. */
611 bool fEnable = false;
612 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
613 if (RT_SUCCESS(rc) && fEnable)
614 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
615
616 /*
617 * Log the cpuid and we're good.
618 */
619 RTCPUSET OnlineSet;
620 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
621 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
622 LogRel(("************************* CPUID dump ************************\n"));
623 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
624 LogRel(("\n"));
625 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
626 LogRel(("******************** End of CPUID dump **********************\n"));
627 return VINF_SUCCESS;
628}
629
630
631
632
633/**
634 * Applies relocations to data and code managed by this
635 * component. This function will be called at init and
636 * whenever the VMM need to relocate it self inside the GC.
637 *
638 * The CPUM will update the addresses used by the switcher.
639 *
640 * @param pVM The VM.
641 */
642VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
643{
644 LogFlow(("CPUMR3Relocate\n"));
645 for (unsigned i=0;i<pVM->cCPUs;i++)
646 {
647 PVMCPU pVCpu = &pVM->aCpus[i];
648 /*
649 * Switcher pointers.
650 */
651 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
652 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
653 }
654}
655
656
657/**
658 * Terminates the CPUM.
659 *
660 * Termination means cleaning up and freeing all resources,
661 * the VM it self is at this point powered off or suspended.
662 *
663 * @returns VBox status code.
664 * @param pVM The VM to operate on.
665 */
666VMMR3DECL(int) CPUMR3Term(PVM pVM)
667{
668 CPUMR3TermCPU(pVM);
669 return 0;
670}
671
672
673/**
674 * Terminates the per-VCPU CPUM.
675 *
676 * Termination means cleaning up and freeing all resources,
677 * the VM it self is at this point powered off or suspended.
678 *
679 * @returns VBox status code.
680 * @param pVM The VM to operate on.
681 */
682VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
683{
684#ifdef VBOX_WITH_CRASHDUMP_MAGIC
685 for (unsigned i=0;i<pVM->cCPUs;i++)
686 {
687 PVMCPU pVCpu = &pVM->aCpus[i];
688 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
689
690 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
691 pVCpu->cpum.s.uMagic = 0;
692 pCtx->dr[5] = 0;
693 }
694#endif
695 return 0;
696}
697
698
699/**
700 * Resets the CPU.
701 *
702 * @returns VINF_SUCCESS.
703 * @param pVM The VM handle.
704 */
705VMMR3DECL(void) CPUMR3Reset(PVM pVM)
706{
707 /* @todo anything different for VCPU > 0? */
708 for (unsigned i=0;i<pVM->cCPUs;i++)
709 {
710 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
711
712 /*
713 * Initialize everything to ZERO first.
714 */
715 uint32_t fUseFlags = pVM->aCpus[i].cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
716 memset(pCtx, 0, sizeof(*pCtx));
717 pVM->aCpus[i].cpum.s.fUseFlags = fUseFlags;
718
719 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
720 pCtx->eip = 0x0000fff0;
721 pCtx->edx = 0x00000600; /* P6 processor */
722 pCtx->eflags.Bits.u1Reserved0 = 1;
723
724 pCtx->cs = 0xf000;
725 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
726 pCtx->csHid.u32Limit = 0x0000ffff;
727 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
728 pCtx->csHid.Attr.n.u1Present = 1;
729 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
730
731 pCtx->dsHid.u32Limit = 0x0000ffff;
732 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
733 pCtx->dsHid.Attr.n.u1Present = 1;
734 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
735
736 pCtx->esHid.u32Limit = 0x0000ffff;
737 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
738 pCtx->esHid.Attr.n.u1Present = 1;
739 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
740
741 pCtx->fsHid.u32Limit = 0x0000ffff;
742 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
743 pCtx->fsHid.Attr.n.u1Present = 1;
744 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
745
746 pCtx->gsHid.u32Limit = 0x0000ffff;
747 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
748 pCtx->gsHid.Attr.n.u1Present = 1;
749 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
750
751 pCtx->ssHid.u32Limit = 0x0000ffff;
752 pCtx->ssHid.Attr.n.u1Present = 1;
753 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
754 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
755
756 pCtx->idtr.cbIdt = 0xffff;
757 pCtx->gdtr.cbGdt = 0xffff;
758
759 pCtx->ldtrHid.u32Limit = 0xffff;
760 pCtx->ldtrHid.Attr.n.u1Present = 1;
761 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
762
763 pCtx->trHid.u32Limit = 0xffff;
764 pCtx->trHid.Attr.n.u1Present = 1;
765 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
766
767 pCtx->dr[6] = X86_DR6_INIT_VAL;
768 pCtx->dr[7] = X86_DR7_INIT_VAL;
769
770 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
771 pCtx->fpu.FCW = 0x37f;
772
773 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
774 pCtx->fpu.MXCSR = 0x1F80;
775
776 /* Init PAT MSR */
777 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
778
779 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
780 * The Intel docs don't mention it.
781 */
782 pCtx->msrEFER = 0;
783
784#ifdef VBOX_WITH_CRASHDUMP_MAGIC
785 /* Magic marker for searching in crash dumps. */
786 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
787 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
788 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
789#endif
790 }
791}
792
793
794/**
795 * Execute state save operation.
796 *
797 * @returns VBox status code.
798 * @param pVM VM Handle.
799 * @param pSSM SSM operation handle.
800 */
801static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
802{
803 /*
804 * Save.
805 */
806 for (unsigned i=0;i<pVM->cCPUs;i++)
807 {
808 PVMCPU pVCpu = &pVM->aCpus[i];
809
810 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
811 }
812
813 SSMR3PutU32(pSSM, pVM->cCPUs);
814 for (unsigned i=0;i<pVM->cCPUs;i++)
815 {
816 PVMCPU pVCpu = &pVM->aCpus[i];
817
818 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
819 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
820 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
821 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
822 }
823
824 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
825 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
826
827 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
828 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
829
830 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
831 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
832
833 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
834
835 /* Add the cpuid for checking that the cpu is unchanged. */
836 uint32_t au32CpuId[8] = {0};
837 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
838 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
839 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
840}
841
842
843/**
844 * Load a version 1.6 CPUMCTX structure.
845 *
846 * @returns VBox status code.
847 * @param pVM VM Handle.
848 * @param pCpumctx16 Version 1.6 CPUMCTX
849 */
850static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
851{
852#define CPUMCTX16_LOADREG(RegName) \
853 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
854
855#define CPUMCTX16_LOADDRXREG(RegName) \
856 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
857
858#define CPUMCTX16_LOADHIDREG(RegName) \
859 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
860 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
861 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
862
863#define CPUMCTX16_LOADSEGREG(RegName) \
864 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
865 CPUMCTX16_LOADHIDREG(RegName);
866
867 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
868
869 CPUMCTX16_LOADREG(rax);
870 CPUMCTX16_LOADREG(rbx);
871 CPUMCTX16_LOADREG(rcx);
872 CPUMCTX16_LOADREG(rdx);
873 CPUMCTX16_LOADREG(rdi);
874 CPUMCTX16_LOADREG(rsi);
875 CPUMCTX16_LOADREG(rbp);
876 CPUMCTX16_LOADREG(esp);
877 CPUMCTX16_LOADREG(rip);
878 CPUMCTX16_LOADREG(rflags);
879
880 CPUMCTX16_LOADSEGREG(cs);
881 CPUMCTX16_LOADSEGREG(ds);
882 CPUMCTX16_LOADSEGREG(es);
883 CPUMCTX16_LOADSEGREG(fs);
884 CPUMCTX16_LOADSEGREG(gs);
885 CPUMCTX16_LOADSEGREG(ss);
886
887 CPUMCTX16_LOADREG(r8);
888 CPUMCTX16_LOADREG(r9);
889 CPUMCTX16_LOADREG(r10);
890 CPUMCTX16_LOADREG(r11);
891 CPUMCTX16_LOADREG(r12);
892 CPUMCTX16_LOADREG(r13);
893 CPUMCTX16_LOADREG(r14);
894 CPUMCTX16_LOADREG(r15);
895
896 CPUMCTX16_LOADREG(cr0);
897 CPUMCTX16_LOADREG(cr2);
898 CPUMCTX16_LOADREG(cr3);
899 CPUMCTX16_LOADREG(cr4);
900
901 CPUMCTX16_LOADDRXREG(0);
902 CPUMCTX16_LOADDRXREG(1);
903 CPUMCTX16_LOADDRXREG(2);
904 CPUMCTX16_LOADDRXREG(3);
905 CPUMCTX16_LOADDRXREG(4);
906 CPUMCTX16_LOADDRXREG(5);
907 CPUMCTX16_LOADDRXREG(6);
908 CPUMCTX16_LOADDRXREG(7);
909
910 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
911 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
912 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
913 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
914
915 CPUMCTX16_LOADREG(ldtr);
916 CPUMCTX16_LOADREG(tr);
917
918 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
919
920 CPUMCTX16_LOADREG(msrEFER);
921 CPUMCTX16_LOADREG(msrSTAR);
922 CPUMCTX16_LOADREG(msrPAT);
923 CPUMCTX16_LOADREG(msrLSTAR);
924 CPUMCTX16_LOADREG(msrCSTAR);
925 CPUMCTX16_LOADREG(msrSFMASK);
926 CPUMCTX16_LOADREG(msrKERNELGSBASE);
927
928 CPUMCTX16_LOADHIDREG(ldtr);
929 CPUMCTX16_LOADHIDREG(tr);
930
931#undef CPUMCTX16_LOADSEGREG
932#undef CPUMCTX16_LOADHIDREG
933#undef CPUMCTX16_LOADDRXREG
934#undef CPUMCTX16_LOADREG
935}
936
937
938/**
939 * Execute state load operation.
940 *
941 * @returns VBox status code.
942 * @param pVM VM Handle.
943 * @param pSSM SSM operation handle.
944 * @param u32Version Data layout version.
945 */
946static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
947{
948 /*
949 * Validate version.
950 */
951 if ( u32Version != CPUM_SAVED_STATE_VERSION
952 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
953 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
954 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
955 {
956 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
957 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
958 }
959
960 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
961 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
962 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
963 else if (u32Version <= CPUM_SAVED_STATE_VERSION)
964 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
965
966 /*
967 * Restore.
968 */
969 for (unsigned i=0;i<pVM->cCPUs;i++)
970 {
971 PVMCPU pVCpu = &pVM->aCpus[i];
972 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
973 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
974
975 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
976 pVCpu->cpum.s.Hyper.cr3 = uCR3;
977 pVCpu->cpum.s.Hyper.esp = uESP;
978 }
979
980 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
981 {
982 CPUMCTX_VER1_6 cpumctx16;
983 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
984 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
985
986 /* Save the old cpumctx state into the new one. */
987 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
988
989 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
990 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
991 }
992 else
993 {
994 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
995 {
996 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
997 AssertRCReturn(rc, rc);
998 }
999
1000 if ( !pVM->cCPUs
1001 || pVM->cCPUs > VMCPU_MAX_CPU_COUNT
1002 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
1003 && pVM->cCPUs != 1))
1004 {
1005 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
1006 return VERR_SSM_UNEXPECTED_DATA;
1007 }
1008
1009 for (unsigned i=0;i<pVM->cCPUs;i++)
1010 {
1011 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1012 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1013 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1014 if (u32Version == CPUM_SAVED_STATE_VERSION)
1015 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1016 }
1017 }
1018
1019
1020 uint32_t cElements;
1021 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1022 /* Support old saved states with a smaller standard cpuid array. */
1023 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1024 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1025 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1026
1027 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1028 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1029 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1030 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1031
1032 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1033 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1034 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1035 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1036
1037 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1038
1039 /*
1040 * Check that the basic cpuid id information is unchanged.
1041 * @todo we should check the 64 bits capabilities too!
1042 */
1043 uint32_t au32CpuId[8] = {0};
1044 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1045 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1046 uint32_t au32CpuIdSaved[8];
1047 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1048 if (RT_SUCCESS(rc))
1049 {
1050 /* Ignore CPU stepping. */
1051 au32CpuId[4] &= 0xfffffff0;
1052 au32CpuIdSaved[4] &= 0xfffffff0;
1053
1054 /* Ignore APIC ID (AMD specs). */
1055 au32CpuId[5] &= ~0xff000000;
1056 au32CpuIdSaved[5] &= ~0xff000000;
1057
1058 /* Ignore the number of Logical CPUs (AMD specs). */
1059 au32CpuId[5] &= ~0x00ff0000;
1060 au32CpuIdSaved[5] &= ~0x00ff0000;
1061
1062 /* do the compare */
1063 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1064 {
1065 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1066 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1067 "Saved=%.*Rhxs\n"
1068 "Real =%.*Rhxs\n",
1069 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1070 sizeof(au32CpuId), au32CpuId));
1071 else
1072 {
1073 LogRel(("cpumR3Load: CpuId mismatch!\n"
1074 "Saved=%.*Rhxs\n"
1075 "Real =%.*Rhxs\n",
1076 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1077 sizeof(au32CpuId), au32CpuId));
1078 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1079 }
1080 }
1081 }
1082
1083 return rc;
1084}
1085
1086
1087/**
1088 * Formats the EFLAGS value into mnemonics.
1089 *
1090 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1091 * @param efl The EFLAGS value.
1092 */
1093static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1094{
1095 /*
1096 * Format the flags.
1097 */
1098 static const struct
1099 {
1100 const char *pszSet; const char *pszClear; uint32_t fFlag;
1101 } s_aFlags[] =
1102 {
1103 { "vip",NULL, X86_EFL_VIP },
1104 { "vif",NULL, X86_EFL_VIF },
1105 { "ac", NULL, X86_EFL_AC },
1106 { "vm", NULL, X86_EFL_VM },
1107 { "rf", NULL, X86_EFL_RF },
1108 { "nt", NULL, X86_EFL_NT },
1109 { "ov", "nv", X86_EFL_OF },
1110 { "dn", "up", X86_EFL_DF },
1111 { "ei", "di", X86_EFL_IF },
1112 { "tf", NULL, X86_EFL_TF },
1113 { "nt", "pl", X86_EFL_SF },
1114 { "nz", "zr", X86_EFL_ZF },
1115 { "ac", "na", X86_EFL_AF },
1116 { "po", "pe", X86_EFL_PF },
1117 { "cy", "nc", X86_EFL_CF },
1118 };
1119 char *psz = pszEFlags;
1120 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1121 {
1122 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1123 if (pszAdd)
1124 {
1125 strcpy(psz, pszAdd);
1126 psz += strlen(pszAdd);
1127 *psz++ = ' ';
1128 }
1129 }
1130 psz[-1] = '\0';
1131}
1132
1133
1134/**
1135 * Formats a full register dump.
1136 *
1137 * @param pVM VM Handle.
1138 * @param pCtx The context to format.
1139 * @param pCtxCore The context core to format.
1140 * @param pHlp Output functions.
1141 * @param enmType The dump type.
1142 * @param pszPrefix Register name prefix.
1143 */
1144static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1145{
1146 /*
1147 * Format the EFLAGS.
1148 */
1149 uint32_t efl = pCtxCore->eflags.u32;
1150 char szEFlags[80];
1151 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1152
1153 /*
1154 * Format the registers.
1155 */
1156 switch (enmType)
1157 {
1158 case CPUMDUMPTYPE_TERSE:
1159 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1160 pHlp->pfnPrintf(pHlp,
1161 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1162 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1163 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1164 "%sr14=%016RX64 %sr15=%016RX64\n"
1165 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1166 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1167 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1168 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1169 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1170 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1171 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1172 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1173 else
1174 pHlp->pfnPrintf(pHlp,
1175 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1176 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1177 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1178 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1179 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1180 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1181 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1182 break;
1183
1184 case CPUMDUMPTYPE_DEFAULT:
1185 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1186 pHlp->pfnPrintf(pHlp,
1187 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1188 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1189 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1190 "%sr14=%016RX64 %sr15=%016RX64\n"
1191 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1192 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1193 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1194 ,
1195 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1196 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1197 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1198 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1199 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1200 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1201 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1202 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1203 else
1204 pHlp->pfnPrintf(pHlp,
1205 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1206 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1207 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1208 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1209 ,
1210 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1211 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1212 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1213 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1214 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1215 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1216 break;
1217
1218 case CPUMDUMPTYPE_VERBOSE:
1219 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1220 pHlp->pfnPrintf(pHlp,
1221 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1222 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1223 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1224 "%sr14=%016RX64 %sr15=%016RX64\n"
1225 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1226 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1227 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1228 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1229 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1230 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1231 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1232 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1233 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1234 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1235 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1236 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1237 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1238 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1239 ,
1240 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1241 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1242 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1243 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1244 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1245 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1246 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1247 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1248 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1249 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1250 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1251 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1252 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1253 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1254 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1255 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1256 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1257 else
1258 pHlp->pfnPrintf(pHlp,
1259 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1260 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1261 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1262 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1263 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1264 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1265 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1266 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1267 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1268 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1269 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1270 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1271 ,
1272 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1273 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1274 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1275 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1276 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1277 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1278 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1279 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1280 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1281 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1282 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1283 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1284
1285 pHlp->pfnPrintf(pHlp,
1286 "FPU:\n"
1287 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1288 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1289 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1290 ,
1291 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1292 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1293 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1294 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1295
1296 pHlp->pfnPrintf(pHlp,
1297 "MSR:\n"
1298 "%sEFER =%016RX64\n"
1299 "%sPAT =%016RX64\n"
1300 "%sSTAR =%016RX64\n"
1301 "%sCSTAR =%016RX64\n"
1302 "%sLSTAR =%016RX64\n"
1303 "%sSFMASK =%016RX64\n"
1304 "%sKERNELGSBASE =%016RX64\n",
1305 pszPrefix, pCtx->msrEFER,
1306 pszPrefix, pCtx->msrPAT,
1307 pszPrefix, pCtx->msrSTAR,
1308 pszPrefix, pCtx->msrCSTAR,
1309 pszPrefix, pCtx->msrLSTAR,
1310 pszPrefix, pCtx->msrSFMASK,
1311 pszPrefix, pCtx->msrKERNELGSBASE);
1312 break;
1313 }
1314}
1315
1316
1317/**
1318 * Display all cpu states and any other cpum info.
1319 *
1320 * @param pVM VM Handle.
1321 * @param pHlp The info helper functions.
1322 * @param pszArgs Arguments, ignored.
1323 */
1324static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1325{
1326 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1327 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1328 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1329 cpumR3InfoHost(pVM, pHlp, pszArgs);
1330}
1331
1332
1333/**
1334 * Parses the info argument.
1335 *
1336 * The argument starts with 'verbose', 'terse' or 'default' and then
1337 * continues with the comment string.
1338 *
1339 * @param pszArgs The pointer to the argument string.
1340 * @param penmType Where to store the dump type request.
1341 * @param ppszComment Where to store the pointer to the comment string.
1342 */
1343static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1344{
1345 if (!pszArgs)
1346 {
1347 *penmType = CPUMDUMPTYPE_DEFAULT;
1348 *ppszComment = "";
1349 }
1350 else
1351 {
1352 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1353 {
1354 pszArgs += 5;
1355 *penmType = CPUMDUMPTYPE_VERBOSE;
1356 }
1357 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1358 {
1359 pszArgs += 5;
1360 *penmType = CPUMDUMPTYPE_TERSE;
1361 }
1362 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1363 {
1364 pszArgs += 7;
1365 *penmType = CPUMDUMPTYPE_DEFAULT;
1366 }
1367 else
1368 *penmType = CPUMDUMPTYPE_DEFAULT;
1369 *ppszComment = RTStrStripL(pszArgs);
1370 }
1371}
1372
1373
1374/**
1375 * Display the guest cpu state.
1376 *
1377 * @param pVM VM Handle.
1378 * @param pHlp The info helper functions.
1379 * @param pszArgs Arguments, ignored.
1380 */
1381static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1382{
1383 CPUMDUMPTYPE enmType;
1384 const char *pszComment;
1385 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1386 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1387
1388 /* @todo SMP support! */
1389 PVMCPU pVCpu = &pVM->aCpus[0];
1390 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1391 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1392}
1393
1394
1395/**
1396 * Display the current guest instruction
1397 *
1398 * @param pVM VM Handle.
1399 * @param pHlp The info helper functions.
1400 * @param pszArgs Arguments, ignored.
1401 */
1402static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1403{
1404 char szInstruction[256];
1405 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1406 if (RT_SUCCESS(rc))
1407 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1408}
1409
1410
1411/**
1412 * Display the hypervisor cpu state.
1413 *
1414 * @param pVM VM Handle.
1415 * @param pHlp The info helper functions.
1416 * @param pszArgs Arguments, ignored.
1417 */
1418static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1419{
1420 CPUMDUMPTYPE enmType;
1421 const char *pszComment;
1422 /* @todo SMP */
1423 PVMCPU pVCpu = &pVM->aCpus[0];
1424
1425 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1426 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1427 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1428 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1429}
1430
1431
1432/**
1433 * Display the host cpu state.
1434 *
1435 * @param pVM VM Handle.
1436 * @param pHlp The info helper functions.
1437 * @param pszArgs Arguments, ignored.
1438 */
1439static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1440{
1441 CPUMDUMPTYPE enmType;
1442 const char *pszComment;
1443 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1444 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1445
1446 /*
1447 * Format the EFLAGS.
1448 */
1449 /* @todo SMP */
1450 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1451#if HC_ARCH_BITS == 32
1452 uint32_t efl = pCtx->eflags.u32;
1453#else
1454 uint64_t efl = pCtx->rflags;
1455#endif
1456 char szEFlags[80];
1457 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1458
1459 /*
1460 * Format the registers.
1461 */
1462#if HC_ARCH_BITS == 32
1463# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1464 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1465# endif
1466 {
1467 pHlp->pfnPrintf(pHlp,
1468 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1469 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1470 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1471 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1472 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1473 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1474 ,
1475 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1476 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1477 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1478 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1479 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1480 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1481 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1482 }
1483# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1484 else
1485# endif
1486#endif
1487#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1488 {
1489 pHlp->pfnPrintf(pHlp,
1490 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1491 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1492 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1493 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1494 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1495 "r14=%016RX64 r15=%016RX64\n"
1496 "iopl=%d %31s\n"
1497 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1498 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1499 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1500 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1501 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1502 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1503 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1504 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1505 ,
1506 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1507 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1508 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1509 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1510 pCtx->r11, pCtx->r12, pCtx->r13,
1511 pCtx->r14, pCtx->r15,
1512 X86_EFL_GET_IOPL(efl), szEFlags,
1513 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1514 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1515 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1516 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1517 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1518 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1519 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1520 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1521 }
1522#endif
1523}
1524
1525
1526/**
1527 * Get L1 cache / TLS associativity.
1528 */
1529static const char *getCacheAss(unsigned u, char *pszBuf)
1530{
1531 if (u == 0)
1532 return "res0 ";
1533 if (u == 1)
1534 return "direct";
1535 if (u >= 256)
1536 return "???";
1537
1538 RTStrPrintf(pszBuf, 16, "%d way", u);
1539 return pszBuf;
1540}
1541
1542
1543/**
1544 * Get L2 cache soociativity.
1545 */
1546const char *getL2CacheAss(unsigned u)
1547{
1548 switch (u)
1549 {
1550 case 0: return "off ";
1551 case 1: return "direct";
1552 case 2: return "2 way ";
1553 case 3: return "res3 ";
1554 case 4: return "4 way ";
1555 case 5: return "res5 ";
1556 case 6: return "8 way "; case 7: return "res7 ";
1557 case 8: return "16 way";
1558 case 9: return "res9 ";
1559 case 10: return "res10 ";
1560 case 11: return "res11 ";
1561 case 12: return "res12 ";
1562 case 13: return "res13 ";
1563 case 14: return "res14 ";
1564 case 15: return "fully ";
1565 default:
1566 return "????";
1567 }
1568}
1569
1570
1571/**
1572 * Display the guest CpuId leaves.
1573 *
1574 * @param pVM VM Handle.
1575 * @param pHlp The info helper functions.
1576 * @param pszArgs "terse", "default" or "verbose".
1577 */
1578static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1579{
1580 /*
1581 * Parse the argument.
1582 */
1583 unsigned iVerbosity = 1;
1584 if (pszArgs)
1585 {
1586 pszArgs = RTStrStripL(pszArgs);
1587 if (!strcmp(pszArgs, "terse"))
1588 iVerbosity--;
1589 else if (!strcmp(pszArgs, "verbose"))
1590 iVerbosity++;
1591 }
1592
1593 /*
1594 * Start cracking.
1595 */
1596 CPUMCPUID Host;
1597 CPUMCPUID Guest;
1598 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1599
1600 pHlp->pfnPrintf(pHlp,
1601 " RAW Standard CPUIDs\n"
1602 " Function eax ebx ecx edx\n");
1603 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1604 {
1605 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1606 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1607
1608 pHlp->pfnPrintf(pHlp,
1609 "Gst: %08x %08x %08x %08x %08x%s\n"
1610 "Hst: %08x %08x %08x %08x\n",
1611 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1612 i <= cStdMax ? "" : "*",
1613 Host.eax, Host.ebx, Host.ecx, Host.edx);
1614 }
1615
1616 /*
1617 * If verbose, decode it.
1618 */
1619 if (iVerbosity)
1620 {
1621 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1622 pHlp->pfnPrintf(pHlp,
1623 "Name: %.04s%.04s%.04s\n"
1624 "Supports: 0-%x\n",
1625 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1626 }
1627
1628 /*
1629 * Get Features.
1630 */
1631 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1632 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1633 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1634 if (cStdMax >= 1 && iVerbosity)
1635 {
1636 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1637 uint32_t uEAX = Guest.eax;
1638
1639 pHlp->pfnPrintf(pHlp,
1640 "Family: %d \tExtended: %d \tEffective: %d\n"
1641 "Model: %d \tExtended: %d \tEffective: %d\n"
1642 "Stepping: %d\n"
1643 "APIC ID: %#04x\n"
1644 "Logical CPUs: %d\n"
1645 "CLFLUSH Size: %d\n"
1646 "Brand ID: %#04x\n",
1647 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1648 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1649 ASMGetCpuStepping(uEAX),
1650 (Guest.ebx >> 24) & 0xff,
1651 (Guest.ebx >> 16) & 0xff,
1652 (Guest.ebx >> 8) & 0xff,
1653 (Guest.ebx >> 0) & 0xff);
1654 if (iVerbosity == 1)
1655 {
1656 uint32_t uEDX = Guest.edx;
1657 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1658 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1659 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1660 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1661 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1662 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1663 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1664 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1665 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1666 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1667 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1668 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1669 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1670 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1671 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1672 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1673 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1674 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1675 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1676 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1677 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1678 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1679 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1680 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1681 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1682 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1683 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1684 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1685 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1686 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1687 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1688 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1689 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1690 pHlp->pfnPrintf(pHlp, "\n");
1691
1692 uint32_t uECX = Guest.ecx;
1693 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1694 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1695 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1696 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1697 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1698 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1699 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1700 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1701 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1702 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1703 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1704 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1705 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1706 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1707 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1708 for (unsigned iBit = 14; iBit < 32; iBit++)
1709 if (uECX & RT_BIT(iBit))
1710 pHlp->pfnPrintf(pHlp, " %d", iBit);
1711 pHlp->pfnPrintf(pHlp, "\n");
1712 }
1713 else
1714 {
1715 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1716
1717 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1718 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1719 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1720 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1721
1722 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1723 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1724 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1725 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1726 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1727 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1728 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1729 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1730 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1731 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1732 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1733 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1734 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1735 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1736 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1737 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1738 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1739 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1740 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1741 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1742 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1743 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1744 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1745 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1746 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1747 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1748 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1749 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1750 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1751 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1752 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1753 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1754 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1755
1756 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1757 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1758 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1759 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1760 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1761 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1762 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1763 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1764 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1765 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1766 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1767 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1768 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1769 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1770 }
1771 }
1772 if (cStdMax >= 2 && iVerbosity)
1773 {
1774 /** @todo */
1775 }
1776
1777 /*
1778 * Extended.
1779 * Implemented after AMD specs.
1780 */
1781 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1782
1783 pHlp->pfnPrintf(pHlp,
1784 "\n"
1785 " RAW Extended CPUIDs\n"
1786 " Function eax ebx ecx edx\n");
1787 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1788 {
1789 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1790 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1791
1792 pHlp->pfnPrintf(pHlp,
1793 "Gst: %08x %08x %08x %08x %08x%s\n"
1794 "Hst: %08x %08x %08x %08x\n",
1795 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1796 i <= cExtMax ? "" : "*",
1797 Host.eax, Host.ebx, Host.ecx, Host.edx);
1798 }
1799
1800 /*
1801 * Understandable output
1802 */
1803 if (iVerbosity)
1804 {
1805 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1806 pHlp->pfnPrintf(pHlp,
1807 "Ext Name: %.4s%.4s%.4s\n"
1808 "Ext Supports: 0x80000000-%#010x\n",
1809 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1810 }
1811
1812 if (iVerbosity && cExtMax >= 1)
1813 {
1814 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1815 uint32_t uEAX = Guest.eax;
1816 pHlp->pfnPrintf(pHlp,
1817 "Family: %d \tExtended: %d \tEffective: %d\n"
1818 "Model: %d \tExtended: %d \tEffective: %d\n"
1819 "Stepping: %d\n"
1820 "Brand ID: %#05x\n",
1821 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1822 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1823 ASMGetCpuStepping(uEAX),
1824 Guest.ebx & 0xfff);
1825
1826 if (iVerbosity == 1)
1827 {
1828 uint32_t uEDX = Guest.edx;
1829 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1830 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1831 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1832 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1833 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1834 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1835 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1836 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1837 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1838 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1839 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1840 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1841 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1842 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1843 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1844 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1845 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1846 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1847 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1848 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1849 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1850 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1851 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1852 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1853 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1854 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1855 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1856 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1857 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1858 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1859 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1860 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1861 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1862 pHlp->pfnPrintf(pHlp, "\n");
1863
1864 uint32_t uECX = Guest.ecx;
1865 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1866 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1867 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1868 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1869 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1870 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1871 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1872 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1873 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1874 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1875 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1876 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1877 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1878 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1879 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1880 for (unsigned iBit = 5; iBit < 32; iBit++)
1881 if (uECX & RT_BIT(iBit))
1882 pHlp->pfnPrintf(pHlp, " %d", iBit);
1883 pHlp->pfnPrintf(pHlp, "\n");
1884 }
1885 else
1886 {
1887 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1888
1889 uint32_t uEdxGst = Guest.edx;
1890 uint32_t uEdxHst = Host.edx;
1891 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1892 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1893 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1894 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1895 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1896 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1897 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1898 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1899 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1900 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1901 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1902 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1903 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1904 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1905 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1906 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1907 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1908 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1909 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1910 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1911 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1912 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1913 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1914 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1915 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1916 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1917 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1918 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1919 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1920 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1921 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1922 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1923 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1924
1925 uint32_t uEcxGst = Guest.ecx;
1926 uint32_t uEcxHst = Host.ecx;
1927 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1928 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1929 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1930 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1931 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1932 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1933 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1934 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1935 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1936 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1937 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1938 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1939 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1940 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1941 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1942 }
1943 }
1944
1945 if (iVerbosity && cExtMax >= 2)
1946 {
1947 char szString[4*4*3+1] = {0};
1948 uint32_t *pu32 = (uint32_t *)szString;
1949 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1950 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1951 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1952 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1953 if (cExtMax >= 3)
1954 {
1955 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1956 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1957 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1958 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1959 }
1960 if (cExtMax >= 4)
1961 {
1962 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1963 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1964 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1965 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1966 }
1967 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1968 }
1969
1970 if (iVerbosity && cExtMax >= 5)
1971 {
1972 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1973 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1974 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1975 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1976 char sz1[32];
1977 char sz2[32];
1978
1979 pHlp->pfnPrintf(pHlp,
1980 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1981 "TLB 2/4M Data: %s %3d entries\n",
1982 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1983 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1984 pHlp->pfnPrintf(pHlp,
1985 "TLB 4K Instr/Uni: %s %3d entries\n"
1986 "TLB 4K Data: %s %3d entries\n",
1987 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1988 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1989 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1990 "L1 Instr Cache Lines Per Tag: %d\n"
1991 "L1 Instr Cache Associativity: %s\n"
1992 "L1 Instr Cache Size: %d KB\n",
1993 (uEDX >> 0) & 0xff,
1994 (uEDX >> 8) & 0xff,
1995 getCacheAss((uEDX >> 16) & 0xff, sz1),
1996 (uEDX >> 24) & 0xff);
1997 pHlp->pfnPrintf(pHlp,
1998 "L1 Data Cache Line Size: %d bytes\n"
1999 "L1 Data Cache Lines Per Tag: %d\n"
2000 "L1 Data Cache Associativity: %s\n"
2001 "L1 Data Cache Size: %d KB\n",
2002 (uECX >> 0) & 0xff,
2003 (uECX >> 8) & 0xff,
2004 getCacheAss((uECX >> 16) & 0xff, sz1),
2005 (uECX >> 24) & 0xff);
2006 }
2007
2008 if (iVerbosity && cExtMax >= 6)
2009 {
2010 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2011 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2012 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2013
2014 pHlp->pfnPrintf(pHlp,
2015 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2016 "L2 TLB 2/4M Data: %s %4d entries\n",
2017 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2018 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2019 pHlp->pfnPrintf(pHlp,
2020 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2021 "L2 TLB 4K Data: %s %4d entries\n",
2022 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2023 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2024 pHlp->pfnPrintf(pHlp,
2025 "L2 Cache Line Size: %d bytes\n"
2026 "L2 Cache Lines Per Tag: %d\n"
2027 "L2 Cache Associativity: %s\n"
2028 "L2 Cache Size: %d KB\n",
2029 (uEDX >> 0) & 0xff,
2030 (uEDX >> 8) & 0xf,
2031 getL2CacheAss((uEDX >> 12) & 0xf),
2032 (uEDX >> 16) & 0xffff);
2033 }
2034
2035 if (iVerbosity && cExtMax >= 7)
2036 {
2037 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2038
2039 pHlp->pfnPrintf(pHlp, "APM Features: ");
2040 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2041 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2042 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2043 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2044 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2045 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2046 for (unsigned iBit = 6; iBit < 32; iBit++)
2047 if (uEDX & RT_BIT(iBit))
2048 pHlp->pfnPrintf(pHlp, " %d", iBit);
2049 pHlp->pfnPrintf(pHlp, "\n");
2050 }
2051
2052 if (iVerbosity && cExtMax >= 8)
2053 {
2054 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2055 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2056
2057 pHlp->pfnPrintf(pHlp,
2058 "Physical Address Width: %d bits\n"
2059 "Virtual Address Width: %d bits\n",
2060 (uEAX >> 0) & 0xff,
2061 (uEAX >> 8) & 0xff);
2062 pHlp->pfnPrintf(pHlp,
2063 "Physical Core Count: %d\n",
2064 (uECX >> 0) & 0xff);
2065 }
2066
2067
2068 /*
2069 * Centaur.
2070 */
2071 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2072
2073 pHlp->pfnPrintf(pHlp,
2074 "\n"
2075 " RAW Centaur CPUIDs\n"
2076 " Function eax ebx ecx edx\n");
2077 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2078 {
2079 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2080 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2081
2082 pHlp->pfnPrintf(pHlp,
2083 "Gst: %08x %08x %08x %08x %08x%s\n"
2084 "Hst: %08x %08x %08x %08x\n",
2085 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2086 i <= cCentaurMax ? "" : "*",
2087 Host.eax, Host.ebx, Host.ecx, Host.edx);
2088 }
2089
2090 /*
2091 * Understandable output
2092 */
2093 if (iVerbosity)
2094 {
2095 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2096 pHlp->pfnPrintf(pHlp,
2097 "Centaur Supports: 0xc0000000-%#010x\n",
2098 Guest.eax);
2099 }
2100
2101 if (iVerbosity && cCentaurMax >= 1)
2102 {
2103 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2104 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2105 uint32_t uEdxHst = Host.edx;
2106
2107 if (iVerbosity == 1)
2108 {
2109 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2110 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2111 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2112 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2113 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2114 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2115 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2116 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2117 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2118 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2119 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2120 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2121 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2122 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2123 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2124 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2125 for (unsigned iBit = 14; iBit < 32; iBit++)
2126 if (uEdxGst & RT_BIT(iBit))
2127 pHlp->pfnPrintf(pHlp, " %d", iBit);
2128 pHlp->pfnPrintf(pHlp, "\n");
2129 }
2130 else
2131 {
2132 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2133 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2134 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2135 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2136 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2137 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2138 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2139 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2140 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2141 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2142 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2143 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2144 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2145 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2146 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2147 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2148 for (unsigned iBit = 14; iBit < 32; iBit++)
2149 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2150 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2151 pHlp->pfnPrintf(pHlp, "\n");
2152 }
2153 }
2154}
2155
2156
2157/**
2158 * Structure used when disassembling and instructions in DBGF.
2159 * This is used so the reader function can get the stuff it needs.
2160 */
2161typedef struct CPUMDISASSTATE
2162{
2163 /** Pointer to the CPU structure. */
2164 PDISCPUSTATE pCpu;
2165 /** The VM handle. */
2166 PVM pVM;
2167 /** The VMCPU handle. */
2168 PVMCPU pVCpu;
2169 /** Pointer to the first byte in the segemnt. */
2170 RTGCUINTPTR GCPtrSegBase;
2171 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2172 RTGCUINTPTR GCPtrSegEnd;
2173 /** The size of the segment minus 1. */
2174 RTGCUINTPTR cbSegLimit;
2175 /** Pointer to the current page - R3 Ptr. */
2176 void const *pvPageR3;
2177 /** Pointer to the current page - GC Ptr. */
2178 RTGCPTR pvPageGC;
2179 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2180 PGMPAGEMAPLOCK PageMapLock;
2181 /** Whether the PageMapLock is valid or not. */
2182 bool fLocked;
2183 /** 64 bits mode or not. */
2184 bool f64Bits;
2185} CPUMDISASSTATE, *PCPUMDISASSTATE;
2186
2187
2188/**
2189 * Instruction reader.
2190 *
2191 * @returns VBox status code.
2192 * @param PtrSrc Address to read from.
2193 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2194 * @param pu8Dst Where to store the bytes.
2195 * @param cbRead Number of bytes to read.
2196 * @param uDisCpu Pointer to the disassembler cpu state.
2197 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2198 */
2199static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2200{
2201 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2202 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2203 Assert(cbRead > 0);
2204 for (;;)
2205 {
2206 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2207
2208 /* Need to update the page translation? */
2209 if ( !pState->pvPageR3
2210 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2211 {
2212 int rc = VINF_SUCCESS;
2213
2214 /* translate the address */
2215 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2216 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2217 && !HWACCMIsEnabled(pState->pVM))
2218 {
2219 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2220 if (!pState->pvPageR3)
2221 rc = VERR_INVALID_POINTER;
2222 }
2223 else
2224 {
2225 /* Release mapping lock previously acquired. */
2226 if (pState->fLocked)
2227 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2228 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2229 pState->fLocked = RT_SUCCESS_NP(rc);
2230 }
2231 if (RT_FAILURE(rc))
2232 {
2233 pState->pvPageR3 = NULL;
2234 return rc;
2235 }
2236 }
2237
2238 /* check the segemnt limit */
2239 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2240 return VERR_OUT_OF_SELECTOR_BOUNDS;
2241
2242 /* calc how much we can read */
2243 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2244 if (!pState->f64Bits)
2245 {
2246 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2247 if (cb > cbSeg && cbSeg)
2248 cb = cbSeg;
2249 }
2250 if (cb > cbRead)
2251 cb = cbRead;
2252
2253 /* read and advance */
2254 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2255 cbRead -= cb;
2256 if (!cbRead)
2257 return VINF_SUCCESS;
2258 pu8Dst += cb;
2259 PtrSrc += cb;
2260 }
2261}
2262
2263
2264/**
2265 * Disassemble an instruction and return the information in the provided structure.
2266 *
2267 * @returns VBox status code.
2268 * @param pVM VM Handle
2269 * @param pVCpu VMCPU Handle
2270 * @param pCtx CPU context
2271 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2272 * @param pCpu Disassembly state
2273 * @param pszPrefix String prefix for logging (debug only)
2274 *
2275 */
2276VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2277{
2278 CPUMDISASSTATE State;
2279 int rc;
2280
2281 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2282 State.pCpu = pCpu;
2283 State.pvPageGC = 0;
2284 State.pvPageR3 = NULL;
2285 State.pVM = pVM;
2286 State.pVCpu = pVCpu;
2287 State.fLocked = false;
2288 State.f64Bits = false;
2289
2290 /*
2291 * Get selector information.
2292 */
2293 if ( (pCtx->cr0 & X86_CR0_PE)
2294 && pCtx->eflags.Bits.u1VM == 0)
2295 {
2296 if (CPUMAreHiddenSelRegsValid(pVM))
2297 {
2298 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2299 State.GCPtrSegBase = pCtx->csHid.u64Base;
2300 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2301 State.cbSegLimit = pCtx->csHid.u32Limit;
2302 pCpu->mode = (State.f64Bits)
2303 ? CPUMODE_64BIT
2304 : pCtx->csHid.Attr.n.u1DefBig
2305 ? CPUMODE_32BIT
2306 : CPUMODE_16BIT;
2307 }
2308 else
2309 {
2310 SELMSELINFO SelInfo;
2311
2312 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2313 if (!RT_SUCCESS(rc))
2314 {
2315 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2316 return rc;
2317 }
2318
2319 /*
2320 * Validate the selector.
2321 */
2322 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2323 if (!RT_SUCCESS(rc))
2324 {
2325 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2326 return rc;
2327 }
2328 State.GCPtrSegBase = SelInfo.GCPtrBase;
2329 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2330 State.cbSegLimit = SelInfo.cbLimit;
2331 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2332 }
2333 }
2334 else
2335 {
2336 /* real or V86 mode */
2337 pCpu->mode = CPUMODE_16BIT;
2338 State.GCPtrSegBase = pCtx->cs * 16;
2339 State.GCPtrSegEnd = 0xFFFFFFFF;
2340 State.cbSegLimit = 0xFFFFFFFF;
2341 }
2342
2343 /*
2344 * Disassemble the instruction.
2345 */
2346 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2347 pCpu->apvUserData[0] = &State;
2348
2349 uint32_t cbInstr;
2350#ifndef LOG_ENABLED
2351 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2352 if (RT_SUCCESS(rc))
2353 {
2354#else
2355 char szOutput[160];
2356 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2357 if (RT_SUCCESS(rc))
2358 {
2359 /* log it */
2360 if (pszPrefix)
2361 Log(("%s: %s", pszPrefix, szOutput));
2362 else
2363 Log(("%s", szOutput));
2364#endif
2365 rc = VINF_SUCCESS;
2366 }
2367 else
2368 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2369
2370 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2371 if (State.fLocked)
2372 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2373
2374 return rc;
2375}
2376
2377#ifdef DEBUG
2378
2379/**
2380 * Disassemble an instruction and dump it to the log
2381 *
2382 * @returns VBox status code.
2383 * @param pVM VM Handle
2384 * @param pVCpu VMCPU Handle
2385 * @param pCtx CPU context
2386 * @param pc GC instruction pointer
2387 * @param pszPrefix String prefix for logging
2388 *
2389 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2390 */
2391VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2392{
2393 DISCPUSTATE Cpu;
2394 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2395}
2396
2397
2398/**
2399 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2400 *
2401 * @internal
2402 */
2403VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2404{
2405 /* @todo SMP support!! */
2406 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2407}
2408
2409#endif /* DEBUG */
2410
2411/**
2412 * API for controlling a few of the CPU features found in CR4.
2413 *
2414 * Currently only X86_CR4_TSD is accepted as input.
2415 *
2416 * @returns VBox status code.
2417 *
2418 * @param pVM The VM handle.
2419 * @param fOr The CR4 OR mask.
2420 * @param fAnd The CR4 AND mask.
2421 */
2422VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2423{
2424 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2425 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2426
2427 pVM->cpum.s.CR4.OrMask &= fAnd;
2428 pVM->cpum.s.CR4.OrMask |= fOr;
2429
2430 return VINF_SUCCESS;
2431}
2432
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