VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 19722

Last change on this file since 19722 was 19712, checked in by vboxsync, 16 years ago

Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs.

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1/* $Id: CPUM.cpp 19712 2009-05-15 07:59:32Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 10
71/** The saved state version for the 2.1 trunk before the MSR changes. */
72#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
73/** The saved state version of 2.0, used for backwards compatibility. */
74#define CPUM_SAVED_STATE_VERSION_VER2_0 8
75/** The saved state version of 1.6, used for backwards compatability. */
76#define CPUM_SAVED_STATE_VERSION_VER1_6 6
77
78
79/*******************************************************************************
80* Structures and Typedefs *
81*******************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91
92} CPUMDUMPTYPE;
93/** Pointer to a cpu info dump type. */
94typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97/*******************************************************************************
98* Internal Functions *
99*******************************************************************************/
100static int cpumR3CpuIdInit(PVM pVM);
101static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/**
112 * Initializes the CPUM.
113 *
114 * @returns VBox status code.
115 * @param pVM The VM to operate on.
116 */
117VMMR3DECL(int) CPUMR3Init(PVM pVM)
118{
119 LogFlow(("CPUMR3Init\n"));
120
121 /*
122 * Assert alignment and sizes.
123 */
124 AssertCompileMemberAlignment(VM, cpum.s, 32);
125 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
126 AssertCompileSizeAlignment(CPUMCTX, 64);
127 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
128 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
129 AssertCompileMemberAlignment(VM, cpum, 64);
130 AssertCompileMemberAlignment(VM, aCpus, 64);
131 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
132 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
133
134 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
135 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
136 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
137
138 /* Calculate the offset from CPUMCPU to CPUM. */
139 for (unsigned i=0;i<pVM->cCPUs;i++)
140 {
141 PVMCPU pVCpu = &pVM->aCpus[i];
142
143 /*
144 * Setup any fixed pointers and offsets.
145 */
146 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
147 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
148
149 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
150 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
151 }
152
153 /*
154 * Check that the CPU supports the minimum features we require.
155 */
156 if (!ASMHasCpuId())
157 {
158 Log(("The CPU doesn't support CPUID!\n"));
159 return VERR_UNSUPPORTED_CPU;
160 }
161 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
162 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
163
164 /* Setup the CR4 AND and OR masks used in the switcher */
165 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
166 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
167 {
168 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
169 /* No FXSAVE implies no SSE */
170 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
171 pVM->cpum.s.CR4.OrMask = 0;
172 }
173 else
174 {
175 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
176 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
177 }
178
179 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
180 {
181 Log(("The CPU doesn't support MMX!\n"));
182 return VERR_UNSUPPORTED_CPU;
183 }
184 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
185 {
186 Log(("The CPU doesn't support TSC!\n"));
187 return VERR_UNSUPPORTED_CPU;
188 }
189 /* Bogus on AMD? */
190 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
191 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
192
193 /*
194 * Setup hypervisor startup values.
195 */
196
197 /*
198 * Register saved state data item.
199 */
200 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
201 NULL, cpumR3Save, NULL,
202 NULL, cpumR3Load, NULL);
203 if (RT_FAILURE(rc))
204 return rc;
205
206 /* Query the CPU manufacturer. */
207 uint32_t uEAX, uEBX, uECX, uEDX;
208 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
209 if ( uEAX >= 1
210 && uEBX == X86_CPUID_VENDOR_AMD_EBX
211 && uECX == X86_CPUID_VENDOR_AMD_ECX
212 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
213 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
214 else if ( uEAX >= 1
215 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
216 && uECX == X86_CPUID_VENDOR_INTEL_ECX
217 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
218 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
219 else /** @todo Via */
220 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
221
222 /*
223 * Register info handlers.
224 */
225 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
226 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
227 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
228 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
229 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
230 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
231
232 /*
233 * Initialize the Guest CPU state.
234 */
235 rc = cpumR3CpuIdInit(pVM);
236 if (RT_FAILURE(rc))
237 return rc;
238 CPUMR3Reset(pVM);
239 return VINF_SUCCESS;
240}
241
242
243/**
244 * Initializes the per-VCPU CPUM.
245 *
246 * @returns VBox status code.
247 * @param pVM The VM to operate on.
248 */
249VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
250{
251 LogFlow(("CPUMR3InitCPU\n"));
252 return VINF_SUCCESS;
253}
254
255
256/**
257 * Initializes the emulated CPU's cpuid information.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262static int cpumR3CpuIdInit(PVM pVM)
263{
264 PCPUM pCPUM = &pVM->cpum.s;
265 uint32_t i;
266
267 /*
268 * Get the host CPUIDs.
269 */
270 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
271 ASMCpuId_Idx_ECX(i, 0,
272 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
273 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
274 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
275 ASMCpuId(0x80000000 + i,
276 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
277 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
278 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
279 ASMCpuId(0xc0000000 + i,
280 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
281 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
282
283
284 /*
285 * Only report features we can support.
286 */
287 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
288 | X86_CPUID_FEATURE_EDX_VME
289 | X86_CPUID_FEATURE_EDX_DE
290 | X86_CPUID_FEATURE_EDX_PSE
291 | X86_CPUID_FEATURE_EDX_TSC
292 | X86_CPUID_FEATURE_EDX_MSR
293 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
294 | X86_CPUID_FEATURE_EDX_MCE
295 | X86_CPUID_FEATURE_EDX_CX8
296 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
297 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
298 //| X86_CPUID_FEATURE_EDX_SEP
299 | X86_CPUID_FEATURE_EDX_MTRR
300 | X86_CPUID_FEATURE_EDX_PGE
301 | X86_CPUID_FEATURE_EDX_MCA
302 | X86_CPUID_FEATURE_EDX_CMOV
303 | X86_CPUID_FEATURE_EDX_PAT
304 | X86_CPUID_FEATURE_EDX_PSE36
305 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
306 | X86_CPUID_FEATURE_EDX_CLFSH
307 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
308 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
309 | X86_CPUID_FEATURE_EDX_MMX
310 | X86_CPUID_FEATURE_EDX_FXSR
311 | X86_CPUID_FEATURE_EDX_SSE
312 | X86_CPUID_FEATURE_EDX_SSE2
313 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
314 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
315 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
316 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
317 | 0;
318 pCPUM->aGuestCpuIdStd[1].ecx &= 0
319 | X86_CPUID_FEATURE_ECX_SSE3
320 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
321 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
322 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
323 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
324 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
325 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
326 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
327 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
328 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
329 /* ECX Bit 21 - x2APIC support - not yet. */
330 // | X86_CPUID_FEATURE_ECX_X2APIC
331 /* ECX Bit 23 - POPCOUNT instruction. */
332 //| X86_CPUID_FEATURE_ECX_POPCOUNT
333 | 0;
334
335 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
336 if (pVM->cCPUs == 1)
337 pCPUM->aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_MONITOR;
338
339 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
340 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
341 | X86_CPUID_AMD_FEATURE_EDX_VME
342 | X86_CPUID_AMD_FEATURE_EDX_DE
343 | X86_CPUID_AMD_FEATURE_EDX_PSE
344 | X86_CPUID_AMD_FEATURE_EDX_TSC
345 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
346 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
347 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
348 | X86_CPUID_AMD_FEATURE_EDX_CX8
349 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
350 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
351 //| X86_CPUID_AMD_FEATURE_EDX_SEP
352 | X86_CPUID_AMD_FEATURE_EDX_MTRR
353 | X86_CPUID_AMD_FEATURE_EDX_PGE
354 | X86_CPUID_AMD_FEATURE_EDX_MCA
355 | X86_CPUID_AMD_FEATURE_EDX_CMOV
356 | X86_CPUID_AMD_FEATURE_EDX_PAT
357 | X86_CPUID_AMD_FEATURE_EDX_PSE36
358 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
359 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
360 | X86_CPUID_AMD_FEATURE_EDX_MMX
361 | X86_CPUID_AMD_FEATURE_EDX_FXSR
362 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
363 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
364 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
365 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
366 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
367 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
368 | 0;
369 pCPUM->aGuestCpuIdExt[1].ecx &= 0
370 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
371 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
372 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
373 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
374 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
375 //| X86_CPUID_AMD_FEATURE_ECX_ABM
376 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
377 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
378 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
379 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
380 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
381 //| X86_CPUID_AMD_FEATURE_ECX_WDT
382 | 0;
383
384 /*
385 * Hide HTT, multicode, SMP, whatever.
386 * (APIC-ID := 0 and #LogCpus := 0)
387 */
388 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
389#ifdef VBOX_WITH_MULTI_CORE
390 /* Set the Maximum number of addressable IDs for logical processors in this physical package (bits 16-23) */
391 pCPUM->aGuestCpuIdStd[1].ebx |= ((pVM->cCPUs - 1) << 16);
392
393 if (pVM->cCPUs > 1)
394 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
395#endif
396
397 /* Cpuid 2:
398 * Intel: Cache and TLB information
399 * AMD: Reserved
400 * Safe to expose
401 */
402
403 /* Cpuid 3:
404 * Intel: EAX, EBX - reserved
405 * ECX, EDX - Processor Serial Number if available, otherwise reserved
406 * AMD: Reserved
407 * Safe to expose
408 */
409 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
410 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
411
412 /* Cpuid 4:
413 * Intel: Deterministic Cache Parameters Leaf
414 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
415 * AMD: Reserved
416 * Safe to expose, except for EAX:
417 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
418 * Bits 31-26: Maximum number of processor cores in this physical package**
419 * @Note These SMP values are constant regardless of ECX
420 */
421 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
422 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
423#ifdef VBOX_WITH_MULTI_CORE
424 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_INTEL)
425 {
426 /* One logical processor with possibly multiple cores. */
427 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCPUs - 1) << 26); /* 6 bits only -> 64 cores! */
428 }
429#endif
430
431 /* Cpuid 5: Monitor/mwait Leaf
432 * Intel: ECX, EDX - reserved
433 * EAX, EBX - Smallest and largest monitor line size
434 * AMD: EDX - reserved
435 * EAX, EBX - Smallest and largest monitor line size
436 * ECX - extensions (ignored for now)
437 * Safe to expose
438 */
439 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
440 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
441
442 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
443
444 /*
445 * Determine the default.
446 *
447 * Intel returns values of the highest standard function, while AMD
448 * returns zeros. VIA on the other hand seems to returning nothing or
449 * perhaps some random garbage, we don't try to duplicate this behavior.
450 */
451 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
452 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
453 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
454
455 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
456 * Safe to pass on to the guest.
457 *
458 * Intel: 0x800000005 reserved
459 * 0x800000006 L2 cache information
460 * AMD: 0x800000005 L1 cache information
461 * 0x800000006 L2/L3 cache information
462 */
463
464 /* Cpuid 0x800000007:
465 * AMD: EAX, EBX, ECX - reserved
466 * EDX: Advanced Power Management Information
467 * Intel: Reserved
468 */
469 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
470 {
471 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
472
473 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
474
475 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
476 {
477 /* Only expose the TSC invariant capability bit to the guest. */
478 pCPUM->aGuestCpuIdExt[7].edx &= 0
479 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
480 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
481 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
482 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
483 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
484 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
485 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
486 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
487 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
488 | 0;
489 }
490 else
491 pCPUM->aGuestCpuIdExt[7].edx = 0;
492 }
493
494 /* Cpuid 0x800000008:
495 * AMD: EBX, EDX - reserved
496 * EAX: Virtual/Physical address Size
497 * ECX: Number of cores + APICIdCoreIdSize
498 * Intel: EAX: Virtual/Physical address Size
499 * EBX, ECX, EDX - reserved
500 */
501 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
502 {
503 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
504 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
505 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
506 * NC (0-7) Number of cores; 0 equals 1 core */
507 pCPUM->aGuestCpuIdExt[8].ecx = 0;
508#ifdef VBOX_WITH_MULTI_CORE
509 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
510 {
511
512 }
513#endif
514 }
515
516 /*
517 * Limit it the number of entries and fill the remaining with the defaults.
518 *
519 * The limits are masking off stuff about power saving and similar, this
520 * is perhaps a bit crudely done as there is probably some relatively harmless
521 * info too in these leaves (like words about having a constant TSC).
522 */
523#if 0
524 /** @todo NT4 installation regression - investigate */
525 /** Note from Intel manuals:
526 * CPUID leaves > 3 < 80000000 are visible only when
527 * IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default).
528 *
529 */
530 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
531 pCPUM->aGuestCpuIdStd[0].eax = 5;
532#else
533 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
534 pCPUM->aGuestCpuIdStd[0].eax = 2;
535#endif
536 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
537 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
538
539 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
540 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
541 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
542 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
543 : 0;
544 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
545 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
546
547 /*
548 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
549 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
550 * We currently don't support more than 1 processor.
551 */
552 pCPUM->aGuestCpuIdStd[4].eax = 0;
553
554 /*
555 * Centaur stuff (VIA).
556 *
557 * The important part here (we think) is to make sure the 0xc0000000
558 * function returns 0xc0000001. As for the features, we don't currently
559 * let on about any of those... 0xc0000002 seems to be some
560 * temperature/hz/++ stuff, include it as well (static).
561 */
562 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
563 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
564 {
565 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
566 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
567 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
568 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
569 i++)
570 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
571 }
572 else
573 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
574 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
575
576
577 /*
578 * Load CPUID overrides from configuration.
579 */
580 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
581 * Overloads the CPUID leaf values. */
582 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
583 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
584 for (i=0;; )
585 {
586 while (cElements-- > 0)
587 {
588 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
589 if (pNode)
590 {
591 uint32_t u32;
592 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
593 if (RT_SUCCESS(rc))
594 pCpuId->eax = u32;
595 else
596 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
597
598 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
599 if (RT_SUCCESS(rc))
600 pCpuId->ebx = u32;
601 else
602 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
603
604 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
605 if (RT_SUCCESS(rc))
606 pCpuId->ecx = u32;
607 else
608 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
609
610 rc = CFGMR3QueryU32(pNode, "edx", &u32);
611 if (RT_SUCCESS(rc))
612 pCpuId->edx = u32;
613 else
614 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
615 }
616 pCpuId++;
617 i++;
618 }
619
620 /* next */
621 if ((i & UINT32_C(0xc0000000)) == 0)
622 {
623 pCpuId = &pCPUM->aGuestCpuIdExt[0];
624 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
625 i = UINT32_C(0x80000000);
626 }
627 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
628 {
629 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
630 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
631 i = UINT32_C(0xc0000000);
632 }
633 else
634 break;
635 }
636
637 /* Check if PAE was explicitely enabled by the user. */
638 bool fEnable = false;
639 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
640 if (RT_SUCCESS(rc) && fEnable)
641 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
642
643 /*
644 * Log the cpuid and we're good.
645 */
646 RTCPUSET OnlineSet;
647 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
648 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
649 LogRel(("************************* CPUID dump ************************\n"));
650 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
651 LogRel(("\n"));
652 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
653 LogRel(("******************** End of CPUID dump **********************\n"));
654 return VINF_SUCCESS;
655}
656
657
658
659
660/**
661 * Applies relocations to data and code managed by this
662 * component. This function will be called at init and
663 * whenever the VMM need to relocate it self inside the GC.
664 *
665 * The CPUM will update the addresses used by the switcher.
666 *
667 * @param pVM The VM.
668 */
669VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
670{
671 LogFlow(("CPUMR3Relocate\n"));
672 for (unsigned i=0;i<pVM->cCPUs;i++)
673 {
674 PVMCPU pVCpu = &pVM->aCpus[i];
675 /*
676 * Switcher pointers.
677 */
678 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
679 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
680 }
681}
682
683
684/**
685 * Terminates the CPUM.
686 *
687 * Termination means cleaning up and freeing all resources,
688 * the VM it self is at this point powered off or suspended.
689 *
690 * @returns VBox status code.
691 * @param pVM The VM to operate on.
692 */
693VMMR3DECL(int) CPUMR3Term(PVM pVM)
694{
695 CPUMR3TermCPU(pVM);
696 return 0;
697}
698
699
700/**
701 * Terminates the per-VCPU CPUM.
702 *
703 * Termination means cleaning up and freeing all resources,
704 * the VM it self is at this point powered off or suspended.
705 *
706 * @returns VBox status code.
707 * @param pVM The VM to operate on.
708 */
709VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
710{
711#ifdef VBOX_WITH_CRASHDUMP_MAGIC
712 for (unsigned i=0;i<pVM->cCPUs;i++)
713 {
714 PVMCPU pVCpu = &pVM->aCpus[i];
715 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
716
717 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
718 pVCpu->cpum.s.uMagic = 0;
719 pCtx->dr[5] = 0;
720 }
721#endif
722 return 0;
723}
724
725VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
726{
727 /* @todo anything different for VCPU > 0? */
728 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
729
730 /*
731 * Initialize everything to ZERO first.
732 */
733 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
734 memset(pCtx, 0, sizeof(*pCtx));
735 pVCpu->cpum.s.fUseFlags = fUseFlags;
736
737 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
738 pCtx->eip = 0x0000fff0;
739 pCtx->edx = 0x00000600; /* P6 processor */
740 pCtx->eflags.Bits.u1Reserved0 = 1;
741
742 pCtx->cs = 0xf000;
743 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
744 pCtx->csHid.u32Limit = 0x0000ffff;
745 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
746 pCtx->csHid.Attr.n.u1Present = 1;
747 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
748
749 pCtx->dsHid.u32Limit = 0x0000ffff;
750 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
751 pCtx->dsHid.Attr.n.u1Present = 1;
752 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
753
754 pCtx->esHid.u32Limit = 0x0000ffff;
755 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
756 pCtx->esHid.Attr.n.u1Present = 1;
757 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
758
759 pCtx->fsHid.u32Limit = 0x0000ffff;
760 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
761 pCtx->fsHid.Attr.n.u1Present = 1;
762 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
763
764 pCtx->gsHid.u32Limit = 0x0000ffff;
765 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
766 pCtx->gsHid.Attr.n.u1Present = 1;
767 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
768
769 pCtx->ssHid.u32Limit = 0x0000ffff;
770 pCtx->ssHid.Attr.n.u1Present = 1;
771 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
772 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
773
774 pCtx->idtr.cbIdt = 0xffff;
775 pCtx->gdtr.cbGdt = 0xffff;
776
777 pCtx->ldtrHid.u32Limit = 0xffff;
778 pCtx->ldtrHid.Attr.n.u1Present = 1;
779 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
780
781 pCtx->trHid.u32Limit = 0xffff;
782 pCtx->trHid.Attr.n.u1Present = 1;
783 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
784
785 pCtx->dr[6] = X86_DR6_INIT_VAL;
786 pCtx->dr[7] = X86_DR7_INIT_VAL;
787
788 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
789 pCtx->fpu.FCW = 0x37f;
790
791 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
792 pCtx->fpu.MXCSR = 0x1F80;
793
794 /* Init PAT MSR */
795 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
796
797 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
798 * The Intel docs don't mention it.
799 */
800 pCtx->msrEFER = 0;
801}
802
803/**
804 * Resets the CPU.
805 *
806 * @returns VINF_SUCCESS.
807 * @param pVM The VM handle.
808 */
809VMMR3DECL(void) CPUMR3Reset(PVM pVM)
810{
811 for (unsigned i=0;i<pVM->cCPUs;i++)
812 {
813 CPUMR3ResetCpu(&pVM->aCpus[i]);
814
815#ifdef VBOX_WITH_CRASHDUMP_MAGIC
816 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
817
818 /* Magic marker for searching in crash dumps. */
819 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
820 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
821 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
822#endif
823 }
824}
825
826
827/**
828 * Execute state save operation.
829 *
830 * @returns VBox status code.
831 * @param pVM VM Handle.
832 * @param pSSM SSM operation handle.
833 */
834static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
835{
836 /*
837 * Save.
838 */
839 for (unsigned i=0;i<pVM->cCPUs;i++)
840 {
841 PVMCPU pVCpu = &pVM->aCpus[i];
842
843 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
844 }
845
846 SSMR3PutU32(pSSM, pVM->cCPUs);
847 for (unsigned i=0;i<pVM->cCPUs;i++)
848 {
849 PVMCPU pVCpu = &pVM->aCpus[i];
850
851 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
852 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
853 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
854 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
855 }
856
857 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
858 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
859
860 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
861 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
862
863 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
864 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
865
866 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
867
868 /* Add the cpuid for checking that the cpu is unchanged. */
869 uint32_t au32CpuId[8] = {0};
870 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
871 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
872 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
873}
874
875
876/**
877 * Load a version 1.6 CPUMCTX structure.
878 *
879 * @returns VBox status code.
880 * @param pVM VM Handle.
881 * @param pCpumctx16 Version 1.6 CPUMCTX
882 */
883static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
884{
885#define CPUMCTX16_LOADREG(RegName) \
886 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
887
888#define CPUMCTX16_LOADDRXREG(RegName) \
889 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
890
891#define CPUMCTX16_LOADHIDREG(RegName) \
892 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
893 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
894 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
895
896#define CPUMCTX16_LOADSEGREG(RegName) \
897 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
898 CPUMCTX16_LOADHIDREG(RegName);
899
900 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
901
902 CPUMCTX16_LOADREG(rax);
903 CPUMCTX16_LOADREG(rbx);
904 CPUMCTX16_LOADREG(rcx);
905 CPUMCTX16_LOADREG(rdx);
906 CPUMCTX16_LOADREG(rdi);
907 CPUMCTX16_LOADREG(rsi);
908 CPUMCTX16_LOADREG(rbp);
909 CPUMCTX16_LOADREG(esp);
910 CPUMCTX16_LOADREG(rip);
911 CPUMCTX16_LOADREG(rflags);
912
913 CPUMCTX16_LOADSEGREG(cs);
914 CPUMCTX16_LOADSEGREG(ds);
915 CPUMCTX16_LOADSEGREG(es);
916 CPUMCTX16_LOADSEGREG(fs);
917 CPUMCTX16_LOADSEGREG(gs);
918 CPUMCTX16_LOADSEGREG(ss);
919
920 CPUMCTX16_LOADREG(r8);
921 CPUMCTX16_LOADREG(r9);
922 CPUMCTX16_LOADREG(r10);
923 CPUMCTX16_LOADREG(r11);
924 CPUMCTX16_LOADREG(r12);
925 CPUMCTX16_LOADREG(r13);
926 CPUMCTX16_LOADREG(r14);
927 CPUMCTX16_LOADREG(r15);
928
929 CPUMCTX16_LOADREG(cr0);
930 CPUMCTX16_LOADREG(cr2);
931 CPUMCTX16_LOADREG(cr3);
932 CPUMCTX16_LOADREG(cr4);
933
934 CPUMCTX16_LOADDRXREG(0);
935 CPUMCTX16_LOADDRXREG(1);
936 CPUMCTX16_LOADDRXREG(2);
937 CPUMCTX16_LOADDRXREG(3);
938 CPUMCTX16_LOADDRXREG(4);
939 CPUMCTX16_LOADDRXREG(5);
940 CPUMCTX16_LOADDRXREG(6);
941 CPUMCTX16_LOADDRXREG(7);
942
943 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
944 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
945 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
946 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
947
948 CPUMCTX16_LOADREG(ldtr);
949 CPUMCTX16_LOADREG(tr);
950
951 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
952
953 CPUMCTX16_LOADREG(msrEFER);
954 CPUMCTX16_LOADREG(msrSTAR);
955 CPUMCTX16_LOADREG(msrPAT);
956 CPUMCTX16_LOADREG(msrLSTAR);
957 CPUMCTX16_LOADREG(msrCSTAR);
958 CPUMCTX16_LOADREG(msrSFMASK);
959 CPUMCTX16_LOADREG(msrKERNELGSBASE);
960
961 CPUMCTX16_LOADHIDREG(ldtr);
962 CPUMCTX16_LOADHIDREG(tr);
963
964#undef CPUMCTX16_LOADSEGREG
965#undef CPUMCTX16_LOADHIDREG
966#undef CPUMCTX16_LOADDRXREG
967#undef CPUMCTX16_LOADREG
968}
969
970
971/**
972 * Execute state load operation.
973 *
974 * @returns VBox status code.
975 * @param pVM VM Handle.
976 * @param pSSM SSM operation handle.
977 * @param u32Version Data layout version.
978 */
979static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
980{
981 /*
982 * Validate version.
983 */
984 if ( u32Version != CPUM_SAVED_STATE_VERSION
985 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
986 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
987 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
988 {
989 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
990 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
991 }
992
993 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
994 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
995 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
996 else if (u32Version <= CPUM_SAVED_STATE_VERSION)
997 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
998
999 /*
1000 * Restore.
1001 */
1002 for (unsigned i=0;i<pVM->cCPUs;i++)
1003 {
1004 PVMCPU pVCpu = &pVM->aCpus[i];
1005 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1006 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1007
1008 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1009 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1010 pVCpu->cpum.s.Hyper.esp = uESP;
1011 }
1012
1013 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1014 {
1015 CPUMCTX_VER1_6 cpumctx16;
1016 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1017 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1018
1019 /* Save the old cpumctx state into the new one. */
1020 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1021
1022 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1023 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1024 }
1025 else
1026 {
1027 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1028 {
1029 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
1030 AssertRCReturn(rc, rc);
1031 }
1032
1033 if ( !pVM->cCPUs
1034 || pVM->cCPUs > VMM_MAX_CPU_COUNT
1035 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
1036 && pVM->cCPUs != 1))
1037 {
1038 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
1039 return VERR_SSM_UNEXPECTED_DATA;
1040 }
1041
1042 for (unsigned i=0;i<pVM->cCPUs;i++)
1043 {
1044 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1045 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1046 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1047 if (u32Version == CPUM_SAVED_STATE_VERSION)
1048 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1049 }
1050 }
1051
1052
1053 uint32_t cElements;
1054 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1055 /* Support old saved states with a smaller standard cpuid array. */
1056 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1057 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1058 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1059
1060 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1061 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1062 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1063 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1064
1065 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1066 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1067 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1068 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1069
1070 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1071
1072 /*
1073 * Check that the basic cpuid id information is unchanged.
1074 * @todo we should check the 64 bits capabilities too!
1075 */
1076 uint32_t au32CpuId[8] = {0};
1077 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1078 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1079 uint32_t au32CpuIdSaved[8];
1080 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1081 if (RT_SUCCESS(rc))
1082 {
1083 /* Ignore CPU stepping. */
1084 au32CpuId[4] &= 0xfffffff0;
1085 au32CpuIdSaved[4] &= 0xfffffff0;
1086
1087 /* Ignore APIC ID (AMD specs). */
1088 au32CpuId[5] &= ~0xff000000;
1089 au32CpuIdSaved[5] &= ~0xff000000;
1090
1091 /* Ignore the number of Logical CPUs (AMD specs). */
1092 au32CpuId[5] &= ~0x00ff0000;
1093 au32CpuIdSaved[5] &= ~0x00ff0000;
1094
1095 /* do the compare */
1096 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1097 {
1098 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1099 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1100 "Saved=%.*Rhxs\n"
1101 "Real =%.*Rhxs\n",
1102 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1103 sizeof(au32CpuId), au32CpuId));
1104 else
1105 {
1106 LogRel(("cpumR3Load: CpuId mismatch!\n"
1107 "Saved=%.*Rhxs\n"
1108 "Real =%.*Rhxs\n",
1109 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1110 sizeof(au32CpuId), au32CpuId));
1111 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1112 }
1113 }
1114 }
1115
1116 return rc;
1117}
1118
1119
1120/**
1121 * Formats the EFLAGS value into mnemonics.
1122 *
1123 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1124 * @param efl The EFLAGS value.
1125 */
1126static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1127{
1128 /*
1129 * Format the flags.
1130 */
1131 static const struct
1132 {
1133 const char *pszSet; const char *pszClear; uint32_t fFlag;
1134 } s_aFlags[] =
1135 {
1136 { "vip",NULL, X86_EFL_VIP },
1137 { "vif",NULL, X86_EFL_VIF },
1138 { "ac", NULL, X86_EFL_AC },
1139 { "vm", NULL, X86_EFL_VM },
1140 { "rf", NULL, X86_EFL_RF },
1141 { "nt", NULL, X86_EFL_NT },
1142 { "ov", "nv", X86_EFL_OF },
1143 { "dn", "up", X86_EFL_DF },
1144 { "ei", "di", X86_EFL_IF },
1145 { "tf", NULL, X86_EFL_TF },
1146 { "nt", "pl", X86_EFL_SF },
1147 { "nz", "zr", X86_EFL_ZF },
1148 { "ac", "na", X86_EFL_AF },
1149 { "po", "pe", X86_EFL_PF },
1150 { "cy", "nc", X86_EFL_CF },
1151 };
1152 char *psz = pszEFlags;
1153 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1154 {
1155 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1156 if (pszAdd)
1157 {
1158 strcpy(psz, pszAdd);
1159 psz += strlen(pszAdd);
1160 *psz++ = ' ';
1161 }
1162 }
1163 psz[-1] = '\0';
1164}
1165
1166
1167/**
1168 * Formats a full register dump.
1169 *
1170 * @param pVM VM Handle.
1171 * @param pCtx The context to format.
1172 * @param pCtxCore The context core to format.
1173 * @param pHlp Output functions.
1174 * @param enmType The dump type.
1175 * @param pszPrefix Register name prefix.
1176 */
1177static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1178{
1179 /*
1180 * Format the EFLAGS.
1181 */
1182 uint32_t efl = pCtxCore->eflags.u32;
1183 char szEFlags[80];
1184 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1185
1186 /*
1187 * Format the registers.
1188 */
1189 switch (enmType)
1190 {
1191 case CPUMDUMPTYPE_TERSE:
1192 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1193 pHlp->pfnPrintf(pHlp,
1194 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1195 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1196 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1197 "%sr14=%016RX64 %sr15=%016RX64\n"
1198 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1199 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1200 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1201 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1202 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1203 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1204 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1205 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1206 else
1207 pHlp->pfnPrintf(pHlp,
1208 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1209 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1210 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1211 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1212 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1213 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1214 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1215 break;
1216
1217 case CPUMDUMPTYPE_DEFAULT:
1218 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1219 pHlp->pfnPrintf(pHlp,
1220 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1221 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1222 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1223 "%sr14=%016RX64 %sr15=%016RX64\n"
1224 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1225 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1226 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1227 ,
1228 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1229 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1230 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1231 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1232 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1233 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1234 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1235 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1236 else
1237 pHlp->pfnPrintf(pHlp,
1238 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1239 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1240 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1241 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1242 ,
1243 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1244 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1245 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1246 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1247 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1248 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1249 break;
1250
1251 case CPUMDUMPTYPE_VERBOSE:
1252 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1253 pHlp->pfnPrintf(pHlp,
1254 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1255 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1256 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1257 "%sr14=%016RX64 %sr15=%016RX64\n"
1258 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1259 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1260 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1261 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1262 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1263 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1264 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1265 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1266 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1267 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1268 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1269 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1270 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1271 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1272 ,
1273 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1274 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1275 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1276 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1277 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1278 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1279 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1280 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1281 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1282 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1283 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1284 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1285 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1286 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1287 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1288 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1289 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1290 else
1291 pHlp->pfnPrintf(pHlp,
1292 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1293 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1294 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1295 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1296 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1297 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1298 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1299 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1300 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1301 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1302 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1303 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1304 ,
1305 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1306 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1307 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1308 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1309 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1310 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1311 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1312 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1313 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1314 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1315 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1316 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1317
1318 pHlp->pfnPrintf(pHlp,
1319 "FPU:\n"
1320 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1321 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1322 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1323 ,
1324 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1325 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1326 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1327 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1328
1329 pHlp->pfnPrintf(pHlp,
1330 "MSR:\n"
1331 "%sEFER =%016RX64\n"
1332 "%sPAT =%016RX64\n"
1333 "%sSTAR =%016RX64\n"
1334 "%sCSTAR =%016RX64\n"
1335 "%sLSTAR =%016RX64\n"
1336 "%sSFMASK =%016RX64\n"
1337 "%sKERNELGSBASE =%016RX64\n",
1338 pszPrefix, pCtx->msrEFER,
1339 pszPrefix, pCtx->msrPAT,
1340 pszPrefix, pCtx->msrSTAR,
1341 pszPrefix, pCtx->msrCSTAR,
1342 pszPrefix, pCtx->msrLSTAR,
1343 pszPrefix, pCtx->msrSFMASK,
1344 pszPrefix, pCtx->msrKERNELGSBASE);
1345 break;
1346 }
1347}
1348
1349
1350/**
1351 * Display all cpu states and any other cpum info.
1352 *
1353 * @param pVM VM Handle.
1354 * @param pHlp The info helper functions.
1355 * @param pszArgs Arguments, ignored.
1356 */
1357static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1358{
1359 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1360 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1361 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1362 cpumR3InfoHost(pVM, pHlp, pszArgs);
1363}
1364
1365
1366/**
1367 * Parses the info argument.
1368 *
1369 * The argument starts with 'verbose', 'terse' or 'default' and then
1370 * continues with the comment string.
1371 *
1372 * @param pszArgs The pointer to the argument string.
1373 * @param penmType Where to store the dump type request.
1374 * @param ppszComment Where to store the pointer to the comment string.
1375 */
1376static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1377{
1378 if (!pszArgs)
1379 {
1380 *penmType = CPUMDUMPTYPE_DEFAULT;
1381 *ppszComment = "";
1382 }
1383 else
1384 {
1385 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1386 {
1387 pszArgs += 5;
1388 *penmType = CPUMDUMPTYPE_VERBOSE;
1389 }
1390 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1391 {
1392 pszArgs += 5;
1393 *penmType = CPUMDUMPTYPE_TERSE;
1394 }
1395 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1396 {
1397 pszArgs += 7;
1398 *penmType = CPUMDUMPTYPE_DEFAULT;
1399 }
1400 else
1401 *penmType = CPUMDUMPTYPE_DEFAULT;
1402 *ppszComment = RTStrStripL(pszArgs);
1403 }
1404}
1405
1406
1407/**
1408 * Display the guest cpu state.
1409 *
1410 * @param pVM VM Handle.
1411 * @param pHlp The info helper functions.
1412 * @param pszArgs Arguments, ignored.
1413 */
1414static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1415{
1416 CPUMDUMPTYPE enmType;
1417 const char *pszComment;
1418 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1419
1420 /* @todo SMP support! */
1421 PVMCPU pVCpu = VMMGetCpu(pVM);
1422 if (!pVCpu)
1423 pVCpu = &pVM->aCpus[0];
1424
1425 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1426
1427 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1428 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1429}
1430
1431
1432/**
1433 * Display the current guest instruction
1434 *
1435 * @param pVM VM Handle.
1436 * @param pHlp The info helper functions.
1437 * @param pszArgs Arguments, ignored.
1438 */
1439static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1440{
1441 char szInstruction[256];
1442 /* @todo SMP support! */
1443 PVMCPU pVCpu = VMMGetCpu(pVM);
1444 if (!pVCpu)
1445 pVCpu = &pVM->aCpus[0];
1446
1447 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1448 if (RT_SUCCESS(rc))
1449 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1450}
1451
1452
1453/**
1454 * Display the hypervisor cpu state.
1455 *
1456 * @param pVM VM Handle.
1457 * @param pHlp The info helper functions.
1458 * @param pszArgs Arguments, ignored.
1459 */
1460static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1461{
1462 CPUMDUMPTYPE enmType;
1463 const char *pszComment;
1464 /* @todo SMP */
1465 PVMCPU pVCpu = &pVM->aCpus[0];
1466
1467 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1468 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1469 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1470 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1471}
1472
1473
1474/**
1475 * Display the host cpu state.
1476 *
1477 * @param pVM VM Handle.
1478 * @param pHlp The info helper functions.
1479 * @param pszArgs Arguments, ignored.
1480 */
1481static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1482{
1483 CPUMDUMPTYPE enmType;
1484 const char *pszComment;
1485 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1486 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1487
1488 /*
1489 * Format the EFLAGS.
1490 */
1491 /* @todo SMP */
1492 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1493#if HC_ARCH_BITS == 32
1494 uint32_t efl = pCtx->eflags.u32;
1495#else
1496 uint64_t efl = pCtx->rflags;
1497#endif
1498 char szEFlags[80];
1499 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1500
1501 /*
1502 * Format the registers.
1503 */
1504#if HC_ARCH_BITS == 32
1505# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1506 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1507# endif
1508 {
1509 pHlp->pfnPrintf(pHlp,
1510 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1511 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1512 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1513 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1514 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1515 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1516 ,
1517 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1518 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1519 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1520 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1521 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1522 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1523 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1524 }
1525# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1526 else
1527# endif
1528#endif
1529#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1530 {
1531 pHlp->pfnPrintf(pHlp,
1532 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1533 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1534 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1535 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1536 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1537 "r14=%016RX64 r15=%016RX64\n"
1538 "iopl=%d %31s\n"
1539 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1540 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1541 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1542 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1543 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1544 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1545 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1546 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1547 ,
1548 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1549 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1550 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1551 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1552 pCtx->r11, pCtx->r12, pCtx->r13,
1553 pCtx->r14, pCtx->r15,
1554 X86_EFL_GET_IOPL(efl), szEFlags,
1555 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1556 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1557 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1558 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1559 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1560 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1561 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1562 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1563 }
1564#endif
1565}
1566
1567
1568/**
1569 * Get L1 cache / TLS associativity.
1570 */
1571static const char *getCacheAss(unsigned u, char *pszBuf)
1572{
1573 if (u == 0)
1574 return "res0 ";
1575 if (u == 1)
1576 return "direct";
1577 if (u >= 256)
1578 return "???";
1579
1580 RTStrPrintf(pszBuf, 16, "%d way", u);
1581 return pszBuf;
1582}
1583
1584
1585/**
1586 * Get L2 cache soociativity.
1587 */
1588const char *getL2CacheAss(unsigned u)
1589{
1590 switch (u)
1591 {
1592 case 0: return "off ";
1593 case 1: return "direct";
1594 case 2: return "2 way ";
1595 case 3: return "res3 ";
1596 case 4: return "4 way ";
1597 case 5: return "res5 ";
1598 case 6: return "8 way "; case 7: return "res7 ";
1599 case 8: return "16 way";
1600 case 9: return "res9 ";
1601 case 10: return "res10 ";
1602 case 11: return "res11 ";
1603 case 12: return "res12 ";
1604 case 13: return "res13 ";
1605 case 14: return "res14 ";
1606 case 15: return "fully ";
1607 default:
1608 return "????";
1609 }
1610}
1611
1612
1613/**
1614 * Display the guest CpuId leaves.
1615 *
1616 * @param pVM VM Handle.
1617 * @param pHlp The info helper functions.
1618 * @param pszArgs "terse", "default" or "verbose".
1619 */
1620static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1621{
1622 /*
1623 * Parse the argument.
1624 */
1625 unsigned iVerbosity = 1;
1626 if (pszArgs)
1627 {
1628 pszArgs = RTStrStripL(pszArgs);
1629 if (!strcmp(pszArgs, "terse"))
1630 iVerbosity--;
1631 else if (!strcmp(pszArgs, "verbose"))
1632 iVerbosity++;
1633 }
1634
1635 /*
1636 * Start cracking.
1637 */
1638 CPUMCPUID Host;
1639 CPUMCPUID Guest;
1640 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1641
1642 pHlp->pfnPrintf(pHlp,
1643 " RAW Standard CPUIDs\n"
1644 " Function eax ebx ecx edx\n");
1645 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1646 {
1647 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1648 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1649
1650 pHlp->pfnPrintf(pHlp,
1651 "Gst: %08x %08x %08x %08x %08x%s\n"
1652 "Hst: %08x %08x %08x %08x\n",
1653 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1654 i <= cStdMax ? "" : "*",
1655 Host.eax, Host.ebx, Host.ecx, Host.edx);
1656 }
1657
1658 /*
1659 * If verbose, decode it.
1660 */
1661 if (iVerbosity)
1662 {
1663 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1664 pHlp->pfnPrintf(pHlp,
1665 "Name: %.04s%.04s%.04s\n"
1666 "Supports: 0-%x\n",
1667 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1668 }
1669
1670 /*
1671 * Get Features.
1672 */
1673 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1674 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1675 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1676 if (cStdMax >= 1 && iVerbosity)
1677 {
1678 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1679 uint32_t uEAX = Guest.eax;
1680
1681 pHlp->pfnPrintf(pHlp,
1682 "Family: %d \tExtended: %d \tEffective: %d\n"
1683 "Model: %d \tExtended: %d \tEffective: %d\n"
1684 "Stepping: %d\n"
1685 "APIC ID: %#04x\n"
1686 "Logical CPUs: %d\n"
1687 "CLFLUSH Size: %d\n"
1688 "Brand ID: %#04x\n",
1689 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1690 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1691 ASMGetCpuStepping(uEAX),
1692 (Guest.ebx >> 24) & 0xff,
1693 (Guest.ebx >> 16) & 0xff,
1694 (Guest.ebx >> 8) & 0xff,
1695 (Guest.ebx >> 0) & 0xff);
1696 if (iVerbosity == 1)
1697 {
1698 uint32_t uEDX = Guest.edx;
1699 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1700 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1701 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1702 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1703 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1704 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1705 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1706 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1707 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1708 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1709 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1710 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1711 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1712 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1713 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1714 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1715 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1716 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1717 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1718 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1719 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1720 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1721 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1722 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1723 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1724 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1725 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1726 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1727 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1728 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1729 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1730 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1731 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1732 pHlp->pfnPrintf(pHlp, "\n");
1733
1734 uint32_t uECX = Guest.ecx;
1735 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1736 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1737 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1738 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1739 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1740 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1741 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1742 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1743 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1744 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1745 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1746 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1747 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1748 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1749 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1750 for (unsigned iBit = 14; iBit < 32; iBit++)
1751 if (uECX & RT_BIT(iBit))
1752 pHlp->pfnPrintf(pHlp, " %d", iBit);
1753 pHlp->pfnPrintf(pHlp, "\n");
1754 }
1755 else
1756 {
1757 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1758
1759 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1760 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1761 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1762 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1763
1764 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1765 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1766 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1767 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1768 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1769 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1770 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1771 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1772 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1773 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1774 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1775 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1776 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1777 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1778 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1779 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1780 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1781 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1782 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1783 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1784 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1785 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1786 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1787 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1788 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1789 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1790 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1791 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1792 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1793 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1794 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1795 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1796 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1797
1798 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1799 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1800 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1801 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1802 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1803 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1804 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1805 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1806 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1807 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1808 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1809 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1810 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1811 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1812 }
1813 }
1814 if (cStdMax >= 2 && iVerbosity)
1815 {
1816 /** @todo */
1817 }
1818
1819 /*
1820 * Extended.
1821 * Implemented after AMD specs.
1822 */
1823 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1824
1825 pHlp->pfnPrintf(pHlp,
1826 "\n"
1827 " RAW Extended CPUIDs\n"
1828 " Function eax ebx ecx edx\n");
1829 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1830 {
1831 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1832 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1833
1834 pHlp->pfnPrintf(pHlp,
1835 "Gst: %08x %08x %08x %08x %08x%s\n"
1836 "Hst: %08x %08x %08x %08x\n",
1837 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1838 i <= cExtMax ? "" : "*",
1839 Host.eax, Host.ebx, Host.ecx, Host.edx);
1840 }
1841
1842 /*
1843 * Understandable output
1844 */
1845 if (iVerbosity)
1846 {
1847 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1848 pHlp->pfnPrintf(pHlp,
1849 "Ext Name: %.4s%.4s%.4s\n"
1850 "Ext Supports: 0x80000000-%#010x\n",
1851 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1852 }
1853
1854 if (iVerbosity && cExtMax >= 1)
1855 {
1856 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1857 uint32_t uEAX = Guest.eax;
1858 pHlp->pfnPrintf(pHlp,
1859 "Family: %d \tExtended: %d \tEffective: %d\n"
1860 "Model: %d \tExtended: %d \tEffective: %d\n"
1861 "Stepping: %d\n"
1862 "Brand ID: %#05x\n",
1863 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1864 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1865 ASMGetCpuStepping(uEAX),
1866 Guest.ebx & 0xfff);
1867
1868 if (iVerbosity == 1)
1869 {
1870 uint32_t uEDX = Guest.edx;
1871 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1872 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1873 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1874 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1875 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1876 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1877 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1878 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1879 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1880 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1881 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1882 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1883 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1884 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1885 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1886 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1887 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1888 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1889 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1890 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1891 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1892 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1893 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1894 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1895 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1896 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1897 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1898 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1899 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1900 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1901 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1902 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1903 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1904 pHlp->pfnPrintf(pHlp, "\n");
1905
1906 uint32_t uECX = Guest.ecx;
1907 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1908 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1909 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1910 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1911 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1912 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1913 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1914 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1915 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1916 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1917 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1918 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1919 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1920 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1921 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1922 for (unsigned iBit = 5; iBit < 32; iBit++)
1923 if (uECX & RT_BIT(iBit))
1924 pHlp->pfnPrintf(pHlp, " %d", iBit);
1925 pHlp->pfnPrintf(pHlp, "\n");
1926 }
1927 else
1928 {
1929 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1930
1931 uint32_t uEdxGst = Guest.edx;
1932 uint32_t uEdxHst = Host.edx;
1933 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1934 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1935 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1936 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1937 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1938 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1939 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1940 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1941 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1942 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1943 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1944 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1945 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1946 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1947 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1948 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1949 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1950 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1951 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1952 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1953 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1954 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1955 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1956 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1957 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1958 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1959 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1960 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1961 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1962 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1963 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1964 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1965 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1966
1967 uint32_t uEcxGst = Guest.ecx;
1968 uint32_t uEcxHst = Host.ecx;
1969 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1970 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1971 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1972 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1973 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1974 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1975 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1976 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1977 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1978 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1979 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1980 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1981 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1982 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1983 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1984 }
1985 }
1986
1987 if (iVerbosity && cExtMax >= 2)
1988 {
1989 char szString[4*4*3+1] = {0};
1990 uint32_t *pu32 = (uint32_t *)szString;
1991 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1992 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1993 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1994 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1995 if (cExtMax >= 3)
1996 {
1997 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1998 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1999 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2000 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2001 }
2002 if (cExtMax >= 4)
2003 {
2004 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2005 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2006 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2007 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2008 }
2009 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2010 }
2011
2012 if (iVerbosity && cExtMax >= 5)
2013 {
2014 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2015 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2016 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2017 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2018 char sz1[32];
2019 char sz2[32];
2020
2021 pHlp->pfnPrintf(pHlp,
2022 "TLB 2/4M Instr/Uni: %s %3d entries\n"
2023 "TLB 2/4M Data: %s %3d entries\n",
2024 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2025 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2026 pHlp->pfnPrintf(pHlp,
2027 "TLB 4K Instr/Uni: %s %3d entries\n"
2028 "TLB 4K Data: %s %3d entries\n",
2029 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2030 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2031 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2032 "L1 Instr Cache Lines Per Tag: %d\n"
2033 "L1 Instr Cache Associativity: %s\n"
2034 "L1 Instr Cache Size: %d KB\n",
2035 (uEDX >> 0) & 0xff,
2036 (uEDX >> 8) & 0xff,
2037 getCacheAss((uEDX >> 16) & 0xff, sz1),
2038 (uEDX >> 24) & 0xff);
2039 pHlp->pfnPrintf(pHlp,
2040 "L1 Data Cache Line Size: %d bytes\n"
2041 "L1 Data Cache Lines Per Tag: %d\n"
2042 "L1 Data Cache Associativity: %s\n"
2043 "L1 Data Cache Size: %d KB\n",
2044 (uECX >> 0) & 0xff,
2045 (uECX >> 8) & 0xff,
2046 getCacheAss((uECX >> 16) & 0xff, sz1),
2047 (uECX >> 24) & 0xff);
2048 }
2049
2050 if (iVerbosity && cExtMax >= 6)
2051 {
2052 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2053 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2054 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2055
2056 pHlp->pfnPrintf(pHlp,
2057 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2058 "L2 TLB 2/4M Data: %s %4d entries\n",
2059 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2060 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2061 pHlp->pfnPrintf(pHlp,
2062 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2063 "L2 TLB 4K Data: %s %4d entries\n",
2064 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2065 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2066 pHlp->pfnPrintf(pHlp,
2067 "L2 Cache Line Size: %d bytes\n"
2068 "L2 Cache Lines Per Tag: %d\n"
2069 "L2 Cache Associativity: %s\n"
2070 "L2 Cache Size: %d KB\n",
2071 (uEDX >> 0) & 0xff,
2072 (uEDX >> 8) & 0xf,
2073 getL2CacheAss((uEDX >> 12) & 0xf),
2074 (uEDX >> 16) & 0xffff);
2075 }
2076
2077 if (iVerbosity && cExtMax >= 7)
2078 {
2079 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2080
2081 pHlp->pfnPrintf(pHlp, "APM Features: ");
2082 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2083 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2084 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2085 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2086 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2087 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2088 for (unsigned iBit = 6; iBit < 32; iBit++)
2089 if (uEDX & RT_BIT(iBit))
2090 pHlp->pfnPrintf(pHlp, " %d", iBit);
2091 pHlp->pfnPrintf(pHlp, "\n");
2092 }
2093
2094 if (iVerbosity && cExtMax >= 8)
2095 {
2096 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2097 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2098
2099 pHlp->pfnPrintf(pHlp,
2100 "Physical Address Width: %d bits\n"
2101 "Virtual Address Width: %d bits\n",
2102 (uEAX >> 0) & 0xff,
2103 (uEAX >> 8) & 0xff);
2104 pHlp->pfnPrintf(pHlp,
2105 "Physical Core Count: %d\n",
2106 (uECX >> 0) & 0xff);
2107 }
2108
2109
2110 /*
2111 * Centaur.
2112 */
2113 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2114
2115 pHlp->pfnPrintf(pHlp,
2116 "\n"
2117 " RAW Centaur CPUIDs\n"
2118 " Function eax ebx ecx edx\n");
2119 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2120 {
2121 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2122 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2123
2124 pHlp->pfnPrintf(pHlp,
2125 "Gst: %08x %08x %08x %08x %08x%s\n"
2126 "Hst: %08x %08x %08x %08x\n",
2127 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2128 i <= cCentaurMax ? "" : "*",
2129 Host.eax, Host.ebx, Host.ecx, Host.edx);
2130 }
2131
2132 /*
2133 * Understandable output
2134 */
2135 if (iVerbosity)
2136 {
2137 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2138 pHlp->pfnPrintf(pHlp,
2139 "Centaur Supports: 0xc0000000-%#010x\n",
2140 Guest.eax);
2141 }
2142
2143 if (iVerbosity && cCentaurMax >= 1)
2144 {
2145 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2146 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2147 uint32_t uEdxHst = Host.edx;
2148
2149 if (iVerbosity == 1)
2150 {
2151 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2152 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2153 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2154 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2155 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2156 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2157 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2158 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2159 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2160 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2161 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2162 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2163 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2164 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2165 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2166 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2167 for (unsigned iBit = 14; iBit < 32; iBit++)
2168 if (uEdxGst & RT_BIT(iBit))
2169 pHlp->pfnPrintf(pHlp, " %d", iBit);
2170 pHlp->pfnPrintf(pHlp, "\n");
2171 }
2172 else
2173 {
2174 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2175 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2176 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2177 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2178 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2179 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2180 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2181 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2182 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2183 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2184 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2185 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2186 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2187 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2188 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2189 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2190 for (unsigned iBit = 14; iBit < 32; iBit++)
2191 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2192 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2193 pHlp->pfnPrintf(pHlp, "\n");
2194 }
2195 }
2196}
2197
2198
2199/**
2200 * Structure used when disassembling and instructions in DBGF.
2201 * This is used so the reader function can get the stuff it needs.
2202 */
2203typedef struct CPUMDISASSTATE
2204{
2205 /** Pointer to the CPU structure. */
2206 PDISCPUSTATE pCpu;
2207 /** The VM handle. */
2208 PVM pVM;
2209 /** The VMCPU handle. */
2210 PVMCPU pVCpu;
2211 /** Pointer to the first byte in the segemnt. */
2212 RTGCUINTPTR GCPtrSegBase;
2213 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2214 RTGCUINTPTR GCPtrSegEnd;
2215 /** The size of the segment minus 1. */
2216 RTGCUINTPTR cbSegLimit;
2217 /** Pointer to the current page - R3 Ptr. */
2218 void const *pvPageR3;
2219 /** Pointer to the current page - GC Ptr. */
2220 RTGCPTR pvPageGC;
2221 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2222 PGMPAGEMAPLOCK PageMapLock;
2223 /** Whether the PageMapLock is valid or not. */
2224 bool fLocked;
2225 /** 64 bits mode or not. */
2226 bool f64Bits;
2227} CPUMDISASSTATE, *PCPUMDISASSTATE;
2228
2229
2230/**
2231 * Instruction reader.
2232 *
2233 * @returns VBox status code.
2234 * @param PtrSrc Address to read from.
2235 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2236 * @param pu8Dst Where to store the bytes.
2237 * @param cbRead Number of bytes to read.
2238 * @param uDisCpu Pointer to the disassembler cpu state.
2239 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2240 */
2241static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2242{
2243 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2244 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2245 Assert(cbRead > 0);
2246 for (;;)
2247 {
2248 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2249
2250 /* Need to update the page translation? */
2251 if ( !pState->pvPageR3
2252 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2253 {
2254 int rc = VINF_SUCCESS;
2255
2256 /* translate the address */
2257 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2258 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2259 && !HWACCMIsEnabled(pState->pVM))
2260 {
2261 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2262 if (!pState->pvPageR3)
2263 rc = VERR_INVALID_POINTER;
2264 }
2265 else
2266 {
2267 /* Release mapping lock previously acquired. */
2268 if (pState->fLocked)
2269 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2270 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2271 pState->fLocked = RT_SUCCESS_NP(rc);
2272 }
2273 if (RT_FAILURE(rc))
2274 {
2275 pState->pvPageR3 = NULL;
2276 return rc;
2277 }
2278 }
2279
2280 /* check the segemnt limit */
2281 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2282 return VERR_OUT_OF_SELECTOR_BOUNDS;
2283
2284 /* calc how much we can read */
2285 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2286 if (!pState->f64Bits)
2287 {
2288 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2289 if (cb > cbSeg && cbSeg)
2290 cb = cbSeg;
2291 }
2292 if (cb > cbRead)
2293 cb = cbRead;
2294
2295 /* read and advance */
2296 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2297 cbRead -= cb;
2298 if (!cbRead)
2299 return VINF_SUCCESS;
2300 pu8Dst += cb;
2301 PtrSrc += cb;
2302 }
2303}
2304
2305
2306/**
2307 * Disassemble an instruction and return the information in the provided structure.
2308 *
2309 * @returns VBox status code.
2310 * @param pVM VM Handle
2311 * @param pVCpu VMCPU Handle
2312 * @param pCtx CPU context
2313 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2314 * @param pCpu Disassembly state
2315 * @param pszPrefix String prefix for logging (debug only)
2316 *
2317 */
2318VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2319{
2320 CPUMDISASSTATE State;
2321 int rc;
2322
2323 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2324 State.pCpu = pCpu;
2325 State.pvPageGC = 0;
2326 State.pvPageR3 = NULL;
2327 State.pVM = pVM;
2328 State.pVCpu = pVCpu;
2329 State.fLocked = false;
2330 State.f64Bits = false;
2331
2332 /*
2333 * Get selector information.
2334 */
2335 if ( (pCtx->cr0 & X86_CR0_PE)
2336 && pCtx->eflags.Bits.u1VM == 0)
2337 {
2338 if (CPUMAreHiddenSelRegsValid(pVM))
2339 {
2340 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2341 State.GCPtrSegBase = pCtx->csHid.u64Base;
2342 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2343 State.cbSegLimit = pCtx->csHid.u32Limit;
2344 pCpu->mode = (State.f64Bits)
2345 ? CPUMODE_64BIT
2346 : pCtx->csHid.Attr.n.u1DefBig
2347 ? CPUMODE_32BIT
2348 : CPUMODE_16BIT;
2349 }
2350 else
2351 {
2352 DBGFSELINFO SelInfo;
2353
2354 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2355 if (RT_FAILURE(rc))
2356 {
2357 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2358 return rc;
2359 }
2360
2361 /*
2362 * Validate the selector.
2363 */
2364 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2365 if (RT_FAILURE(rc))
2366 {
2367 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2368 return rc;
2369 }
2370 State.GCPtrSegBase = SelInfo.GCPtrBase;
2371 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2372 State.cbSegLimit = SelInfo.cbLimit;
2373 pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2374 }
2375 }
2376 else
2377 {
2378 /* real or V86 mode */
2379 pCpu->mode = CPUMODE_16BIT;
2380 State.GCPtrSegBase = pCtx->cs * 16;
2381 State.GCPtrSegEnd = 0xFFFFFFFF;
2382 State.cbSegLimit = 0xFFFFFFFF;
2383 }
2384
2385 /*
2386 * Disassemble the instruction.
2387 */
2388 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2389 pCpu->apvUserData[0] = &State;
2390
2391 uint32_t cbInstr;
2392#ifndef LOG_ENABLED
2393 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2394 if (RT_SUCCESS(rc))
2395 {
2396#else
2397 char szOutput[160];
2398 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2399 if (RT_SUCCESS(rc))
2400 {
2401 /* log it */
2402 if (pszPrefix)
2403 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2404 else
2405 Log(("%s", szOutput));
2406#endif
2407 rc = VINF_SUCCESS;
2408 }
2409 else
2410 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2411
2412 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2413 if (State.fLocked)
2414 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2415
2416 return rc;
2417}
2418
2419#ifdef DEBUG
2420
2421/**
2422 * Disassemble an instruction and dump it to the log
2423 *
2424 * @returns VBox status code.
2425 * @param pVM VM Handle
2426 * @param pVCpu VMCPU Handle
2427 * @param pCtx CPU context
2428 * @param pc GC instruction pointer
2429 * @param pszPrefix String prefix for logging
2430 *
2431 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2432 */
2433VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2434{
2435 DISCPUSTATE Cpu;
2436 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2437}
2438
2439
2440/**
2441 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2442 *
2443 * @internal
2444 */
2445VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2446{
2447 /* @todo SMP support!! */
2448 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2449}
2450
2451#endif /* DEBUG */
2452
2453/**
2454 * API for controlling a few of the CPU features found in CR4.
2455 *
2456 * Currently only X86_CR4_TSD is accepted as input.
2457 *
2458 * @returns VBox status code.
2459 *
2460 * @param pVM The VM handle.
2461 * @param fOr The CR4 OR mask.
2462 * @param fAnd The CR4 AND mask.
2463 */
2464VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2465{
2466 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2467 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2468
2469 pVM->cpum.s.CR4.OrMask &= fAnd;
2470 pVM->cpum.s.CR4.OrMask |= fOr;
2471
2472 return VINF_SUCCESS;
2473}
2474
2475
2476/**
2477 * Gets a pointer to the array of standard CPUID leafs.
2478 *
2479 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2480 *
2481 * @returns Pointer to the standard CPUID leafs (read-only).
2482 * @param pVM The VM handle.
2483 * @remark Intended for PATM.
2484 */
2485VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2486{
2487 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2488}
2489
2490
2491/**
2492 * Gets a pointer to the array of extended CPUID leafs.
2493 *
2494 * CPUMGetGuestCpuIdExtMax() give the size of the array.
2495 *
2496 * @returns Pointer to the extended CPUID leafs (read-only).
2497 * @param pVM The VM handle.
2498 * @remark Intended for PATM.
2499 */
2500VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2501{
2502 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2503}
2504
2505
2506/**
2507 * Gets a pointer to the array of centaur CPUID leafs.
2508 *
2509 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2510 *
2511 * @returns Pointer to the centaur CPUID leafs (read-only).
2512 * @param pVM The VM handle.
2513 * @remark Intended for PATM.
2514 */
2515VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2516{
2517 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2518}
2519
2520
2521/**
2522 * Gets a pointer to the default CPUID leaf.
2523 *
2524 * @returns Pointer to the default CPUID leaf (read-only).
2525 * @param pVM The VM handle.
2526 * @remark Intended for PATM.
2527 */
2528VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2529{
2530 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2531}
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