VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 20157

Last change on this file since 20157 was 20157, checked in by vboxsync, 16 years ago

Multi core cpuid changes for AMD (untested)
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1/* $Id: CPUM.cpp 20157 2009-05-29 15:20:13Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 10
71/** The saved state version for the 2.1 trunk before the MSR changes. */
72#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
73/** The saved state version of 2.0, used for backwards compatibility. */
74#define CPUM_SAVED_STATE_VERSION_VER2_0 8
75/** The saved state version of 1.6, used for backwards compatability. */
76#define CPUM_SAVED_STATE_VERSION_VER1_6 6
77
78
79/*******************************************************************************
80* Structures and Typedefs *
81*******************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91
92} CPUMDUMPTYPE;
93/** Pointer to a cpu info dump type. */
94typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97/*******************************************************************************
98* Internal Functions *
99*******************************************************************************/
100static int cpumR3CpuIdInit(PVM pVM);
101static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/**
112 * Initializes the CPUM.
113 *
114 * @returns VBox status code.
115 * @param pVM The VM to operate on.
116 */
117VMMR3DECL(int) CPUMR3Init(PVM pVM)
118{
119 LogFlow(("CPUMR3Init\n"));
120
121 /*
122 * Assert alignment and sizes.
123 */
124 AssertCompileMemberAlignment(VM, cpum.s, 32);
125 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
126 AssertCompileSizeAlignment(CPUMCTX, 64);
127 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
128 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
129 AssertCompileMemberAlignment(VM, cpum, 64);
130 AssertCompileMemberAlignment(VM, aCpus, 64);
131 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
132 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
133
134 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
135 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
136 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
137
138 /* Calculate the offset from CPUMCPU to CPUM. */
139 for (unsigned i=0;i<pVM->cCPUs;i++)
140 {
141 PVMCPU pVCpu = &pVM->aCpus[i];
142
143 /*
144 * Setup any fixed pointers and offsets.
145 */
146 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
147 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
148
149 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
150 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
151 }
152
153 /*
154 * Check that the CPU supports the minimum features we require.
155 */
156 if (!ASMHasCpuId())
157 {
158 Log(("The CPU doesn't support CPUID!\n"));
159 return VERR_UNSUPPORTED_CPU;
160 }
161 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
162 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
163
164 /* Setup the CR4 AND and OR masks used in the switcher */
165 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
166 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
167 {
168 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
169 /* No FXSAVE implies no SSE */
170 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
171 pVM->cpum.s.CR4.OrMask = 0;
172 }
173 else
174 {
175 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
176 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
177 }
178
179 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
180 {
181 Log(("The CPU doesn't support MMX!\n"));
182 return VERR_UNSUPPORTED_CPU;
183 }
184 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
185 {
186 Log(("The CPU doesn't support TSC!\n"));
187 return VERR_UNSUPPORTED_CPU;
188 }
189 /* Bogus on AMD? */
190 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
191 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
192
193 /*
194 * Setup hypervisor startup values.
195 */
196
197 /*
198 * Register saved state data item.
199 */
200 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
201 NULL, cpumR3Save, NULL,
202 NULL, cpumR3Load, NULL);
203 if (RT_FAILURE(rc))
204 return rc;
205
206 /* Query the CPU manufacturer. */
207 uint32_t uEAX, uEBX, uECX, uEDX;
208 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
209 if ( uEAX >= 1
210 && uEBX == X86_CPUID_VENDOR_AMD_EBX
211 && uECX == X86_CPUID_VENDOR_AMD_ECX
212 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
213 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
214 else if ( uEAX >= 1
215 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
216 && uECX == X86_CPUID_VENDOR_INTEL_ECX
217 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
218 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
219 else /** @todo Via */
220 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
221
222 /*
223 * Register info handlers.
224 */
225 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
226 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
227 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
228 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
229 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
230 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
231
232 /*
233 * Initialize the Guest CPU state.
234 */
235 rc = cpumR3CpuIdInit(pVM);
236 if (RT_FAILURE(rc))
237 return rc;
238 CPUMR3Reset(pVM);
239 return VINF_SUCCESS;
240}
241
242
243/**
244 * Initializes the per-VCPU CPUM.
245 *
246 * @returns VBox status code.
247 * @param pVM The VM to operate on.
248 */
249VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
250{
251 LogFlow(("CPUMR3InitCPU\n"));
252 return VINF_SUCCESS;
253}
254
255
256/**
257 * Initializes the emulated CPU's cpuid information.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262static int cpumR3CpuIdInit(PVM pVM)
263{
264 PCPUM pCPUM = &pVM->cpum.s;
265 uint32_t i;
266
267 /*
268 * Get the host CPUIDs.
269 */
270 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
271 ASMCpuId_Idx_ECX(i, 0,
272 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
273 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
274 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
275 ASMCpuId(0x80000000 + i,
276 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
277 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
278 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
279 ASMCpuId(0xc0000000 + i,
280 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
281 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
282
283
284 /*
285 * Only report features we can support.
286 */
287 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
288 | X86_CPUID_FEATURE_EDX_VME
289 | X86_CPUID_FEATURE_EDX_DE
290 | X86_CPUID_FEATURE_EDX_PSE
291 | X86_CPUID_FEATURE_EDX_TSC
292 | X86_CPUID_FEATURE_EDX_MSR
293 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
294 | X86_CPUID_FEATURE_EDX_MCE
295 | X86_CPUID_FEATURE_EDX_CX8
296 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
297 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
298 //| X86_CPUID_FEATURE_EDX_SEP
299 | X86_CPUID_FEATURE_EDX_MTRR
300 | X86_CPUID_FEATURE_EDX_PGE
301 | X86_CPUID_FEATURE_EDX_MCA
302 | X86_CPUID_FEATURE_EDX_CMOV
303 | X86_CPUID_FEATURE_EDX_PAT
304 | X86_CPUID_FEATURE_EDX_PSE36
305 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
306 | X86_CPUID_FEATURE_EDX_CLFSH
307 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
308 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
309 | X86_CPUID_FEATURE_EDX_MMX
310 | X86_CPUID_FEATURE_EDX_FXSR
311 | X86_CPUID_FEATURE_EDX_SSE
312 | X86_CPUID_FEATURE_EDX_SSE2
313 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
314 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
315 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
316 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
317 | 0;
318 pCPUM->aGuestCpuIdStd[1].ecx &= 0
319 | X86_CPUID_FEATURE_ECX_SSE3
320 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
321 | ((pVM->cCPUs == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
322 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
323 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
324 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
325 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
326 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
327 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
328 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
329 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
330 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
331 /* ECX Bit 21 - x2APIC support - not yet. */
332 // | X86_CPUID_FEATURE_ECX_X2APIC
333 /* ECX Bit 23 - POPCOUNT instruction. */
334 //| X86_CPUID_FEATURE_ECX_POPCOUNT
335 | 0;
336
337 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
338 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
339 | X86_CPUID_AMD_FEATURE_EDX_VME
340 | X86_CPUID_AMD_FEATURE_EDX_DE
341 | X86_CPUID_AMD_FEATURE_EDX_PSE
342 | X86_CPUID_AMD_FEATURE_EDX_TSC
343 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
344 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
345 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
346 | X86_CPUID_AMD_FEATURE_EDX_CX8
347 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
348 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
349 //| X86_CPUID_AMD_FEATURE_EDX_SEP
350 | X86_CPUID_AMD_FEATURE_EDX_MTRR
351 | X86_CPUID_AMD_FEATURE_EDX_PGE
352 | X86_CPUID_AMD_FEATURE_EDX_MCA
353 | X86_CPUID_AMD_FEATURE_EDX_CMOV
354 | X86_CPUID_AMD_FEATURE_EDX_PAT
355 | X86_CPUID_AMD_FEATURE_EDX_PSE36
356 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
357 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
358 | X86_CPUID_AMD_FEATURE_EDX_MMX
359 | X86_CPUID_AMD_FEATURE_EDX_FXSR
360 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
361 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
362 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
363 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
364 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
365 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
366 | 0;
367 pCPUM->aGuestCpuIdExt[1].ecx &= 0
368 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
369 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
370 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
371 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
372 /** Note: This could prevent migration from AMD to Intel CPUs! */
373 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
374 //| X86_CPUID_AMD_FEATURE_ECX_ABM
375 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
376 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
377 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
378 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
379 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
380 //| X86_CPUID_AMD_FEATURE_ECX_WDT
381 | 0;
382
383 /*
384 * Hide HTT, multicode, SMP, whatever.
385 * (APIC-ID := 0 and #LogCpus := 0)
386 */
387 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
388#ifdef VBOX_WITH_MULTI_CORE
389 /* Set the Maximum number of addressable IDs for logical processors in this physical package (bits 16-23) */
390 pCPUM->aGuestCpuIdStd[1].ebx |= ((pVM->cCPUs - 1) << 16);
391
392 if (pVM->cCPUs > 1)
393 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
394#endif
395
396 /* Cpuid 2:
397 * Intel: Cache and TLB information
398 * AMD: Reserved
399 * Safe to expose
400 */
401
402 /* Cpuid 3:
403 * Intel: EAX, EBX - reserved
404 * ECX, EDX - Processor Serial Number if available, otherwise reserved
405 * AMD: Reserved
406 * Safe to expose
407 */
408 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
409 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
410
411 /* Cpuid 4:
412 * Intel: Deterministic Cache Parameters Leaf
413 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
414 * AMD: Reserved
415 * Safe to expose, except for EAX:
416 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
417 * Bits 31-26: Maximum number of processor cores in this physical package**
418 * @Note These SMP values are constant regardless of ECX
419 */
420 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
421 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
422#ifdef VBOX_WITH_MULTI_CORE
423 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_INTEL)
424 {
425 /* One logical processor with possibly multiple cores. */
426 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCPUs - 1) << 26); /* 6 bits only -> 64 cores! */
427 }
428#endif
429
430 /* Cpuid 5: Monitor/mwait Leaf
431 * Intel: ECX, EDX - reserved
432 * EAX, EBX - Smallest and largest monitor line size
433 * AMD: EDX - reserved
434 * EAX, EBX - Smallest and largest monitor line size
435 * ECX - extensions (ignored for now)
436 * Safe to expose
437 */
438 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
439 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
440
441 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
442
443 /*
444 * Determine the default.
445 *
446 * Intel returns values of the highest standard function, while AMD
447 * returns zeros. VIA on the other hand seems to returning nothing or
448 * perhaps some random garbage, we don't try to duplicate this behavior.
449 */
450 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
451 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
452 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
453
454 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
455 * Safe to pass on to the guest.
456 *
457 * Intel: 0x800000005 reserved
458 * 0x800000006 L2 cache information
459 * AMD: 0x800000005 L1 cache information
460 * 0x800000006 L2/L3 cache information
461 */
462
463 /* Cpuid 0x800000007:
464 * AMD: EAX, EBX, ECX - reserved
465 * EDX: Advanced Power Management Information
466 * Intel: Reserved
467 */
468 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
469 {
470 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
471
472 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
473
474 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
475 {
476 /* Only expose the TSC invariant capability bit to the guest. */
477 pCPUM->aGuestCpuIdExt[7].edx &= 0
478 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
479 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
480 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
481 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
482 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
483 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
484 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
485 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
486 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
487 | 0;
488 }
489 else
490 pCPUM->aGuestCpuIdExt[7].edx = 0;
491 }
492
493 /* Cpuid 0x800000008:
494 * AMD: EBX, EDX - reserved
495 * EAX: Virtual/Physical address Size
496 * ECX: Number of cores + APICIdCoreIdSize
497 * Intel: EAX: Virtual/Physical address Size
498 * EBX, ECX, EDX - reserved
499 */
500 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
501 {
502 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
503 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
504 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
505 * NC (0-7) Number of cores; 0 equals 1 core */
506 pCPUM->aGuestCpuIdExt[8].ecx = 0;
507#ifdef VBOX_WITH_MULTI_CORE
508 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
509 {
510 /* Legacy method to determine the number of cores. */
511 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
512 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCPUs - 1); /* NC: Number of CPU cores - 1; 8 bits */
513
514 }
515#endif
516 }
517
518 /*
519 * Limit it the number of entries and fill the remaining with the defaults.
520 *
521 * The limits are masking off stuff about power saving and similar, this
522 * is perhaps a bit crudely done as there is probably some relatively harmless
523 * info too in these leaves (like words about having a constant TSC).
524 */
525#if 0
526 /** @todo NT4 installation regression - investigate */
527 /** Note from Intel manuals:
528 * CPUID leaves > 3 < 80000000 are visible only when
529 * IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default).
530 *
531 */
532 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
533 pCPUM->aGuestCpuIdStd[0].eax = 5;
534#else
535 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
536 pCPUM->aGuestCpuIdStd[0].eax = 2;
537#endif
538 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
539 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
540
541 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
542 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
543 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
544 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
545 : 0;
546 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
547 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
548
549 /*
550 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
551 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
552 * We currently don't support more than 1 processor.
553 */
554 pCPUM->aGuestCpuIdStd[4].eax = 0;
555
556 /*
557 * Centaur stuff (VIA).
558 *
559 * The important part here (we think) is to make sure the 0xc0000000
560 * function returns 0xc0000001. As for the features, we don't currently
561 * let on about any of those... 0xc0000002 seems to be some
562 * temperature/hz/++ stuff, include it as well (static).
563 */
564 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
565 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
566 {
567 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
568 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
569 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
570 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
571 i++)
572 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
573 }
574 else
575 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
576 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
577
578
579 /*
580 * Load CPUID overrides from configuration.
581 */
582 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
583 * Overloads the CPUID leaf values. */
584 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
585 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
586 for (i=0;; )
587 {
588 while (cElements-- > 0)
589 {
590 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
591 if (pNode)
592 {
593 uint32_t u32;
594 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
595 if (RT_SUCCESS(rc))
596 pCpuId->eax = u32;
597 else
598 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
599
600 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
601 if (RT_SUCCESS(rc))
602 pCpuId->ebx = u32;
603 else
604 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
605
606 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
607 if (RT_SUCCESS(rc))
608 pCpuId->ecx = u32;
609 else
610 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
611
612 rc = CFGMR3QueryU32(pNode, "edx", &u32);
613 if (RT_SUCCESS(rc))
614 pCpuId->edx = u32;
615 else
616 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
617 }
618 pCpuId++;
619 i++;
620 }
621
622 /* next */
623 if ((i & UINT32_C(0xc0000000)) == 0)
624 {
625 pCpuId = &pCPUM->aGuestCpuIdExt[0];
626 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
627 i = UINT32_C(0x80000000);
628 }
629 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
630 {
631 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
632 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
633 i = UINT32_C(0xc0000000);
634 }
635 else
636 break;
637 }
638
639 /* Check if PAE was explicitely enabled by the user. */
640 bool fEnable = false;
641 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
642 if (RT_SUCCESS(rc) && fEnable)
643 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
644
645 /*
646 * Log the cpuid and we're good.
647 */
648 RTCPUSET OnlineSet;
649 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
650 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
651 LogRel(("************************* CPUID dump ************************\n"));
652 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
653 LogRel(("\n"));
654 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
655 LogRel(("******************** End of CPUID dump **********************\n"));
656 return VINF_SUCCESS;
657}
658
659
660
661
662/**
663 * Applies relocations to data and code managed by this
664 * component. This function will be called at init and
665 * whenever the VMM need to relocate it self inside the GC.
666 *
667 * The CPUM will update the addresses used by the switcher.
668 *
669 * @param pVM The VM.
670 */
671VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
672{
673 LogFlow(("CPUMR3Relocate\n"));
674 for (unsigned i=0;i<pVM->cCPUs;i++)
675 {
676 PVMCPU pVCpu = &pVM->aCpus[i];
677 /*
678 * Switcher pointers.
679 */
680 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
681 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
682 }
683}
684
685
686/**
687 * Terminates the CPUM.
688 *
689 * Termination means cleaning up and freeing all resources,
690 * the VM it self is at this point powered off or suspended.
691 *
692 * @returns VBox status code.
693 * @param pVM The VM to operate on.
694 */
695VMMR3DECL(int) CPUMR3Term(PVM pVM)
696{
697 CPUMR3TermCPU(pVM);
698 return 0;
699}
700
701
702/**
703 * Terminates the per-VCPU CPUM.
704 *
705 * Termination means cleaning up and freeing all resources,
706 * the VM it self is at this point powered off or suspended.
707 *
708 * @returns VBox status code.
709 * @param pVM The VM to operate on.
710 */
711VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
712{
713#ifdef VBOX_WITH_CRASHDUMP_MAGIC
714 for (unsigned i=0;i<pVM->cCPUs;i++)
715 {
716 PVMCPU pVCpu = &pVM->aCpus[i];
717 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
718
719 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
720 pVCpu->cpum.s.uMagic = 0;
721 pCtx->dr[5] = 0;
722 }
723#endif
724 return 0;
725}
726
727VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
728{
729 /* @todo anything different for VCPU > 0? */
730 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
731
732 /*
733 * Initialize everything to ZERO first.
734 */
735 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
736 memset(pCtx, 0, sizeof(*pCtx));
737 pVCpu->cpum.s.fUseFlags = fUseFlags;
738
739 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
740 pCtx->eip = 0x0000fff0;
741 pCtx->edx = 0x00000600; /* P6 processor */
742 pCtx->eflags.Bits.u1Reserved0 = 1;
743
744 pCtx->cs = 0xf000;
745 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
746 pCtx->csHid.u32Limit = 0x0000ffff;
747 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
748 pCtx->csHid.Attr.n.u1Present = 1;
749 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
750
751 pCtx->dsHid.u32Limit = 0x0000ffff;
752 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
753 pCtx->dsHid.Attr.n.u1Present = 1;
754 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
755
756 pCtx->esHid.u32Limit = 0x0000ffff;
757 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
758 pCtx->esHid.Attr.n.u1Present = 1;
759 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
760
761 pCtx->fsHid.u32Limit = 0x0000ffff;
762 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
763 pCtx->fsHid.Attr.n.u1Present = 1;
764 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
765
766 pCtx->gsHid.u32Limit = 0x0000ffff;
767 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
768 pCtx->gsHid.Attr.n.u1Present = 1;
769 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
770
771 pCtx->ssHid.u32Limit = 0x0000ffff;
772 pCtx->ssHid.Attr.n.u1Present = 1;
773 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
774 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
775
776 pCtx->idtr.cbIdt = 0xffff;
777 pCtx->gdtr.cbGdt = 0xffff;
778
779 pCtx->ldtrHid.u32Limit = 0xffff;
780 pCtx->ldtrHid.Attr.n.u1Present = 1;
781 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
782
783 pCtx->trHid.u32Limit = 0xffff;
784 pCtx->trHid.Attr.n.u1Present = 1;
785 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
786
787 pCtx->dr[6] = X86_DR6_INIT_VAL;
788 pCtx->dr[7] = X86_DR7_INIT_VAL;
789
790 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
791 pCtx->fpu.FCW = 0x37f;
792
793 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
794 pCtx->fpu.MXCSR = 0x1F80;
795
796 /* Init PAT MSR */
797 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
798
799 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
800 * The Intel docs don't mention it.
801 */
802 pCtx->msrEFER = 0;
803}
804
805/**
806 * Resets the CPU.
807 *
808 * @returns VINF_SUCCESS.
809 * @param pVM The VM handle.
810 */
811VMMR3DECL(void) CPUMR3Reset(PVM pVM)
812{
813 for (unsigned i=0;i<pVM->cCPUs;i++)
814 {
815 CPUMR3ResetCpu(&pVM->aCpus[i]);
816
817#ifdef VBOX_WITH_CRASHDUMP_MAGIC
818 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
819
820 /* Magic marker for searching in crash dumps. */
821 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
822 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
823 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
824#endif
825 }
826}
827
828
829/**
830 * Execute state save operation.
831 *
832 * @returns VBox status code.
833 * @param pVM VM Handle.
834 * @param pSSM SSM operation handle.
835 */
836static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
837{
838 /*
839 * Save.
840 */
841 for (unsigned i=0;i<pVM->cCPUs;i++)
842 {
843 PVMCPU pVCpu = &pVM->aCpus[i];
844
845 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
846 }
847
848 SSMR3PutU32(pSSM, pVM->cCPUs);
849 for (unsigned i=0;i<pVM->cCPUs;i++)
850 {
851 PVMCPU pVCpu = &pVM->aCpus[i];
852
853 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
854 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
855 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
856 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
857 }
858
859 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
860 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
861
862 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
863 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
864
865 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
866 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
867
868 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
869
870 /* Add the cpuid for checking that the cpu is unchanged. */
871 uint32_t au32CpuId[8] = {0};
872 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
873 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
874 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
875}
876
877
878/**
879 * Load a version 1.6 CPUMCTX structure.
880 *
881 * @returns VBox status code.
882 * @param pVM VM Handle.
883 * @param pCpumctx16 Version 1.6 CPUMCTX
884 */
885static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
886{
887#define CPUMCTX16_LOADREG(RegName) \
888 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
889
890#define CPUMCTX16_LOADDRXREG(RegName) \
891 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
892
893#define CPUMCTX16_LOADHIDREG(RegName) \
894 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
895 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
896 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
897
898#define CPUMCTX16_LOADSEGREG(RegName) \
899 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
900 CPUMCTX16_LOADHIDREG(RegName);
901
902 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
903
904 CPUMCTX16_LOADREG(rax);
905 CPUMCTX16_LOADREG(rbx);
906 CPUMCTX16_LOADREG(rcx);
907 CPUMCTX16_LOADREG(rdx);
908 CPUMCTX16_LOADREG(rdi);
909 CPUMCTX16_LOADREG(rsi);
910 CPUMCTX16_LOADREG(rbp);
911 CPUMCTX16_LOADREG(esp);
912 CPUMCTX16_LOADREG(rip);
913 CPUMCTX16_LOADREG(rflags);
914
915 CPUMCTX16_LOADSEGREG(cs);
916 CPUMCTX16_LOADSEGREG(ds);
917 CPUMCTX16_LOADSEGREG(es);
918 CPUMCTX16_LOADSEGREG(fs);
919 CPUMCTX16_LOADSEGREG(gs);
920 CPUMCTX16_LOADSEGREG(ss);
921
922 CPUMCTX16_LOADREG(r8);
923 CPUMCTX16_LOADREG(r9);
924 CPUMCTX16_LOADREG(r10);
925 CPUMCTX16_LOADREG(r11);
926 CPUMCTX16_LOADREG(r12);
927 CPUMCTX16_LOADREG(r13);
928 CPUMCTX16_LOADREG(r14);
929 CPUMCTX16_LOADREG(r15);
930
931 CPUMCTX16_LOADREG(cr0);
932 CPUMCTX16_LOADREG(cr2);
933 CPUMCTX16_LOADREG(cr3);
934 CPUMCTX16_LOADREG(cr4);
935
936 CPUMCTX16_LOADDRXREG(0);
937 CPUMCTX16_LOADDRXREG(1);
938 CPUMCTX16_LOADDRXREG(2);
939 CPUMCTX16_LOADDRXREG(3);
940 CPUMCTX16_LOADDRXREG(4);
941 CPUMCTX16_LOADDRXREG(5);
942 CPUMCTX16_LOADDRXREG(6);
943 CPUMCTX16_LOADDRXREG(7);
944
945 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
946 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
947 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
948 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
949
950 CPUMCTX16_LOADREG(ldtr);
951 CPUMCTX16_LOADREG(tr);
952
953 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
954
955 CPUMCTX16_LOADREG(msrEFER);
956 CPUMCTX16_LOADREG(msrSTAR);
957 CPUMCTX16_LOADREG(msrPAT);
958 CPUMCTX16_LOADREG(msrLSTAR);
959 CPUMCTX16_LOADREG(msrCSTAR);
960 CPUMCTX16_LOADREG(msrSFMASK);
961 CPUMCTX16_LOADREG(msrKERNELGSBASE);
962
963 CPUMCTX16_LOADHIDREG(ldtr);
964 CPUMCTX16_LOADHIDREG(tr);
965
966#undef CPUMCTX16_LOADSEGREG
967#undef CPUMCTX16_LOADHIDREG
968#undef CPUMCTX16_LOADDRXREG
969#undef CPUMCTX16_LOADREG
970}
971
972
973/**
974 * Execute state load operation.
975 *
976 * @returns VBox status code.
977 * @param pVM VM Handle.
978 * @param pSSM SSM operation handle.
979 * @param u32Version Data layout version.
980 */
981static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
982{
983 /*
984 * Validate version.
985 */
986 if ( u32Version != CPUM_SAVED_STATE_VERSION
987 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
988 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
989 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
990 {
991 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
992 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
993 }
994
995 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
996 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
997 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
998 else if (u32Version <= CPUM_SAVED_STATE_VERSION)
999 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1000
1001 /*
1002 * Restore.
1003 */
1004 for (unsigned i=0;i<pVM->cCPUs;i++)
1005 {
1006 PVMCPU pVCpu = &pVM->aCpus[i];
1007 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1008 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1009
1010 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1011 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1012 pVCpu->cpum.s.Hyper.esp = uESP;
1013 }
1014
1015 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1016 {
1017 CPUMCTX_VER1_6 cpumctx16;
1018 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1019 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1020
1021 /* Save the old cpumctx state into the new one. */
1022 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1023
1024 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1025 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1026 }
1027 else
1028 {
1029 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1030 {
1031 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
1032 AssertRCReturn(rc, rc);
1033 }
1034
1035 if ( !pVM->cCPUs
1036 || pVM->cCPUs > VMM_MAX_CPU_COUNT
1037 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
1038 && pVM->cCPUs != 1))
1039 {
1040 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
1041 return VERR_SSM_UNEXPECTED_DATA;
1042 }
1043
1044 for (unsigned i=0;i<pVM->cCPUs;i++)
1045 {
1046 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1047 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1048 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1049 if (u32Version == CPUM_SAVED_STATE_VERSION)
1050 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1051 }
1052 }
1053
1054
1055 uint32_t cElements;
1056 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1057 /* Support old saved states with a smaller standard cpuid array. */
1058 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1059 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1060 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1061
1062 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1063 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1064 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1065 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1066
1067 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1068 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1069 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1070 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1071
1072 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1073
1074 /*
1075 * Check that the basic cpuid id information is unchanged.
1076 * @todo we should check the 64 bits capabilities too!
1077 */
1078 uint32_t au32CpuId[8] = {0};
1079 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1080 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1081 uint32_t au32CpuIdSaved[8];
1082 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1083 if (RT_SUCCESS(rc))
1084 {
1085 /* Ignore CPU stepping. */
1086 au32CpuId[4] &= 0xfffffff0;
1087 au32CpuIdSaved[4] &= 0xfffffff0;
1088
1089 /* Ignore APIC ID (AMD specs). */
1090 au32CpuId[5] &= ~0xff000000;
1091 au32CpuIdSaved[5] &= ~0xff000000;
1092
1093 /* Ignore the number of Logical CPUs (AMD specs). */
1094 au32CpuId[5] &= ~0x00ff0000;
1095 au32CpuIdSaved[5] &= ~0x00ff0000;
1096
1097 /* do the compare */
1098 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1099 {
1100 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1101 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1102 "Saved=%.*Rhxs\n"
1103 "Real =%.*Rhxs\n",
1104 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1105 sizeof(au32CpuId), au32CpuId));
1106 else
1107 {
1108 LogRel(("cpumR3Load: CpuId mismatch!\n"
1109 "Saved=%.*Rhxs\n"
1110 "Real =%.*Rhxs\n",
1111 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1112 sizeof(au32CpuId), au32CpuId));
1113 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1114 }
1115 }
1116 }
1117
1118 return rc;
1119}
1120
1121
1122/**
1123 * Formats the EFLAGS value into mnemonics.
1124 *
1125 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1126 * @param efl The EFLAGS value.
1127 */
1128static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1129{
1130 /*
1131 * Format the flags.
1132 */
1133 static const struct
1134 {
1135 const char *pszSet; const char *pszClear; uint32_t fFlag;
1136 } s_aFlags[] =
1137 {
1138 { "vip",NULL, X86_EFL_VIP },
1139 { "vif",NULL, X86_EFL_VIF },
1140 { "ac", NULL, X86_EFL_AC },
1141 { "vm", NULL, X86_EFL_VM },
1142 { "rf", NULL, X86_EFL_RF },
1143 { "nt", NULL, X86_EFL_NT },
1144 { "ov", "nv", X86_EFL_OF },
1145 { "dn", "up", X86_EFL_DF },
1146 { "ei", "di", X86_EFL_IF },
1147 { "tf", NULL, X86_EFL_TF },
1148 { "nt", "pl", X86_EFL_SF },
1149 { "nz", "zr", X86_EFL_ZF },
1150 { "ac", "na", X86_EFL_AF },
1151 { "po", "pe", X86_EFL_PF },
1152 { "cy", "nc", X86_EFL_CF },
1153 };
1154 char *psz = pszEFlags;
1155 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1156 {
1157 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1158 if (pszAdd)
1159 {
1160 strcpy(psz, pszAdd);
1161 psz += strlen(pszAdd);
1162 *psz++ = ' ';
1163 }
1164 }
1165 psz[-1] = '\0';
1166}
1167
1168
1169/**
1170 * Formats a full register dump.
1171 *
1172 * @param pVM VM Handle.
1173 * @param pCtx The context to format.
1174 * @param pCtxCore The context core to format.
1175 * @param pHlp Output functions.
1176 * @param enmType The dump type.
1177 * @param pszPrefix Register name prefix.
1178 */
1179static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1180{
1181 /*
1182 * Format the EFLAGS.
1183 */
1184 uint32_t efl = pCtxCore->eflags.u32;
1185 char szEFlags[80];
1186 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1187
1188 /*
1189 * Format the registers.
1190 */
1191 switch (enmType)
1192 {
1193 case CPUMDUMPTYPE_TERSE:
1194 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1195 pHlp->pfnPrintf(pHlp,
1196 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1197 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1198 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1199 "%sr14=%016RX64 %sr15=%016RX64\n"
1200 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1201 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1202 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1203 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1204 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1205 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1206 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1207 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1208 else
1209 pHlp->pfnPrintf(pHlp,
1210 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1211 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1212 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1213 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1214 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1215 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1216 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1217 break;
1218
1219 case CPUMDUMPTYPE_DEFAULT:
1220 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1221 pHlp->pfnPrintf(pHlp,
1222 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1223 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1224 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1225 "%sr14=%016RX64 %sr15=%016RX64\n"
1226 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1227 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1228 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1229 ,
1230 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1231 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1232 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1233 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1234 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1235 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1236 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1237 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1238 else
1239 pHlp->pfnPrintf(pHlp,
1240 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1241 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1242 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1243 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1244 ,
1245 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1246 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1247 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1248 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1249 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1250 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1251 break;
1252
1253 case CPUMDUMPTYPE_VERBOSE:
1254 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1255 pHlp->pfnPrintf(pHlp,
1256 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1257 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1258 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1259 "%sr14=%016RX64 %sr15=%016RX64\n"
1260 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1261 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1262 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1263 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1264 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1265 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1266 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1267 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1268 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1269 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1270 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1271 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1272 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1273 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1274 ,
1275 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1276 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1277 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1278 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1279 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1280 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1281 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1282 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1283 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1284 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1285 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1286 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1287 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1288 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1289 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1290 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1291 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1292 else
1293 pHlp->pfnPrintf(pHlp,
1294 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1295 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1296 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1297 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1298 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1299 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1300 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1301 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1302 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1303 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1304 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1305 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1306 ,
1307 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1308 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1309 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1310 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1311 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1312 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1313 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1314 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1315 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1316 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1317 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1318 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1319
1320 pHlp->pfnPrintf(pHlp,
1321 "FPU:\n"
1322 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1323 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1324 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1325 ,
1326 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1327 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1328 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1329 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1330
1331 pHlp->pfnPrintf(pHlp,
1332 "MSR:\n"
1333 "%sEFER =%016RX64\n"
1334 "%sPAT =%016RX64\n"
1335 "%sSTAR =%016RX64\n"
1336 "%sCSTAR =%016RX64\n"
1337 "%sLSTAR =%016RX64\n"
1338 "%sSFMASK =%016RX64\n"
1339 "%sKERNELGSBASE =%016RX64\n",
1340 pszPrefix, pCtx->msrEFER,
1341 pszPrefix, pCtx->msrPAT,
1342 pszPrefix, pCtx->msrSTAR,
1343 pszPrefix, pCtx->msrCSTAR,
1344 pszPrefix, pCtx->msrLSTAR,
1345 pszPrefix, pCtx->msrSFMASK,
1346 pszPrefix, pCtx->msrKERNELGSBASE);
1347 break;
1348 }
1349}
1350
1351
1352/**
1353 * Display all cpu states and any other cpum info.
1354 *
1355 * @param pVM VM Handle.
1356 * @param pHlp The info helper functions.
1357 * @param pszArgs Arguments, ignored.
1358 */
1359static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1360{
1361 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1362 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1363 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1364 cpumR3InfoHost(pVM, pHlp, pszArgs);
1365}
1366
1367
1368/**
1369 * Parses the info argument.
1370 *
1371 * The argument starts with 'verbose', 'terse' or 'default' and then
1372 * continues with the comment string.
1373 *
1374 * @param pszArgs The pointer to the argument string.
1375 * @param penmType Where to store the dump type request.
1376 * @param ppszComment Where to store the pointer to the comment string.
1377 */
1378static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1379{
1380 if (!pszArgs)
1381 {
1382 *penmType = CPUMDUMPTYPE_DEFAULT;
1383 *ppszComment = "";
1384 }
1385 else
1386 {
1387 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1388 {
1389 pszArgs += 5;
1390 *penmType = CPUMDUMPTYPE_VERBOSE;
1391 }
1392 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1393 {
1394 pszArgs += 5;
1395 *penmType = CPUMDUMPTYPE_TERSE;
1396 }
1397 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1398 {
1399 pszArgs += 7;
1400 *penmType = CPUMDUMPTYPE_DEFAULT;
1401 }
1402 else
1403 *penmType = CPUMDUMPTYPE_DEFAULT;
1404 *ppszComment = RTStrStripL(pszArgs);
1405 }
1406}
1407
1408
1409/**
1410 * Display the guest cpu state.
1411 *
1412 * @param pVM VM Handle.
1413 * @param pHlp The info helper functions.
1414 * @param pszArgs Arguments, ignored.
1415 */
1416static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1417{
1418 CPUMDUMPTYPE enmType;
1419 const char *pszComment;
1420 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1421
1422 /* @todo SMP support! */
1423 PVMCPU pVCpu = VMMGetCpu(pVM);
1424 if (!pVCpu)
1425 pVCpu = &pVM->aCpus[0];
1426
1427 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1428
1429 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1430 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1431}
1432
1433
1434/**
1435 * Display the current guest instruction
1436 *
1437 * @param pVM VM Handle.
1438 * @param pHlp The info helper functions.
1439 * @param pszArgs Arguments, ignored.
1440 */
1441static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1442{
1443 char szInstruction[256];
1444 /* @todo SMP support! */
1445 PVMCPU pVCpu = VMMGetCpu(pVM);
1446 if (!pVCpu)
1447 pVCpu = &pVM->aCpus[0];
1448
1449 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1450 if (RT_SUCCESS(rc))
1451 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1452}
1453
1454
1455/**
1456 * Display the hypervisor cpu state.
1457 *
1458 * @param pVM VM Handle.
1459 * @param pHlp The info helper functions.
1460 * @param pszArgs Arguments, ignored.
1461 */
1462static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1463{
1464 CPUMDUMPTYPE enmType;
1465 const char *pszComment;
1466 /* @todo SMP */
1467 PVMCPU pVCpu = &pVM->aCpus[0];
1468
1469 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1470 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1471 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1472 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1473}
1474
1475
1476/**
1477 * Display the host cpu state.
1478 *
1479 * @param pVM VM Handle.
1480 * @param pHlp The info helper functions.
1481 * @param pszArgs Arguments, ignored.
1482 */
1483static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1484{
1485 CPUMDUMPTYPE enmType;
1486 const char *pszComment;
1487 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1488 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1489
1490 /*
1491 * Format the EFLAGS.
1492 */
1493 /* @todo SMP */
1494 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1495#if HC_ARCH_BITS == 32
1496 uint32_t efl = pCtx->eflags.u32;
1497#else
1498 uint64_t efl = pCtx->rflags;
1499#endif
1500 char szEFlags[80];
1501 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1502
1503 /*
1504 * Format the registers.
1505 */
1506#if HC_ARCH_BITS == 32
1507# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1508 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1509# endif
1510 {
1511 pHlp->pfnPrintf(pHlp,
1512 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1513 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1514 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1515 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1516 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1517 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1518 ,
1519 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1520 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1521 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1522 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1523 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1524 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1525 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1526 }
1527# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1528 else
1529# endif
1530#endif
1531#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1532 {
1533 pHlp->pfnPrintf(pHlp,
1534 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1535 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1536 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1537 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1538 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1539 "r14=%016RX64 r15=%016RX64\n"
1540 "iopl=%d %31s\n"
1541 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1542 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1543 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1544 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1545 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1546 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1547 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1548 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1549 ,
1550 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1551 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1552 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1553 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1554 pCtx->r11, pCtx->r12, pCtx->r13,
1555 pCtx->r14, pCtx->r15,
1556 X86_EFL_GET_IOPL(efl), szEFlags,
1557 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1558 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1559 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1560 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1561 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1562 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1563 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1564 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1565 }
1566#endif
1567}
1568
1569
1570/**
1571 * Get L1 cache / TLS associativity.
1572 */
1573static const char *getCacheAss(unsigned u, char *pszBuf)
1574{
1575 if (u == 0)
1576 return "res0 ";
1577 if (u == 1)
1578 return "direct";
1579 if (u >= 256)
1580 return "???";
1581
1582 RTStrPrintf(pszBuf, 16, "%d way", u);
1583 return pszBuf;
1584}
1585
1586
1587/**
1588 * Get L2 cache soociativity.
1589 */
1590const char *getL2CacheAss(unsigned u)
1591{
1592 switch (u)
1593 {
1594 case 0: return "off ";
1595 case 1: return "direct";
1596 case 2: return "2 way ";
1597 case 3: return "res3 ";
1598 case 4: return "4 way ";
1599 case 5: return "res5 ";
1600 case 6: return "8 way "; case 7: return "res7 ";
1601 case 8: return "16 way";
1602 case 9: return "res9 ";
1603 case 10: return "res10 ";
1604 case 11: return "res11 ";
1605 case 12: return "res12 ";
1606 case 13: return "res13 ";
1607 case 14: return "res14 ";
1608 case 15: return "fully ";
1609 default:
1610 return "????";
1611 }
1612}
1613
1614
1615/**
1616 * Display the guest CpuId leaves.
1617 *
1618 * @param pVM VM Handle.
1619 * @param pHlp The info helper functions.
1620 * @param pszArgs "terse", "default" or "verbose".
1621 */
1622static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1623{
1624 /*
1625 * Parse the argument.
1626 */
1627 unsigned iVerbosity = 1;
1628 if (pszArgs)
1629 {
1630 pszArgs = RTStrStripL(pszArgs);
1631 if (!strcmp(pszArgs, "terse"))
1632 iVerbosity--;
1633 else if (!strcmp(pszArgs, "verbose"))
1634 iVerbosity++;
1635 }
1636
1637 /*
1638 * Start cracking.
1639 */
1640 CPUMCPUID Host;
1641 CPUMCPUID Guest;
1642 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1643
1644 pHlp->pfnPrintf(pHlp,
1645 " RAW Standard CPUIDs\n"
1646 " Function eax ebx ecx edx\n");
1647 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1648 {
1649 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1650 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1651
1652 pHlp->pfnPrintf(pHlp,
1653 "Gst: %08x %08x %08x %08x %08x%s\n"
1654 "Hst: %08x %08x %08x %08x\n",
1655 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1656 i <= cStdMax ? "" : "*",
1657 Host.eax, Host.ebx, Host.ecx, Host.edx);
1658 }
1659
1660 /*
1661 * If verbose, decode it.
1662 */
1663 if (iVerbosity)
1664 {
1665 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1666 pHlp->pfnPrintf(pHlp,
1667 "Name: %.04s%.04s%.04s\n"
1668 "Supports: 0-%x\n",
1669 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1670 }
1671
1672 /*
1673 * Get Features.
1674 */
1675 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1676 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1677 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1678 if (cStdMax >= 1 && iVerbosity)
1679 {
1680 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1681 uint32_t uEAX = Guest.eax;
1682
1683 pHlp->pfnPrintf(pHlp,
1684 "Family: %d \tExtended: %d \tEffective: %d\n"
1685 "Model: %d \tExtended: %d \tEffective: %d\n"
1686 "Stepping: %d\n"
1687 "APIC ID: %#04x\n"
1688 "Logical CPUs: %d\n"
1689 "CLFLUSH Size: %d\n"
1690 "Brand ID: %#04x\n",
1691 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1692 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1693 ASMGetCpuStepping(uEAX),
1694 (Guest.ebx >> 24) & 0xff,
1695 (Guest.ebx >> 16) & 0xff,
1696 (Guest.ebx >> 8) & 0xff,
1697 (Guest.ebx >> 0) & 0xff);
1698 if (iVerbosity == 1)
1699 {
1700 uint32_t uEDX = Guest.edx;
1701 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1702 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1703 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1704 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1705 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1706 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1707 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1708 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1709 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1710 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1711 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1712 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1713 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1714 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1715 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1716 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1717 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1718 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1719 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1720 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1721 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1722 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1723 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1724 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1725 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1726 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1727 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1728 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1729 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1730 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1731 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1732 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1733 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1734 pHlp->pfnPrintf(pHlp, "\n");
1735
1736 uint32_t uECX = Guest.ecx;
1737 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1738 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1739 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1740 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1741 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1742 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1743 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1744 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1745 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1746 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1747 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1748 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1749 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1750 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1751 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1752 for (unsigned iBit = 14; iBit < 32; iBit++)
1753 if (uECX & RT_BIT(iBit))
1754 pHlp->pfnPrintf(pHlp, " %d", iBit);
1755 pHlp->pfnPrintf(pHlp, "\n");
1756 }
1757 else
1758 {
1759 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1760
1761 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1762 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1763 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1764 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1765
1766 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1767 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1768 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1769 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1770 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1771 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1772 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1773 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1774 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1775 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1776 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1777 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1778 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1779 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1780 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1781 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1782 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1783 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1784 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1785 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1786 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1787 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1788 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1789 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1790 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1791 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1792 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1793 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1794 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1795 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1796 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1797 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1798 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1799
1800 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1801 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1802 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1803 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1804 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1805 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1806 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1807 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1808 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1809 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1810 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1811 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1812 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1813 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1814 }
1815 }
1816 if (cStdMax >= 2 && iVerbosity)
1817 {
1818 /** @todo */
1819 }
1820
1821 /*
1822 * Extended.
1823 * Implemented after AMD specs.
1824 */
1825 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1826
1827 pHlp->pfnPrintf(pHlp,
1828 "\n"
1829 " RAW Extended CPUIDs\n"
1830 " Function eax ebx ecx edx\n");
1831 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1832 {
1833 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1834 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1835
1836 pHlp->pfnPrintf(pHlp,
1837 "Gst: %08x %08x %08x %08x %08x%s\n"
1838 "Hst: %08x %08x %08x %08x\n",
1839 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1840 i <= cExtMax ? "" : "*",
1841 Host.eax, Host.ebx, Host.ecx, Host.edx);
1842 }
1843
1844 /*
1845 * Understandable output
1846 */
1847 if (iVerbosity)
1848 {
1849 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1850 pHlp->pfnPrintf(pHlp,
1851 "Ext Name: %.4s%.4s%.4s\n"
1852 "Ext Supports: 0x80000000-%#010x\n",
1853 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1854 }
1855
1856 if (iVerbosity && cExtMax >= 1)
1857 {
1858 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1859 uint32_t uEAX = Guest.eax;
1860 pHlp->pfnPrintf(pHlp,
1861 "Family: %d \tExtended: %d \tEffective: %d\n"
1862 "Model: %d \tExtended: %d \tEffective: %d\n"
1863 "Stepping: %d\n"
1864 "Brand ID: %#05x\n",
1865 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1866 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1867 ASMGetCpuStepping(uEAX),
1868 Guest.ebx & 0xfff);
1869
1870 if (iVerbosity == 1)
1871 {
1872 uint32_t uEDX = Guest.edx;
1873 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1874 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1875 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1876 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1877 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1878 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1879 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1880 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1881 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1882 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1883 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1884 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1885 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1886 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1887 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1888 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1889 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1890 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1891 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1892 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1893 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1894 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1895 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1896 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1897 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1898 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1899 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1900 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1901 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1902 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1903 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1904 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1905 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1906 pHlp->pfnPrintf(pHlp, "\n");
1907
1908 uint32_t uECX = Guest.ecx;
1909 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1910 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1911 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1912 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1913 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1914 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1915 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1916 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1917 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1918 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1919 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1920 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1921 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1922 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1923 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1924 for (unsigned iBit = 5; iBit < 32; iBit++)
1925 if (uECX & RT_BIT(iBit))
1926 pHlp->pfnPrintf(pHlp, " %d", iBit);
1927 pHlp->pfnPrintf(pHlp, "\n");
1928 }
1929 else
1930 {
1931 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1932
1933 uint32_t uEdxGst = Guest.edx;
1934 uint32_t uEdxHst = Host.edx;
1935 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1936 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1937 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1938 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1939 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1940 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1941 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1942 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1943 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1944 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1945 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1946 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1947 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1948 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1949 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1950 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1951 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1952 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1953 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1954 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1955 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1956 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1957 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1958 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1959 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1960 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1961 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1962 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1963 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1964 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1965 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1966 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1967 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1968
1969 uint32_t uEcxGst = Guest.ecx;
1970 uint32_t uEcxHst = Host.ecx;
1971 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1972 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1973 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1974 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1975 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1976 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1977 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1978 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1979 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1980 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1981 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1982 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1983 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1984 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1985 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1986 }
1987 }
1988
1989 if (iVerbosity && cExtMax >= 2)
1990 {
1991 char szString[4*4*3+1] = {0};
1992 uint32_t *pu32 = (uint32_t *)szString;
1993 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1994 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1995 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1996 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1997 if (cExtMax >= 3)
1998 {
1999 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
2000 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
2001 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2002 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2003 }
2004 if (cExtMax >= 4)
2005 {
2006 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2007 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2008 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2009 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2010 }
2011 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2012 }
2013
2014 if (iVerbosity && cExtMax >= 5)
2015 {
2016 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2017 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2018 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2019 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2020 char sz1[32];
2021 char sz2[32];
2022
2023 pHlp->pfnPrintf(pHlp,
2024 "TLB 2/4M Instr/Uni: %s %3d entries\n"
2025 "TLB 2/4M Data: %s %3d entries\n",
2026 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2027 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2028 pHlp->pfnPrintf(pHlp,
2029 "TLB 4K Instr/Uni: %s %3d entries\n"
2030 "TLB 4K Data: %s %3d entries\n",
2031 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2032 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2033 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2034 "L1 Instr Cache Lines Per Tag: %d\n"
2035 "L1 Instr Cache Associativity: %s\n"
2036 "L1 Instr Cache Size: %d KB\n",
2037 (uEDX >> 0) & 0xff,
2038 (uEDX >> 8) & 0xff,
2039 getCacheAss((uEDX >> 16) & 0xff, sz1),
2040 (uEDX >> 24) & 0xff);
2041 pHlp->pfnPrintf(pHlp,
2042 "L1 Data Cache Line Size: %d bytes\n"
2043 "L1 Data Cache Lines Per Tag: %d\n"
2044 "L1 Data Cache Associativity: %s\n"
2045 "L1 Data Cache Size: %d KB\n",
2046 (uECX >> 0) & 0xff,
2047 (uECX >> 8) & 0xff,
2048 getCacheAss((uECX >> 16) & 0xff, sz1),
2049 (uECX >> 24) & 0xff);
2050 }
2051
2052 if (iVerbosity && cExtMax >= 6)
2053 {
2054 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2055 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2056 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2057
2058 pHlp->pfnPrintf(pHlp,
2059 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2060 "L2 TLB 2/4M Data: %s %4d entries\n",
2061 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2062 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2063 pHlp->pfnPrintf(pHlp,
2064 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2065 "L2 TLB 4K Data: %s %4d entries\n",
2066 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2067 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2068 pHlp->pfnPrintf(pHlp,
2069 "L2 Cache Line Size: %d bytes\n"
2070 "L2 Cache Lines Per Tag: %d\n"
2071 "L2 Cache Associativity: %s\n"
2072 "L2 Cache Size: %d KB\n",
2073 (uEDX >> 0) & 0xff,
2074 (uEDX >> 8) & 0xf,
2075 getL2CacheAss((uEDX >> 12) & 0xf),
2076 (uEDX >> 16) & 0xffff);
2077 }
2078
2079 if (iVerbosity && cExtMax >= 7)
2080 {
2081 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2082
2083 pHlp->pfnPrintf(pHlp, "APM Features: ");
2084 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2085 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2086 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2087 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2088 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2089 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2090 for (unsigned iBit = 6; iBit < 32; iBit++)
2091 if (uEDX & RT_BIT(iBit))
2092 pHlp->pfnPrintf(pHlp, " %d", iBit);
2093 pHlp->pfnPrintf(pHlp, "\n");
2094 }
2095
2096 if (iVerbosity && cExtMax >= 8)
2097 {
2098 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2099 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2100
2101 pHlp->pfnPrintf(pHlp,
2102 "Physical Address Width: %d bits\n"
2103 "Virtual Address Width: %d bits\n",
2104 (uEAX >> 0) & 0xff,
2105 (uEAX >> 8) & 0xff);
2106 pHlp->pfnPrintf(pHlp,
2107 "Physical Core Count: %d\n",
2108 (uECX >> 0) & 0xff);
2109 }
2110
2111
2112 /*
2113 * Centaur.
2114 */
2115 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2116
2117 pHlp->pfnPrintf(pHlp,
2118 "\n"
2119 " RAW Centaur CPUIDs\n"
2120 " Function eax ebx ecx edx\n");
2121 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2122 {
2123 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2124 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2125
2126 pHlp->pfnPrintf(pHlp,
2127 "Gst: %08x %08x %08x %08x %08x%s\n"
2128 "Hst: %08x %08x %08x %08x\n",
2129 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2130 i <= cCentaurMax ? "" : "*",
2131 Host.eax, Host.ebx, Host.ecx, Host.edx);
2132 }
2133
2134 /*
2135 * Understandable output
2136 */
2137 if (iVerbosity)
2138 {
2139 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2140 pHlp->pfnPrintf(pHlp,
2141 "Centaur Supports: 0xc0000000-%#010x\n",
2142 Guest.eax);
2143 }
2144
2145 if (iVerbosity && cCentaurMax >= 1)
2146 {
2147 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2148 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2149 uint32_t uEdxHst = Host.edx;
2150
2151 if (iVerbosity == 1)
2152 {
2153 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2154 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2155 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2156 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2157 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2158 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2159 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2160 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2161 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2162 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2163 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2164 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2165 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2166 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2167 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2168 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2169 for (unsigned iBit = 14; iBit < 32; iBit++)
2170 if (uEdxGst & RT_BIT(iBit))
2171 pHlp->pfnPrintf(pHlp, " %d", iBit);
2172 pHlp->pfnPrintf(pHlp, "\n");
2173 }
2174 else
2175 {
2176 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2177 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2178 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2179 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2180 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2181 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2182 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2183 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2184 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2185 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2186 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2187 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2188 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2189 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2190 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2191 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2192 for (unsigned iBit = 14; iBit < 32; iBit++)
2193 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2194 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2195 pHlp->pfnPrintf(pHlp, "\n");
2196 }
2197 }
2198}
2199
2200
2201/**
2202 * Structure used when disassembling and instructions in DBGF.
2203 * This is used so the reader function can get the stuff it needs.
2204 */
2205typedef struct CPUMDISASSTATE
2206{
2207 /** Pointer to the CPU structure. */
2208 PDISCPUSTATE pCpu;
2209 /** The VM handle. */
2210 PVM pVM;
2211 /** The VMCPU handle. */
2212 PVMCPU pVCpu;
2213 /** Pointer to the first byte in the segemnt. */
2214 RTGCUINTPTR GCPtrSegBase;
2215 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2216 RTGCUINTPTR GCPtrSegEnd;
2217 /** The size of the segment minus 1. */
2218 RTGCUINTPTR cbSegLimit;
2219 /** Pointer to the current page - R3 Ptr. */
2220 void const *pvPageR3;
2221 /** Pointer to the current page - GC Ptr. */
2222 RTGCPTR pvPageGC;
2223 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2224 PGMPAGEMAPLOCK PageMapLock;
2225 /** Whether the PageMapLock is valid or not. */
2226 bool fLocked;
2227 /** 64 bits mode or not. */
2228 bool f64Bits;
2229} CPUMDISASSTATE, *PCPUMDISASSTATE;
2230
2231
2232/**
2233 * Instruction reader.
2234 *
2235 * @returns VBox status code.
2236 * @param PtrSrc Address to read from.
2237 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2238 * @param pu8Dst Where to store the bytes.
2239 * @param cbRead Number of bytes to read.
2240 * @param uDisCpu Pointer to the disassembler cpu state.
2241 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2242 */
2243static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2244{
2245 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2246 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2247 Assert(cbRead > 0);
2248 for (;;)
2249 {
2250 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2251
2252 /* Need to update the page translation? */
2253 if ( !pState->pvPageR3
2254 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2255 {
2256 int rc = VINF_SUCCESS;
2257
2258 /* translate the address */
2259 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2260 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2261 && !HWACCMIsEnabled(pState->pVM))
2262 {
2263 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2264 if (!pState->pvPageR3)
2265 rc = VERR_INVALID_POINTER;
2266 }
2267 else
2268 {
2269 /* Release mapping lock previously acquired. */
2270 if (pState->fLocked)
2271 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2272 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2273 pState->fLocked = RT_SUCCESS_NP(rc);
2274 }
2275 if (RT_FAILURE(rc))
2276 {
2277 pState->pvPageR3 = NULL;
2278 return rc;
2279 }
2280 }
2281
2282 /* check the segemnt limit */
2283 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2284 return VERR_OUT_OF_SELECTOR_BOUNDS;
2285
2286 /* calc how much we can read */
2287 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2288 if (!pState->f64Bits)
2289 {
2290 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2291 if (cb > cbSeg && cbSeg)
2292 cb = cbSeg;
2293 }
2294 if (cb > cbRead)
2295 cb = cbRead;
2296
2297 /* read and advance */
2298 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2299 cbRead -= cb;
2300 if (!cbRead)
2301 return VINF_SUCCESS;
2302 pu8Dst += cb;
2303 PtrSrc += cb;
2304 }
2305}
2306
2307
2308/**
2309 * Disassemble an instruction and return the information in the provided structure.
2310 *
2311 * @returns VBox status code.
2312 * @param pVM VM Handle
2313 * @param pVCpu VMCPU Handle
2314 * @param pCtx CPU context
2315 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2316 * @param pCpu Disassembly state
2317 * @param pszPrefix String prefix for logging (debug only)
2318 *
2319 */
2320VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2321{
2322 CPUMDISASSTATE State;
2323 int rc;
2324
2325 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2326 State.pCpu = pCpu;
2327 State.pvPageGC = 0;
2328 State.pvPageR3 = NULL;
2329 State.pVM = pVM;
2330 State.pVCpu = pVCpu;
2331 State.fLocked = false;
2332 State.f64Bits = false;
2333
2334 /*
2335 * Get selector information.
2336 */
2337 if ( (pCtx->cr0 & X86_CR0_PE)
2338 && pCtx->eflags.Bits.u1VM == 0)
2339 {
2340 if (CPUMAreHiddenSelRegsValid(pVM))
2341 {
2342 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2343 State.GCPtrSegBase = pCtx->csHid.u64Base;
2344 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2345 State.cbSegLimit = pCtx->csHid.u32Limit;
2346 pCpu->mode = (State.f64Bits)
2347 ? CPUMODE_64BIT
2348 : pCtx->csHid.Attr.n.u1DefBig
2349 ? CPUMODE_32BIT
2350 : CPUMODE_16BIT;
2351 }
2352 else
2353 {
2354 DBGFSELINFO SelInfo;
2355
2356 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2357 if (RT_FAILURE(rc))
2358 {
2359 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2360 return rc;
2361 }
2362
2363 /*
2364 * Validate the selector.
2365 */
2366 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2367 if (RT_FAILURE(rc))
2368 {
2369 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2370 return rc;
2371 }
2372 State.GCPtrSegBase = SelInfo.GCPtrBase;
2373 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2374 State.cbSegLimit = SelInfo.cbLimit;
2375 pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2376 }
2377 }
2378 else
2379 {
2380 /* real or V86 mode */
2381 pCpu->mode = CPUMODE_16BIT;
2382 State.GCPtrSegBase = pCtx->cs * 16;
2383 State.GCPtrSegEnd = 0xFFFFFFFF;
2384 State.cbSegLimit = 0xFFFFFFFF;
2385 }
2386
2387 /*
2388 * Disassemble the instruction.
2389 */
2390 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2391 pCpu->apvUserData[0] = &State;
2392
2393 uint32_t cbInstr;
2394#ifndef LOG_ENABLED
2395 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2396 if (RT_SUCCESS(rc))
2397 {
2398#else
2399 char szOutput[160];
2400 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2401 if (RT_SUCCESS(rc))
2402 {
2403 /* log it */
2404 if (pszPrefix)
2405 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2406 else
2407 Log(("%s", szOutput));
2408#endif
2409 rc = VINF_SUCCESS;
2410 }
2411 else
2412 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2413
2414 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2415 if (State.fLocked)
2416 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2417
2418 return rc;
2419}
2420
2421#ifdef DEBUG
2422
2423/**
2424 * Disassemble an instruction and dump it to the log
2425 *
2426 * @returns VBox status code.
2427 * @param pVM VM Handle
2428 * @param pVCpu VMCPU Handle
2429 * @param pCtx CPU context
2430 * @param pc GC instruction pointer
2431 * @param pszPrefix String prefix for logging
2432 *
2433 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2434 */
2435VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2436{
2437 DISCPUSTATE Cpu;
2438 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2439}
2440
2441
2442/**
2443 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2444 *
2445 * @internal
2446 */
2447VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2448{
2449 /* @todo SMP support!! */
2450 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2451}
2452
2453#endif /* DEBUG */
2454
2455/**
2456 * API for controlling a few of the CPU features found in CR4.
2457 *
2458 * Currently only X86_CR4_TSD is accepted as input.
2459 *
2460 * @returns VBox status code.
2461 *
2462 * @param pVM The VM handle.
2463 * @param fOr The CR4 OR mask.
2464 * @param fAnd The CR4 AND mask.
2465 */
2466VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2467{
2468 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2469 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2470
2471 pVM->cpum.s.CR4.OrMask &= fAnd;
2472 pVM->cpum.s.CR4.OrMask |= fOr;
2473
2474 return VINF_SUCCESS;
2475}
2476
2477
2478/**
2479 * Gets a pointer to the array of standard CPUID leafs.
2480 *
2481 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2482 *
2483 * @returns Pointer to the standard CPUID leafs (read-only).
2484 * @param pVM The VM handle.
2485 * @remark Intended for PATM.
2486 */
2487VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2488{
2489 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2490}
2491
2492
2493/**
2494 * Gets a pointer to the array of extended CPUID leafs.
2495 *
2496 * CPUMGetGuestCpuIdExtMax() give the size of the array.
2497 *
2498 * @returns Pointer to the extended CPUID leafs (read-only).
2499 * @param pVM The VM handle.
2500 * @remark Intended for PATM.
2501 */
2502VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2503{
2504 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2505}
2506
2507
2508/**
2509 * Gets a pointer to the array of centaur CPUID leafs.
2510 *
2511 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2512 *
2513 * @returns Pointer to the centaur CPUID leafs (read-only).
2514 * @param pVM The VM handle.
2515 * @remark Intended for PATM.
2516 */
2517VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2518{
2519 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2520}
2521
2522
2523/**
2524 * Gets a pointer to the default CPUID leaf.
2525 *
2526 * @returns Pointer to the default CPUID leaf (read-only).
2527 * @param pVM The VM handle.
2528 * @remark Intended for PATM.
2529 */
2530VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2531{
2532 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2533}
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