VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 20368

Last change on this file since 20368 was 20229, checked in by vboxsync, 16 years ago

Enable multi-core VCPUs by default.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 114.0 KB
Line 
1/* $Id: CPUM.cpp 20229 2009-06-03 12:30:46Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65/* Enable multi-core VCPUs. */
66#define VBOX_WITH_MULTI_CORE
67
68/*******************************************************************************
69* Defined Constants And Macros *
70*******************************************************************************/
71/** The saved state version. */
72#define CPUM_SAVED_STATE_VERSION 10
73/** The saved state version for the 2.1 trunk before the MSR changes. */
74#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
75/** The saved state version of 2.0, used for backwards compatibility. */
76#define CPUM_SAVED_STATE_VERSION_VER2_0 8
77/** The saved state version of 1.6, used for backwards compatability. */
78#define CPUM_SAVED_STATE_VERSION_VER1_6 6
79
80
81/*******************************************************************************
82* Structures and Typedefs *
83*******************************************************************************/
84
85/**
86 * What kind of cpu info dump to perform.
87 */
88typedef enum CPUMDUMPTYPE
89{
90 CPUMDUMPTYPE_TERSE,
91 CPUMDUMPTYPE_DEFAULT,
92 CPUMDUMPTYPE_VERBOSE
93
94} CPUMDUMPTYPE;
95/** Pointer to a cpu info dump type. */
96typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
97
98
99/*******************************************************************************
100* Internal Functions *
101*******************************************************************************/
102static int cpumR3CpuIdInit(PVM pVM);
103static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
104static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
105static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111
112
113/**
114 * Initializes the CPUM.
115 *
116 * @returns VBox status code.
117 * @param pVM The VM to operate on.
118 */
119VMMR3DECL(int) CPUMR3Init(PVM pVM)
120{
121 LogFlow(("CPUMR3Init\n"));
122
123 /*
124 * Assert alignment and sizes.
125 */
126 AssertCompileMemberAlignment(VM, cpum.s, 32);
127 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
128 AssertCompileSizeAlignment(CPUMCTX, 64);
129 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
130 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
131 AssertCompileMemberAlignment(VM, cpum, 64);
132 AssertCompileMemberAlignment(VM, aCpus, 64);
133 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
134 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
135
136 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
137 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
138 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
139
140 /* Calculate the offset from CPUMCPU to CPUM. */
141 for (unsigned i=0;i<pVM->cCPUs;i++)
142 {
143 PVMCPU pVCpu = &pVM->aCpus[i];
144
145 /*
146 * Setup any fixed pointers and offsets.
147 */
148 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
149 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
150
151 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
152 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
153 }
154
155 /*
156 * Check that the CPU supports the minimum features we require.
157 */
158 if (!ASMHasCpuId())
159 {
160 Log(("The CPU doesn't support CPUID!\n"));
161 return VERR_UNSUPPORTED_CPU;
162 }
163 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
164 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
165
166 /* Setup the CR4 AND and OR masks used in the switcher */
167 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
168 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
169 {
170 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
171 /* No FXSAVE implies no SSE */
172 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
173 pVM->cpum.s.CR4.OrMask = 0;
174 }
175 else
176 {
177 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
178 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
179 }
180
181 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
182 {
183 Log(("The CPU doesn't support MMX!\n"));
184 return VERR_UNSUPPORTED_CPU;
185 }
186 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
187 {
188 Log(("The CPU doesn't support TSC!\n"));
189 return VERR_UNSUPPORTED_CPU;
190 }
191 /* Bogus on AMD? */
192 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
193 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
194
195 /*
196 * Setup hypervisor startup values.
197 */
198
199 /*
200 * Register saved state data item.
201 */
202 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
203 NULL, cpumR3Save, NULL,
204 NULL, cpumR3Load, NULL);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 /* Query the CPU manufacturer. */
209 uint32_t uEAX, uEBX, uECX, uEDX;
210 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
211 if ( uEAX >= 1
212 && uEBX == X86_CPUID_VENDOR_AMD_EBX
213 && uECX == X86_CPUID_VENDOR_AMD_ECX
214 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
215 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
216 else if ( uEAX >= 1
217 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
218 && uECX == X86_CPUID_VENDOR_INTEL_ECX
219 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
220 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
221 else /** @todo Via */
222 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
223
224 /*
225 * Register info handlers.
226 */
227 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
228 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
229 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
230 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
231 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
232 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
233
234 /*
235 * Initialize the Guest CPU state.
236 */
237 rc = cpumR3CpuIdInit(pVM);
238 if (RT_FAILURE(rc))
239 return rc;
240 CPUMR3Reset(pVM);
241 return VINF_SUCCESS;
242}
243
244
245/**
246 * Initializes the per-VCPU CPUM.
247 *
248 * @returns VBox status code.
249 * @param pVM The VM to operate on.
250 */
251VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
252{
253 LogFlow(("CPUMR3InitCPU\n"));
254 return VINF_SUCCESS;
255}
256
257
258/**
259 * Initializes the emulated CPU's cpuid information.
260 *
261 * @returns VBox status code.
262 * @param pVM The VM to operate on.
263 */
264static int cpumR3CpuIdInit(PVM pVM)
265{
266 PCPUM pCPUM = &pVM->cpum.s;
267 uint32_t i;
268
269 /*
270 * Get the host CPUIDs.
271 */
272 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
273 ASMCpuId_Idx_ECX(i, 0,
274 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
275 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
276 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
277 ASMCpuId(0x80000000 + i,
278 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
279 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
280 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
281 ASMCpuId(0xc0000000 + i,
282 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
283 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
284
285
286 /*
287 * Only report features we can support.
288 */
289 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
290 | X86_CPUID_FEATURE_EDX_VME
291 | X86_CPUID_FEATURE_EDX_DE
292 | X86_CPUID_FEATURE_EDX_PSE
293 | X86_CPUID_FEATURE_EDX_TSC
294 | X86_CPUID_FEATURE_EDX_MSR
295 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
296 | X86_CPUID_FEATURE_EDX_MCE
297 | X86_CPUID_FEATURE_EDX_CX8
298 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
299 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
300 //| X86_CPUID_FEATURE_EDX_SEP
301 | X86_CPUID_FEATURE_EDX_MTRR
302 | X86_CPUID_FEATURE_EDX_PGE
303 | X86_CPUID_FEATURE_EDX_MCA
304 | X86_CPUID_FEATURE_EDX_CMOV
305 | X86_CPUID_FEATURE_EDX_PAT
306 | X86_CPUID_FEATURE_EDX_PSE36
307 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
308 | X86_CPUID_FEATURE_EDX_CLFSH
309 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
310 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
311 | X86_CPUID_FEATURE_EDX_MMX
312 | X86_CPUID_FEATURE_EDX_FXSR
313 | X86_CPUID_FEATURE_EDX_SSE
314 | X86_CPUID_FEATURE_EDX_SSE2
315 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
316 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
317 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
318 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
319 | 0;
320 pCPUM->aGuestCpuIdStd[1].ecx &= 0
321 | X86_CPUID_FEATURE_ECX_SSE3
322 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
323 | ((pVM->cCPUs == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
324 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
325 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
326 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
327 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
328 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
329 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
330 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
331 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
332 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
333 /* ECX Bit 21 - x2APIC support - not yet. */
334 // | X86_CPUID_FEATURE_ECX_X2APIC
335 /* ECX Bit 23 - POPCOUNT instruction. */
336 //| X86_CPUID_FEATURE_ECX_POPCOUNT
337 | 0;
338
339 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
340 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
341 | X86_CPUID_AMD_FEATURE_EDX_VME
342 | X86_CPUID_AMD_FEATURE_EDX_DE
343 | X86_CPUID_AMD_FEATURE_EDX_PSE
344 | X86_CPUID_AMD_FEATURE_EDX_TSC
345 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
346 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
347 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
348 | X86_CPUID_AMD_FEATURE_EDX_CX8
349 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
350 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
351 //| X86_CPUID_AMD_FEATURE_EDX_SEP
352 | X86_CPUID_AMD_FEATURE_EDX_MTRR
353 | X86_CPUID_AMD_FEATURE_EDX_PGE
354 | X86_CPUID_AMD_FEATURE_EDX_MCA
355 | X86_CPUID_AMD_FEATURE_EDX_CMOV
356 | X86_CPUID_AMD_FEATURE_EDX_PAT
357 | X86_CPUID_AMD_FEATURE_EDX_PSE36
358 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
359 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
360 | X86_CPUID_AMD_FEATURE_EDX_MMX
361 | X86_CPUID_AMD_FEATURE_EDX_FXSR
362 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
363 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
364 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
365 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
366 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
367 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
368 | 0;
369 pCPUM->aGuestCpuIdExt[1].ecx &= 0
370 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
371 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
372 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
373 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
374 /** Note: This could prevent migration from AMD to Intel CPUs! */
375 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
376 //| X86_CPUID_AMD_FEATURE_ECX_ABM
377 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
378 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
379 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
380 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
381 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
382 //| X86_CPUID_AMD_FEATURE_ECX_WDT
383 | 0;
384
385 /*
386 * Hide HTT, multicode, SMP, whatever.
387 * (APIC-ID := 0 and #LogCpus := 0)
388 */
389 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
390#ifdef VBOX_WITH_MULTI_CORE
391 if (pVM->cCPUs > 1)
392 {
393 /* Set the Maximum number of addressable IDs for logical processors in this physical package (bits 16-23) */
394 pCPUM->aGuestCpuIdStd[1].ebx |= ((pVM->cCPUs - 1) << 16);
395 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
396 }
397#endif
398
399 /* Cpuid 2:
400 * Intel: Cache and TLB information
401 * AMD: Reserved
402 * Safe to expose
403 */
404
405 /* Cpuid 3:
406 * Intel: EAX, EBX - reserved
407 * ECX, EDX - Processor Serial Number if available, otherwise reserved
408 * AMD: Reserved
409 * Safe to expose
410 */
411 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
412 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
413
414 /* Cpuid 4:
415 * Intel: Deterministic Cache Parameters Leaf
416 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
417 * AMD: Reserved
418 * Safe to expose, except for EAX:
419 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
420 * Bits 31-26: Maximum number of processor cores in this physical package**
421 * @Note These SMP values are constant regardless of ECX
422 */
423 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
424 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
425#ifdef VBOX_WITH_MULTI_CORE
426 if ( pVM->cCPUs > 1
427 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_INTEL)
428 {
429 AssertReturn(pVM->cCPUs <= 64, VERR_TOO_MANY_CPUS);
430 /* One logical processor with possibly multiple cores. */
431 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCPUs - 1) << 26); /* 6 bits only -> 64 cores! */
432 }
433#endif
434
435 /* Cpuid 5: Monitor/mwait Leaf
436 * Intel: ECX, EDX - reserved
437 * EAX, EBX - Smallest and largest monitor line size
438 * AMD: EDX - reserved
439 * EAX, EBX - Smallest and largest monitor line size
440 * ECX - extensions (ignored for now)
441 * Safe to expose
442 */
443 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
444 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
445
446 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
447
448 /*
449 * Determine the default.
450 *
451 * Intel returns values of the highest standard function, while AMD
452 * returns zeros. VIA on the other hand seems to returning nothing or
453 * perhaps some random garbage, we don't try to duplicate this behavior.
454 */
455 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
456 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
457 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
458
459 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
460 * Safe to pass on to the guest.
461 *
462 * Intel: 0x800000005 reserved
463 * 0x800000006 L2 cache information
464 * AMD: 0x800000005 L1 cache information
465 * 0x800000006 L2/L3 cache information
466 */
467
468 /* Cpuid 0x800000007:
469 * AMD: EAX, EBX, ECX - reserved
470 * EDX: Advanced Power Management Information
471 * Intel: Reserved
472 */
473 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
474 {
475 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
476
477 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
478
479 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
480 {
481 /* Only expose the TSC invariant capability bit to the guest. */
482 pCPUM->aGuestCpuIdExt[7].edx &= 0
483 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
484 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
485 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
486 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
487 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
488 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
489 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
490 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
491 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
492 | 0;
493 }
494 else
495 pCPUM->aGuestCpuIdExt[7].edx = 0;
496 }
497
498 /* Cpuid 0x800000008:
499 * AMD: EBX, EDX - reserved
500 * EAX: Virtual/Physical address Size
501 * ECX: Number of cores + APICIdCoreIdSize
502 * Intel: EAX: Virtual/Physical address Size
503 * EBX, ECX, EDX - reserved
504 */
505 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
506 {
507 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
508 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
509 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
510 * NC (0-7) Number of cores; 0 equals 1 core */
511 pCPUM->aGuestCpuIdExt[8].ecx = 0;
512#ifdef VBOX_WITH_MULTI_CORE
513 if ( pVM->cCPUs > 1
514 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
515 {
516 /* Legacy method to determine the number of cores. */
517 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
518 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCPUs - 1); /* NC: Number of CPU cores - 1; 8 bits */
519
520 }
521#endif
522 }
523
524 /*
525 * Limit it the number of entries and fill the remaining with the defaults.
526 *
527 * The limits are masking off stuff about power saving and similar, this
528 * is perhaps a bit crudely done as there is probably some relatively harmless
529 * info too in these leaves (like words about having a constant TSC).
530 */
531#if 0
532 /** @todo NT4 installation regression - investigate */
533 /** Note from Intel manuals:
534 * CPUID leaves > 3 < 80000000 are visible only when
535 * IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default).
536 *
537 */
538 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
539 pCPUM->aGuestCpuIdStd[0].eax = 5;
540#else
541 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
542 pCPUM->aGuestCpuIdStd[0].eax = 2;
543#endif
544 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
545 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
546
547 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
548 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
549 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
550 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
551 : 0;
552 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
553 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
554
555 /*
556 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
557 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
558 * We currently don't support more than 1 processor.
559 */
560 pCPUM->aGuestCpuIdStd[4].eax = 0;
561
562 /*
563 * Centaur stuff (VIA).
564 *
565 * The important part here (we think) is to make sure the 0xc0000000
566 * function returns 0xc0000001. As for the features, we don't currently
567 * let on about any of those... 0xc0000002 seems to be some
568 * temperature/hz/++ stuff, include it as well (static).
569 */
570 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
571 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
572 {
573 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
574 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
575 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
576 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
577 i++)
578 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
579 }
580 else
581 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
582 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
583
584
585 /*
586 * Load CPUID overrides from configuration.
587 */
588 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
589 * Overloads the CPUID leaf values. */
590 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
591 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
592 for (i=0;; )
593 {
594 while (cElements-- > 0)
595 {
596 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
597 if (pNode)
598 {
599 uint32_t u32;
600 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
601 if (RT_SUCCESS(rc))
602 pCpuId->eax = u32;
603 else
604 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
605
606 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
607 if (RT_SUCCESS(rc))
608 pCpuId->ebx = u32;
609 else
610 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
611
612 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
613 if (RT_SUCCESS(rc))
614 pCpuId->ecx = u32;
615 else
616 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
617
618 rc = CFGMR3QueryU32(pNode, "edx", &u32);
619 if (RT_SUCCESS(rc))
620 pCpuId->edx = u32;
621 else
622 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
623 }
624 pCpuId++;
625 i++;
626 }
627
628 /* next */
629 if ((i & UINT32_C(0xc0000000)) == 0)
630 {
631 pCpuId = &pCPUM->aGuestCpuIdExt[0];
632 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
633 i = UINT32_C(0x80000000);
634 }
635 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
636 {
637 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
638 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
639 i = UINT32_C(0xc0000000);
640 }
641 else
642 break;
643 }
644
645 /* Check if PAE was explicitely enabled by the user. */
646 bool fEnable = false;
647 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
648 if (RT_SUCCESS(rc) && fEnable)
649 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
650
651 /*
652 * Log the cpuid and we're good.
653 */
654 RTCPUSET OnlineSet;
655 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
656 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
657 LogRel(("************************* CPUID dump ************************\n"));
658 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
659 LogRel(("\n"));
660 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
661 LogRel(("******************** End of CPUID dump **********************\n"));
662 return VINF_SUCCESS;
663}
664
665
666
667
668/**
669 * Applies relocations to data and code managed by this
670 * component. This function will be called at init and
671 * whenever the VMM need to relocate it self inside the GC.
672 *
673 * The CPUM will update the addresses used by the switcher.
674 *
675 * @param pVM The VM.
676 */
677VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
678{
679 LogFlow(("CPUMR3Relocate\n"));
680 for (unsigned i=0;i<pVM->cCPUs;i++)
681 {
682 PVMCPU pVCpu = &pVM->aCpus[i];
683 /*
684 * Switcher pointers.
685 */
686 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
687 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
688 }
689}
690
691
692/**
693 * Terminates the CPUM.
694 *
695 * Termination means cleaning up and freeing all resources,
696 * the VM it self is at this point powered off or suspended.
697 *
698 * @returns VBox status code.
699 * @param pVM The VM to operate on.
700 */
701VMMR3DECL(int) CPUMR3Term(PVM pVM)
702{
703 CPUMR3TermCPU(pVM);
704 return 0;
705}
706
707
708/**
709 * Terminates the per-VCPU CPUM.
710 *
711 * Termination means cleaning up and freeing all resources,
712 * the VM it self is at this point powered off or suspended.
713 *
714 * @returns VBox status code.
715 * @param pVM The VM to operate on.
716 */
717VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
718{
719#ifdef VBOX_WITH_CRASHDUMP_MAGIC
720 for (unsigned i=0;i<pVM->cCPUs;i++)
721 {
722 PVMCPU pVCpu = &pVM->aCpus[i];
723 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
724
725 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
726 pVCpu->cpum.s.uMagic = 0;
727 pCtx->dr[5] = 0;
728 }
729#endif
730 return 0;
731}
732
733VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
734{
735 /* @todo anything different for VCPU > 0? */
736 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
737
738 /*
739 * Initialize everything to ZERO first.
740 */
741 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
742 memset(pCtx, 0, sizeof(*pCtx));
743 pVCpu->cpum.s.fUseFlags = fUseFlags;
744
745 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
746 pCtx->eip = 0x0000fff0;
747 pCtx->edx = 0x00000600; /* P6 processor */
748 pCtx->eflags.Bits.u1Reserved0 = 1;
749
750 pCtx->cs = 0xf000;
751 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
752 pCtx->csHid.u32Limit = 0x0000ffff;
753 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
754 pCtx->csHid.Attr.n.u1Present = 1;
755 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
756
757 pCtx->dsHid.u32Limit = 0x0000ffff;
758 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
759 pCtx->dsHid.Attr.n.u1Present = 1;
760 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
761
762 pCtx->esHid.u32Limit = 0x0000ffff;
763 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
764 pCtx->esHid.Attr.n.u1Present = 1;
765 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
766
767 pCtx->fsHid.u32Limit = 0x0000ffff;
768 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
769 pCtx->fsHid.Attr.n.u1Present = 1;
770 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
771
772 pCtx->gsHid.u32Limit = 0x0000ffff;
773 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
774 pCtx->gsHid.Attr.n.u1Present = 1;
775 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
776
777 pCtx->ssHid.u32Limit = 0x0000ffff;
778 pCtx->ssHid.Attr.n.u1Present = 1;
779 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
780 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
781
782 pCtx->idtr.cbIdt = 0xffff;
783 pCtx->gdtr.cbGdt = 0xffff;
784
785 pCtx->ldtrHid.u32Limit = 0xffff;
786 pCtx->ldtrHid.Attr.n.u1Present = 1;
787 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
788
789 pCtx->trHid.u32Limit = 0xffff;
790 pCtx->trHid.Attr.n.u1Present = 1;
791 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
792
793 pCtx->dr[6] = X86_DR6_INIT_VAL;
794 pCtx->dr[7] = X86_DR7_INIT_VAL;
795
796 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
797 pCtx->fpu.FCW = 0x37f;
798
799 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
800 pCtx->fpu.MXCSR = 0x1F80;
801
802 /* Init PAT MSR */
803 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
804
805 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
806 * The Intel docs don't mention it.
807 */
808 pCtx->msrEFER = 0;
809}
810
811/**
812 * Resets the CPU.
813 *
814 * @returns VINF_SUCCESS.
815 * @param pVM The VM handle.
816 */
817VMMR3DECL(void) CPUMR3Reset(PVM pVM)
818{
819 for (unsigned i=0;i<pVM->cCPUs;i++)
820 {
821 CPUMR3ResetCpu(&pVM->aCpus[i]);
822
823#ifdef VBOX_WITH_CRASHDUMP_MAGIC
824 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
825
826 /* Magic marker for searching in crash dumps. */
827 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
828 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
829 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
830#endif
831 }
832}
833
834
835/**
836 * Execute state save operation.
837 *
838 * @returns VBox status code.
839 * @param pVM VM Handle.
840 * @param pSSM SSM operation handle.
841 */
842static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
843{
844 /*
845 * Save.
846 */
847 for (unsigned i=0;i<pVM->cCPUs;i++)
848 {
849 PVMCPU pVCpu = &pVM->aCpus[i];
850
851 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
852 }
853
854 SSMR3PutU32(pSSM, pVM->cCPUs);
855 for (unsigned i=0;i<pVM->cCPUs;i++)
856 {
857 PVMCPU pVCpu = &pVM->aCpus[i];
858
859 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
860 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
861 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
862 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
863 }
864
865 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
866 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
867
868 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
869 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
870
871 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
872 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
873
874 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
875
876 /* Add the cpuid for checking that the cpu is unchanged. */
877 uint32_t au32CpuId[8] = {0};
878 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
879 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
880 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
881}
882
883
884/**
885 * Load a version 1.6 CPUMCTX structure.
886 *
887 * @returns VBox status code.
888 * @param pVM VM Handle.
889 * @param pCpumctx16 Version 1.6 CPUMCTX
890 */
891static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
892{
893#define CPUMCTX16_LOADREG(RegName) \
894 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
895
896#define CPUMCTX16_LOADDRXREG(RegName) \
897 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
898
899#define CPUMCTX16_LOADHIDREG(RegName) \
900 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
901 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
902 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
903
904#define CPUMCTX16_LOADSEGREG(RegName) \
905 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
906 CPUMCTX16_LOADHIDREG(RegName);
907
908 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
909
910 CPUMCTX16_LOADREG(rax);
911 CPUMCTX16_LOADREG(rbx);
912 CPUMCTX16_LOADREG(rcx);
913 CPUMCTX16_LOADREG(rdx);
914 CPUMCTX16_LOADREG(rdi);
915 CPUMCTX16_LOADREG(rsi);
916 CPUMCTX16_LOADREG(rbp);
917 CPUMCTX16_LOADREG(esp);
918 CPUMCTX16_LOADREG(rip);
919 CPUMCTX16_LOADREG(rflags);
920
921 CPUMCTX16_LOADSEGREG(cs);
922 CPUMCTX16_LOADSEGREG(ds);
923 CPUMCTX16_LOADSEGREG(es);
924 CPUMCTX16_LOADSEGREG(fs);
925 CPUMCTX16_LOADSEGREG(gs);
926 CPUMCTX16_LOADSEGREG(ss);
927
928 CPUMCTX16_LOADREG(r8);
929 CPUMCTX16_LOADREG(r9);
930 CPUMCTX16_LOADREG(r10);
931 CPUMCTX16_LOADREG(r11);
932 CPUMCTX16_LOADREG(r12);
933 CPUMCTX16_LOADREG(r13);
934 CPUMCTX16_LOADREG(r14);
935 CPUMCTX16_LOADREG(r15);
936
937 CPUMCTX16_LOADREG(cr0);
938 CPUMCTX16_LOADREG(cr2);
939 CPUMCTX16_LOADREG(cr3);
940 CPUMCTX16_LOADREG(cr4);
941
942 CPUMCTX16_LOADDRXREG(0);
943 CPUMCTX16_LOADDRXREG(1);
944 CPUMCTX16_LOADDRXREG(2);
945 CPUMCTX16_LOADDRXREG(3);
946 CPUMCTX16_LOADDRXREG(4);
947 CPUMCTX16_LOADDRXREG(5);
948 CPUMCTX16_LOADDRXREG(6);
949 CPUMCTX16_LOADDRXREG(7);
950
951 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
952 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
953 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
954 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
955
956 CPUMCTX16_LOADREG(ldtr);
957 CPUMCTX16_LOADREG(tr);
958
959 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
960
961 CPUMCTX16_LOADREG(msrEFER);
962 CPUMCTX16_LOADREG(msrSTAR);
963 CPUMCTX16_LOADREG(msrPAT);
964 CPUMCTX16_LOADREG(msrLSTAR);
965 CPUMCTX16_LOADREG(msrCSTAR);
966 CPUMCTX16_LOADREG(msrSFMASK);
967 CPUMCTX16_LOADREG(msrKERNELGSBASE);
968
969 CPUMCTX16_LOADHIDREG(ldtr);
970 CPUMCTX16_LOADHIDREG(tr);
971
972#undef CPUMCTX16_LOADSEGREG
973#undef CPUMCTX16_LOADHIDREG
974#undef CPUMCTX16_LOADDRXREG
975#undef CPUMCTX16_LOADREG
976}
977
978
979/**
980 * Execute state load operation.
981 *
982 * @returns VBox status code.
983 * @param pVM VM Handle.
984 * @param pSSM SSM operation handle.
985 * @param u32Version Data layout version.
986 */
987static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
988{
989 /*
990 * Validate version.
991 */
992 if ( u32Version != CPUM_SAVED_STATE_VERSION
993 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
994 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
995 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
996 {
997 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
998 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
999 }
1000
1001 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
1002 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1003 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1004 else if (u32Version <= CPUM_SAVED_STATE_VERSION)
1005 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1006
1007 /*
1008 * Restore.
1009 */
1010 for (unsigned i=0;i<pVM->cCPUs;i++)
1011 {
1012 PVMCPU pVCpu = &pVM->aCpus[i];
1013 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1014 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1015
1016 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1017 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1018 pVCpu->cpum.s.Hyper.esp = uESP;
1019 }
1020
1021 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1022 {
1023 CPUMCTX_VER1_6 cpumctx16;
1024 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1025 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1026
1027 /* Save the old cpumctx state into the new one. */
1028 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1029
1030 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1031 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1032 }
1033 else
1034 {
1035 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1036 {
1037 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
1038 AssertRCReturn(rc, rc);
1039 }
1040
1041 if ( !pVM->cCPUs
1042 || pVM->cCPUs > VMM_MAX_CPU_COUNT
1043 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
1044 && pVM->cCPUs != 1))
1045 {
1046 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
1047 return VERR_SSM_UNEXPECTED_DATA;
1048 }
1049
1050 for (unsigned i=0;i<pVM->cCPUs;i++)
1051 {
1052 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1053 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1054 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1055 if (u32Version == CPUM_SAVED_STATE_VERSION)
1056 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1057 }
1058 }
1059
1060
1061 uint32_t cElements;
1062 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1063 /* Support old saved states with a smaller standard cpuid array. */
1064 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1065 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1066 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1067
1068 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1069 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1070 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1071 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1072
1073 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1074 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1075 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1076 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1077
1078 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1079
1080 /*
1081 * Check that the basic cpuid id information is unchanged.
1082 * @todo we should check the 64 bits capabilities too!
1083 */
1084 uint32_t au32CpuId[8] = {0};
1085 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1086 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1087 uint32_t au32CpuIdSaved[8];
1088 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1089 if (RT_SUCCESS(rc))
1090 {
1091 /* Ignore CPU stepping. */
1092 au32CpuId[4] &= 0xfffffff0;
1093 au32CpuIdSaved[4] &= 0xfffffff0;
1094
1095 /* Ignore APIC ID (AMD specs). */
1096 au32CpuId[5] &= ~0xff000000;
1097 au32CpuIdSaved[5] &= ~0xff000000;
1098
1099 /* Ignore the number of Logical CPUs (AMD specs). */
1100 au32CpuId[5] &= ~0x00ff0000;
1101 au32CpuIdSaved[5] &= ~0x00ff0000;
1102
1103 /* do the compare */
1104 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1105 {
1106 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1107 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1108 "Saved=%.*Rhxs\n"
1109 "Real =%.*Rhxs\n",
1110 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1111 sizeof(au32CpuId), au32CpuId));
1112 else
1113 {
1114 LogRel(("cpumR3Load: CpuId mismatch!\n"
1115 "Saved=%.*Rhxs\n"
1116 "Real =%.*Rhxs\n",
1117 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1118 sizeof(au32CpuId), au32CpuId));
1119 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1120 }
1121 }
1122 }
1123
1124 return rc;
1125}
1126
1127
1128/**
1129 * Formats the EFLAGS value into mnemonics.
1130 *
1131 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1132 * @param efl The EFLAGS value.
1133 */
1134static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1135{
1136 /*
1137 * Format the flags.
1138 */
1139 static const struct
1140 {
1141 const char *pszSet; const char *pszClear; uint32_t fFlag;
1142 } s_aFlags[] =
1143 {
1144 { "vip",NULL, X86_EFL_VIP },
1145 { "vif",NULL, X86_EFL_VIF },
1146 { "ac", NULL, X86_EFL_AC },
1147 { "vm", NULL, X86_EFL_VM },
1148 { "rf", NULL, X86_EFL_RF },
1149 { "nt", NULL, X86_EFL_NT },
1150 { "ov", "nv", X86_EFL_OF },
1151 { "dn", "up", X86_EFL_DF },
1152 { "ei", "di", X86_EFL_IF },
1153 { "tf", NULL, X86_EFL_TF },
1154 { "nt", "pl", X86_EFL_SF },
1155 { "nz", "zr", X86_EFL_ZF },
1156 { "ac", "na", X86_EFL_AF },
1157 { "po", "pe", X86_EFL_PF },
1158 { "cy", "nc", X86_EFL_CF },
1159 };
1160 char *psz = pszEFlags;
1161 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1162 {
1163 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1164 if (pszAdd)
1165 {
1166 strcpy(psz, pszAdd);
1167 psz += strlen(pszAdd);
1168 *psz++ = ' ';
1169 }
1170 }
1171 psz[-1] = '\0';
1172}
1173
1174
1175/**
1176 * Formats a full register dump.
1177 *
1178 * @param pVM VM Handle.
1179 * @param pCtx The context to format.
1180 * @param pCtxCore The context core to format.
1181 * @param pHlp Output functions.
1182 * @param enmType The dump type.
1183 * @param pszPrefix Register name prefix.
1184 */
1185static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1186{
1187 /*
1188 * Format the EFLAGS.
1189 */
1190 uint32_t efl = pCtxCore->eflags.u32;
1191 char szEFlags[80];
1192 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1193
1194 /*
1195 * Format the registers.
1196 */
1197 switch (enmType)
1198 {
1199 case CPUMDUMPTYPE_TERSE:
1200 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1201 pHlp->pfnPrintf(pHlp,
1202 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1203 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1204 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1205 "%sr14=%016RX64 %sr15=%016RX64\n"
1206 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1207 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1208 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1209 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1210 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1211 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1212 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1213 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1214 else
1215 pHlp->pfnPrintf(pHlp,
1216 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1217 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1218 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1219 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1220 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1221 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1222 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1223 break;
1224
1225 case CPUMDUMPTYPE_DEFAULT:
1226 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1227 pHlp->pfnPrintf(pHlp,
1228 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1229 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1230 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1231 "%sr14=%016RX64 %sr15=%016RX64\n"
1232 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1233 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1234 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1235 ,
1236 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1237 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1238 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1239 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1240 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1241 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1242 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1243 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1244 else
1245 pHlp->pfnPrintf(pHlp,
1246 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1247 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1248 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1249 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1250 ,
1251 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1252 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1253 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1254 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1255 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1256 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1257 break;
1258
1259 case CPUMDUMPTYPE_VERBOSE:
1260 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1261 pHlp->pfnPrintf(pHlp,
1262 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1263 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1264 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1265 "%sr14=%016RX64 %sr15=%016RX64\n"
1266 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1267 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1268 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1269 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1270 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1271 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1272 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1273 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1274 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1275 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1276 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1277 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1278 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1279 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1280 ,
1281 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1282 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1283 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1284 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1285 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1286 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1287 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1288 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1289 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1290 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1291 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1292 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1293 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1294 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1295 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1296 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1297 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1298 else
1299 pHlp->pfnPrintf(pHlp,
1300 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1301 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1302 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1303 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1304 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1305 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1306 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1307 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1308 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1309 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1310 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1311 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1312 ,
1313 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1314 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1315 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1316 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1317 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1318 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1319 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1320 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1321 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1322 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1323 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1324 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1325
1326 pHlp->pfnPrintf(pHlp,
1327 "FPU:\n"
1328 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1329 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1330 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1331 ,
1332 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1333 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1334 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1335 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1336
1337 pHlp->pfnPrintf(pHlp,
1338 "MSR:\n"
1339 "%sEFER =%016RX64\n"
1340 "%sPAT =%016RX64\n"
1341 "%sSTAR =%016RX64\n"
1342 "%sCSTAR =%016RX64\n"
1343 "%sLSTAR =%016RX64\n"
1344 "%sSFMASK =%016RX64\n"
1345 "%sKERNELGSBASE =%016RX64\n",
1346 pszPrefix, pCtx->msrEFER,
1347 pszPrefix, pCtx->msrPAT,
1348 pszPrefix, pCtx->msrSTAR,
1349 pszPrefix, pCtx->msrCSTAR,
1350 pszPrefix, pCtx->msrLSTAR,
1351 pszPrefix, pCtx->msrSFMASK,
1352 pszPrefix, pCtx->msrKERNELGSBASE);
1353 break;
1354 }
1355}
1356
1357
1358/**
1359 * Display all cpu states and any other cpum info.
1360 *
1361 * @param pVM VM Handle.
1362 * @param pHlp The info helper functions.
1363 * @param pszArgs Arguments, ignored.
1364 */
1365static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1366{
1367 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1368 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1369 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1370 cpumR3InfoHost(pVM, pHlp, pszArgs);
1371}
1372
1373
1374/**
1375 * Parses the info argument.
1376 *
1377 * The argument starts with 'verbose', 'terse' or 'default' and then
1378 * continues with the comment string.
1379 *
1380 * @param pszArgs The pointer to the argument string.
1381 * @param penmType Where to store the dump type request.
1382 * @param ppszComment Where to store the pointer to the comment string.
1383 */
1384static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1385{
1386 if (!pszArgs)
1387 {
1388 *penmType = CPUMDUMPTYPE_DEFAULT;
1389 *ppszComment = "";
1390 }
1391 else
1392 {
1393 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1394 {
1395 pszArgs += 5;
1396 *penmType = CPUMDUMPTYPE_VERBOSE;
1397 }
1398 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1399 {
1400 pszArgs += 5;
1401 *penmType = CPUMDUMPTYPE_TERSE;
1402 }
1403 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1404 {
1405 pszArgs += 7;
1406 *penmType = CPUMDUMPTYPE_DEFAULT;
1407 }
1408 else
1409 *penmType = CPUMDUMPTYPE_DEFAULT;
1410 *ppszComment = RTStrStripL(pszArgs);
1411 }
1412}
1413
1414
1415/**
1416 * Display the guest cpu state.
1417 *
1418 * @param pVM VM Handle.
1419 * @param pHlp The info helper functions.
1420 * @param pszArgs Arguments, ignored.
1421 */
1422static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1423{
1424 CPUMDUMPTYPE enmType;
1425 const char *pszComment;
1426 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1427
1428 /* @todo SMP support! */
1429 PVMCPU pVCpu = VMMGetCpu(pVM);
1430 if (!pVCpu)
1431 pVCpu = &pVM->aCpus[0];
1432
1433 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1434
1435 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1436 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1437}
1438
1439
1440/**
1441 * Display the current guest instruction
1442 *
1443 * @param pVM VM Handle.
1444 * @param pHlp The info helper functions.
1445 * @param pszArgs Arguments, ignored.
1446 */
1447static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1448{
1449 char szInstruction[256];
1450 /* @todo SMP support! */
1451 PVMCPU pVCpu = VMMGetCpu(pVM);
1452 if (!pVCpu)
1453 pVCpu = &pVM->aCpus[0];
1454
1455 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1456 if (RT_SUCCESS(rc))
1457 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1458}
1459
1460
1461/**
1462 * Display the hypervisor cpu state.
1463 *
1464 * @param pVM VM Handle.
1465 * @param pHlp The info helper functions.
1466 * @param pszArgs Arguments, ignored.
1467 */
1468static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1469{
1470 CPUMDUMPTYPE enmType;
1471 const char *pszComment;
1472 /* @todo SMP */
1473 PVMCPU pVCpu = &pVM->aCpus[0];
1474
1475 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1476 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1477 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1478 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1479}
1480
1481
1482/**
1483 * Display the host cpu state.
1484 *
1485 * @param pVM VM Handle.
1486 * @param pHlp The info helper functions.
1487 * @param pszArgs Arguments, ignored.
1488 */
1489static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1490{
1491 CPUMDUMPTYPE enmType;
1492 const char *pszComment;
1493 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1494 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1495
1496 /*
1497 * Format the EFLAGS.
1498 */
1499 /* @todo SMP */
1500 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1501#if HC_ARCH_BITS == 32
1502 uint32_t efl = pCtx->eflags.u32;
1503#else
1504 uint64_t efl = pCtx->rflags;
1505#endif
1506 char szEFlags[80];
1507 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1508
1509 /*
1510 * Format the registers.
1511 */
1512#if HC_ARCH_BITS == 32
1513# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1514 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1515# endif
1516 {
1517 pHlp->pfnPrintf(pHlp,
1518 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1519 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1520 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1521 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1522 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1523 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1524 ,
1525 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1526 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1527 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1528 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1529 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1530 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1531 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1532 }
1533# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1534 else
1535# endif
1536#endif
1537#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1538 {
1539 pHlp->pfnPrintf(pHlp,
1540 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1541 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1542 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1543 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1544 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1545 "r14=%016RX64 r15=%016RX64\n"
1546 "iopl=%d %31s\n"
1547 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1548 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1549 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1550 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1551 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1552 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1553 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1554 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1555 ,
1556 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1557 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1558 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1559 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1560 pCtx->r11, pCtx->r12, pCtx->r13,
1561 pCtx->r14, pCtx->r15,
1562 X86_EFL_GET_IOPL(efl), szEFlags,
1563 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1564 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1565 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1566 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1567 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1568 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1569 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1570 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1571 }
1572#endif
1573}
1574
1575
1576/**
1577 * Get L1 cache / TLS associativity.
1578 */
1579static const char *getCacheAss(unsigned u, char *pszBuf)
1580{
1581 if (u == 0)
1582 return "res0 ";
1583 if (u == 1)
1584 return "direct";
1585 if (u >= 256)
1586 return "???";
1587
1588 RTStrPrintf(pszBuf, 16, "%d way", u);
1589 return pszBuf;
1590}
1591
1592
1593/**
1594 * Get L2 cache soociativity.
1595 */
1596const char *getL2CacheAss(unsigned u)
1597{
1598 switch (u)
1599 {
1600 case 0: return "off ";
1601 case 1: return "direct";
1602 case 2: return "2 way ";
1603 case 3: return "res3 ";
1604 case 4: return "4 way ";
1605 case 5: return "res5 ";
1606 case 6: return "8 way "; case 7: return "res7 ";
1607 case 8: return "16 way";
1608 case 9: return "res9 ";
1609 case 10: return "res10 ";
1610 case 11: return "res11 ";
1611 case 12: return "res12 ";
1612 case 13: return "res13 ";
1613 case 14: return "res14 ";
1614 case 15: return "fully ";
1615 default:
1616 return "????";
1617 }
1618}
1619
1620
1621/**
1622 * Display the guest CpuId leaves.
1623 *
1624 * @param pVM VM Handle.
1625 * @param pHlp The info helper functions.
1626 * @param pszArgs "terse", "default" or "verbose".
1627 */
1628static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1629{
1630 /*
1631 * Parse the argument.
1632 */
1633 unsigned iVerbosity = 1;
1634 if (pszArgs)
1635 {
1636 pszArgs = RTStrStripL(pszArgs);
1637 if (!strcmp(pszArgs, "terse"))
1638 iVerbosity--;
1639 else if (!strcmp(pszArgs, "verbose"))
1640 iVerbosity++;
1641 }
1642
1643 /*
1644 * Start cracking.
1645 */
1646 CPUMCPUID Host;
1647 CPUMCPUID Guest;
1648 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1649
1650 pHlp->pfnPrintf(pHlp,
1651 " RAW Standard CPUIDs\n"
1652 " Function eax ebx ecx edx\n");
1653 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1654 {
1655 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1656 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1657
1658 pHlp->pfnPrintf(pHlp,
1659 "Gst: %08x %08x %08x %08x %08x%s\n"
1660 "Hst: %08x %08x %08x %08x\n",
1661 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1662 i <= cStdMax ? "" : "*",
1663 Host.eax, Host.ebx, Host.ecx, Host.edx);
1664 }
1665
1666 /*
1667 * If verbose, decode it.
1668 */
1669 if (iVerbosity)
1670 {
1671 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1672 pHlp->pfnPrintf(pHlp,
1673 "Name: %.04s%.04s%.04s\n"
1674 "Supports: 0-%x\n",
1675 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1676 }
1677
1678 /*
1679 * Get Features.
1680 */
1681 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1682 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1683 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1684 if (cStdMax >= 1 && iVerbosity)
1685 {
1686 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1687 uint32_t uEAX = Guest.eax;
1688
1689 pHlp->pfnPrintf(pHlp,
1690 "Family: %d \tExtended: %d \tEffective: %d\n"
1691 "Model: %d \tExtended: %d \tEffective: %d\n"
1692 "Stepping: %d\n"
1693 "APIC ID: %#04x\n"
1694 "Logical CPUs: %d\n"
1695 "CLFLUSH Size: %d\n"
1696 "Brand ID: %#04x\n",
1697 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1698 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1699 ASMGetCpuStepping(uEAX),
1700 (Guest.ebx >> 24) & 0xff,
1701 (Guest.ebx >> 16) & 0xff,
1702 (Guest.ebx >> 8) & 0xff,
1703 (Guest.ebx >> 0) & 0xff);
1704 if (iVerbosity == 1)
1705 {
1706 uint32_t uEDX = Guest.edx;
1707 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1708 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1709 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1710 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1711 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1712 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1713 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1714 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1715 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1716 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1717 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1718 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1719 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1720 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1721 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1722 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1723 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1724 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1725 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1726 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1727 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1728 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1729 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1730 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1731 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1732 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1733 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1734 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1735 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1736 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1737 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1738 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1739 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1740 pHlp->pfnPrintf(pHlp, "\n");
1741
1742 uint32_t uECX = Guest.ecx;
1743 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1744 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1745 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1746 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1747 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1748 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1749 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1750 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1751 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1752 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1753 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1754 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1755 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1756 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1757 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1758 for (unsigned iBit = 14; iBit < 32; iBit++)
1759 if (uECX & RT_BIT(iBit))
1760 pHlp->pfnPrintf(pHlp, " %d", iBit);
1761 pHlp->pfnPrintf(pHlp, "\n");
1762 }
1763 else
1764 {
1765 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1766
1767 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1768 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1769 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1770 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1771
1772 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1773 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1774 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1775 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1776 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1777 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1778 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1779 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1780 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1781 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1782 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1783 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1784 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1785 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1786 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1787 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1788 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1789 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1790 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1791 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1792 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1793 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1794 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1795 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1796 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1797 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1798 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1799 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1800 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1801 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1802 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1803 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1804 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1805
1806 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1807 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1808 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1809 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1810 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1811 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1812 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1813 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1814 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1815 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1816 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1817 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1818 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1819 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1820 }
1821 }
1822 if (cStdMax >= 2 && iVerbosity)
1823 {
1824 /** @todo */
1825 }
1826
1827 /*
1828 * Extended.
1829 * Implemented after AMD specs.
1830 */
1831 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1832
1833 pHlp->pfnPrintf(pHlp,
1834 "\n"
1835 " RAW Extended CPUIDs\n"
1836 " Function eax ebx ecx edx\n");
1837 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1838 {
1839 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1840 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1841
1842 pHlp->pfnPrintf(pHlp,
1843 "Gst: %08x %08x %08x %08x %08x%s\n"
1844 "Hst: %08x %08x %08x %08x\n",
1845 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1846 i <= cExtMax ? "" : "*",
1847 Host.eax, Host.ebx, Host.ecx, Host.edx);
1848 }
1849
1850 /*
1851 * Understandable output
1852 */
1853 if (iVerbosity)
1854 {
1855 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1856 pHlp->pfnPrintf(pHlp,
1857 "Ext Name: %.4s%.4s%.4s\n"
1858 "Ext Supports: 0x80000000-%#010x\n",
1859 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1860 }
1861
1862 if (iVerbosity && cExtMax >= 1)
1863 {
1864 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1865 uint32_t uEAX = Guest.eax;
1866 pHlp->pfnPrintf(pHlp,
1867 "Family: %d \tExtended: %d \tEffective: %d\n"
1868 "Model: %d \tExtended: %d \tEffective: %d\n"
1869 "Stepping: %d\n"
1870 "Brand ID: %#05x\n",
1871 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1872 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1873 ASMGetCpuStepping(uEAX),
1874 Guest.ebx & 0xfff);
1875
1876 if (iVerbosity == 1)
1877 {
1878 uint32_t uEDX = Guest.edx;
1879 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1880 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1881 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1882 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1883 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1884 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1885 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1886 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1887 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1888 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1889 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1890 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1891 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1892 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1893 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1894 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1895 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1896 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1897 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1898 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1899 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1900 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1901 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1902 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1903 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1904 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1905 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1906 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1907 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1908 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1909 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1910 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1911 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1912 pHlp->pfnPrintf(pHlp, "\n");
1913
1914 uint32_t uECX = Guest.ecx;
1915 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1916 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1917 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1918 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1919 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1920 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1921 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1922 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1923 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1924 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1925 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1926 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1927 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1928 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1929 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1930 for (unsigned iBit = 5; iBit < 32; iBit++)
1931 if (uECX & RT_BIT(iBit))
1932 pHlp->pfnPrintf(pHlp, " %d", iBit);
1933 pHlp->pfnPrintf(pHlp, "\n");
1934 }
1935 else
1936 {
1937 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1938
1939 uint32_t uEdxGst = Guest.edx;
1940 uint32_t uEdxHst = Host.edx;
1941 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1942 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1943 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1944 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1945 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1946 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1947 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1948 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1949 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1950 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1951 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1952 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1953 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1954 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1955 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1956 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1957 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1958 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1959 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1960 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1961 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1962 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1963 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1964 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1965 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1966 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1967 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1968 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1969 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1970 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1971 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1972 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1973 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1974
1975 uint32_t uEcxGst = Guest.ecx;
1976 uint32_t uEcxHst = Host.ecx;
1977 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1978 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1979 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1980 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1981 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1982 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1983 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1984 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1985 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1986 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1987 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1988 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1989 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1990 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1991 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1992 }
1993 }
1994
1995 if (iVerbosity && cExtMax >= 2)
1996 {
1997 char szString[4*4*3+1] = {0};
1998 uint32_t *pu32 = (uint32_t *)szString;
1999 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
2000 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
2001 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
2002 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
2003 if (cExtMax >= 3)
2004 {
2005 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
2006 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
2007 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2008 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2009 }
2010 if (cExtMax >= 4)
2011 {
2012 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2013 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2014 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2015 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2016 }
2017 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2018 }
2019
2020 if (iVerbosity && cExtMax >= 5)
2021 {
2022 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2023 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2024 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2025 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2026 char sz1[32];
2027 char sz2[32];
2028
2029 pHlp->pfnPrintf(pHlp,
2030 "TLB 2/4M Instr/Uni: %s %3d entries\n"
2031 "TLB 2/4M Data: %s %3d entries\n",
2032 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2033 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2034 pHlp->pfnPrintf(pHlp,
2035 "TLB 4K Instr/Uni: %s %3d entries\n"
2036 "TLB 4K Data: %s %3d entries\n",
2037 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2038 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2039 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2040 "L1 Instr Cache Lines Per Tag: %d\n"
2041 "L1 Instr Cache Associativity: %s\n"
2042 "L1 Instr Cache Size: %d KB\n",
2043 (uEDX >> 0) & 0xff,
2044 (uEDX >> 8) & 0xff,
2045 getCacheAss((uEDX >> 16) & 0xff, sz1),
2046 (uEDX >> 24) & 0xff);
2047 pHlp->pfnPrintf(pHlp,
2048 "L1 Data Cache Line Size: %d bytes\n"
2049 "L1 Data Cache Lines Per Tag: %d\n"
2050 "L1 Data Cache Associativity: %s\n"
2051 "L1 Data Cache Size: %d KB\n",
2052 (uECX >> 0) & 0xff,
2053 (uECX >> 8) & 0xff,
2054 getCacheAss((uECX >> 16) & 0xff, sz1),
2055 (uECX >> 24) & 0xff);
2056 }
2057
2058 if (iVerbosity && cExtMax >= 6)
2059 {
2060 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2061 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2062 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2063
2064 pHlp->pfnPrintf(pHlp,
2065 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2066 "L2 TLB 2/4M Data: %s %4d entries\n",
2067 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2068 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2069 pHlp->pfnPrintf(pHlp,
2070 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2071 "L2 TLB 4K Data: %s %4d entries\n",
2072 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2073 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2074 pHlp->pfnPrintf(pHlp,
2075 "L2 Cache Line Size: %d bytes\n"
2076 "L2 Cache Lines Per Tag: %d\n"
2077 "L2 Cache Associativity: %s\n"
2078 "L2 Cache Size: %d KB\n",
2079 (uEDX >> 0) & 0xff,
2080 (uEDX >> 8) & 0xf,
2081 getL2CacheAss((uEDX >> 12) & 0xf),
2082 (uEDX >> 16) & 0xffff);
2083 }
2084
2085 if (iVerbosity && cExtMax >= 7)
2086 {
2087 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2088
2089 pHlp->pfnPrintf(pHlp, "APM Features: ");
2090 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2091 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2092 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2093 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2094 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2095 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2096 for (unsigned iBit = 6; iBit < 32; iBit++)
2097 if (uEDX & RT_BIT(iBit))
2098 pHlp->pfnPrintf(pHlp, " %d", iBit);
2099 pHlp->pfnPrintf(pHlp, "\n");
2100 }
2101
2102 if (iVerbosity && cExtMax >= 8)
2103 {
2104 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2105 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2106
2107 pHlp->pfnPrintf(pHlp,
2108 "Physical Address Width: %d bits\n"
2109 "Virtual Address Width: %d bits\n",
2110 (uEAX >> 0) & 0xff,
2111 (uEAX >> 8) & 0xff);
2112 pHlp->pfnPrintf(pHlp,
2113 "Physical Core Count: %d\n",
2114 (uECX >> 0) & 0xff);
2115 }
2116
2117
2118 /*
2119 * Centaur.
2120 */
2121 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2122
2123 pHlp->pfnPrintf(pHlp,
2124 "\n"
2125 " RAW Centaur CPUIDs\n"
2126 " Function eax ebx ecx edx\n");
2127 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2128 {
2129 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2130 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2131
2132 pHlp->pfnPrintf(pHlp,
2133 "Gst: %08x %08x %08x %08x %08x%s\n"
2134 "Hst: %08x %08x %08x %08x\n",
2135 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2136 i <= cCentaurMax ? "" : "*",
2137 Host.eax, Host.ebx, Host.ecx, Host.edx);
2138 }
2139
2140 /*
2141 * Understandable output
2142 */
2143 if (iVerbosity)
2144 {
2145 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2146 pHlp->pfnPrintf(pHlp,
2147 "Centaur Supports: 0xc0000000-%#010x\n",
2148 Guest.eax);
2149 }
2150
2151 if (iVerbosity && cCentaurMax >= 1)
2152 {
2153 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2154 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2155 uint32_t uEdxHst = Host.edx;
2156
2157 if (iVerbosity == 1)
2158 {
2159 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2160 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2161 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2162 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2163 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2164 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2165 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2166 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2167 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2168 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2169 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2170 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2171 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2172 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2173 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2174 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2175 for (unsigned iBit = 14; iBit < 32; iBit++)
2176 if (uEdxGst & RT_BIT(iBit))
2177 pHlp->pfnPrintf(pHlp, " %d", iBit);
2178 pHlp->pfnPrintf(pHlp, "\n");
2179 }
2180 else
2181 {
2182 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2183 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2184 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2185 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2186 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2187 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2188 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2189 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2190 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2191 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2192 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2193 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2194 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2195 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2196 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2197 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2198 for (unsigned iBit = 14; iBit < 32; iBit++)
2199 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2200 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2201 pHlp->pfnPrintf(pHlp, "\n");
2202 }
2203 }
2204}
2205
2206
2207/**
2208 * Structure used when disassembling and instructions in DBGF.
2209 * This is used so the reader function can get the stuff it needs.
2210 */
2211typedef struct CPUMDISASSTATE
2212{
2213 /** Pointer to the CPU structure. */
2214 PDISCPUSTATE pCpu;
2215 /** The VM handle. */
2216 PVM pVM;
2217 /** The VMCPU handle. */
2218 PVMCPU pVCpu;
2219 /** Pointer to the first byte in the segemnt. */
2220 RTGCUINTPTR GCPtrSegBase;
2221 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2222 RTGCUINTPTR GCPtrSegEnd;
2223 /** The size of the segment minus 1. */
2224 RTGCUINTPTR cbSegLimit;
2225 /** Pointer to the current page - R3 Ptr. */
2226 void const *pvPageR3;
2227 /** Pointer to the current page - GC Ptr. */
2228 RTGCPTR pvPageGC;
2229 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2230 PGMPAGEMAPLOCK PageMapLock;
2231 /** Whether the PageMapLock is valid or not. */
2232 bool fLocked;
2233 /** 64 bits mode or not. */
2234 bool f64Bits;
2235} CPUMDISASSTATE, *PCPUMDISASSTATE;
2236
2237
2238/**
2239 * Instruction reader.
2240 *
2241 * @returns VBox status code.
2242 * @param PtrSrc Address to read from.
2243 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2244 * @param pu8Dst Where to store the bytes.
2245 * @param cbRead Number of bytes to read.
2246 * @param uDisCpu Pointer to the disassembler cpu state.
2247 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2248 */
2249static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2250{
2251 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2252 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2253 Assert(cbRead > 0);
2254 for (;;)
2255 {
2256 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2257
2258 /* Need to update the page translation? */
2259 if ( !pState->pvPageR3
2260 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2261 {
2262 int rc = VINF_SUCCESS;
2263
2264 /* translate the address */
2265 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2266 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2267 && !HWACCMIsEnabled(pState->pVM))
2268 {
2269 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2270 if (!pState->pvPageR3)
2271 rc = VERR_INVALID_POINTER;
2272 }
2273 else
2274 {
2275 /* Release mapping lock previously acquired. */
2276 if (pState->fLocked)
2277 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2278 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2279 pState->fLocked = RT_SUCCESS_NP(rc);
2280 }
2281 if (RT_FAILURE(rc))
2282 {
2283 pState->pvPageR3 = NULL;
2284 return rc;
2285 }
2286 }
2287
2288 /* check the segemnt limit */
2289 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2290 return VERR_OUT_OF_SELECTOR_BOUNDS;
2291
2292 /* calc how much we can read */
2293 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2294 if (!pState->f64Bits)
2295 {
2296 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2297 if (cb > cbSeg && cbSeg)
2298 cb = cbSeg;
2299 }
2300 if (cb > cbRead)
2301 cb = cbRead;
2302
2303 /* read and advance */
2304 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2305 cbRead -= cb;
2306 if (!cbRead)
2307 return VINF_SUCCESS;
2308 pu8Dst += cb;
2309 PtrSrc += cb;
2310 }
2311}
2312
2313
2314/**
2315 * Disassemble an instruction and return the information in the provided structure.
2316 *
2317 * @returns VBox status code.
2318 * @param pVM VM Handle
2319 * @param pVCpu VMCPU Handle
2320 * @param pCtx CPU context
2321 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2322 * @param pCpu Disassembly state
2323 * @param pszPrefix String prefix for logging (debug only)
2324 *
2325 */
2326VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2327{
2328 CPUMDISASSTATE State;
2329 int rc;
2330
2331 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2332 State.pCpu = pCpu;
2333 State.pvPageGC = 0;
2334 State.pvPageR3 = NULL;
2335 State.pVM = pVM;
2336 State.pVCpu = pVCpu;
2337 State.fLocked = false;
2338 State.f64Bits = false;
2339
2340 /*
2341 * Get selector information.
2342 */
2343 if ( (pCtx->cr0 & X86_CR0_PE)
2344 && pCtx->eflags.Bits.u1VM == 0)
2345 {
2346 if (CPUMAreHiddenSelRegsValid(pVM))
2347 {
2348 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2349 State.GCPtrSegBase = pCtx->csHid.u64Base;
2350 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2351 State.cbSegLimit = pCtx->csHid.u32Limit;
2352 pCpu->mode = (State.f64Bits)
2353 ? CPUMODE_64BIT
2354 : pCtx->csHid.Attr.n.u1DefBig
2355 ? CPUMODE_32BIT
2356 : CPUMODE_16BIT;
2357 }
2358 else
2359 {
2360 DBGFSELINFO SelInfo;
2361
2362 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2363 if (RT_FAILURE(rc))
2364 {
2365 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2366 return rc;
2367 }
2368
2369 /*
2370 * Validate the selector.
2371 */
2372 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2373 if (RT_FAILURE(rc))
2374 {
2375 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2376 return rc;
2377 }
2378 State.GCPtrSegBase = SelInfo.GCPtrBase;
2379 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2380 State.cbSegLimit = SelInfo.cbLimit;
2381 pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2382 }
2383 }
2384 else
2385 {
2386 /* real or V86 mode */
2387 pCpu->mode = CPUMODE_16BIT;
2388 State.GCPtrSegBase = pCtx->cs * 16;
2389 State.GCPtrSegEnd = 0xFFFFFFFF;
2390 State.cbSegLimit = 0xFFFFFFFF;
2391 }
2392
2393 /*
2394 * Disassemble the instruction.
2395 */
2396 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2397 pCpu->apvUserData[0] = &State;
2398
2399 uint32_t cbInstr;
2400#ifndef LOG_ENABLED
2401 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2402 if (RT_SUCCESS(rc))
2403 {
2404#else
2405 char szOutput[160];
2406 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2407 if (RT_SUCCESS(rc))
2408 {
2409 /* log it */
2410 if (pszPrefix)
2411 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2412 else
2413 Log(("%s", szOutput));
2414#endif
2415 rc = VINF_SUCCESS;
2416 }
2417 else
2418 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2419
2420 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2421 if (State.fLocked)
2422 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2423
2424 return rc;
2425}
2426
2427#ifdef DEBUG
2428
2429/**
2430 * Disassemble an instruction and dump it to the log
2431 *
2432 * @returns VBox status code.
2433 * @param pVM VM Handle
2434 * @param pVCpu VMCPU Handle
2435 * @param pCtx CPU context
2436 * @param pc GC instruction pointer
2437 * @param pszPrefix String prefix for logging
2438 *
2439 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2440 */
2441VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2442{
2443 DISCPUSTATE Cpu;
2444 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2445}
2446
2447
2448/**
2449 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2450 *
2451 * @internal
2452 */
2453VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2454{
2455 /* @todo SMP support!! */
2456 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2457}
2458
2459#endif /* DEBUG */
2460
2461/**
2462 * API for controlling a few of the CPU features found in CR4.
2463 *
2464 * Currently only X86_CR4_TSD is accepted as input.
2465 *
2466 * @returns VBox status code.
2467 *
2468 * @param pVM The VM handle.
2469 * @param fOr The CR4 OR mask.
2470 * @param fAnd The CR4 AND mask.
2471 */
2472VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2473{
2474 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2475 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2476
2477 pVM->cpum.s.CR4.OrMask &= fAnd;
2478 pVM->cpum.s.CR4.OrMask |= fOr;
2479
2480 return VINF_SUCCESS;
2481}
2482
2483
2484/**
2485 * Gets a pointer to the array of standard CPUID leafs.
2486 *
2487 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2488 *
2489 * @returns Pointer to the standard CPUID leafs (read-only).
2490 * @param pVM The VM handle.
2491 * @remark Intended for PATM.
2492 */
2493VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2494{
2495 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2496}
2497
2498
2499/**
2500 * Gets a pointer to the array of extended CPUID leafs.
2501 *
2502 * CPUMGetGuestCpuIdExtMax() give the size of the array.
2503 *
2504 * @returns Pointer to the extended CPUID leafs (read-only).
2505 * @param pVM The VM handle.
2506 * @remark Intended for PATM.
2507 */
2508VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2509{
2510 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2511}
2512
2513
2514/**
2515 * Gets a pointer to the array of centaur CPUID leafs.
2516 *
2517 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2518 *
2519 * @returns Pointer to the centaur CPUID leafs (read-only).
2520 * @param pVM The VM handle.
2521 * @remark Intended for PATM.
2522 */
2523VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2524{
2525 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2526}
2527
2528
2529/**
2530 * Gets a pointer to the default CPUID leaf.
2531 *
2532 * @returns Pointer to the default CPUID leaf (read-only).
2533 * @param pVM The VM handle.
2534 * @remark Intended for PATM.
2535 */
2536VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2537{
2538 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2539}
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette