VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 20481

Last change on this file since 20481 was 20463, checked in by vboxsync, 16 years ago

Don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR to the guest
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1/* $Id: CPUM.cpp 20463 2009-06-10 12:25:23Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65/* Enable multi-core VCPUs. */
66#define VBOX_WITH_MULTI_CORE
67
68/*******************************************************************************
69* Defined Constants And Macros *
70*******************************************************************************/
71/** The saved state version. */
72#define CPUM_SAVED_STATE_VERSION 10
73/** The saved state version for the 2.1 trunk before the MSR changes. */
74#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
75/** The saved state version of 2.0, used for backwards compatibility. */
76#define CPUM_SAVED_STATE_VERSION_VER2_0 8
77/** The saved state version of 1.6, used for backwards compatability. */
78#define CPUM_SAVED_STATE_VERSION_VER1_6 6
79
80
81/*******************************************************************************
82* Structures and Typedefs *
83*******************************************************************************/
84
85/**
86 * What kind of cpu info dump to perform.
87 */
88typedef enum CPUMDUMPTYPE
89{
90 CPUMDUMPTYPE_TERSE,
91 CPUMDUMPTYPE_DEFAULT,
92 CPUMDUMPTYPE_VERBOSE
93
94} CPUMDUMPTYPE;
95/** Pointer to a cpu info dump type. */
96typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
97
98
99/*******************************************************************************
100* Internal Functions *
101*******************************************************************************/
102static int cpumR3CpuIdInit(PVM pVM);
103static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
104static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
105static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111
112
113/**
114 * Initializes the CPUM.
115 *
116 * @returns VBox status code.
117 * @param pVM The VM to operate on.
118 */
119VMMR3DECL(int) CPUMR3Init(PVM pVM)
120{
121 LogFlow(("CPUMR3Init\n"));
122
123 /*
124 * Assert alignment and sizes.
125 */
126 AssertCompileMemberAlignment(VM, cpum.s, 32);
127 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
128 AssertCompileSizeAlignment(CPUMCTX, 64);
129 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
130 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
131 AssertCompileMemberAlignment(VM, cpum, 64);
132 AssertCompileMemberAlignment(VM, aCpus, 64);
133 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
134 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
135
136 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
137 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
138 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
139
140 /* Calculate the offset from CPUMCPU to CPUM. */
141 for (unsigned i=0;i<pVM->cCPUs;i++)
142 {
143 PVMCPU pVCpu = &pVM->aCpus[i];
144
145 /*
146 * Setup any fixed pointers and offsets.
147 */
148 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
149 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
150
151 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
152 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
153 }
154
155 /*
156 * Check that the CPU supports the minimum features we require.
157 */
158 if (!ASMHasCpuId())
159 {
160 Log(("The CPU doesn't support CPUID!\n"));
161 return VERR_UNSUPPORTED_CPU;
162 }
163 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
164 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
165
166 /* Setup the CR4 AND and OR masks used in the switcher */
167 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
168 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
169 {
170 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
171 /* No FXSAVE implies no SSE */
172 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
173 pVM->cpum.s.CR4.OrMask = 0;
174 }
175 else
176 {
177 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
178 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
179 }
180
181 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
182 {
183 Log(("The CPU doesn't support MMX!\n"));
184 return VERR_UNSUPPORTED_CPU;
185 }
186 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
187 {
188 Log(("The CPU doesn't support TSC!\n"));
189 return VERR_UNSUPPORTED_CPU;
190 }
191 /* Bogus on AMD? */
192 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
193 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
194
195 /*
196 * Setup hypervisor startup values.
197 */
198
199 /*
200 * Register saved state data item.
201 */
202 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
203 NULL, cpumR3Save, NULL,
204 NULL, cpumR3Load, NULL);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 /* Query the CPU manufacturer. */
209 uint32_t uEAX, uEBX, uECX, uEDX;
210 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
211 if ( uEAX >= 1
212 && uEBX == X86_CPUID_VENDOR_AMD_EBX
213 && uECX == X86_CPUID_VENDOR_AMD_ECX
214 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
215 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
216 else if ( uEAX >= 1
217 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
218 && uECX == X86_CPUID_VENDOR_INTEL_ECX
219 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
220 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
221 else /** @todo Via */
222 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
223
224 /*
225 * Register info handlers.
226 */
227 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
228 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
229 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
230 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
231 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
232 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
233
234 /*
235 * Initialize the Guest CPU state.
236 */
237 rc = cpumR3CpuIdInit(pVM);
238 if (RT_FAILURE(rc))
239 return rc;
240 CPUMR3Reset(pVM);
241 return VINF_SUCCESS;
242}
243
244
245/**
246 * Initializes the per-VCPU CPUM.
247 *
248 * @returns VBox status code.
249 * @param pVM The VM to operate on.
250 */
251VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
252{
253 LogFlow(("CPUMR3InitCPU\n"));
254 return VINF_SUCCESS;
255}
256
257
258/**
259 * Initializes the emulated CPU's cpuid information.
260 *
261 * @returns VBox status code.
262 * @param pVM The VM to operate on.
263 */
264static int cpumR3CpuIdInit(PVM pVM)
265{
266 PCPUM pCPUM = &pVM->cpum.s;
267 uint32_t i;
268
269 /*
270 * Get the host CPUIDs.
271 */
272 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
273 ASMCpuId_Idx_ECX(i, 0,
274 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
275 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
276 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
277 ASMCpuId(0x80000000 + i,
278 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
279 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
280 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
281 ASMCpuId(0xc0000000 + i,
282 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
283 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
284
285
286 /*
287 * Only report features we can support.
288 */
289 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
290 | X86_CPUID_FEATURE_EDX_VME
291 | X86_CPUID_FEATURE_EDX_DE
292 | X86_CPUID_FEATURE_EDX_PSE
293 | X86_CPUID_FEATURE_EDX_TSC
294 | X86_CPUID_FEATURE_EDX_MSR
295 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
296 | X86_CPUID_FEATURE_EDX_MCE
297 | X86_CPUID_FEATURE_EDX_CX8
298 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
299 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
300 //| X86_CPUID_FEATURE_EDX_SEP
301 | X86_CPUID_FEATURE_EDX_MTRR
302 | X86_CPUID_FEATURE_EDX_PGE
303 | X86_CPUID_FEATURE_EDX_MCA
304 | X86_CPUID_FEATURE_EDX_CMOV
305 | X86_CPUID_FEATURE_EDX_PAT
306 | X86_CPUID_FEATURE_EDX_PSE36
307 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
308 | X86_CPUID_FEATURE_EDX_CLFSH
309 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
310 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
311 | X86_CPUID_FEATURE_EDX_MMX
312 | X86_CPUID_FEATURE_EDX_FXSR
313 | X86_CPUID_FEATURE_EDX_SSE
314 | X86_CPUID_FEATURE_EDX_SSE2
315 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
316 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
317 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
318 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
319 | 0;
320 pCPUM->aGuestCpuIdStd[1].ecx &= 0
321 | X86_CPUID_FEATURE_ECX_SSE3
322 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
323 | ((pVM->cCPUs == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
324 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
325 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
326 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
327 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
328 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
329 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
330 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
331 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
332 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
333 /* ECX Bit 21 - x2APIC support - not yet. */
334 // | X86_CPUID_FEATURE_ECX_X2APIC
335 /* ECX Bit 23 - POPCOUNT instruction. */
336 //| X86_CPUID_FEATURE_ECX_POPCOUNT
337 | 0;
338
339 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
340 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
341 | X86_CPUID_AMD_FEATURE_EDX_VME
342 | X86_CPUID_AMD_FEATURE_EDX_DE
343 | X86_CPUID_AMD_FEATURE_EDX_PSE
344 | X86_CPUID_AMD_FEATURE_EDX_TSC
345 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
346 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
347 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
348 | X86_CPUID_AMD_FEATURE_EDX_CX8
349 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
350 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
351 //| X86_CPUID_AMD_FEATURE_EDX_SEP
352 | X86_CPUID_AMD_FEATURE_EDX_MTRR
353 | X86_CPUID_AMD_FEATURE_EDX_PGE
354 | X86_CPUID_AMD_FEATURE_EDX_MCA
355 | X86_CPUID_AMD_FEATURE_EDX_CMOV
356 | X86_CPUID_AMD_FEATURE_EDX_PAT
357 | X86_CPUID_AMD_FEATURE_EDX_PSE36
358 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
359 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
360 | X86_CPUID_AMD_FEATURE_EDX_MMX
361 | X86_CPUID_AMD_FEATURE_EDX_FXSR
362 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
363 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
364 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
365 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
366 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
367 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
368 | 0;
369 pCPUM->aGuestCpuIdExt[1].ecx &= 0
370 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
371 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
372 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
373 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
374 /** Note: This could prevent migration from AMD to Intel CPUs! */
375 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
376 //| X86_CPUID_AMD_FEATURE_ECX_ABM
377 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
378 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
379 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
380 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
381 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
382 //| X86_CPUID_AMD_FEATURE_ECX_WDT
383 | 0;
384
385 /*
386 * Hide HTT, multicode, SMP, whatever.
387 * (APIC-ID := 0 and #LogCpus := 0)
388 */
389 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
390#ifdef VBOX_WITH_MULTI_CORE
391 if (pVM->cCPUs > 1)
392 {
393 /* Set the Maximum number of addressable IDs for logical processors in this physical package (bits 16-23) */
394 pCPUM->aGuestCpuIdStd[1].ebx |= ((pVM->cCPUs - 1) << 16);
395 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
396 }
397#endif
398
399 /* Cpuid 2:
400 * Intel: Cache and TLB information
401 * AMD: Reserved
402 * Safe to expose
403 */
404
405 /* Cpuid 3:
406 * Intel: EAX, EBX - reserved
407 * ECX, EDX - Processor Serial Number if available, otherwise reserved
408 * AMD: Reserved
409 * Safe to expose
410 */
411 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
412 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
413
414 /* Cpuid 4:
415 * Intel: Deterministic Cache Parameters Leaf
416 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
417 * AMD: Reserved
418 * Safe to expose, except for EAX:
419 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
420 * Bits 31-26: Maximum number of processor cores in this physical package**
421 * @Note These SMP values are constant regardless of ECX
422 */
423 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
424 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
425#ifdef VBOX_WITH_MULTI_CORE
426 if ( pVM->cCPUs > 1
427 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_INTEL)
428 {
429 AssertReturn(pVM->cCPUs <= 64, VERR_TOO_MANY_CPUS);
430 /* One logical processor with possibly multiple cores. */
431 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCPUs - 1) << 26); /* 6 bits only -> 64 cores! */
432 }
433#endif
434
435 /* Cpuid 5: Monitor/mwait Leaf
436 * Intel: ECX, EDX - reserved
437 * EAX, EBX - Smallest and largest monitor line size
438 * AMD: EDX - reserved
439 * EAX, EBX - Smallest and largest monitor line size
440 * ECX - extensions (ignored for now)
441 * Safe to expose
442 */
443 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
444 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
445
446 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
447
448 /*
449 * Determine the default.
450 *
451 * Intel returns values of the highest standard function, while AMD
452 * returns zeros. VIA on the other hand seems to returning nothing or
453 * perhaps some random garbage, we don't try to duplicate this behavior.
454 */
455 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
456 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
457 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
458
459 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
460 * Safe to pass on to the guest.
461 *
462 * Intel: 0x800000005 reserved
463 * 0x800000006 L2 cache information
464 * AMD: 0x800000005 L1 cache information
465 * 0x800000006 L2/L3 cache information
466 */
467
468 /* Cpuid 0x800000007:
469 * AMD: EAX, EBX, ECX - reserved
470 * EDX: Advanced Power Management Information
471 * Intel: Reserved
472 */
473 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
474 {
475 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
476
477 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
478
479 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
480 {
481 /* Only expose the TSC invariant capability bit to the guest. */
482 pCPUM->aGuestCpuIdExt[7].edx &= 0
483 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
484 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
485 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
486 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
487 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
488 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
489 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
490 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
491#if 1
492 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
493 * that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
494 */
495#else
496 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
497#endif
498 | 0;
499 }
500 else
501 pCPUM->aGuestCpuIdExt[7].edx = 0;
502 }
503
504 /* Cpuid 0x800000008:
505 * AMD: EBX, EDX - reserved
506 * EAX: Virtual/Physical address Size
507 * ECX: Number of cores + APICIdCoreIdSize
508 * Intel: EAX: Virtual/Physical address Size
509 * EBX, ECX, EDX - reserved
510 */
511 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
512 {
513 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
514 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
515 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
516 * NC (0-7) Number of cores; 0 equals 1 core */
517 pCPUM->aGuestCpuIdExt[8].ecx = 0;
518#ifdef VBOX_WITH_MULTI_CORE
519 if ( pVM->cCPUs > 1
520 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
521 {
522 /* Legacy method to determine the number of cores. */
523 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
524 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCPUs - 1); /* NC: Number of CPU cores - 1; 8 bits */
525
526 }
527#endif
528 }
529
530 /*
531 * Limit it the number of entries and fill the remaining with the defaults.
532 *
533 * The limits are masking off stuff about power saving and similar, this
534 * is perhaps a bit crudely done as there is probably some relatively harmless
535 * info too in these leaves (like words about having a constant TSC).
536 */
537#if 0
538 /** @todo NT4 installation regression - investigate */
539 /** Note from Intel manuals:
540 * CPUID leaves > 3 < 80000000 are visible only when
541 * IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default).
542 *
543 */
544 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
545 pCPUM->aGuestCpuIdStd[0].eax = 5;
546#else
547 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
548 pCPUM->aGuestCpuIdStd[0].eax = 2;
549#endif
550 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
551 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
552
553 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
554 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
555 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
556 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
557 : 0;
558 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
559 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
560
561 /*
562 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
563 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
564 * We currently don't support more than 1 processor.
565 */
566 pCPUM->aGuestCpuIdStd[4].eax = 0;
567
568 /*
569 * Centaur stuff (VIA).
570 *
571 * The important part here (we think) is to make sure the 0xc0000000
572 * function returns 0xc0000001. As for the features, we don't currently
573 * let on about any of those... 0xc0000002 seems to be some
574 * temperature/hz/++ stuff, include it as well (static).
575 */
576 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
577 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
578 {
579 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
580 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
581 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
582 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
583 i++)
584 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
585 }
586 else
587 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
588 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
589
590
591 /*
592 * Load CPUID overrides from configuration.
593 */
594 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
595 * Overloads the CPUID leaf values. */
596 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
597 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
598 for (i=0;; )
599 {
600 while (cElements-- > 0)
601 {
602 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
603 if (pNode)
604 {
605 uint32_t u32;
606 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
607 if (RT_SUCCESS(rc))
608 pCpuId->eax = u32;
609 else
610 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
611
612 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
613 if (RT_SUCCESS(rc))
614 pCpuId->ebx = u32;
615 else
616 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
617
618 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
619 if (RT_SUCCESS(rc))
620 pCpuId->ecx = u32;
621 else
622 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
623
624 rc = CFGMR3QueryU32(pNode, "edx", &u32);
625 if (RT_SUCCESS(rc))
626 pCpuId->edx = u32;
627 else
628 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
629 }
630 pCpuId++;
631 i++;
632 }
633
634 /* next */
635 if ((i & UINT32_C(0xc0000000)) == 0)
636 {
637 pCpuId = &pCPUM->aGuestCpuIdExt[0];
638 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
639 i = UINT32_C(0x80000000);
640 }
641 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
642 {
643 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
644 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
645 i = UINT32_C(0xc0000000);
646 }
647 else
648 break;
649 }
650
651 /* Check if PAE was explicitely enabled by the user. */
652 bool fEnable = false;
653 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
654 if (RT_SUCCESS(rc) && fEnable)
655 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
656
657 /*
658 * Log the cpuid and we're good.
659 */
660 RTCPUSET OnlineSet;
661 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
662 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
663 LogRel(("************************* CPUID dump ************************\n"));
664 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
665 LogRel(("\n"));
666 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
667 LogRel(("******************** End of CPUID dump **********************\n"));
668 return VINF_SUCCESS;
669}
670
671
672
673
674/**
675 * Applies relocations to data and code managed by this
676 * component. This function will be called at init and
677 * whenever the VMM need to relocate it self inside the GC.
678 *
679 * The CPUM will update the addresses used by the switcher.
680 *
681 * @param pVM The VM.
682 */
683VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
684{
685 LogFlow(("CPUMR3Relocate\n"));
686 for (unsigned i=0;i<pVM->cCPUs;i++)
687 {
688 PVMCPU pVCpu = &pVM->aCpus[i];
689 /*
690 * Switcher pointers.
691 */
692 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
693 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
694 }
695}
696
697
698/**
699 * Terminates the CPUM.
700 *
701 * Termination means cleaning up and freeing all resources,
702 * the VM it self is at this point powered off or suspended.
703 *
704 * @returns VBox status code.
705 * @param pVM The VM to operate on.
706 */
707VMMR3DECL(int) CPUMR3Term(PVM pVM)
708{
709 CPUMR3TermCPU(pVM);
710 return 0;
711}
712
713
714/**
715 * Terminates the per-VCPU CPUM.
716 *
717 * Termination means cleaning up and freeing all resources,
718 * the VM it self is at this point powered off or suspended.
719 *
720 * @returns VBox status code.
721 * @param pVM The VM to operate on.
722 */
723VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
724{
725#ifdef VBOX_WITH_CRASHDUMP_MAGIC
726 for (unsigned i=0;i<pVM->cCPUs;i++)
727 {
728 PVMCPU pVCpu = &pVM->aCpus[i];
729 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
730
731 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
732 pVCpu->cpum.s.uMagic = 0;
733 pCtx->dr[5] = 0;
734 }
735#endif
736 return 0;
737}
738
739VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
740{
741 /* @todo anything different for VCPU > 0? */
742 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
743
744 /*
745 * Initialize everything to ZERO first.
746 */
747 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
748 memset(pCtx, 0, sizeof(*pCtx));
749 pVCpu->cpum.s.fUseFlags = fUseFlags;
750
751 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
752 pCtx->eip = 0x0000fff0;
753 pCtx->edx = 0x00000600; /* P6 processor */
754 pCtx->eflags.Bits.u1Reserved0 = 1;
755
756 pCtx->cs = 0xf000;
757 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
758 pCtx->csHid.u32Limit = 0x0000ffff;
759 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
760 pCtx->csHid.Attr.n.u1Present = 1;
761 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
762
763 pCtx->dsHid.u32Limit = 0x0000ffff;
764 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
765 pCtx->dsHid.Attr.n.u1Present = 1;
766 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
767
768 pCtx->esHid.u32Limit = 0x0000ffff;
769 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
770 pCtx->esHid.Attr.n.u1Present = 1;
771 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
772
773 pCtx->fsHid.u32Limit = 0x0000ffff;
774 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
775 pCtx->fsHid.Attr.n.u1Present = 1;
776 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
777
778 pCtx->gsHid.u32Limit = 0x0000ffff;
779 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
780 pCtx->gsHid.Attr.n.u1Present = 1;
781 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
782
783 pCtx->ssHid.u32Limit = 0x0000ffff;
784 pCtx->ssHid.Attr.n.u1Present = 1;
785 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
786 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
787
788 pCtx->idtr.cbIdt = 0xffff;
789 pCtx->gdtr.cbGdt = 0xffff;
790
791 pCtx->ldtrHid.u32Limit = 0xffff;
792 pCtx->ldtrHid.Attr.n.u1Present = 1;
793 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
794
795 pCtx->trHid.u32Limit = 0xffff;
796 pCtx->trHid.Attr.n.u1Present = 1;
797 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
798
799 pCtx->dr[6] = X86_DR6_INIT_VAL;
800 pCtx->dr[7] = X86_DR7_INIT_VAL;
801
802 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
803 pCtx->fpu.FCW = 0x37f;
804
805 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
806 pCtx->fpu.MXCSR = 0x1F80;
807
808 /* Init PAT MSR */
809 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
810
811 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
812 * The Intel docs don't mention it.
813 */
814 pCtx->msrEFER = 0;
815}
816
817/**
818 * Resets the CPU.
819 *
820 * @returns VINF_SUCCESS.
821 * @param pVM The VM handle.
822 */
823VMMR3DECL(void) CPUMR3Reset(PVM pVM)
824{
825 for (unsigned i=0;i<pVM->cCPUs;i++)
826 {
827 CPUMR3ResetCpu(&pVM->aCpus[i]);
828
829#ifdef VBOX_WITH_CRASHDUMP_MAGIC
830 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
831
832 /* Magic marker for searching in crash dumps. */
833 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
834 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
835 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
836#endif
837 }
838}
839
840
841/**
842 * Execute state save operation.
843 *
844 * @returns VBox status code.
845 * @param pVM VM Handle.
846 * @param pSSM SSM operation handle.
847 */
848static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
849{
850 /*
851 * Save.
852 */
853 for (unsigned i=0;i<pVM->cCPUs;i++)
854 {
855 PVMCPU pVCpu = &pVM->aCpus[i];
856
857 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
858 }
859
860 SSMR3PutU32(pSSM, pVM->cCPUs);
861 for (unsigned i=0;i<pVM->cCPUs;i++)
862 {
863 PVMCPU pVCpu = &pVM->aCpus[i];
864
865 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
866 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
867 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
868 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
869 }
870
871 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
872 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
873
874 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
875 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
876
877 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
878 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
879
880 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
881
882 /* Add the cpuid for checking that the cpu is unchanged. */
883 uint32_t au32CpuId[8] = {0};
884 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
885 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
886 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
887}
888
889
890/**
891 * Load a version 1.6 CPUMCTX structure.
892 *
893 * @returns VBox status code.
894 * @param pVM VM Handle.
895 * @param pCpumctx16 Version 1.6 CPUMCTX
896 */
897static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
898{
899#define CPUMCTX16_LOADREG(RegName) \
900 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
901
902#define CPUMCTX16_LOADDRXREG(RegName) \
903 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
904
905#define CPUMCTX16_LOADHIDREG(RegName) \
906 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
907 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
908 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
909
910#define CPUMCTX16_LOADSEGREG(RegName) \
911 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
912 CPUMCTX16_LOADHIDREG(RegName);
913
914 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
915
916 CPUMCTX16_LOADREG(rax);
917 CPUMCTX16_LOADREG(rbx);
918 CPUMCTX16_LOADREG(rcx);
919 CPUMCTX16_LOADREG(rdx);
920 CPUMCTX16_LOADREG(rdi);
921 CPUMCTX16_LOADREG(rsi);
922 CPUMCTX16_LOADREG(rbp);
923 CPUMCTX16_LOADREG(esp);
924 CPUMCTX16_LOADREG(rip);
925 CPUMCTX16_LOADREG(rflags);
926
927 CPUMCTX16_LOADSEGREG(cs);
928 CPUMCTX16_LOADSEGREG(ds);
929 CPUMCTX16_LOADSEGREG(es);
930 CPUMCTX16_LOADSEGREG(fs);
931 CPUMCTX16_LOADSEGREG(gs);
932 CPUMCTX16_LOADSEGREG(ss);
933
934 CPUMCTX16_LOADREG(r8);
935 CPUMCTX16_LOADREG(r9);
936 CPUMCTX16_LOADREG(r10);
937 CPUMCTX16_LOADREG(r11);
938 CPUMCTX16_LOADREG(r12);
939 CPUMCTX16_LOADREG(r13);
940 CPUMCTX16_LOADREG(r14);
941 CPUMCTX16_LOADREG(r15);
942
943 CPUMCTX16_LOADREG(cr0);
944 CPUMCTX16_LOADREG(cr2);
945 CPUMCTX16_LOADREG(cr3);
946 CPUMCTX16_LOADREG(cr4);
947
948 CPUMCTX16_LOADDRXREG(0);
949 CPUMCTX16_LOADDRXREG(1);
950 CPUMCTX16_LOADDRXREG(2);
951 CPUMCTX16_LOADDRXREG(3);
952 CPUMCTX16_LOADDRXREG(4);
953 CPUMCTX16_LOADDRXREG(5);
954 CPUMCTX16_LOADDRXREG(6);
955 CPUMCTX16_LOADDRXREG(7);
956
957 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
958 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
959 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
960 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
961
962 CPUMCTX16_LOADREG(ldtr);
963 CPUMCTX16_LOADREG(tr);
964
965 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
966
967 CPUMCTX16_LOADREG(msrEFER);
968 CPUMCTX16_LOADREG(msrSTAR);
969 CPUMCTX16_LOADREG(msrPAT);
970 CPUMCTX16_LOADREG(msrLSTAR);
971 CPUMCTX16_LOADREG(msrCSTAR);
972 CPUMCTX16_LOADREG(msrSFMASK);
973 CPUMCTX16_LOADREG(msrKERNELGSBASE);
974
975 CPUMCTX16_LOADHIDREG(ldtr);
976 CPUMCTX16_LOADHIDREG(tr);
977
978#undef CPUMCTX16_LOADSEGREG
979#undef CPUMCTX16_LOADHIDREG
980#undef CPUMCTX16_LOADDRXREG
981#undef CPUMCTX16_LOADREG
982}
983
984
985/**
986 * Execute state load operation.
987 *
988 * @returns VBox status code.
989 * @param pVM VM Handle.
990 * @param pSSM SSM operation handle.
991 * @param u32Version Data layout version.
992 */
993static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
994{
995 /*
996 * Validate version.
997 */
998 if ( u32Version != CPUM_SAVED_STATE_VERSION
999 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1000 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
1001 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
1002 {
1003 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
1004 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1005 }
1006
1007 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
1008 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1009 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1010 else if (u32Version <= CPUM_SAVED_STATE_VERSION)
1011 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1012
1013 /*
1014 * Restore.
1015 */
1016 for (unsigned i=0;i<pVM->cCPUs;i++)
1017 {
1018 PVMCPU pVCpu = &pVM->aCpus[i];
1019 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1020 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1021
1022 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1023 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1024 pVCpu->cpum.s.Hyper.esp = uESP;
1025 }
1026
1027 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1028 {
1029 CPUMCTX_VER1_6 cpumctx16;
1030 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1031 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1032
1033 /* Save the old cpumctx state into the new one. */
1034 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1035
1036 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1037 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1038 }
1039 else
1040 {
1041 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1042 {
1043 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
1044 AssertRCReturn(rc, rc);
1045 }
1046
1047 if ( !pVM->cCPUs
1048 || pVM->cCPUs > VMM_MAX_CPU_COUNT
1049 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
1050 && pVM->cCPUs != 1))
1051 {
1052 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
1053 return VERR_SSM_UNEXPECTED_DATA;
1054 }
1055
1056 for (unsigned i=0;i<pVM->cCPUs;i++)
1057 {
1058 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1059 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1060 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1061 if (u32Version == CPUM_SAVED_STATE_VERSION)
1062 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1063 }
1064 }
1065
1066
1067 uint32_t cElements;
1068 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1069 /* Support old saved states with a smaller standard cpuid array. */
1070 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1071 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1072 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1073
1074 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1075 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1076 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1077 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1078
1079 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1080 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1081 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1082 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1083
1084 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1085
1086 /*
1087 * Check that the basic cpuid id information is unchanged.
1088 * @todo we should check the 64 bits capabilities too!
1089 */
1090 uint32_t au32CpuId[8] = {0};
1091 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1092 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1093 uint32_t au32CpuIdSaved[8];
1094 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1095 if (RT_SUCCESS(rc))
1096 {
1097 /* Ignore CPU stepping. */
1098 au32CpuId[4] &= 0xfffffff0;
1099 au32CpuIdSaved[4] &= 0xfffffff0;
1100
1101 /* Ignore APIC ID (AMD specs). */
1102 au32CpuId[5] &= ~0xff000000;
1103 au32CpuIdSaved[5] &= ~0xff000000;
1104
1105 /* Ignore the number of Logical CPUs (AMD specs). */
1106 au32CpuId[5] &= ~0x00ff0000;
1107 au32CpuIdSaved[5] &= ~0x00ff0000;
1108
1109 /* do the compare */
1110 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1111 {
1112 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1113 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1114 "Saved=%.*Rhxs\n"
1115 "Real =%.*Rhxs\n",
1116 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1117 sizeof(au32CpuId), au32CpuId));
1118 else
1119 {
1120 LogRel(("cpumR3Load: CpuId mismatch!\n"
1121 "Saved=%.*Rhxs\n"
1122 "Real =%.*Rhxs\n",
1123 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1124 sizeof(au32CpuId), au32CpuId));
1125 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1126 }
1127 }
1128 }
1129
1130 return rc;
1131}
1132
1133
1134/**
1135 * Formats the EFLAGS value into mnemonics.
1136 *
1137 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1138 * @param efl The EFLAGS value.
1139 */
1140static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1141{
1142 /*
1143 * Format the flags.
1144 */
1145 static const struct
1146 {
1147 const char *pszSet; const char *pszClear; uint32_t fFlag;
1148 } s_aFlags[] =
1149 {
1150 { "vip",NULL, X86_EFL_VIP },
1151 { "vif",NULL, X86_EFL_VIF },
1152 { "ac", NULL, X86_EFL_AC },
1153 { "vm", NULL, X86_EFL_VM },
1154 { "rf", NULL, X86_EFL_RF },
1155 { "nt", NULL, X86_EFL_NT },
1156 { "ov", "nv", X86_EFL_OF },
1157 { "dn", "up", X86_EFL_DF },
1158 { "ei", "di", X86_EFL_IF },
1159 { "tf", NULL, X86_EFL_TF },
1160 { "nt", "pl", X86_EFL_SF },
1161 { "nz", "zr", X86_EFL_ZF },
1162 { "ac", "na", X86_EFL_AF },
1163 { "po", "pe", X86_EFL_PF },
1164 { "cy", "nc", X86_EFL_CF },
1165 };
1166 char *psz = pszEFlags;
1167 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1168 {
1169 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1170 if (pszAdd)
1171 {
1172 strcpy(psz, pszAdd);
1173 psz += strlen(pszAdd);
1174 *psz++ = ' ';
1175 }
1176 }
1177 psz[-1] = '\0';
1178}
1179
1180
1181/**
1182 * Formats a full register dump.
1183 *
1184 * @param pVM VM Handle.
1185 * @param pCtx The context to format.
1186 * @param pCtxCore The context core to format.
1187 * @param pHlp Output functions.
1188 * @param enmType The dump type.
1189 * @param pszPrefix Register name prefix.
1190 */
1191static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1192{
1193 /*
1194 * Format the EFLAGS.
1195 */
1196 uint32_t efl = pCtxCore->eflags.u32;
1197 char szEFlags[80];
1198 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1199
1200 /*
1201 * Format the registers.
1202 */
1203 switch (enmType)
1204 {
1205 case CPUMDUMPTYPE_TERSE:
1206 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1207 pHlp->pfnPrintf(pHlp,
1208 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1209 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1210 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1211 "%sr14=%016RX64 %sr15=%016RX64\n"
1212 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1213 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1214 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1215 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1216 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1217 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1218 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1219 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1220 else
1221 pHlp->pfnPrintf(pHlp,
1222 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1223 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1224 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1225 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1226 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1227 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1228 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1229 break;
1230
1231 case CPUMDUMPTYPE_DEFAULT:
1232 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1233 pHlp->pfnPrintf(pHlp,
1234 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1235 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1236 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1237 "%sr14=%016RX64 %sr15=%016RX64\n"
1238 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1239 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1240 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1241 ,
1242 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1243 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1244 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1245 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1246 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1247 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1248 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1249 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1250 else
1251 pHlp->pfnPrintf(pHlp,
1252 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1253 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1254 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1255 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1256 ,
1257 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1258 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1259 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1260 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1261 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1262 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1263 break;
1264
1265 case CPUMDUMPTYPE_VERBOSE:
1266 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1267 pHlp->pfnPrintf(pHlp,
1268 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1269 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1270 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1271 "%sr14=%016RX64 %sr15=%016RX64\n"
1272 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1273 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1274 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1275 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1276 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1277 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1278 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1279 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1280 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1281 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1282 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1283 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1284 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1285 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1286 ,
1287 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1288 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1289 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1290 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1291 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1292 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1293 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1294 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1295 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1296 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1297 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1298 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1299 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1300 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1301 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1302 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1303 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1304 else
1305 pHlp->pfnPrintf(pHlp,
1306 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1307 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1308 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1309 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1310 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1311 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1312 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1313 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1314 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1315 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1316 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1317 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1318 ,
1319 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1320 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1321 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1322 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1323 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1324 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1325 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1326 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1327 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1328 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1329 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1330 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1331
1332 pHlp->pfnPrintf(pHlp,
1333 "FPU:\n"
1334 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1335 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1336 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1337 ,
1338 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1339 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1340 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1341 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1342
1343 pHlp->pfnPrintf(pHlp,
1344 "MSR:\n"
1345 "%sEFER =%016RX64\n"
1346 "%sPAT =%016RX64\n"
1347 "%sSTAR =%016RX64\n"
1348 "%sCSTAR =%016RX64\n"
1349 "%sLSTAR =%016RX64\n"
1350 "%sSFMASK =%016RX64\n"
1351 "%sKERNELGSBASE =%016RX64\n",
1352 pszPrefix, pCtx->msrEFER,
1353 pszPrefix, pCtx->msrPAT,
1354 pszPrefix, pCtx->msrSTAR,
1355 pszPrefix, pCtx->msrCSTAR,
1356 pszPrefix, pCtx->msrLSTAR,
1357 pszPrefix, pCtx->msrSFMASK,
1358 pszPrefix, pCtx->msrKERNELGSBASE);
1359 break;
1360 }
1361}
1362
1363
1364/**
1365 * Display all cpu states and any other cpum info.
1366 *
1367 * @param pVM VM Handle.
1368 * @param pHlp The info helper functions.
1369 * @param pszArgs Arguments, ignored.
1370 */
1371static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1372{
1373 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1374 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1375 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1376 cpumR3InfoHost(pVM, pHlp, pszArgs);
1377}
1378
1379
1380/**
1381 * Parses the info argument.
1382 *
1383 * The argument starts with 'verbose', 'terse' or 'default' and then
1384 * continues with the comment string.
1385 *
1386 * @param pszArgs The pointer to the argument string.
1387 * @param penmType Where to store the dump type request.
1388 * @param ppszComment Where to store the pointer to the comment string.
1389 */
1390static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1391{
1392 if (!pszArgs)
1393 {
1394 *penmType = CPUMDUMPTYPE_DEFAULT;
1395 *ppszComment = "";
1396 }
1397 else
1398 {
1399 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1400 {
1401 pszArgs += 5;
1402 *penmType = CPUMDUMPTYPE_VERBOSE;
1403 }
1404 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1405 {
1406 pszArgs += 5;
1407 *penmType = CPUMDUMPTYPE_TERSE;
1408 }
1409 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1410 {
1411 pszArgs += 7;
1412 *penmType = CPUMDUMPTYPE_DEFAULT;
1413 }
1414 else
1415 *penmType = CPUMDUMPTYPE_DEFAULT;
1416 *ppszComment = RTStrStripL(pszArgs);
1417 }
1418}
1419
1420
1421/**
1422 * Display the guest cpu state.
1423 *
1424 * @param pVM VM Handle.
1425 * @param pHlp The info helper functions.
1426 * @param pszArgs Arguments, ignored.
1427 */
1428static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1429{
1430 CPUMDUMPTYPE enmType;
1431 const char *pszComment;
1432 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1433
1434 /* @todo SMP support! */
1435 PVMCPU pVCpu = VMMGetCpu(pVM);
1436 if (!pVCpu)
1437 pVCpu = &pVM->aCpus[0];
1438
1439 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1440
1441 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1442 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1443}
1444
1445
1446/**
1447 * Display the current guest instruction
1448 *
1449 * @param pVM VM Handle.
1450 * @param pHlp The info helper functions.
1451 * @param pszArgs Arguments, ignored.
1452 */
1453static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1454{
1455 char szInstruction[256];
1456 /* @todo SMP support! */
1457 PVMCPU pVCpu = VMMGetCpu(pVM);
1458 if (!pVCpu)
1459 pVCpu = &pVM->aCpus[0];
1460
1461 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1462 if (RT_SUCCESS(rc))
1463 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1464}
1465
1466
1467/**
1468 * Display the hypervisor cpu state.
1469 *
1470 * @param pVM VM Handle.
1471 * @param pHlp The info helper functions.
1472 * @param pszArgs Arguments, ignored.
1473 */
1474static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1475{
1476 CPUMDUMPTYPE enmType;
1477 const char *pszComment;
1478 /* @todo SMP */
1479 PVMCPU pVCpu = &pVM->aCpus[0];
1480
1481 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1482 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1483 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1484 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1485}
1486
1487
1488/**
1489 * Display the host cpu state.
1490 *
1491 * @param pVM VM Handle.
1492 * @param pHlp The info helper functions.
1493 * @param pszArgs Arguments, ignored.
1494 */
1495static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1496{
1497 CPUMDUMPTYPE enmType;
1498 const char *pszComment;
1499 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1500 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1501
1502 /*
1503 * Format the EFLAGS.
1504 */
1505 /* @todo SMP */
1506 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1507#if HC_ARCH_BITS == 32
1508 uint32_t efl = pCtx->eflags.u32;
1509#else
1510 uint64_t efl = pCtx->rflags;
1511#endif
1512 char szEFlags[80];
1513 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1514
1515 /*
1516 * Format the registers.
1517 */
1518#if HC_ARCH_BITS == 32
1519# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1520 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1521# endif
1522 {
1523 pHlp->pfnPrintf(pHlp,
1524 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1525 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1526 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1527 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1528 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1529 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1530 ,
1531 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1532 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1533 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1534 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1535 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1536 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1537 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1538 }
1539# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1540 else
1541# endif
1542#endif
1543#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1544 {
1545 pHlp->pfnPrintf(pHlp,
1546 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1547 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1548 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1549 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1550 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1551 "r14=%016RX64 r15=%016RX64\n"
1552 "iopl=%d %31s\n"
1553 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1554 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1555 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1556 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1557 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1558 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1559 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1560 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1561 ,
1562 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1563 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1564 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1565 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1566 pCtx->r11, pCtx->r12, pCtx->r13,
1567 pCtx->r14, pCtx->r15,
1568 X86_EFL_GET_IOPL(efl), szEFlags,
1569 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1570 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1571 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1572 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1573 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1574 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1575 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1576 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1577 }
1578#endif
1579}
1580
1581
1582/**
1583 * Get L1 cache / TLS associativity.
1584 */
1585static const char *getCacheAss(unsigned u, char *pszBuf)
1586{
1587 if (u == 0)
1588 return "res0 ";
1589 if (u == 1)
1590 return "direct";
1591 if (u >= 256)
1592 return "???";
1593
1594 RTStrPrintf(pszBuf, 16, "%d way", u);
1595 return pszBuf;
1596}
1597
1598
1599/**
1600 * Get L2 cache soociativity.
1601 */
1602const char *getL2CacheAss(unsigned u)
1603{
1604 switch (u)
1605 {
1606 case 0: return "off ";
1607 case 1: return "direct";
1608 case 2: return "2 way ";
1609 case 3: return "res3 ";
1610 case 4: return "4 way ";
1611 case 5: return "res5 ";
1612 case 6: return "8 way "; case 7: return "res7 ";
1613 case 8: return "16 way";
1614 case 9: return "res9 ";
1615 case 10: return "res10 ";
1616 case 11: return "res11 ";
1617 case 12: return "res12 ";
1618 case 13: return "res13 ";
1619 case 14: return "res14 ";
1620 case 15: return "fully ";
1621 default:
1622 return "????";
1623 }
1624}
1625
1626
1627/**
1628 * Display the guest CpuId leaves.
1629 *
1630 * @param pVM VM Handle.
1631 * @param pHlp The info helper functions.
1632 * @param pszArgs "terse", "default" or "verbose".
1633 */
1634static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1635{
1636 /*
1637 * Parse the argument.
1638 */
1639 unsigned iVerbosity = 1;
1640 if (pszArgs)
1641 {
1642 pszArgs = RTStrStripL(pszArgs);
1643 if (!strcmp(pszArgs, "terse"))
1644 iVerbosity--;
1645 else if (!strcmp(pszArgs, "verbose"))
1646 iVerbosity++;
1647 }
1648
1649 /*
1650 * Start cracking.
1651 */
1652 CPUMCPUID Host;
1653 CPUMCPUID Guest;
1654 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1655
1656 pHlp->pfnPrintf(pHlp,
1657 " RAW Standard CPUIDs\n"
1658 " Function eax ebx ecx edx\n");
1659 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1660 {
1661 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1662 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1663
1664 pHlp->pfnPrintf(pHlp,
1665 "Gst: %08x %08x %08x %08x %08x%s\n"
1666 "Hst: %08x %08x %08x %08x\n",
1667 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1668 i <= cStdMax ? "" : "*",
1669 Host.eax, Host.ebx, Host.ecx, Host.edx);
1670 }
1671
1672 /*
1673 * If verbose, decode it.
1674 */
1675 if (iVerbosity)
1676 {
1677 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1678 pHlp->pfnPrintf(pHlp,
1679 "Name: %.04s%.04s%.04s\n"
1680 "Supports: 0-%x\n",
1681 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1682 }
1683
1684 /*
1685 * Get Features.
1686 */
1687 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1688 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1689 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1690 if (cStdMax >= 1 && iVerbosity)
1691 {
1692 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1693 uint32_t uEAX = Guest.eax;
1694
1695 pHlp->pfnPrintf(pHlp,
1696 "Family: %d \tExtended: %d \tEffective: %d\n"
1697 "Model: %d \tExtended: %d \tEffective: %d\n"
1698 "Stepping: %d\n"
1699 "APIC ID: %#04x\n"
1700 "Logical CPUs: %d\n"
1701 "CLFLUSH Size: %d\n"
1702 "Brand ID: %#04x\n",
1703 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1704 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1705 ASMGetCpuStepping(uEAX),
1706 (Guest.ebx >> 24) & 0xff,
1707 (Guest.ebx >> 16) & 0xff,
1708 (Guest.ebx >> 8) & 0xff,
1709 (Guest.ebx >> 0) & 0xff);
1710 if (iVerbosity == 1)
1711 {
1712 uint32_t uEDX = Guest.edx;
1713 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1714 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1715 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1716 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1717 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1718 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1719 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1720 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1721 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1722 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1723 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1724 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1725 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1726 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1727 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1728 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1729 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1730 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1731 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1732 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1733 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1734 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1735 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1736 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1737 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1738 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1739 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1740 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1741 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1742 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1743 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1744 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1745 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1746 pHlp->pfnPrintf(pHlp, "\n");
1747
1748 uint32_t uECX = Guest.ecx;
1749 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1750 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1751 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1752 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1753 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1754 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1755 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1756 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1757 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1758 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1759 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1760 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1761 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1762 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1763 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1764 for (unsigned iBit = 14; iBit < 32; iBit++)
1765 if (uECX & RT_BIT(iBit))
1766 pHlp->pfnPrintf(pHlp, " %d", iBit);
1767 pHlp->pfnPrintf(pHlp, "\n");
1768 }
1769 else
1770 {
1771 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1772
1773 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1774 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1775 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1776 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1777
1778 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1779 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1780 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1781 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1782 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1783 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1784 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1785 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1786 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1787 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1788 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1789 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1790 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1791 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1792 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1793 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1794 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1795 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1796 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1797 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1798 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1799 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1800 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1801 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1802 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1803 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1804 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1805 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1806 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1807 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1808 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1809 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1810 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1811
1812 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1813 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1814 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1815 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1816 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1817 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1818 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1819 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1820 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1821 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1822 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1823 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1824 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1825 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1826 }
1827 }
1828 if (cStdMax >= 2 && iVerbosity)
1829 {
1830 /** @todo */
1831 }
1832
1833 /*
1834 * Extended.
1835 * Implemented after AMD specs.
1836 */
1837 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1838
1839 pHlp->pfnPrintf(pHlp,
1840 "\n"
1841 " RAW Extended CPUIDs\n"
1842 " Function eax ebx ecx edx\n");
1843 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1844 {
1845 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1846 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1847
1848 pHlp->pfnPrintf(pHlp,
1849 "Gst: %08x %08x %08x %08x %08x%s\n"
1850 "Hst: %08x %08x %08x %08x\n",
1851 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1852 i <= cExtMax ? "" : "*",
1853 Host.eax, Host.ebx, Host.ecx, Host.edx);
1854 }
1855
1856 /*
1857 * Understandable output
1858 */
1859 if (iVerbosity)
1860 {
1861 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1862 pHlp->pfnPrintf(pHlp,
1863 "Ext Name: %.4s%.4s%.4s\n"
1864 "Ext Supports: 0x80000000-%#010x\n",
1865 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1866 }
1867
1868 if (iVerbosity && cExtMax >= 1)
1869 {
1870 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1871 uint32_t uEAX = Guest.eax;
1872 pHlp->pfnPrintf(pHlp,
1873 "Family: %d \tExtended: %d \tEffective: %d\n"
1874 "Model: %d \tExtended: %d \tEffective: %d\n"
1875 "Stepping: %d\n"
1876 "Brand ID: %#05x\n",
1877 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1878 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1879 ASMGetCpuStepping(uEAX),
1880 Guest.ebx & 0xfff);
1881
1882 if (iVerbosity == 1)
1883 {
1884 uint32_t uEDX = Guest.edx;
1885 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1886 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1887 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1888 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1889 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1890 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1891 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1892 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1893 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1894 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1895 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1896 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1897 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1898 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1899 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1900 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1901 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1902 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1903 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1904 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1905 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1906 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1907 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1908 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1909 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1910 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1911 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1912 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1913 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1914 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1915 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1916 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1917 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1918 pHlp->pfnPrintf(pHlp, "\n");
1919
1920 uint32_t uECX = Guest.ecx;
1921 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1922 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1923 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1924 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1925 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1926 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1927 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1928 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1929 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1930 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1931 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1932 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1933 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1934 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1935 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1936 for (unsigned iBit = 5; iBit < 32; iBit++)
1937 if (uECX & RT_BIT(iBit))
1938 pHlp->pfnPrintf(pHlp, " %d", iBit);
1939 pHlp->pfnPrintf(pHlp, "\n");
1940 }
1941 else
1942 {
1943 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1944
1945 uint32_t uEdxGst = Guest.edx;
1946 uint32_t uEdxHst = Host.edx;
1947 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1948 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1949 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1950 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1951 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1952 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1953 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1954 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1955 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1956 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1957 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1958 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1959 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1960 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1961 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1962 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1963 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1964 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1965 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1966 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1967 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1968 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1969 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1970 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1971 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1972 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1973 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1974 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1975 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1976 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1977 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1978 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1979 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1980
1981 uint32_t uEcxGst = Guest.ecx;
1982 uint32_t uEcxHst = Host.ecx;
1983 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1984 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1985 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1986 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1987 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1988 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1989 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1990 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1991 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1992 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1993 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1994 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1995 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1996 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1997 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1998 }
1999 }
2000
2001 if (iVerbosity && cExtMax >= 2)
2002 {
2003 char szString[4*4*3+1] = {0};
2004 uint32_t *pu32 = (uint32_t *)szString;
2005 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
2006 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
2007 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
2008 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
2009 if (cExtMax >= 3)
2010 {
2011 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
2012 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
2013 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2014 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2015 }
2016 if (cExtMax >= 4)
2017 {
2018 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2019 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2020 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2021 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2022 }
2023 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2024 }
2025
2026 if (iVerbosity && cExtMax >= 5)
2027 {
2028 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2029 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2030 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2031 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2032 char sz1[32];
2033 char sz2[32];
2034
2035 pHlp->pfnPrintf(pHlp,
2036 "TLB 2/4M Instr/Uni: %s %3d entries\n"
2037 "TLB 2/4M Data: %s %3d entries\n",
2038 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2039 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2040 pHlp->pfnPrintf(pHlp,
2041 "TLB 4K Instr/Uni: %s %3d entries\n"
2042 "TLB 4K Data: %s %3d entries\n",
2043 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2044 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2045 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2046 "L1 Instr Cache Lines Per Tag: %d\n"
2047 "L1 Instr Cache Associativity: %s\n"
2048 "L1 Instr Cache Size: %d KB\n",
2049 (uEDX >> 0) & 0xff,
2050 (uEDX >> 8) & 0xff,
2051 getCacheAss((uEDX >> 16) & 0xff, sz1),
2052 (uEDX >> 24) & 0xff);
2053 pHlp->pfnPrintf(pHlp,
2054 "L1 Data Cache Line Size: %d bytes\n"
2055 "L1 Data Cache Lines Per Tag: %d\n"
2056 "L1 Data Cache Associativity: %s\n"
2057 "L1 Data Cache Size: %d KB\n",
2058 (uECX >> 0) & 0xff,
2059 (uECX >> 8) & 0xff,
2060 getCacheAss((uECX >> 16) & 0xff, sz1),
2061 (uECX >> 24) & 0xff);
2062 }
2063
2064 if (iVerbosity && cExtMax >= 6)
2065 {
2066 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2067 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2068 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2069
2070 pHlp->pfnPrintf(pHlp,
2071 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2072 "L2 TLB 2/4M Data: %s %4d entries\n",
2073 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2074 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2075 pHlp->pfnPrintf(pHlp,
2076 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2077 "L2 TLB 4K Data: %s %4d entries\n",
2078 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2079 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2080 pHlp->pfnPrintf(pHlp,
2081 "L2 Cache Line Size: %d bytes\n"
2082 "L2 Cache Lines Per Tag: %d\n"
2083 "L2 Cache Associativity: %s\n"
2084 "L2 Cache Size: %d KB\n",
2085 (uEDX >> 0) & 0xff,
2086 (uEDX >> 8) & 0xf,
2087 getL2CacheAss((uEDX >> 12) & 0xf),
2088 (uEDX >> 16) & 0xffff);
2089 }
2090
2091 if (iVerbosity && cExtMax >= 7)
2092 {
2093 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2094
2095 pHlp->pfnPrintf(pHlp, "APM Features: ");
2096 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2097 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2098 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2099 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2100 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2101 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2102 for (unsigned iBit = 6; iBit < 32; iBit++)
2103 if (uEDX & RT_BIT(iBit))
2104 pHlp->pfnPrintf(pHlp, " %d", iBit);
2105 pHlp->pfnPrintf(pHlp, "\n");
2106 }
2107
2108 if (iVerbosity && cExtMax >= 8)
2109 {
2110 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2111 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2112
2113 pHlp->pfnPrintf(pHlp,
2114 "Physical Address Width: %d bits\n"
2115 "Virtual Address Width: %d bits\n",
2116 (uEAX >> 0) & 0xff,
2117 (uEAX >> 8) & 0xff);
2118 pHlp->pfnPrintf(pHlp,
2119 "Physical Core Count: %d\n",
2120 (uECX >> 0) & 0xff);
2121 }
2122
2123
2124 /*
2125 * Centaur.
2126 */
2127 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2128
2129 pHlp->pfnPrintf(pHlp,
2130 "\n"
2131 " RAW Centaur CPUIDs\n"
2132 " Function eax ebx ecx edx\n");
2133 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2134 {
2135 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2136 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2137
2138 pHlp->pfnPrintf(pHlp,
2139 "Gst: %08x %08x %08x %08x %08x%s\n"
2140 "Hst: %08x %08x %08x %08x\n",
2141 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2142 i <= cCentaurMax ? "" : "*",
2143 Host.eax, Host.ebx, Host.ecx, Host.edx);
2144 }
2145
2146 /*
2147 * Understandable output
2148 */
2149 if (iVerbosity)
2150 {
2151 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2152 pHlp->pfnPrintf(pHlp,
2153 "Centaur Supports: 0xc0000000-%#010x\n",
2154 Guest.eax);
2155 }
2156
2157 if (iVerbosity && cCentaurMax >= 1)
2158 {
2159 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2160 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2161 uint32_t uEdxHst = Host.edx;
2162
2163 if (iVerbosity == 1)
2164 {
2165 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2166 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2167 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2168 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2169 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2170 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2171 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2172 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2173 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2174 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2175 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2176 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2177 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2178 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2179 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2180 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2181 for (unsigned iBit = 14; iBit < 32; iBit++)
2182 if (uEdxGst & RT_BIT(iBit))
2183 pHlp->pfnPrintf(pHlp, " %d", iBit);
2184 pHlp->pfnPrintf(pHlp, "\n");
2185 }
2186 else
2187 {
2188 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2189 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2190 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2191 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2192 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2193 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2194 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2195 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2196 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2197 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2198 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2199 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2200 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2201 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2202 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2203 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2204 for (unsigned iBit = 14; iBit < 32; iBit++)
2205 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2206 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2207 pHlp->pfnPrintf(pHlp, "\n");
2208 }
2209 }
2210}
2211
2212
2213/**
2214 * Structure used when disassembling and instructions in DBGF.
2215 * This is used so the reader function can get the stuff it needs.
2216 */
2217typedef struct CPUMDISASSTATE
2218{
2219 /** Pointer to the CPU structure. */
2220 PDISCPUSTATE pCpu;
2221 /** The VM handle. */
2222 PVM pVM;
2223 /** The VMCPU handle. */
2224 PVMCPU pVCpu;
2225 /** Pointer to the first byte in the segemnt. */
2226 RTGCUINTPTR GCPtrSegBase;
2227 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2228 RTGCUINTPTR GCPtrSegEnd;
2229 /** The size of the segment minus 1. */
2230 RTGCUINTPTR cbSegLimit;
2231 /** Pointer to the current page - R3 Ptr. */
2232 void const *pvPageR3;
2233 /** Pointer to the current page - GC Ptr. */
2234 RTGCPTR pvPageGC;
2235 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2236 PGMPAGEMAPLOCK PageMapLock;
2237 /** Whether the PageMapLock is valid or not. */
2238 bool fLocked;
2239 /** 64 bits mode or not. */
2240 bool f64Bits;
2241} CPUMDISASSTATE, *PCPUMDISASSTATE;
2242
2243
2244/**
2245 * Instruction reader.
2246 *
2247 * @returns VBox status code.
2248 * @param PtrSrc Address to read from.
2249 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2250 * @param pu8Dst Where to store the bytes.
2251 * @param cbRead Number of bytes to read.
2252 * @param uDisCpu Pointer to the disassembler cpu state.
2253 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2254 */
2255static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2256{
2257 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2258 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2259 Assert(cbRead > 0);
2260 for (;;)
2261 {
2262 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2263
2264 /* Need to update the page translation? */
2265 if ( !pState->pvPageR3
2266 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2267 {
2268 int rc = VINF_SUCCESS;
2269
2270 /* translate the address */
2271 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2272 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2273 && !HWACCMIsEnabled(pState->pVM))
2274 {
2275 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2276 if (!pState->pvPageR3)
2277 rc = VERR_INVALID_POINTER;
2278 }
2279 else
2280 {
2281 /* Release mapping lock previously acquired. */
2282 if (pState->fLocked)
2283 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2284 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2285 pState->fLocked = RT_SUCCESS_NP(rc);
2286 }
2287 if (RT_FAILURE(rc))
2288 {
2289 pState->pvPageR3 = NULL;
2290 return rc;
2291 }
2292 }
2293
2294 /* check the segemnt limit */
2295 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2296 return VERR_OUT_OF_SELECTOR_BOUNDS;
2297
2298 /* calc how much we can read */
2299 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2300 if (!pState->f64Bits)
2301 {
2302 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2303 if (cb > cbSeg && cbSeg)
2304 cb = cbSeg;
2305 }
2306 if (cb > cbRead)
2307 cb = cbRead;
2308
2309 /* read and advance */
2310 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2311 cbRead -= cb;
2312 if (!cbRead)
2313 return VINF_SUCCESS;
2314 pu8Dst += cb;
2315 PtrSrc += cb;
2316 }
2317}
2318
2319
2320/**
2321 * Disassemble an instruction and return the information in the provided structure.
2322 *
2323 * @returns VBox status code.
2324 * @param pVM VM Handle
2325 * @param pVCpu VMCPU Handle
2326 * @param pCtx CPU context
2327 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2328 * @param pCpu Disassembly state
2329 * @param pszPrefix String prefix for logging (debug only)
2330 *
2331 */
2332VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2333{
2334 CPUMDISASSTATE State;
2335 int rc;
2336
2337 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2338 State.pCpu = pCpu;
2339 State.pvPageGC = 0;
2340 State.pvPageR3 = NULL;
2341 State.pVM = pVM;
2342 State.pVCpu = pVCpu;
2343 State.fLocked = false;
2344 State.f64Bits = false;
2345
2346 /*
2347 * Get selector information.
2348 */
2349 if ( (pCtx->cr0 & X86_CR0_PE)
2350 && pCtx->eflags.Bits.u1VM == 0)
2351 {
2352 if (CPUMAreHiddenSelRegsValid(pVM))
2353 {
2354 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2355 State.GCPtrSegBase = pCtx->csHid.u64Base;
2356 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2357 State.cbSegLimit = pCtx->csHid.u32Limit;
2358 pCpu->mode = (State.f64Bits)
2359 ? CPUMODE_64BIT
2360 : pCtx->csHid.Attr.n.u1DefBig
2361 ? CPUMODE_32BIT
2362 : CPUMODE_16BIT;
2363 }
2364 else
2365 {
2366 DBGFSELINFO SelInfo;
2367
2368 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2369 if (RT_FAILURE(rc))
2370 {
2371 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2372 return rc;
2373 }
2374
2375 /*
2376 * Validate the selector.
2377 */
2378 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2379 if (RT_FAILURE(rc))
2380 {
2381 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2382 return rc;
2383 }
2384 State.GCPtrSegBase = SelInfo.GCPtrBase;
2385 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2386 State.cbSegLimit = SelInfo.cbLimit;
2387 pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2388 }
2389 }
2390 else
2391 {
2392 /* real or V86 mode */
2393 pCpu->mode = CPUMODE_16BIT;
2394 State.GCPtrSegBase = pCtx->cs * 16;
2395 State.GCPtrSegEnd = 0xFFFFFFFF;
2396 State.cbSegLimit = 0xFFFFFFFF;
2397 }
2398
2399 /*
2400 * Disassemble the instruction.
2401 */
2402 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2403 pCpu->apvUserData[0] = &State;
2404
2405 uint32_t cbInstr;
2406#ifndef LOG_ENABLED
2407 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2408 if (RT_SUCCESS(rc))
2409 {
2410#else
2411 char szOutput[160];
2412 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2413 if (RT_SUCCESS(rc))
2414 {
2415 /* log it */
2416 if (pszPrefix)
2417 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2418 else
2419 Log(("%s", szOutput));
2420#endif
2421 rc = VINF_SUCCESS;
2422 }
2423 else
2424 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2425
2426 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2427 if (State.fLocked)
2428 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2429
2430 return rc;
2431}
2432
2433#ifdef DEBUG
2434
2435/**
2436 * Disassemble an instruction and dump it to the log
2437 *
2438 * @returns VBox status code.
2439 * @param pVM VM Handle
2440 * @param pVCpu VMCPU Handle
2441 * @param pCtx CPU context
2442 * @param pc GC instruction pointer
2443 * @param pszPrefix String prefix for logging
2444 *
2445 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2446 */
2447VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2448{
2449 DISCPUSTATE Cpu;
2450 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2451}
2452
2453
2454/**
2455 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2456 *
2457 * @internal
2458 */
2459VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2460{
2461 /* @todo SMP support!! */
2462 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2463}
2464
2465#endif /* DEBUG */
2466
2467/**
2468 * API for controlling a few of the CPU features found in CR4.
2469 *
2470 * Currently only X86_CR4_TSD is accepted as input.
2471 *
2472 * @returns VBox status code.
2473 *
2474 * @param pVM The VM handle.
2475 * @param fOr The CR4 OR mask.
2476 * @param fAnd The CR4 AND mask.
2477 */
2478VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2479{
2480 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2481 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2482
2483 pVM->cpum.s.CR4.OrMask &= fAnd;
2484 pVM->cpum.s.CR4.OrMask |= fOr;
2485
2486 return VINF_SUCCESS;
2487}
2488
2489
2490/**
2491 * Gets a pointer to the array of standard CPUID leafs.
2492 *
2493 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2494 *
2495 * @returns Pointer to the standard CPUID leafs (read-only).
2496 * @param pVM The VM handle.
2497 * @remark Intended for PATM.
2498 */
2499VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2500{
2501 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2502}
2503
2504
2505/**
2506 * Gets a pointer to the array of extended CPUID leafs.
2507 *
2508 * CPUMGetGuestCpuIdExtMax() give the size of the array.
2509 *
2510 * @returns Pointer to the extended CPUID leafs (read-only).
2511 * @param pVM The VM handle.
2512 * @remark Intended for PATM.
2513 */
2514VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2515{
2516 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2517}
2518
2519
2520/**
2521 * Gets a pointer to the array of centaur CPUID leafs.
2522 *
2523 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2524 *
2525 * @returns Pointer to the centaur CPUID leafs (read-only).
2526 * @param pVM The VM handle.
2527 * @remark Intended for PATM.
2528 */
2529VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2530{
2531 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2532}
2533
2534
2535/**
2536 * Gets a pointer to the default CPUID leaf.
2537 *
2538 * @returns Pointer to the default CPUID leaf (read-only).
2539 * @param pVM The VM handle.
2540 * @remark Intended for PATM.
2541 */
2542VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2543{
2544 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2545}
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