VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 22474

Last change on this file since 22474 was 22070, checked in by vboxsync, 15 years ago

VMM,ConsoleImpl2: Moved NT4LeafLimit down into /CPUM and documented it. Cleanup.
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1/* $Id: CPUM.cpp 22070 2009-08-07 13:34:10Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 10
71/** The saved state version for the 2.1 trunk before the MSR changes. */
72#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
73/** The saved state version of 2.0, used for backwards compatibility. */
74#define CPUM_SAVED_STATE_VERSION_VER2_0 8
75/** The saved state version of 1.6, used for backwards compatability. */
76#define CPUM_SAVED_STATE_VERSION_VER1_6 6
77
78
79/*******************************************************************************
80* Structures and Typedefs *
81*******************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91
92} CPUMDUMPTYPE;
93/** Pointer to a cpu info dump type. */
94typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97/*******************************************************************************
98* Internal Functions *
99*******************************************************************************/
100static int cpumR3CpuIdInit(PVM pVM);
101static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/**
112 * Initializes the CPUM.
113 *
114 * @returns VBox status code.
115 * @param pVM The VM to operate on.
116 */
117VMMR3DECL(int) CPUMR3Init(PVM pVM)
118{
119 LogFlow(("CPUMR3Init\n"));
120
121 /*
122 * Assert alignment and sizes.
123 */
124 AssertCompileMemberAlignment(VM, cpum.s, 32);
125 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
126 AssertCompileSizeAlignment(CPUMCTX, 64);
127 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
128 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
129 AssertCompileMemberAlignment(VM, cpum, 64);
130 AssertCompileMemberAlignment(VM, aCpus, 64);
131 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
132 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
133
134 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
135 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
136 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
137
138 /* Calculate the offset from CPUMCPU to CPUM. */
139 for (unsigned i=0;i<pVM->cCPUs;i++)
140 {
141 PVMCPU pVCpu = &pVM->aCpus[i];
142
143 /*
144 * Setup any fixed pointers and offsets.
145 */
146 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
147 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
148
149 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
150 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
151 }
152
153 /*
154 * Check that the CPU supports the minimum features we require.
155 */
156 if (!ASMHasCpuId())
157 {
158 Log(("The CPU doesn't support CPUID!\n"));
159 return VERR_UNSUPPORTED_CPU;
160 }
161 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
162 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
163
164 /* Setup the CR4 AND and OR masks used in the switcher */
165 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
166 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
167 {
168 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
169 /* No FXSAVE implies no SSE */
170 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
171 pVM->cpum.s.CR4.OrMask = 0;
172 }
173 else
174 {
175 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
176 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
177 }
178
179 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
180 {
181 Log(("The CPU doesn't support MMX!\n"));
182 return VERR_UNSUPPORTED_CPU;
183 }
184 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
185 {
186 Log(("The CPU doesn't support TSC!\n"));
187 return VERR_UNSUPPORTED_CPU;
188 }
189 /* Bogus on AMD? */
190 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
191 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
192
193 /*
194 * Setup hypervisor startup values.
195 */
196
197 /*
198 * Register saved state data item.
199 */
200 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
201 NULL, cpumR3Save, NULL,
202 NULL, cpumR3Load, NULL);
203 if (RT_FAILURE(rc))
204 return rc;
205
206 /* Query the CPU manufacturer. */
207 uint32_t uEAX, uEBX, uECX, uEDX;
208 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
209 if ( uEAX >= 1
210 && uEBX == X86_CPUID_VENDOR_AMD_EBX
211 && uECX == X86_CPUID_VENDOR_AMD_ECX
212 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
213 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
214 else if ( uEAX >= 1
215 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
216 && uECX == X86_CPUID_VENDOR_INTEL_ECX
217 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
218 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
219 else /** @todo Via */
220 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
221
222 /*
223 * Register info handlers.
224 */
225 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
226 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
227 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
228 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
229 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
230 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
231
232 /*
233 * Initialize the Guest CPU state.
234 */
235 rc = cpumR3CpuIdInit(pVM);
236 if (RT_FAILURE(rc))
237 return rc;
238 CPUMR3Reset(pVM);
239 return VINF_SUCCESS;
240}
241
242
243/**
244 * Initializes the per-VCPU CPUM.
245 *
246 * @returns VBox status code.
247 * @param pVM The VM to operate on.
248 */
249VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
250{
251 LogFlow(("CPUMR3InitCPU\n"));
252 return VINF_SUCCESS;
253}
254
255
256/**
257 * Initializes the emulated CPU's cpuid information.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262static int cpumR3CpuIdInit(PVM pVM)
263{
264 PCPUM pCPUM = &pVM->cpum.s;
265 uint32_t i;
266
267 /*
268 * Get the host CPUIDs.
269 */
270 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
271 ASMCpuId_Idx_ECX(i, 0,
272 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
273 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
274 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
275 ASMCpuId(0x80000000 + i,
276 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
277 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
278 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
279 ASMCpuId(0xc0000000 + i,
280 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
281 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
282
283
284 /*
285 * Only report features we can support.
286 */
287 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
288 | X86_CPUID_FEATURE_EDX_VME
289 | X86_CPUID_FEATURE_EDX_DE
290 | X86_CPUID_FEATURE_EDX_PSE
291 | X86_CPUID_FEATURE_EDX_TSC
292 | X86_CPUID_FEATURE_EDX_MSR
293 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
294 | X86_CPUID_FEATURE_EDX_MCE
295 | X86_CPUID_FEATURE_EDX_CX8
296 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
297 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
298 //| X86_CPUID_FEATURE_EDX_SEP
299 | X86_CPUID_FEATURE_EDX_MTRR
300 | X86_CPUID_FEATURE_EDX_PGE
301 | X86_CPUID_FEATURE_EDX_MCA
302 | X86_CPUID_FEATURE_EDX_CMOV
303 | X86_CPUID_FEATURE_EDX_PAT
304 | X86_CPUID_FEATURE_EDX_PSE36
305 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
306 | X86_CPUID_FEATURE_EDX_CLFSH
307 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
308 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
309 | X86_CPUID_FEATURE_EDX_MMX
310 | X86_CPUID_FEATURE_EDX_FXSR
311 | X86_CPUID_FEATURE_EDX_SSE
312 | X86_CPUID_FEATURE_EDX_SSE2
313 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
314 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
315 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
316 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
317 | 0;
318 pCPUM->aGuestCpuIdStd[1].ecx &= 0
319 | X86_CPUID_FEATURE_ECX_SSE3
320 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
321 | ((pVM->cCPUs == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
322 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
323 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
324 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
325 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
326 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
327 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
328 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
329 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
330 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
331 /* ECX Bit 21 - x2APIC support - not yet. */
332 // | X86_CPUID_FEATURE_ECX_X2APIC
333 /* ECX Bit 23 - POPCOUNT instruction. */
334 //| X86_CPUID_FEATURE_ECX_POPCOUNT
335 | 0;
336
337 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
338 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
339 | X86_CPUID_AMD_FEATURE_EDX_VME
340 | X86_CPUID_AMD_FEATURE_EDX_DE
341 | X86_CPUID_AMD_FEATURE_EDX_PSE
342 | X86_CPUID_AMD_FEATURE_EDX_TSC
343 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
344 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
345 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
346 | X86_CPUID_AMD_FEATURE_EDX_CX8
347 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
348 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
349 //| X86_CPUID_AMD_FEATURE_EDX_SEP
350 | X86_CPUID_AMD_FEATURE_EDX_MTRR
351 | X86_CPUID_AMD_FEATURE_EDX_PGE
352 | X86_CPUID_AMD_FEATURE_EDX_MCA
353 | X86_CPUID_AMD_FEATURE_EDX_CMOV
354 | X86_CPUID_AMD_FEATURE_EDX_PAT
355 | X86_CPUID_AMD_FEATURE_EDX_PSE36
356 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
357 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
358 | X86_CPUID_AMD_FEATURE_EDX_MMX
359 | X86_CPUID_AMD_FEATURE_EDX_FXSR
360 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
361 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
362 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
363 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
364 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
365 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
366 | 0;
367 pCPUM->aGuestCpuIdExt[1].ecx &= 0
368 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
369 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
370 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
371 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
372 /** Note: This could prevent migration from AMD to Intel CPUs! */
373 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
374 //| X86_CPUID_AMD_FEATURE_ECX_ABM
375 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
376 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
377 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
378 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
379 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
380 //| X86_CPUID_AMD_FEATURE_ECX_WDT
381 | 0;
382
383 /*
384 * Hide HTT, multicode, SMP, whatever.
385 * (APIC-ID := 0 and #LogCpus := 0)
386 */
387 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
388#ifdef VBOX_WITH_MULTI_CORE
389 if (pVM->cCPUs > 1)
390 {
391 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
392 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCPUs << 16);
393 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
394 }
395#endif
396
397 /* Cpuid 2:
398 * Intel: Cache and TLB information
399 * AMD: Reserved
400 * Safe to expose
401 */
402
403 /* Cpuid 3:
404 * Intel: EAX, EBX - reserved
405 * ECX, EDX - Processor Serial Number if available, otherwise reserved
406 * AMD: Reserved
407 * Safe to expose
408 */
409 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
410 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
411
412 /* Cpuid 4:
413 * Intel: Deterministic Cache Parameters Leaf
414 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
415 * AMD: Reserved
416 * Safe to expose, except for EAX:
417 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
418 * Bits 31-26: Maximum number of processor cores in this physical package**
419 * @Note These SMP values are constant regardless of ECX
420 */
421 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
422 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
423#ifdef VBOX_WITH_MULTI_CORE
424 if ( pVM->cCPUs > 1
425 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_INTEL)
426 {
427 AssertReturn(pVM->cCPUs <= 64, VERR_TOO_MANY_CPUS);
428 /* One logical processor with possibly multiple cores. */
429 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
430 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCPUs - 1) << 26); /* 6 bits only -> 64 cores! */
431 }
432#endif
433
434 /* Cpuid 5: Monitor/mwait Leaf
435 * Intel: ECX, EDX - reserved
436 * EAX, EBX - Smallest and largest monitor line size
437 * AMD: EDX - reserved
438 * EAX, EBX - Smallest and largest monitor line size
439 * ECX - extensions (ignored for now)
440 * Safe to expose
441 */
442 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
443 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
444
445 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
446
447 /*
448 * Determine the default.
449 *
450 * Intel returns values of the highest standard function, while AMD
451 * returns zeros. VIA on the other hand seems to returning nothing or
452 * perhaps some random garbage, we don't try to duplicate this behavior.
453 */
454 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
455 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
456 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
457
458 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
459 * Safe to pass on to the guest.
460 *
461 * Intel: 0x800000005 reserved
462 * 0x800000006 L2 cache information
463 * AMD: 0x800000005 L1 cache information
464 * 0x800000006 L2/L3 cache information
465 */
466
467 /* Cpuid 0x800000007:
468 * AMD: EAX, EBX, ECX - reserved
469 * EDX: Advanced Power Management Information
470 * Intel: Reserved
471 */
472 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
473 {
474 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
475
476 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
477
478 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
479 {
480 /* Only expose the TSC invariant capability bit to the guest. */
481 pCPUM->aGuestCpuIdExt[7].edx &= 0
482 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
483 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
484 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
485 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
486 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
487 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
488 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
489 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
490#if 1
491 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
492 * that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
493 */
494#else
495 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
496#endif
497 | 0;
498 }
499 else
500 pCPUM->aGuestCpuIdExt[7].edx = 0;
501 }
502
503 /* Cpuid 0x800000008:
504 * AMD: EBX, EDX - reserved
505 * EAX: Virtual/Physical address Size
506 * ECX: Number of cores + APICIdCoreIdSize
507 * Intel: EAX: Virtual/Physical address Size
508 * EBX, ECX, EDX - reserved
509 */
510 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
511 {
512 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
513 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
514 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
515 * NC (0-7) Number of cores; 0 equals 1 core */
516 pCPUM->aGuestCpuIdExt[8].ecx = 0;
517#ifdef VBOX_WITH_MULTI_CORE
518 if ( pVM->cCPUs > 1
519 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
520 {
521 /* Legacy method to determine the number of cores. */
522 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
523 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCPUs - 1); /* NC: Number of CPU cores - 1; 8 bits */
524
525 }
526#endif
527 }
528
529 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
530 * Limit the number of standard CPUID leafs to 0..2 to prevent NT4 from
531 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
532 * This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
533 * @todo r=bird: The intel docs states that leafs 3 is included, why don't we?
534 */
535 bool fNt4LeafLimit;
536 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "NT4LeafLimit", &fNt4LeafLimit, false);
537 if (fNt4LeafLimit)
538 pCPUM->aGuestCpuIdStd[0].eax = 2;
539
540 /*
541 * Limit it the number of entries and fill the remaining with the defaults.
542 *
543 * The limits are masking off stuff about power saving and similar, this
544 * is perhaps a bit crudely done as there is probably some relatively harmless
545 * info too in these leaves (like words about having a constant TSC).
546 */
547 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
548 pCPUM->aGuestCpuIdStd[0].eax = 5;
549
550 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
551 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
552
553 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
554 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
555 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
556 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
557 : 0;
558 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
559 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
560
561 /*
562 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
563 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
564 * of processors from (cpuid(4).eax >> 26) + 1.
565 */
566 if (pVM->cCPUs == 1)
567 pCPUM->aGuestCpuIdStd[4].eax = 0;
568
569 /*
570 * Centaur stuff (VIA).
571 *
572 * The important part here (we think) is to make sure the 0xc0000000
573 * function returns 0xc0000001. As for the features, we don't currently
574 * let on about any of those... 0xc0000002 seems to be some
575 * temperature/hz/++ stuff, include it as well (static).
576 */
577 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
578 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
579 {
580 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
581 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
582 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
583 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
584 i++)
585 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
586 }
587 else
588 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
589 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
590
591
592 /*
593 * Load CPUID overrides from configuration.
594 */
595 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
596 * Overloads the CPUID leaf values. */
597 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
598 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
599 for (i=0;; )
600 {
601 while (cElements-- > 0)
602 {
603 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
604 if (pNode)
605 {
606 uint32_t u32;
607 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
608 if (RT_SUCCESS(rc))
609 pCpuId->eax = u32;
610 else
611 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
612
613 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
614 if (RT_SUCCESS(rc))
615 pCpuId->ebx = u32;
616 else
617 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
618
619 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
620 if (RT_SUCCESS(rc))
621 pCpuId->ecx = u32;
622 else
623 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
624
625 rc = CFGMR3QueryU32(pNode, "edx", &u32);
626 if (RT_SUCCESS(rc))
627 pCpuId->edx = u32;
628 else
629 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
630 }
631 pCpuId++;
632 i++;
633 }
634
635 /* next */
636 if ((i & UINT32_C(0xc0000000)) == 0)
637 {
638 pCpuId = &pCPUM->aGuestCpuIdExt[0];
639 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
640 i = UINT32_C(0x80000000);
641 }
642 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
643 {
644 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
645 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
646 i = UINT32_C(0xc0000000);
647 }
648 else
649 break;
650 }
651
652 /* Check if PAE was explicitely enabled by the user. */
653 bool fEnable = false;
654 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
655 if (RT_SUCCESS(rc) && fEnable)
656 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
657
658 /*
659 * Log the cpuid and we're good.
660 */
661 RTCPUSET OnlineSet;
662 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
663 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
664 LogRel(("************************* CPUID dump ************************\n"));
665 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
666 LogRel(("\n"));
667 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
668 LogRel(("******************** End of CPUID dump **********************\n"));
669 return VINF_SUCCESS;
670}
671
672
673
674
675/**
676 * Applies relocations to data and code managed by this
677 * component. This function will be called at init and
678 * whenever the VMM need to relocate it self inside the GC.
679 *
680 * The CPUM will update the addresses used by the switcher.
681 *
682 * @param pVM The VM.
683 */
684VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
685{
686 LogFlow(("CPUMR3Relocate\n"));
687 for (unsigned i=0;i<pVM->cCPUs;i++)
688 {
689 PVMCPU pVCpu = &pVM->aCpus[i];
690 /*
691 * Switcher pointers.
692 */
693 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
694 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
695 }
696}
697
698
699/**
700 * Terminates the CPUM.
701 *
702 * Termination means cleaning up and freeing all resources,
703 * the VM it self is at this point powered off or suspended.
704 *
705 * @returns VBox status code.
706 * @param pVM The VM to operate on.
707 */
708VMMR3DECL(int) CPUMR3Term(PVM pVM)
709{
710 CPUMR3TermCPU(pVM);
711 return 0;
712}
713
714
715/**
716 * Terminates the per-VCPU CPUM.
717 *
718 * Termination means cleaning up and freeing all resources,
719 * the VM it self is at this point powered off or suspended.
720 *
721 * @returns VBox status code.
722 * @param pVM The VM to operate on.
723 */
724VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
725{
726#ifdef VBOX_WITH_CRASHDUMP_MAGIC
727 for (unsigned i=0;i<pVM->cCPUs;i++)
728 {
729 PVMCPU pVCpu = &pVM->aCpus[i];
730 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
731
732 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
733 pVCpu->cpum.s.uMagic = 0;
734 pCtx->dr[5] = 0;
735 }
736#endif
737 return 0;
738}
739
740VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
741{
742 /* @todo anything different for VCPU > 0? */
743 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
744
745 /*
746 * Initialize everything to ZERO first.
747 */
748 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
749 memset(pCtx, 0, sizeof(*pCtx));
750 pVCpu->cpum.s.fUseFlags = fUseFlags;
751
752 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
753 pCtx->eip = 0x0000fff0;
754 pCtx->edx = 0x00000600; /* P6 processor */
755 pCtx->eflags.Bits.u1Reserved0 = 1;
756
757 pCtx->cs = 0xf000;
758 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
759 pCtx->csHid.u32Limit = 0x0000ffff;
760 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
761 pCtx->csHid.Attr.n.u1Present = 1;
762 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
763
764 pCtx->dsHid.u32Limit = 0x0000ffff;
765 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
766 pCtx->dsHid.Attr.n.u1Present = 1;
767 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
768
769 pCtx->esHid.u32Limit = 0x0000ffff;
770 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
771 pCtx->esHid.Attr.n.u1Present = 1;
772 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
773
774 pCtx->fsHid.u32Limit = 0x0000ffff;
775 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
776 pCtx->fsHid.Attr.n.u1Present = 1;
777 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
778
779 pCtx->gsHid.u32Limit = 0x0000ffff;
780 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
781 pCtx->gsHid.Attr.n.u1Present = 1;
782 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
783
784 pCtx->ssHid.u32Limit = 0x0000ffff;
785 pCtx->ssHid.Attr.n.u1Present = 1;
786 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
787 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
788
789 pCtx->idtr.cbIdt = 0xffff;
790 pCtx->gdtr.cbGdt = 0xffff;
791
792 pCtx->ldtrHid.u32Limit = 0xffff;
793 pCtx->ldtrHid.Attr.n.u1Present = 1;
794 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
795
796 pCtx->trHid.u32Limit = 0xffff;
797 pCtx->trHid.Attr.n.u1Present = 1;
798 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
799
800 pCtx->dr[6] = X86_DR6_INIT_VAL;
801 pCtx->dr[7] = X86_DR7_INIT_VAL;
802
803 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
804 pCtx->fpu.FCW = 0x37f;
805
806 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
807 pCtx->fpu.MXCSR = 0x1F80;
808
809 /* Init PAT MSR */
810 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
811
812 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
813 * The Intel docs don't mention it.
814 */
815 pCtx->msrEFER = 0;
816}
817
818/**
819 * Resets the CPU.
820 *
821 * @returns VINF_SUCCESS.
822 * @param pVM The VM handle.
823 */
824VMMR3DECL(void) CPUMR3Reset(PVM pVM)
825{
826 for (unsigned i=0;i<pVM->cCPUs;i++)
827 {
828 CPUMR3ResetCpu(&pVM->aCpus[i]);
829
830#ifdef VBOX_WITH_CRASHDUMP_MAGIC
831 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
832
833 /* Magic marker for searching in crash dumps. */
834 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
835 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
836 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
837#endif
838 }
839}
840
841
842/**
843 * Execute state save operation.
844 *
845 * @returns VBox status code.
846 * @param pVM VM Handle.
847 * @param pSSM SSM operation handle.
848 */
849static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
850{
851 /*
852 * Save.
853 */
854 for (unsigned i=0;i<pVM->cCPUs;i++)
855 {
856 PVMCPU pVCpu = &pVM->aCpus[i];
857
858 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
859 }
860
861 SSMR3PutU32(pSSM, pVM->cCPUs);
862 for (unsigned i=0;i<pVM->cCPUs;i++)
863 {
864 PVMCPU pVCpu = &pVM->aCpus[i];
865
866 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
867 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
868 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
869 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
870 }
871
872 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
873 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
874
875 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
876 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
877
878 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
879 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
880
881 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
882
883 /* Add the cpuid for checking that the cpu is unchanged. */
884 uint32_t au32CpuId[8] = {0};
885 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
886 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
887 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
888}
889
890
891/**
892 * Load a version 1.6 CPUMCTX structure.
893 *
894 * @returns VBox status code.
895 * @param pVM VM Handle.
896 * @param pCpumctx16 Version 1.6 CPUMCTX
897 */
898static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
899{
900#define CPUMCTX16_LOADREG(RegName) \
901 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
902
903#define CPUMCTX16_LOADDRXREG(RegName) \
904 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
905
906#define CPUMCTX16_LOADHIDREG(RegName) \
907 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
908 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
909 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
910
911#define CPUMCTX16_LOADSEGREG(RegName) \
912 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
913 CPUMCTX16_LOADHIDREG(RegName);
914
915 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
916
917 CPUMCTX16_LOADREG(rax);
918 CPUMCTX16_LOADREG(rbx);
919 CPUMCTX16_LOADREG(rcx);
920 CPUMCTX16_LOADREG(rdx);
921 CPUMCTX16_LOADREG(rdi);
922 CPUMCTX16_LOADREG(rsi);
923 CPUMCTX16_LOADREG(rbp);
924 CPUMCTX16_LOADREG(esp);
925 CPUMCTX16_LOADREG(rip);
926 CPUMCTX16_LOADREG(rflags);
927
928 CPUMCTX16_LOADSEGREG(cs);
929 CPUMCTX16_LOADSEGREG(ds);
930 CPUMCTX16_LOADSEGREG(es);
931 CPUMCTX16_LOADSEGREG(fs);
932 CPUMCTX16_LOADSEGREG(gs);
933 CPUMCTX16_LOADSEGREG(ss);
934
935 CPUMCTX16_LOADREG(r8);
936 CPUMCTX16_LOADREG(r9);
937 CPUMCTX16_LOADREG(r10);
938 CPUMCTX16_LOADREG(r11);
939 CPUMCTX16_LOADREG(r12);
940 CPUMCTX16_LOADREG(r13);
941 CPUMCTX16_LOADREG(r14);
942 CPUMCTX16_LOADREG(r15);
943
944 CPUMCTX16_LOADREG(cr0);
945 CPUMCTX16_LOADREG(cr2);
946 CPUMCTX16_LOADREG(cr3);
947 CPUMCTX16_LOADREG(cr4);
948
949 CPUMCTX16_LOADDRXREG(0);
950 CPUMCTX16_LOADDRXREG(1);
951 CPUMCTX16_LOADDRXREG(2);
952 CPUMCTX16_LOADDRXREG(3);
953 CPUMCTX16_LOADDRXREG(4);
954 CPUMCTX16_LOADDRXREG(5);
955 CPUMCTX16_LOADDRXREG(6);
956 CPUMCTX16_LOADDRXREG(7);
957
958 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
959 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
960 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
961 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
962
963 CPUMCTX16_LOADREG(ldtr);
964 CPUMCTX16_LOADREG(tr);
965
966 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
967
968 CPUMCTX16_LOADREG(msrEFER);
969 CPUMCTX16_LOADREG(msrSTAR);
970 CPUMCTX16_LOADREG(msrPAT);
971 CPUMCTX16_LOADREG(msrLSTAR);
972 CPUMCTX16_LOADREG(msrCSTAR);
973 CPUMCTX16_LOADREG(msrSFMASK);
974 CPUMCTX16_LOADREG(msrKERNELGSBASE);
975
976 CPUMCTX16_LOADHIDREG(ldtr);
977 CPUMCTX16_LOADHIDREG(tr);
978
979#undef CPUMCTX16_LOADSEGREG
980#undef CPUMCTX16_LOADHIDREG
981#undef CPUMCTX16_LOADDRXREG
982#undef CPUMCTX16_LOADREG
983}
984
985
986/**
987 * Execute state load operation.
988 *
989 * @returns VBox status code.
990 * @param pVM VM Handle.
991 * @param pSSM SSM operation handle.
992 * @param u32Version Data layout version.
993 */
994static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
995{
996 /*
997 * Validate version.
998 */
999 if ( u32Version != CPUM_SAVED_STATE_VERSION
1000 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1001 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
1002 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
1003 {
1004 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
1005 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1006 }
1007
1008 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
1009 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1010 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1011 else if (u32Version <= CPUM_SAVED_STATE_VERSION)
1012 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1013
1014 /*
1015 * Restore.
1016 */
1017 for (unsigned i=0;i<pVM->cCPUs;i++)
1018 {
1019 PVMCPU pVCpu = &pVM->aCpus[i];
1020 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1021 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1022
1023 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1024 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1025 pVCpu->cpum.s.Hyper.esp = uESP;
1026 }
1027
1028 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1029 {
1030 CPUMCTX_VER1_6 cpumctx16;
1031 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1032 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1033
1034 /* Save the old cpumctx state into the new one. */
1035 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1036
1037 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1038 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1039 }
1040 else
1041 {
1042 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1043 {
1044 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
1045 AssertRCReturn(rc, rc);
1046 }
1047
1048 if ( !pVM->cCPUs
1049 || pVM->cCPUs > VMM_MAX_CPU_COUNT
1050 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
1051 && pVM->cCPUs != 1))
1052 {
1053 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
1054 return VERR_SSM_UNEXPECTED_DATA;
1055 }
1056
1057 for (unsigned i=0;i<pVM->cCPUs;i++)
1058 {
1059 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1060 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1061 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1062 if (u32Version == CPUM_SAVED_STATE_VERSION)
1063 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1064 }
1065 }
1066
1067
1068 uint32_t cElements;
1069 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1070 /* Support old saved states with a smaller standard cpuid array. */
1071 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1072 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1073 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1074
1075 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1076 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1077 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1078 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1079
1080 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1081 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1082 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1083 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1084
1085 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1086
1087 /*
1088 * Check that the basic cpuid id information is unchanged.
1089 * @todo we should check the 64 bits capabilities too!
1090 */
1091 uint32_t au32CpuId[8] = {0};
1092 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1093 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1094 uint32_t au32CpuIdSaved[8];
1095 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1096 if (RT_SUCCESS(rc))
1097 {
1098 /* Ignore CPU stepping. */
1099 au32CpuId[4] &= 0xfffffff0;
1100 au32CpuIdSaved[4] &= 0xfffffff0;
1101
1102 /* Ignore APIC ID (AMD specs). */
1103 au32CpuId[5] &= ~0xff000000;
1104 au32CpuIdSaved[5] &= ~0xff000000;
1105
1106 /* Ignore the number of Logical CPUs (AMD specs). */
1107 au32CpuId[5] &= ~0x00ff0000;
1108 au32CpuIdSaved[5] &= ~0x00ff0000;
1109
1110 /* Ignore some advanced capability bits, that we don't expose to the guest. */
1111 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1112 | X86_CPUID_FEATURE_ECX_VMX
1113 | X86_CPUID_FEATURE_ECX_SMX
1114 | X86_CPUID_FEATURE_ECX_EST
1115 | X86_CPUID_FEATURE_ECX_TM2
1116 | X86_CPUID_FEATURE_ECX_CNTXID
1117 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1118 | X86_CPUID_FEATURE_ECX_PDCM
1119 | X86_CPUID_FEATURE_ECX_DCA
1120 | X86_CPUID_FEATURE_ECX_X2APIC
1121 );
1122 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1123 | X86_CPUID_FEATURE_ECX_VMX
1124 | X86_CPUID_FEATURE_ECX_SMX
1125 | X86_CPUID_FEATURE_ECX_EST
1126 | X86_CPUID_FEATURE_ECX_TM2
1127 | X86_CPUID_FEATURE_ECX_CNTXID
1128 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1129 | X86_CPUID_FEATURE_ECX_PDCM
1130 | X86_CPUID_FEATURE_ECX_DCA
1131 | X86_CPUID_FEATURE_ECX_X2APIC
1132 );
1133
1134 /* Make sure we don't forget to update the masks when enabling
1135 * features in the future.
1136 */
1137 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
1138 ( X86_CPUID_FEATURE_ECX_DTES64
1139 | X86_CPUID_FEATURE_ECX_VMX
1140 | X86_CPUID_FEATURE_ECX_SMX
1141 | X86_CPUID_FEATURE_ECX_EST
1142 | X86_CPUID_FEATURE_ECX_TM2
1143 | X86_CPUID_FEATURE_ECX_CNTXID
1144 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1145 | X86_CPUID_FEATURE_ECX_PDCM
1146 | X86_CPUID_FEATURE_ECX_DCA
1147 | X86_CPUID_FEATURE_ECX_X2APIC
1148 )));
1149 /* do the compare */
1150 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1151 {
1152 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1153 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1154 "Saved=%.*Rhxs\n"
1155 "Real =%.*Rhxs\n",
1156 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1157 sizeof(au32CpuId), au32CpuId));
1158 else
1159 {
1160 LogRel(("cpumR3Load: CpuId mismatch!\n"
1161 "Saved=%.*Rhxs\n"
1162 "Real =%.*Rhxs\n",
1163 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1164 sizeof(au32CpuId), au32CpuId));
1165 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1166 }
1167 }
1168 }
1169
1170 return rc;
1171}
1172
1173
1174/**
1175 * Formats the EFLAGS value into mnemonics.
1176 *
1177 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1178 * @param efl The EFLAGS value.
1179 */
1180static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1181{
1182 /*
1183 * Format the flags.
1184 */
1185 static const struct
1186 {
1187 const char *pszSet; const char *pszClear; uint32_t fFlag;
1188 } s_aFlags[] =
1189 {
1190 { "vip",NULL, X86_EFL_VIP },
1191 { "vif",NULL, X86_EFL_VIF },
1192 { "ac", NULL, X86_EFL_AC },
1193 { "vm", NULL, X86_EFL_VM },
1194 { "rf", NULL, X86_EFL_RF },
1195 { "nt", NULL, X86_EFL_NT },
1196 { "ov", "nv", X86_EFL_OF },
1197 { "dn", "up", X86_EFL_DF },
1198 { "ei", "di", X86_EFL_IF },
1199 { "tf", NULL, X86_EFL_TF },
1200 { "nt", "pl", X86_EFL_SF },
1201 { "nz", "zr", X86_EFL_ZF },
1202 { "ac", "na", X86_EFL_AF },
1203 { "po", "pe", X86_EFL_PF },
1204 { "cy", "nc", X86_EFL_CF },
1205 };
1206 char *psz = pszEFlags;
1207 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1208 {
1209 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1210 if (pszAdd)
1211 {
1212 strcpy(psz, pszAdd);
1213 psz += strlen(pszAdd);
1214 *psz++ = ' ';
1215 }
1216 }
1217 psz[-1] = '\0';
1218}
1219
1220
1221/**
1222 * Formats a full register dump.
1223 *
1224 * @param pVM VM Handle.
1225 * @param pCtx The context to format.
1226 * @param pCtxCore The context core to format.
1227 * @param pHlp Output functions.
1228 * @param enmType The dump type.
1229 * @param pszPrefix Register name prefix.
1230 */
1231static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1232{
1233 /*
1234 * Format the EFLAGS.
1235 */
1236 uint32_t efl = pCtxCore->eflags.u32;
1237 char szEFlags[80];
1238 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1239
1240 /*
1241 * Format the registers.
1242 */
1243 switch (enmType)
1244 {
1245 case CPUMDUMPTYPE_TERSE:
1246 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1247 pHlp->pfnPrintf(pHlp,
1248 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1249 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1250 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1251 "%sr14=%016RX64 %sr15=%016RX64\n"
1252 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1253 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1254 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1255 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1256 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1257 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1258 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1259 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1260 else
1261 pHlp->pfnPrintf(pHlp,
1262 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1263 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1264 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1265 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1266 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1267 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1268 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1269 break;
1270
1271 case CPUMDUMPTYPE_DEFAULT:
1272 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1273 pHlp->pfnPrintf(pHlp,
1274 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1275 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1276 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1277 "%sr14=%016RX64 %sr15=%016RX64\n"
1278 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1279 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1280 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1281 ,
1282 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1283 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1284 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1285 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1286 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1287 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1288 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1289 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1290 else
1291 pHlp->pfnPrintf(pHlp,
1292 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1293 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1294 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1295 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1296 ,
1297 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1298 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1299 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1300 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1301 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1302 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1303 break;
1304
1305 case CPUMDUMPTYPE_VERBOSE:
1306 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1307 pHlp->pfnPrintf(pHlp,
1308 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1309 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1310 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1311 "%sr14=%016RX64 %sr15=%016RX64\n"
1312 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1313 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1314 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1315 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1316 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1317 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1318 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1319 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1320 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1321 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1322 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1323 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1324 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1325 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1326 ,
1327 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1328 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1329 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1330 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1331 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1332 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1333 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1334 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1335 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1336 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1337 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1338 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1339 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1340 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1341 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1342 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1343 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1344 else
1345 pHlp->pfnPrintf(pHlp,
1346 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1347 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1348 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1349 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1350 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1351 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1352 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1353 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1354 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1355 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1356 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1357 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1358 ,
1359 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1360 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1361 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1362 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1363 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1364 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1365 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1366 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1367 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1368 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1369 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1370 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1371
1372 pHlp->pfnPrintf(pHlp,
1373 "FPU:\n"
1374 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1375 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1376 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1377 ,
1378 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1379 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1380 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1381 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1382
1383 pHlp->pfnPrintf(pHlp,
1384 "MSR:\n"
1385 "%sEFER =%016RX64\n"
1386 "%sPAT =%016RX64\n"
1387 "%sSTAR =%016RX64\n"
1388 "%sCSTAR =%016RX64\n"
1389 "%sLSTAR =%016RX64\n"
1390 "%sSFMASK =%016RX64\n"
1391 "%sKERNELGSBASE =%016RX64\n",
1392 pszPrefix, pCtx->msrEFER,
1393 pszPrefix, pCtx->msrPAT,
1394 pszPrefix, pCtx->msrSTAR,
1395 pszPrefix, pCtx->msrCSTAR,
1396 pszPrefix, pCtx->msrLSTAR,
1397 pszPrefix, pCtx->msrSFMASK,
1398 pszPrefix, pCtx->msrKERNELGSBASE);
1399 break;
1400 }
1401}
1402
1403
1404/**
1405 * Display all cpu states and any other cpum info.
1406 *
1407 * @param pVM VM Handle.
1408 * @param pHlp The info helper functions.
1409 * @param pszArgs Arguments, ignored.
1410 */
1411static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1412{
1413 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1414 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1415 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1416 cpumR3InfoHost(pVM, pHlp, pszArgs);
1417}
1418
1419
1420/**
1421 * Parses the info argument.
1422 *
1423 * The argument starts with 'verbose', 'terse' or 'default' and then
1424 * continues with the comment string.
1425 *
1426 * @param pszArgs The pointer to the argument string.
1427 * @param penmType Where to store the dump type request.
1428 * @param ppszComment Where to store the pointer to the comment string.
1429 */
1430static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1431{
1432 if (!pszArgs)
1433 {
1434 *penmType = CPUMDUMPTYPE_DEFAULT;
1435 *ppszComment = "";
1436 }
1437 else
1438 {
1439 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1440 {
1441 pszArgs += 5;
1442 *penmType = CPUMDUMPTYPE_VERBOSE;
1443 }
1444 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1445 {
1446 pszArgs += 5;
1447 *penmType = CPUMDUMPTYPE_TERSE;
1448 }
1449 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1450 {
1451 pszArgs += 7;
1452 *penmType = CPUMDUMPTYPE_DEFAULT;
1453 }
1454 else
1455 *penmType = CPUMDUMPTYPE_DEFAULT;
1456 *ppszComment = RTStrStripL(pszArgs);
1457 }
1458}
1459
1460
1461/**
1462 * Display the guest cpu state.
1463 *
1464 * @param pVM VM Handle.
1465 * @param pHlp The info helper functions.
1466 * @param pszArgs Arguments, ignored.
1467 */
1468static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1469{
1470 CPUMDUMPTYPE enmType;
1471 const char *pszComment;
1472 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1473
1474 /* @todo SMP support! */
1475 PVMCPU pVCpu = VMMGetCpu(pVM);
1476 if (!pVCpu)
1477 pVCpu = &pVM->aCpus[0];
1478
1479 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1480
1481 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1482 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1483}
1484
1485
1486/**
1487 * Display the current guest instruction
1488 *
1489 * @param pVM VM Handle.
1490 * @param pHlp The info helper functions.
1491 * @param pszArgs Arguments, ignored.
1492 */
1493static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1494{
1495 char szInstruction[256];
1496 /* @todo SMP support! */
1497 PVMCPU pVCpu = VMMGetCpu(pVM);
1498 if (!pVCpu)
1499 pVCpu = &pVM->aCpus[0];
1500
1501 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1502 if (RT_SUCCESS(rc))
1503 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1504}
1505
1506
1507/**
1508 * Display the hypervisor cpu state.
1509 *
1510 * @param pVM VM Handle.
1511 * @param pHlp The info helper functions.
1512 * @param pszArgs Arguments, ignored.
1513 */
1514static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1515{
1516 CPUMDUMPTYPE enmType;
1517 const char *pszComment;
1518 /* @todo SMP */
1519 PVMCPU pVCpu = &pVM->aCpus[0];
1520
1521 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1522 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1523 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1524 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1525}
1526
1527
1528/**
1529 * Display the host cpu state.
1530 *
1531 * @param pVM VM Handle.
1532 * @param pHlp The info helper functions.
1533 * @param pszArgs Arguments, ignored.
1534 */
1535static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1536{
1537 CPUMDUMPTYPE enmType;
1538 const char *pszComment;
1539 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1540 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1541
1542 /*
1543 * Format the EFLAGS.
1544 */
1545 /* @todo SMP */
1546 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1547#if HC_ARCH_BITS == 32
1548 uint32_t efl = pCtx->eflags.u32;
1549#else
1550 uint64_t efl = pCtx->rflags;
1551#endif
1552 char szEFlags[80];
1553 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1554
1555 /*
1556 * Format the registers.
1557 */
1558#if HC_ARCH_BITS == 32
1559# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1560 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1561# endif
1562 {
1563 pHlp->pfnPrintf(pHlp,
1564 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1565 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1566 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1567 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1568 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1569 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1570 ,
1571 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1572 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1573 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1574 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1575 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1576 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1577 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1578 }
1579# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1580 else
1581# endif
1582#endif
1583#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1584 {
1585 pHlp->pfnPrintf(pHlp,
1586 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1587 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1588 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1589 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1590 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1591 "r14=%016RX64 r15=%016RX64\n"
1592 "iopl=%d %31s\n"
1593 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1594 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1595 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1596 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1597 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1598 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1599 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1600 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1601 ,
1602 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1603 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1604 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1605 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1606 pCtx->r11, pCtx->r12, pCtx->r13,
1607 pCtx->r14, pCtx->r15,
1608 X86_EFL_GET_IOPL(efl), szEFlags,
1609 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1610 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1611 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1612 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1613 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1614 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1615 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1616 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1617 }
1618#endif
1619}
1620
1621
1622/**
1623 * Get L1 cache / TLS associativity.
1624 */
1625static const char *getCacheAss(unsigned u, char *pszBuf)
1626{
1627 if (u == 0)
1628 return "res0 ";
1629 if (u == 1)
1630 return "direct";
1631 if (u >= 256)
1632 return "???";
1633
1634 RTStrPrintf(pszBuf, 16, "%d way", u);
1635 return pszBuf;
1636}
1637
1638
1639/**
1640 * Get L2 cache soociativity.
1641 */
1642const char *getL2CacheAss(unsigned u)
1643{
1644 switch (u)
1645 {
1646 case 0: return "off ";
1647 case 1: return "direct";
1648 case 2: return "2 way ";
1649 case 3: return "res3 ";
1650 case 4: return "4 way ";
1651 case 5: return "res5 ";
1652 case 6: return "8 way "; case 7: return "res7 ";
1653 case 8: return "16 way";
1654 case 9: return "res9 ";
1655 case 10: return "res10 ";
1656 case 11: return "res11 ";
1657 case 12: return "res12 ";
1658 case 13: return "res13 ";
1659 case 14: return "res14 ";
1660 case 15: return "fully ";
1661 default:
1662 return "????";
1663 }
1664}
1665
1666
1667/**
1668 * Display the guest CpuId leaves.
1669 *
1670 * @param pVM VM Handle.
1671 * @param pHlp The info helper functions.
1672 * @param pszArgs "terse", "default" or "verbose".
1673 */
1674static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1675{
1676 /*
1677 * Parse the argument.
1678 */
1679 unsigned iVerbosity = 1;
1680 if (pszArgs)
1681 {
1682 pszArgs = RTStrStripL(pszArgs);
1683 if (!strcmp(pszArgs, "terse"))
1684 iVerbosity--;
1685 else if (!strcmp(pszArgs, "verbose"))
1686 iVerbosity++;
1687 }
1688
1689 /*
1690 * Start cracking.
1691 */
1692 CPUMCPUID Host;
1693 CPUMCPUID Guest;
1694 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1695
1696 pHlp->pfnPrintf(pHlp,
1697 " RAW Standard CPUIDs\n"
1698 " Function eax ebx ecx edx\n");
1699 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1700 {
1701 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1702 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1703
1704 pHlp->pfnPrintf(pHlp,
1705 "Gst: %08x %08x %08x %08x %08x%s\n"
1706 "Hst: %08x %08x %08x %08x\n",
1707 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1708 i <= cStdMax ? "" : "*",
1709 Host.eax, Host.ebx, Host.ecx, Host.edx);
1710 }
1711
1712 /*
1713 * If verbose, decode it.
1714 */
1715 if (iVerbosity)
1716 {
1717 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1718 pHlp->pfnPrintf(pHlp,
1719 "Name: %.04s%.04s%.04s\n"
1720 "Supports: 0-%x\n",
1721 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1722 }
1723
1724 /*
1725 * Get Features.
1726 */
1727 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1728 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1729 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1730 if (cStdMax >= 1 && iVerbosity)
1731 {
1732 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1733 uint32_t uEAX = Guest.eax;
1734
1735 pHlp->pfnPrintf(pHlp,
1736 "Family: %d \tExtended: %d \tEffective: %d\n"
1737 "Model: %d \tExtended: %d \tEffective: %d\n"
1738 "Stepping: %d\n"
1739 "APIC ID: %#04x\n"
1740 "Logical CPUs: %d\n"
1741 "CLFLUSH Size: %d\n"
1742 "Brand ID: %#04x\n",
1743 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1744 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1745 ASMGetCpuStepping(uEAX),
1746 (Guest.ebx >> 24) & 0xff,
1747 (Guest.ebx >> 16) & 0xff,
1748 (Guest.ebx >> 8) & 0xff,
1749 (Guest.ebx >> 0) & 0xff);
1750 if (iVerbosity == 1)
1751 {
1752 uint32_t uEDX = Guest.edx;
1753 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1754 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1755 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1756 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1757 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1758 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1759 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1760 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1761 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1762 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1763 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1764 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1765 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1766 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1767 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1768 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1769 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1770 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1771 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1772 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1773 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1774 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1775 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1776 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1777 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1778 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1779 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1780 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1781 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1782 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1783 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1784 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1785 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1786 pHlp->pfnPrintf(pHlp, "\n");
1787
1788 uint32_t uECX = Guest.ecx;
1789 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1790 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1791 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1792 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1793 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1794 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1795 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1796 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1797 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1798 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1799 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1800 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1801 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1802 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1803 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1804 for (unsigned iBit = 14; iBit < 32; iBit++)
1805 if (uECX & RT_BIT(iBit))
1806 pHlp->pfnPrintf(pHlp, " %d", iBit);
1807 pHlp->pfnPrintf(pHlp, "\n");
1808 }
1809 else
1810 {
1811 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1812
1813 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1814 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1815 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1816 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1817
1818 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1819 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1820 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1821 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1822 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1823 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1824 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1825 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1826 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1827 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1828 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1829 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1830 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1831 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1832 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1833 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1834 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1835 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1836 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1837 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1838 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1839 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1840 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1841 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1842 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1843 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1844 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1845 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1846 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1847 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1848 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1849 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1850 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1851
1852 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1853 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
1854 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
1855 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1856 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1857 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1858 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
1859 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1860 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1861 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1862 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1863 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved2, EcxHost.u2Reserved2);
1864 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1865 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1866 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
1867 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
1868 pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
1869 pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
1870 pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
1871 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
1872 pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
1873 pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
1874 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1875 pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
1876 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
1877 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
1878 }
1879 }
1880 if (cStdMax >= 2 && iVerbosity)
1881 {
1882 /** @todo */
1883 }
1884
1885 /*
1886 * Extended.
1887 * Implemented after AMD specs.
1888 */
1889 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1890
1891 pHlp->pfnPrintf(pHlp,
1892 "\n"
1893 " RAW Extended CPUIDs\n"
1894 " Function eax ebx ecx edx\n");
1895 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1896 {
1897 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1898 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1899
1900 pHlp->pfnPrintf(pHlp,
1901 "Gst: %08x %08x %08x %08x %08x%s\n"
1902 "Hst: %08x %08x %08x %08x\n",
1903 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1904 i <= cExtMax ? "" : "*",
1905 Host.eax, Host.ebx, Host.ecx, Host.edx);
1906 }
1907
1908 /*
1909 * Understandable output
1910 */
1911 if (iVerbosity)
1912 {
1913 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1914 pHlp->pfnPrintf(pHlp,
1915 "Ext Name: %.4s%.4s%.4s\n"
1916 "Ext Supports: 0x80000000-%#010x\n",
1917 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1918 }
1919
1920 if (iVerbosity && cExtMax >= 1)
1921 {
1922 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1923 uint32_t uEAX = Guest.eax;
1924 pHlp->pfnPrintf(pHlp,
1925 "Family: %d \tExtended: %d \tEffective: %d\n"
1926 "Model: %d \tExtended: %d \tEffective: %d\n"
1927 "Stepping: %d\n"
1928 "Brand ID: %#05x\n",
1929 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1930 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1931 ASMGetCpuStepping(uEAX),
1932 Guest.ebx & 0xfff);
1933
1934 if (iVerbosity == 1)
1935 {
1936 uint32_t uEDX = Guest.edx;
1937 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1938 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1939 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1940 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1941 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1942 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1943 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1944 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1945 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1946 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1947 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1948 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1949 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1950 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1951 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1952 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1953 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1954 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1955 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1956 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1957 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1958 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1959 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1960 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1961 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1962 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1963 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1964 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1965 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1966 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1967 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1968 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1969 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1970 pHlp->pfnPrintf(pHlp, "\n");
1971
1972 uint32_t uECX = Guest.ecx;
1973 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1974 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1975 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1976 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1977 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1978 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1979 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1980 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1981 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1982 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1983 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1984 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1985 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1986 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1987 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1988 for (unsigned iBit = 5; iBit < 32; iBit++)
1989 if (uECX & RT_BIT(iBit))
1990 pHlp->pfnPrintf(pHlp, " %d", iBit);
1991 pHlp->pfnPrintf(pHlp, "\n");
1992 }
1993 else
1994 {
1995 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1996
1997 uint32_t uEdxGst = Guest.edx;
1998 uint32_t uEdxHst = Host.edx;
1999 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2000 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2001 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2002 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2003 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2004 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2005 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2006 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2007 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2008 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2009 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2010 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2011 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2012 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2013 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2014 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
2015 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
2016 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
2017 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
2018 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
2019 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
2020 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
2021 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
2022 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
2023 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
2024 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
2025 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
2026 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
2027 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
2028 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
2029 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
2030 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
2031 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
2032
2033 uint32_t uEcxGst = Guest.ecx;
2034 uint32_t uEcxHst = Host.ecx;
2035 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
2036 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
2037 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
2038 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
2039 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
2040 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
2041 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
2042 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
2043 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
2044 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
2045 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
2046 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
2047 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
2048 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
2049 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
2050 }
2051 }
2052
2053 if (iVerbosity && cExtMax >= 2)
2054 {
2055 char szString[4*4*3+1] = {0};
2056 uint32_t *pu32 = (uint32_t *)szString;
2057 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
2058 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
2059 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
2060 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
2061 if (cExtMax >= 3)
2062 {
2063 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
2064 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
2065 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2066 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2067 }
2068 if (cExtMax >= 4)
2069 {
2070 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2071 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2072 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2073 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2074 }
2075 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2076 }
2077
2078 if (iVerbosity && cExtMax >= 5)
2079 {
2080 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2081 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2082 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2083 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2084 char sz1[32];
2085 char sz2[32];
2086
2087 pHlp->pfnPrintf(pHlp,
2088 "TLB 2/4M Instr/Uni: %s %3d entries\n"
2089 "TLB 2/4M Data: %s %3d entries\n",
2090 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2091 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2092 pHlp->pfnPrintf(pHlp,
2093 "TLB 4K Instr/Uni: %s %3d entries\n"
2094 "TLB 4K Data: %s %3d entries\n",
2095 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2096 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2097 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2098 "L1 Instr Cache Lines Per Tag: %d\n"
2099 "L1 Instr Cache Associativity: %s\n"
2100 "L1 Instr Cache Size: %d KB\n",
2101 (uEDX >> 0) & 0xff,
2102 (uEDX >> 8) & 0xff,
2103 getCacheAss((uEDX >> 16) & 0xff, sz1),
2104 (uEDX >> 24) & 0xff);
2105 pHlp->pfnPrintf(pHlp,
2106 "L1 Data Cache Line Size: %d bytes\n"
2107 "L1 Data Cache Lines Per Tag: %d\n"
2108 "L1 Data Cache Associativity: %s\n"
2109 "L1 Data Cache Size: %d KB\n",
2110 (uECX >> 0) & 0xff,
2111 (uECX >> 8) & 0xff,
2112 getCacheAss((uECX >> 16) & 0xff, sz1),
2113 (uECX >> 24) & 0xff);
2114 }
2115
2116 if (iVerbosity && cExtMax >= 6)
2117 {
2118 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2119 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2120 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2121
2122 pHlp->pfnPrintf(pHlp,
2123 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2124 "L2 TLB 2/4M Data: %s %4d entries\n",
2125 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2126 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2127 pHlp->pfnPrintf(pHlp,
2128 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2129 "L2 TLB 4K Data: %s %4d entries\n",
2130 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2131 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2132 pHlp->pfnPrintf(pHlp,
2133 "L2 Cache Line Size: %d bytes\n"
2134 "L2 Cache Lines Per Tag: %d\n"
2135 "L2 Cache Associativity: %s\n"
2136 "L2 Cache Size: %d KB\n",
2137 (uEDX >> 0) & 0xff,
2138 (uEDX >> 8) & 0xf,
2139 getL2CacheAss((uEDX >> 12) & 0xf),
2140 (uEDX >> 16) & 0xffff);
2141 }
2142
2143 if (iVerbosity && cExtMax >= 7)
2144 {
2145 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2146
2147 pHlp->pfnPrintf(pHlp, "APM Features: ");
2148 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2149 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2150 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2151 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2152 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2153 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2154 for (unsigned iBit = 6; iBit < 32; iBit++)
2155 if (uEDX & RT_BIT(iBit))
2156 pHlp->pfnPrintf(pHlp, " %d", iBit);
2157 pHlp->pfnPrintf(pHlp, "\n");
2158 }
2159
2160 if (iVerbosity && cExtMax >= 8)
2161 {
2162 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2163 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2164
2165 pHlp->pfnPrintf(pHlp,
2166 "Physical Address Width: %d bits\n"
2167 "Virtual Address Width: %d bits\n",
2168 (uEAX >> 0) & 0xff,
2169 (uEAX >> 8) & 0xff);
2170 pHlp->pfnPrintf(pHlp,
2171 "Physical Core Count: %d\n",
2172 (uECX >> 0) & 0xff);
2173 }
2174
2175
2176 /*
2177 * Centaur.
2178 */
2179 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2180
2181 pHlp->pfnPrintf(pHlp,
2182 "\n"
2183 " RAW Centaur CPUIDs\n"
2184 " Function eax ebx ecx edx\n");
2185 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2186 {
2187 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2188 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2189
2190 pHlp->pfnPrintf(pHlp,
2191 "Gst: %08x %08x %08x %08x %08x%s\n"
2192 "Hst: %08x %08x %08x %08x\n",
2193 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2194 i <= cCentaurMax ? "" : "*",
2195 Host.eax, Host.ebx, Host.ecx, Host.edx);
2196 }
2197
2198 /*
2199 * Understandable output
2200 */
2201 if (iVerbosity)
2202 {
2203 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2204 pHlp->pfnPrintf(pHlp,
2205 "Centaur Supports: 0xc0000000-%#010x\n",
2206 Guest.eax);
2207 }
2208
2209 if (iVerbosity && cCentaurMax >= 1)
2210 {
2211 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2212 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2213 uint32_t uEdxHst = Host.edx;
2214
2215 if (iVerbosity == 1)
2216 {
2217 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2218 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2219 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2220 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2221 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2222 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2223 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2224 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2225 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2226 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2227 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2228 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2229 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2230 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2231 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2232 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2233 for (unsigned iBit = 14; iBit < 32; iBit++)
2234 if (uEdxGst & RT_BIT(iBit))
2235 pHlp->pfnPrintf(pHlp, " %d", iBit);
2236 pHlp->pfnPrintf(pHlp, "\n");
2237 }
2238 else
2239 {
2240 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2241 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2242 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2243 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2244 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2245 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2246 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2247 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2248 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2249 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2250 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2251 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2252 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2253 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2254 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2255 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2256 for (unsigned iBit = 14; iBit < 32; iBit++)
2257 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2258 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2259 pHlp->pfnPrintf(pHlp, "\n");
2260 }
2261 }
2262}
2263
2264
2265/**
2266 * Structure used when disassembling and instructions in DBGF.
2267 * This is used so the reader function can get the stuff it needs.
2268 */
2269typedef struct CPUMDISASSTATE
2270{
2271 /** Pointer to the CPU structure. */
2272 PDISCPUSTATE pCpu;
2273 /** The VM handle. */
2274 PVM pVM;
2275 /** The VMCPU handle. */
2276 PVMCPU pVCpu;
2277 /** Pointer to the first byte in the segemnt. */
2278 RTGCUINTPTR GCPtrSegBase;
2279 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2280 RTGCUINTPTR GCPtrSegEnd;
2281 /** The size of the segment minus 1. */
2282 RTGCUINTPTR cbSegLimit;
2283 /** Pointer to the current page - R3 Ptr. */
2284 void const *pvPageR3;
2285 /** Pointer to the current page - GC Ptr. */
2286 RTGCPTR pvPageGC;
2287 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2288 PGMPAGEMAPLOCK PageMapLock;
2289 /** Whether the PageMapLock is valid or not. */
2290 bool fLocked;
2291 /** 64 bits mode or not. */
2292 bool f64Bits;
2293} CPUMDISASSTATE, *PCPUMDISASSTATE;
2294
2295
2296/**
2297 * Instruction reader.
2298 *
2299 * @returns VBox status code.
2300 * @param PtrSrc Address to read from.
2301 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2302 * @param pu8Dst Where to store the bytes.
2303 * @param cbRead Number of bytes to read.
2304 * @param uDisCpu Pointer to the disassembler cpu state.
2305 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2306 */
2307static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2308{
2309 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2310 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2311 Assert(cbRead > 0);
2312 for (;;)
2313 {
2314 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2315
2316 /* Need to update the page translation? */
2317 if ( !pState->pvPageR3
2318 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2319 {
2320 int rc = VINF_SUCCESS;
2321
2322 /* translate the address */
2323 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2324 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2325 && !HWACCMIsEnabled(pState->pVM))
2326 {
2327 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2328 if (!pState->pvPageR3)
2329 rc = VERR_INVALID_POINTER;
2330 }
2331 else
2332 {
2333 /* Release mapping lock previously acquired. */
2334 if (pState->fLocked)
2335 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2336 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2337 pState->fLocked = RT_SUCCESS_NP(rc);
2338 }
2339 if (RT_FAILURE(rc))
2340 {
2341 pState->pvPageR3 = NULL;
2342 return rc;
2343 }
2344 }
2345
2346 /* check the segemnt limit */
2347 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2348 return VERR_OUT_OF_SELECTOR_BOUNDS;
2349
2350 /* calc how much we can read */
2351 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2352 if (!pState->f64Bits)
2353 {
2354 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2355 if (cb > cbSeg && cbSeg)
2356 cb = cbSeg;
2357 }
2358 if (cb > cbRead)
2359 cb = cbRead;
2360
2361 /* read and advance */
2362 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2363 cbRead -= cb;
2364 if (!cbRead)
2365 return VINF_SUCCESS;
2366 pu8Dst += cb;
2367 PtrSrc += cb;
2368 }
2369}
2370
2371
2372/**
2373 * Disassemble an instruction and return the information in the provided structure.
2374 *
2375 * @returns VBox status code.
2376 * @param pVM VM Handle
2377 * @param pVCpu VMCPU Handle
2378 * @param pCtx CPU context
2379 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2380 * @param pCpu Disassembly state
2381 * @param pszPrefix String prefix for logging (debug only)
2382 *
2383 */
2384VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2385{
2386 CPUMDISASSTATE State;
2387 int rc;
2388
2389 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2390 State.pCpu = pCpu;
2391 State.pvPageGC = 0;
2392 State.pvPageR3 = NULL;
2393 State.pVM = pVM;
2394 State.pVCpu = pVCpu;
2395 State.fLocked = false;
2396 State.f64Bits = false;
2397
2398 /*
2399 * Get selector information.
2400 */
2401 if ( (pCtx->cr0 & X86_CR0_PE)
2402 && pCtx->eflags.Bits.u1VM == 0)
2403 {
2404 if (CPUMAreHiddenSelRegsValid(pVM))
2405 {
2406 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2407 State.GCPtrSegBase = pCtx->csHid.u64Base;
2408 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2409 State.cbSegLimit = pCtx->csHid.u32Limit;
2410 pCpu->mode = (State.f64Bits)
2411 ? CPUMODE_64BIT
2412 : pCtx->csHid.Attr.n.u1DefBig
2413 ? CPUMODE_32BIT
2414 : CPUMODE_16BIT;
2415 }
2416 else
2417 {
2418 DBGFSELINFO SelInfo;
2419
2420 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2421 if (RT_FAILURE(rc))
2422 {
2423 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2424 return rc;
2425 }
2426
2427 /*
2428 * Validate the selector.
2429 */
2430 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2431 if (RT_FAILURE(rc))
2432 {
2433 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2434 return rc;
2435 }
2436 State.GCPtrSegBase = SelInfo.GCPtrBase;
2437 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2438 State.cbSegLimit = SelInfo.cbLimit;
2439 pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2440 }
2441 }
2442 else
2443 {
2444 /* real or V86 mode */
2445 pCpu->mode = CPUMODE_16BIT;
2446 State.GCPtrSegBase = pCtx->cs * 16;
2447 State.GCPtrSegEnd = 0xFFFFFFFF;
2448 State.cbSegLimit = 0xFFFFFFFF;
2449 }
2450
2451 /*
2452 * Disassemble the instruction.
2453 */
2454 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2455 pCpu->apvUserData[0] = &State;
2456
2457 uint32_t cbInstr;
2458#ifndef LOG_ENABLED
2459 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2460 if (RT_SUCCESS(rc))
2461 {
2462#else
2463 char szOutput[160];
2464 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2465 if (RT_SUCCESS(rc))
2466 {
2467 /* log it */
2468 if (pszPrefix)
2469 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2470 else
2471 Log(("%s", szOutput));
2472#endif
2473 rc = VINF_SUCCESS;
2474 }
2475 else
2476 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2477
2478 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2479 if (State.fLocked)
2480 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2481
2482 return rc;
2483}
2484
2485#ifdef DEBUG
2486
2487/**
2488 * Disassemble an instruction and dump it to the log
2489 *
2490 * @returns VBox status code.
2491 * @param pVM VM Handle
2492 * @param pVCpu VMCPU Handle
2493 * @param pCtx CPU context
2494 * @param pc GC instruction pointer
2495 * @param pszPrefix String prefix for logging
2496 *
2497 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2498 */
2499VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2500{
2501 DISCPUSTATE Cpu;
2502 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2503}
2504
2505
2506/**
2507 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2508 *
2509 * @internal
2510 */
2511VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2512{
2513 /* @todo SMP support!! */
2514 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2515}
2516
2517#endif /* DEBUG */
2518
2519/**
2520 * API for controlling a few of the CPU features found in CR4.
2521 *
2522 * Currently only X86_CR4_TSD is accepted as input.
2523 *
2524 * @returns VBox status code.
2525 *
2526 * @param pVM The VM handle.
2527 * @param fOr The CR4 OR mask.
2528 * @param fAnd The CR4 AND mask.
2529 */
2530VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2531{
2532 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2533 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2534
2535 pVM->cpum.s.CR4.OrMask &= fAnd;
2536 pVM->cpum.s.CR4.OrMask |= fOr;
2537
2538 return VINF_SUCCESS;
2539}
2540
2541
2542/**
2543 * Gets a pointer to the array of standard CPUID leafs.
2544 *
2545 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2546 *
2547 * @returns Pointer to the standard CPUID leafs (read-only).
2548 * @param pVM The VM handle.
2549 * @remark Intended for PATM.
2550 */
2551VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2552{
2553 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2554}
2555
2556
2557/**
2558 * Gets a pointer to the array of extended CPUID leafs.
2559 *
2560 * CPUMGetGuestCpuIdExtMax() give the size of the array.
2561 *
2562 * @returns Pointer to the extended CPUID leafs (read-only).
2563 * @param pVM The VM handle.
2564 * @remark Intended for PATM.
2565 */
2566VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2567{
2568 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2569}
2570
2571
2572/**
2573 * Gets a pointer to the array of centaur CPUID leafs.
2574 *
2575 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2576 *
2577 * @returns Pointer to the centaur CPUID leafs (read-only).
2578 * @param pVM The VM handle.
2579 * @remark Intended for PATM.
2580 */
2581VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2582{
2583 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2584}
2585
2586
2587/**
2588 * Gets a pointer to the default CPUID leaf.
2589 *
2590 * @returns Pointer to the default CPUID leaf (read-only).
2591 * @param pVM The VM handle.
2592 * @remark Intended for PATM.
2593 */
2594VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2595{
2596 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2597}
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