VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 22480

Last change on this file since 22480 was 22480, checked in by vboxsync, 15 years ago

SSM,VMM,Devices,Main,VBoxBFE: Live snapshot/migration SSM API adjustments.
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1/* $Id: CPUM.cpp 22480 2009-08-26 17:14:13Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 10
71/** The saved state version for the 2.1 trunk before the MSR changes. */
72#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
73/** The saved state version of 2.0, used for backwards compatibility. */
74#define CPUM_SAVED_STATE_VERSION_VER2_0 8
75/** The saved state version of 1.6, used for backwards compatability. */
76#define CPUM_SAVED_STATE_VERSION_VER1_6 6
77
78
79/*******************************************************************************
80* Structures and Typedefs *
81*******************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91
92} CPUMDUMPTYPE;
93/** Pointer to a cpu info dump type. */
94typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97/*******************************************************************************
98* Internal Functions *
99*******************************************************************************/
100static int cpumR3CpuIdInit(PVM pVM);
101static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPhase);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/**
112 * Initializes the CPUM.
113 *
114 * @returns VBox status code.
115 * @param pVM The VM to operate on.
116 */
117VMMR3DECL(int) CPUMR3Init(PVM pVM)
118{
119 LogFlow(("CPUMR3Init\n"));
120
121 /*
122 * Assert alignment and sizes.
123 */
124 AssertCompileMemberAlignment(VM, cpum.s, 32);
125 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
126 AssertCompileSizeAlignment(CPUMCTX, 64);
127 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
128 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
129 AssertCompileMemberAlignment(VM, cpum, 64);
130 AssertCompileMemberAlignment(VM, aCpus, 64);
131 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
132 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
133
134 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
135 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
136 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
137
138 /* Calculate the offset from CPUMCPU to CPUM. */
139 for (unsigned i=0;i<pVM->cCPUs;i++)
140 {
141 PVMCPU pVCpu = &pVM->aCpus[i];
142
143 /*
144 * Setup any fixed pointers and offsets.
145 */
146 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
147 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
148
149 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
150 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
151 }
152
153 /*
154 * Check that the CPU supports the minimum features we require.
155 */
156 if (!ASMHasCpuId())
157 {
158 Log(("The CPU doesn't support CPUID!\n"));
159 return VERR_UNSUPPORTED_CPU;
160 }
161 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
162 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
163
164 /* Setup the CR4 AND and OR masks used in the switcher */
165 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
166 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
167 {
168 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
169 /* No FXSAVE implies no SSE */
170 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
171 pVM->cpum.s.CR4.OrMask = 0;
172 }
173 else
174 {
175 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
176 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
177 }
178
179 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
180 {
181 Log(("The CPU doesn't support MMX!\n"));
182 return VERR_UNSUPPORTED_CPU;
183 }
184 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
185 {
186 Log(("The CPU doesn't support TSC!\n"));
187 return VERR_UNSUPPORTED_CPU;
188 }
189 /* Bogus on AMD? */
190 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
191 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
192
193 /*
194 * Setup hypervisor startup values.
195 */
196
197 /*
198 * Register saved state data item.
199 */
200 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
201 NULL, NULL, NULL,
202 NULL, cpumR3Save, NULL,
203 NULL, cpumR3Load, NULL);
204 if (RT_FAILURE(rc))
205 return rc;
206
207 /* Query the CPU manufacturer. */
208 uint32_t uEAX, uEBX, uECX, uEDX;
209 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
210 if ( uEAX >= 1
211 && uEBX == X86_CPUID_VENDOR_AMD_EBX
212 && uECX == X86_CPUID_VENDOR_AMD_ECX
213 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
214 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
215 else if ( uEAX >= 1
216 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
217 && uECX == X86_CPUID_VENDOR_INTEL_ECX
218 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
219 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
220 else /** @todo Via */
221 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
222
223 /*
224 * Register info handlers.
225 */
226 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
227 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
228 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
229 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
230 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
231 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
232
233 /*
234 * Initialize the Guest CPU state.
235 */
236 rc = cpumR3CpuIdInit(pVM);
237 if (RT_FAILURE(rc))
238 return rc;
239 CPUMR3Reset(pVM);
240 return VINF_SUCCESS;
241}
242
243
244/**
245 * Initializes the per-VCPU CPUM.
246 *
247 * @returns VBox status code.
248 * @param pVM The VM to operate on.
249 */
250VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
251{
252 LogFlow(("CPUMR3InitCPU\n"));
253 return VINF_SUCCESS;
254}
255
256
257/**
258 * Initializes the emulated CPU's cpuid information.
259 *
260 * @returns VBox status code.
261 * @param pVM The VM to operate on.
262 */
263static int cpumR3CpuIdInit(PVM pVM)
264{
265 PCPUM pCPUM = &pVM->cpum.s;
266 uint32_t i;
267
268 /*
269 * Get the host CPUIDs.
270 */
271 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
272 ASMCpuId_Idx_ECX(i, 0,
273 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
274 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
275 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
276 ASMCpuId(0x80000000 + i,
277 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
278 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
279 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
280 ASMCpuId(0xc0000000 + i,
281 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
282 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
283
284
285 /*
286 * Only report features we can support.
287 */
288 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
289 | X86_CPUID_FEATURE_EDX_VME
290 | X86_CPUID_FEATURE_EDX_DE
291 | X86_CPUID_FEATURE_EDX_PSE
292 | X86_CPUID_FEATURE_EDX_TSC
293 | X86_CPUID_FEATURE_EDX_MSR
294 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
295 | X86_CPUID_FEATURE_EDX_MCE
296 | X86_CPUID_FEATURE_EDX_CX8
297 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
298 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
299 //| X86_CPUID_FEATURE_EDX_SEP
300 | X86_CPUID_FEATURE_EDX_MTRR
301 | X86_CPUID_FEATURE_EDX_PGE
302 | X86_CPUID_FEATURE_EDX_MCA
303 | X86_CPUID_FEATURE_EDX_CMOV
304 | X86_CPUID_FEATURE_EDX_PAT
305 | X86_CPUID_FEATURE_EDX_PSE36
306 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
307 | X86_CPUID_FEATURE_EDX_CLFSH
308 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
309 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
310 | X86_CPUID_FEATURE_EDX_MMX
311 | X86_CPUID_FEATURE_EDX_FXSR
312 | X86_CPUID_FEATURE_EDX_SSE
313 | X86_CPUID_FEATURE_EDX_SSE2
314 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
315 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
316 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
317 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
318 | 0;
319 pCPUM->aGuestCpuIdStd[1].ecx &= 0
320 | X86_CPUID_FEATURE_ECX_SSE3
321 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
322 | ((pVM->cCPUs == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
323 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
324 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
325 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
326 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
327 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
328 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
329 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
330 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
331 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
332 /* ECX Bit 21 - x2APIC support - not yet. */
333 // | X86_CPUID_FEATURE_ECX_X2APIC
334 /* ECX Bit 23 - POPCOUNT instruction. */
335 //| X86_CPUID_FEATURE_ECX_POPCOUNT
336 | 0;
337
338 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
339 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
340 | X86_CPUID_AMD_FEATURE_EDX_VME
341 | X86_CPUID_AMD_FEATURE_EDX_DE
342 | X86_CPUID_AMD_FEATURE_EDX_PSE
343 | X86_CPUID_AMD_FEATURE_EDX_TSC
344 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
345 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
346 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
347 | X86_CPUID_AMD_FEATURE_EDX_CX8
348 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
349 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
350 //| X86_CPUID_AMD_FEATURE_EDX_SEP
351 | X86_CPUID_AMD_FEATURE_EDX_MTRR
352 | X86_CPUID_AMD_FEATURE_EDX_PGE
353 | X86_CPUID_AMD_FEATURE_EDX_MCA
354 | X86_CPUID_AMD_FEATURE_EDX_CMOV
355 | X86_CPUID_AMD_FEATURE_EDX_PAT
356 | X86_CPUID_AMD_FEATURE_EDX_PSE36
357 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
358 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
359 | X86_CPUID_AMD_FEATURE_EDX_MMX
360 | X86_CPUID_AMD_FEATURE_EDX_FXSR
361 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
362 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
363 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
364 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
365 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
366 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
367 | 0;
368 pCPUM->aGuestCpuIdExt[1].ecx &= 0
369 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
370 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
371 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
372 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
373 /** Note: This could prevent migration from AMD to Intel CPUs! */
374 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
375 //| X86_CPUID_AMD_FEATURE_ECX_ABM
376 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
377 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
378 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
379 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
380 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
381 //| X86_CPUID_AMD_FEATURE_ECX_WDT
382 | 0;
383
384 /*
385 * Hide HTT, multicode, SMP, whatever.
386 * (APIC-ID := 0 and #LogCpus := 0)
387 */
388 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
389#ifdef VBOX_WITH_MULTI_CORE
390 if (pVM->cCPUs > 1)
391 {
392 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
393 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCPUs << 16);
394 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
395 }
396#endif
397
398 /* Cpuid 2:
399 * Intel: Cache and TLB information
400 * AMD: Reserved
401 * Safe to expose
402 */
403
404 /* Cpuid 3:
405 * Intel: EAX, EBX - reserved
406 * ECX, EDX - Processor Serial Number if available, otherwise reserved
407 * AMD: Reserved
408 * Safe to expose
409 */
410 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
411 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
412
413 /* Cpuid 4:
414 * Intel: Deterministic Cache Parameters Leaf
415 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
416 * AMD: Reserved
417 * Safe to expose, except for EAX:
418 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
419 * Bits 31-26: Maximum number of processor cores in this physical package**
420 * @Note These SMP values are constant regardless of ECX
421 */
422 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
423 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
424#ifdef VBOX_WITH_MULTI_CORE
425 if ( pVM->cCPUs > 1
426 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_INTEL)
427 {
428 AssertReturn(pVM->cCPUs <= 64, VERR_TOO_MANY_CPUS);
429 /* One logical processor with possibly multiple cores. */
430 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
431 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCPUs - 1) << 26); /* 6 bits only -> 64 cores! */
432 }
433#endif
434
435 /* Cpuid 5: Monitor/mwait Leaf
436 * Intel: ECX, EDX - reserved
437 * EAX, EBX - Smallest and largest monitor line size
438 * AMD: EDX - reserved
439 * EAX, EBX - Smallest and largest monitor line size
440 * ECX - extensions (ignored for now)
441 * Safe to expose
442 */
443 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
444 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
445
446 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
447
448 /*
449 * Determine the default.
450 *
451 * Intel returns values of the highest standard function, while AMD
452 * returns zeros. VIA on the other hand seems to returning nothing or
453 * perhaps some random garbage, we don't try to duplicate this behavior.
454 */
455 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
456 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
457 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
458
459 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
460 * Safe to pass on to the guest.
461 *
462 * Intel: 0x800000005 reserved
463 * 0x800000006 L2 cache information
464 * AMD: 0x800000005 L1 cache information
465 * 0x800000006 L2/L3 cache information
466 */
467
468 /* Cpuid 0x800000007:
469 * AMD: EAX, EBX, ECX - reserved
470 * EDX: Advanced Power Management Information
471 * Intel: Reserved
472 */
473 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
474 {
475 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
476
477 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
478
479 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
480 {
481 /* Only expose the TSC invariant capability bit to the guest. */
482 pCPUM->aGuestCpuIdExt[7].edx &= 0
483 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
484 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
485 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
486 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
487 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
488 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
489 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
490 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
491#if 1
492 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
493 * that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
494 */
495#else
496 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
497#endif
498 | 0;
499 }
500 else
501 pCPUM->aGuestCpuIdExt[7].edx = 0;
502 }
503
504 /* Cpuid 0x800000008:
505 * AMD: EBX, EDX - reserved
506 * EAX: Virtual/Physical address Size
507 * ECX: Number of cores + APICIdCoreIdSize
508 * Intel: EAX: Virtual/Physical address Size
509 * EBX, ECX, EDX - reserved
510 */
511 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
512 {
513 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
514 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
515 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
516 * NC (0-7) Number of cores; 0 equals 1 core */
517 pCPUM->aGuestCpuIdExt[8].ecx = 0;
518#ifdef VBOX_WITH_MULTI_CORE
519 if ( pVM->cCPUs > 1
520 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
521 {
522 /* Legacy method to determine the number of cores. */
523 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
524 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCPUs - 1); /* NC: Number of CPU cores - 1; 8 bits */
525
526 }
527#endif
528 }
529
530 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
531 * Limit the number of standard CPUID leafs to 0..2 to prevent NT4 from
532 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
533 * This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
534 * @todo r=bird: The intel docs states that leafs 3 is included, why don't we?
535 */
536 bool fNt4LeafLimit;
537 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "NT4LeafLimit", &fNt4LeafLimit, false);
538 if (fNt4LeafLimit)
539 pCPUM->aGuestCpuIdStd[0].eax = 2;
540
541 /*
542 * Limit it the number of entries and fill the remaining with the defaults.
543 *
544 * The limits are masking off stuff about power saving and similar, this
545 * is perhaps a bit crudely done as there is probably some relatively harmless
546 * info too in these leaves (like words about having a constant TSC).
547 */
548 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
549 pCPUM->aGuestCpuIdStd[0].eax = 5;
550
551 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
552 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
553
554 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
555 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
556 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
557 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
558 : 0;
559 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
560 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
561
562 /*
563 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
564 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
565 * of processors from (cpuid(4).eax >> 26) + 1.
566 */
567 if (pVM->cCPUs == 1)
568 pCPUM->aGuestCpuIdStd[4].eax = 0;
569
570 /*
571 * Centaur stuff (VIA).
572 *
573 * The important part here (we think) is to make sure the 0xc0000000
574 * function returns 0xc0000001. As for the features, we don't currently
575 * let on about any of those... 0xc0000002 seems to be some
576 * temperature/hz/++ stuff, include it as well (static).
577 */
578 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
579 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
580 {
581 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
582 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
583 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
584 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
585 i++)
586 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
587 }
588 else
589 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
590 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
591
592
593 /*
594 * Load CPUID overrides from configuration.
595 */
596 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
597 * Overloads the CPUID leaf values. */
598 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
599 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
600 for (i=0;; )
601 {
602 while (cElements-- > 0)
603 {
604 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
605 if (pNode)
606 {
607 uint32_t u32;
608 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
609 if (RT_SUCCESS(rc))
610 pCpuId->eax = u32;
611 else
612 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
613
614 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
615 if (RT_SUCCESS(rc))
616 pCpuId->ebx = u32;
617 else
618 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
619
620 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
621 if (RT_SUCCESS(rc))
622 pCpuId->ecx = u32;
623 else
624 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
625
626 rc = CFGMR3QueryU32(pNode, "edx", &u32);
627 if (RT_SUCCESS(rc))
628 pCpuId->edx = u32;
629 else
630 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
631 }
632 pCpuId++;
633 i++;
634 }
635
636 /* next */
637 if ((i & UINT32_C(0xc0000000)) == 0)
638 {
639 pCpuId = &pCPUM->aGuestCpuIdExt[0];
640 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
641 i = UINT32_C(0x80000000);
642 }
643 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
644 {
645 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
646 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
647 i = UINT32_C(0xc0000000);
648 }
649 else
650 break;
651 }
652
653 /* Check if PAE was explicitely enabled by the user. */
654 bool fEnable = false;
655 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
656 if (RT_SUCCESS(rc) && fEnable)
657 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
658
659 /*
660 * Log the cpuid and we're good.
661 */
662 RTCPUSET OnlineSet;
663 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
664 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
665 LogRel(("************************* CPUID dump ************************\n"));
666 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
667 LogRel(("\n"));
668 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
669 LogRel(("******************** End of CPUID dump **********************\n"));
670 return VINF_SUCCESS;
671}
672
673
674
675
676/**
677 * Applies relocations to data and code managed by this
678 * component. This function will be called at init and
679 * whenever the VMM need to relocate it self inside the GC.
680 *
681 * The CPUM will update the addresses used by the switcher.
682 *
683 * @param pVM The VM.
684 */
685VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
686{
687 LogFlow(("CPUMR3Relocate\n"));
688 for (unsigned i=0;i<pVM->cCPUs;i++)
689 {
690 PVMCPU pVCpu = &pVM->aCpus[i];
691 /*
692 * Switcher pointers.
693 */
694 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
695 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
696 }
697}
698
699
700/**
701 * Terminates the CPUM.
702 *
703 * Termination means cleaning up and freeing all resources,
704 * the VM it self is at this point powered off or suspended.
705 *
706 * @returns VBox status code.
707 * @param pVM The VM to operate on.
708 */
709VMMR3DECL(int) CPUMR3Term(PVM pVM)
710{
711 CPUMR3TermCPU(pVM);
712 return 0;
713}
714
715
716/**
717 * Terminates the per-VCPU CPUM.
718 *
719 * Termination means cleaning up and freeing all resources,
720 * the VM it self is at this point powered off or suspended.
721 *
722 * @returns VBox status code.
723 * @param pVM The VM to operate on.
724 */
725VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
726{
727#ifdef VBOX_WITH_CRASHDUMP_MAGIC
728 for (unsigned i=0;i<pVM->cCPUs;i++)
729 {
730 PVMCPU pVCpu = &pVM->aCpus[i];
731 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
732
733 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
734 pVCpu->cpum.s.uMagic = 0;
735 pCtx->dr[5] = 0;
736 }
737#endif
738 return 0;
739}
740
741VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
742{
743 /* @todo anything different for VCPU > 0? */
744 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
745
746 /*
747 * Initialize everything to ZERO first.
748 */
749 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
750 memset(pCtx, 0, sizeof(*pCtx));
751 pVCpu->cpum.s.fUseFlags = fUseFlags;
752
753 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
754 pCtx->eip = 0x0000fff0;
755 pCtx->edx = 0x00000600; /* P6 processor */
756 pCtx->eflags.Bits.u1Reserved0 = 1;
757
758 pCtx->cs = 0xf000;
759 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
760 pCtx->csHid.u32Limit = 0x0000ffff;
761 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
762 pCtx->csHid.Attr.n.u1Present = 1;
763 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
764
765 pCtx->dsHid.u32Limit = 0x0000ffff;
766 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
767 pCtx->dsHid.Attr.n.u1Present = 1;
768 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
769
770 pCtx->esHid.u32Limit = 0x0000ffff;
771 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
772 pCtx->esHid.Attr.n.u1Present = 1;
773 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
774
775 pCtx->fsHid.u32Limit = 0x0000ffff;
776 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
777 pCtx->fsHid.Attr.n.u1Present = 1;
778 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
779
780 pCtx->gsHid.u32Limit = 0x0000ffff;
781 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
782 pCtx->gsHid.Attr.n.u1Present = 1;
783 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
784
785 pCtx->ssHid.u32Limit = 0x0000ffff;
786 pCtx->ssHid.Attr.n.u1Present = 1;
787 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
788 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
789
790 pCtx->idtr.cbIdt = 0xffff;
791 pCtx->gdtr.cbGdt = 0xffff;
792
793 pCtx->ldtrHid.u32Limit = 0xffff;
794 pCtx->ldtrHid.Attr.n.u1Present = 1;
795 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
796
797 pCtx->trHid.u32Limit = 0xffff;
798 pCtx->trHid.Attr.n.u1Present = 1;
799 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
800
801 pCtx->dr[6] = X86_DR6_INIT_VAL;
802 pCtx->dr[7] = X86_DR7_INIT_VAL;
803
804 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
805 pCtx->fpu.FCW = 0x37f;
806
807 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
808 pCtx->fpu.MXCSR = 0x1F80;
809
810 /* Init PAT MSR */
811 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
812
813 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
814 * The Intel docs don't mention it.
815 */
816 pCtx->msrEFER = 0;
817}
818
819/**
820 * Resets the CPU.
821 *
822 * @returns VINF_SUCCESS.
823 * @param pVM The VM handle.
824 */
825VMMR3DECL(void) CPUMR3Reset(PVM pVM)
826{
827 for (unsigned i=0;i<pVM->cCPUs;i++)
828 {
829 CPUMR3ResetCpu(&pVM->aCpus[i]);
830
831#ifdef VBOX_WITH_CRASHDUMP_MAGIC
832 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
833
834 /* Magic marker for searching in crash dumps. */
835 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
836 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
837 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
838#endif
839 }
840}
841
842
843/**
844 * Execute state save operation.
845 *
846 * @returns VBox status code.
847 * @param pVM VM Handle.
848 * @param pSSM SSM operation handle.
849 */
850static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
851{
852 /*
853 * Save.
854 */
855 for (unsigned i=0;i<pVM->cCPUs;i++)
856 {
857 PVMCPU pVCpu = &pVM->aCpus[i];
858
859 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
860 }
861
862 SSMR3PutU32(pSSM, pVM->cCPUs);
863 for (unsigned i=0;i<pVM->cCPUs;i++)
864 {
865 PVMCPU pVCpu = &pVM->aCpus[i];
866
867 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
868 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
869 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
870 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
871 }
872
873 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
874 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
875
876 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
877 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
878
879 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
880 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
881
882 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
883
884 /* Add the cpuid for checking that the cpu is unchanged. */
885 uint32_t au32CpuId[8] = {0};
886 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
887 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
888 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
889}
890
891
892/**
893 * Load a version 1.6 CPUMCTX structure.
894 *
895 * @returns VBox status code.
896 * @param pVM VM Handle.
897 * @param pCpumctx16 Version 1.6 CPUMCTX
898 */
899static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
900{
901#define CPUMCTX16_LOADREG(RegName) \
902 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
903
904#define CPUMCTX16_LOADDRXREG(RegName) \
905 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
906
907#define CPUMCTX16_LOADHIDREG(RegName) \
908 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
909 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
910 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
911
912#define CPUMCTX16_LOADSEGREG(RegName) \
913 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
914 CPUMCTX16_LOADHIDREG(RegName);
915
916 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
917
918 CPUMCTX16_LOADREG(rax);
919 CPUMCTX16_LOADREG(rbx);
920 CPUMCTX16_LOADREG(rcx);
921 CPUMCTX16_LOADREG(rdx);
922 CPUMCTX16_LOADREG(rdi);
923 CPUMCTX16_LOADREG(rsi);
924 CPUMCTX16_LOADREG(rbp);
925 CPUMCTX16_LOADREG(esp);
926 CPUMCTX16_LOADREG(rip);
927 CPUMCTX16_LOADREG(rflags);
928
929 CPUMCTX16_LOADSEGREG(cs);
930 CPUMCTX16_LOADSEGREG(ds);
931 CPUMCTX16_LOADSEGREG(es);
932 CPUMCTX16_LOADSEGREG(fs);
933 CPUMCTX16_LOADSEGREG(gs);
934 CPUMCTX16_LOADSEGREG(ss);
935
936 CPUMCTX16_LOADREG(r8);
937 CPUMCTX16_LOADREG(r9);
938 CPUMCTX16_LOADREG(r10);
939 CPUMCTX16_LOADREG(r11);
940 CPUMCTX16_LOADREG(r12);
941 CPUMCTX16_LOADREG(r13);
942 CPUMCTX16_LOADREG(r14);
943 CPUMCTX16_LOADREG(r15);
944
945 CPUMCTX16_LOADREG(cr0);
946 CPUMCTX16_LOADREG(cr2);
947 CPUMCTX16_LOADREG(cr3);
948 CPUMCTX16_LOADREG(cr4);
949
950 CPUMCTX16_LOADDRXREG(0);
951 CPUMCTX16_LOADDRXREG(1);
952 CPUMCTX16_LOADDRXREG(2);
953 CPUMCTX16_LOADDRXREG(3);
954 CPUMCTX16_LOADDRXREG(4);
955 CPUMCTX16_LOADDRXREG(5);
956 CPUMCTX16_LOADDRXREG(6);
957 CPUMCTX16_LOADDRXREG(7);
958
959 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
960 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
961 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
962 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
963
964 CPUMCTX16_LOADREG(ldtr);
965 CPUMCTX16_LOADREG(tr);
966
967 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
968
969 CPUMCTX16_LOADREG(msrEFER);
970 CPUMCTX16_LOADREG(msrSTAR);
971 CPUMCTX16_LOADREG(msrPAT);
972 CPUMCTX16_LOADREG(msrLSTAR);
973 CPUMCTX16_LOADREG(msrCSTAR);
974 CPUMCTX16_LOADREG(msrSFMASK);
975 CPUMCTX16_LOADREG(msrKERNELGSBASE);
976
977 CPUMCTX16_LOADHIDREG(ldtr);
978 CPUMCTX16_LOADHIDREG(tr);
979
980#undef CPUMCTX16_LOADSEGREG
981#undef CPUMCTX16_LOADHIDREG
982#undef CPUMCTX16_LOADDRXREG
983#undef CPUMCTX16_LOADREG
984}
985
986
987/**
988 * Execute state load operation.
989 *
990 * @returns VBox status code.
991 * @param pVM VM Handle.
992 * @param pSSM SSM operation handle.
993 * @param uVersion Data layout version.
994 */
995static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPhase)
996{
997 Assert(uPhase == SSM_PHASE_FINAL); NOREF(uPhase);
998
999 /*
1000 * Validate version.
1001 */
1002 if ( uVersion != CPUM_SAVED_STATE_VERSION
1003 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1004 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1005 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1006 {
1007 AssertMsgFailed(("cpuR3Load: Invalid version uVersion=%d!\n", uVersion));
1008 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1009 }
1010
1011 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
1012 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1013 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1014 else if (uVersion <= CPUM_SAVED_STATE_VERSION)
1015 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1016
1017 /*
1018 * Restore.
1019 */
1020 for (VMCPUID i = 0; i < pVM->cCPUs; i++)
1021 {
1022 PVMCPU pVCpu = &pVM->aCpus[i];
1023 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1024 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1025
1026 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1027 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1028 pVCpu->cpum.s.Hyper.esp = uESP;
1029 }
1030
1031 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1032 {
1033 CPUMCTX_VER1_6 cpumctx16;
1034 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1035 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1036
1037 /* Save the old cpumctx state into the new one. */
1038 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1039
1040 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1041 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1042 }
1043 else
1044 {
1045 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1046 {
1047 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
1048 AssertRCReturn(rc, rc);
1049 }
1050
1051 if ( !pVM->cCPUs
1052 || pVM->cCPUs > VMM_MAX_CPU_COUNT
1053 || ( uVersion == CPUM_SAVED_STATE_VERSION_VER2_0
1054 && pVM->cCPUs != 1))
1055 {
1056 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
1057 return VERR_SSM_UNEXPECTED_DATA;
1058 }
1059
1060 for (VMCPUID i = 0; i < pVM->cCPUs; i++)
1061 {
1062 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1063 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1064 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1065 if (uVersion == CPUM_SAVED_STATE_VERSION)
1066 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1067 }
1068 }
1069
1070
1071 uint32_t cElements;
1072 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1073 /* Support old saved states with a smaller standard cpuid array. */
1074 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1075 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1076 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1077
1078 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1079 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1080 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1081 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1082
1083 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1084 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1085 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1086 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1087
1088 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1089
1090 /*
1091 * Check that the basic cpuid id information is unchanged.
1092 * @todo we should check the 64 bits capabilities too!
1093 */
1094 uint32_t au32CpuId[8] = {0};
1095 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1096 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1097 uint32_t au32CpuIdSaved[8];
1098 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1099 if (RT_SUCCESS(rc))
1100 {
1101 /* Ignore CPU stepping. */
1102 au32CpuId[4] &= 0xfffffff0;
1103 au32CpuIdSaved[4] &= 0xfffffff0;
1104
1105 /* Ignore APIC ID (AMD specs). */
1106 au32CpuId[5] &= ~0xff000000;
1107 au32CpuIdSaved[5] &= ~0xff000000;
1108
1109 /* Ignore the number of Logical CPUs (AMD specs). */
1110 au32CpuId[5] &= ~0x00ff0000;
1111 au32CpuIdSaved[5] &= ~0x00ff0000;
1112
1113 /* Ignore some advanced capability bits, that we don't expose to the guest. */
1114 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1115 | X86_CPUID_FEATURE_ECX_VMX
1116 | X86_CPUID_FEATURE_ECX_SMX
1117 | X86_CPUID_FEATURE_ECX_EST
1118 | X86_CPUID_FEATURE_ECX_TM2
1119 | X86_CPUID_FEATURE_ECX_CNTXID
1120 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1121 | X86_CPUID_FEATURE_ECX_PDCM
1122 | X86_CPUID_FEATURE_ECX_DCA
1123 | X86_CPUID_FEATURE_ECX_X2APIC
1124 );
1125 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1126 | X86_CPUID_FEATURE_ECX_VMX
1127 | X86_CPUID_FEATURE_ECX_SMX
1128 | X86_CPUID_FEATURE_ECX_EST
1129 | X86_CPUID_FEATURE_ECX_TM2
1130 | X86_CPUID_FEATURE_ECX_CNTXID
1131 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1132 | X86_CPUID_FEATURE_ECX_PDCM
1133 | X86_CPUID_FEATURE_ECX_DCA
1134 | X86_CPUID_FEATURE_ECX_X2APIC
1135 );
1136
1137 /* Make sure we don't forget to update the masks when enabling
1138 * features in the future.
1139 */
1140 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
1141 ( X86_CPUID_FEATURE_ECX_DTES64
1142 | X86_CPUID_FEATURE_ECX_VMX
1143 | X86_CPUID_FEATURE_ECX_SMX
1144 | X86_CPUID_FEATURE_ECX_EST
1145 | X86_CPUID_FEATURE_ECX_TM2
1146 | X86_CPUID_FEATURE_ECX_CNTXID
1147 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1148 | X86_CPUID_FEATURE_ECX_PDCM
1149 | X86_CPUID_FEATURE_ECX_DCA
1150 | X86_CPUID_FEATURE_ECX_X2APIC
1151 )));
1152 /* do the compare */
1153 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1154 {
1155 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1156 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1157 "Saved=%.*Rhxs\n"
1158 "Real =%.*Rhxs\n",
1159 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1160 sizeof(au32CpuId), au32CpuId));
1161 else
1162 {
1163 LogRel(("cpumR3Load: CpuId mismatch!\n"
1164 "Saved=%.*Rhxs\n"
1165 "Real =%.*Rhxs\n",
1166 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1167 sizeof(au32CpuId), au32CpuId));
1168 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1169 }
1170 }
1171 }
1172
1173 return rc;
1174}
1175
1176
1177/**
1178 * Formats the EFLAGS value into mnemonics.
1179 *
1180 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1181 * @param efl The EFLAGS value.
1182 */
1183static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1184{
1185 /*
1186 * Format the flags.
1187 */
1188 static const struct
1189 {
1190 const char *pszSet; const char *pszClear; uint32_t fFlag;
1191 } s_aFlags[] =
1192 {
1193 { "vip",NULL, X86_EFL_VIP },
1194 { "vif",NULL, X86_EFL_VIF },
1195 { "ac", NULL, X86_EFL_AC },
1196 { "vm", NULL, X86_EFL_VM },
1197 { "rf", NULL, X86_EFL_RF },
1198 { "nt", NULL, X86_EFL_NT },
1199 { "ov", "nv", X86_EFL_OF },
1200 { "dn", "up", X86_EFL_DF },
1201 { "ei", "di", X86_EFL_IF },
1202 { "tf", NULL, X86_EFL_TF },
1203 { "nt", "pl", X86_EFL_SF },
1204 { "nz", "zr", X86_EFL_ZF },
1205 { "ac", "na", X86_EFL_AF },
1206 { "po", "pe", X86_EFL_PF },
1207 { "cy", "nc", X86_EFL_CF },
1208 };
1209 char *psz = pszEFlags;
1210 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1211 {
1212 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1213 if (pszAdd)
1214 {
1215 strcpy(psz, pszAdd);
1216 psz += strlen(pszAdd);
1217 *psz++ = ' ';
1218 }
1219 }
1220 psz[-1] = '\0';
1221}
1222
1223
1224/**
1225 * Formats a full register dump.
1226 *
1227 * @param pVM VM Handle.
1228 * @param pCtx The context to format.
1229 * @param pCtxCore The context core to format.
1230 * @param pHlp Output functions.
1231 * @param enmType The dump type.
1232 * @param pszPrefix Register name prefix.
1233 */
1234static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1235{
1236 /*
1237 * Format the EFLAGS.
1238 */
1239 uint32_t efl = pCtxCore->eflags.u32;
1240 char szEFlags[80];
1241 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1242
1243 /*
1244 * Format the registers.
1245 */
1246 switch (enmType)
1247 {
1248 case CPUMDUMPTYPE_TERSE:
1249 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1250 pHlp->pfnPrintf(pHlp,
1251 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1252 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1253 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1254 "%sr14=%016RX64 %sr15=%016RX64\n"
1255 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1256 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1257 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1258 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1259 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1260 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1261 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1262 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1263 else
1264 pHlp->pfnPrintf(pHlp,
1265 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1266 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1267 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1268 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1269 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1270 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1271 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1272 break;
1273
1274 case CPUMDUMPTYPE_DEFAULT:
1275 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1276 pHlp->pfnPrintf(pHlp,
1277 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1278 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1279 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1280 "%sr14=%016RX64 %sr15=%016RX64\n"
1281 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1282 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1283 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1284 ,
1285 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1286 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1287 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1288 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1289 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1290 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1291 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1292 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1293 else
1294 pHlp->pfnPrintf(pHlp,
1295 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1296 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1297 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1298 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1299 ,
1300 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1301 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1302 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1303 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1304 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1305 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1306 break;
1307
1308 case CPUMDUMPTYPE_VERBOSE:
1309 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1310 pHlp->pfnPrintf(pHlp,
1311 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1312 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1313 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1314 "%sr14=%016RX64 %sr15=%016RX64\n"
1315 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1316 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1317 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1318 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1319 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1320 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1321 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1322 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1323 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1324 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1325 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1326 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1327 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1328 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1329 ,
1330 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1331 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1332 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1333 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1334 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1335 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1336 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1337 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1338 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1339 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1340 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1341 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1342 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1343 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1344 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1345 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1346 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1347 else
1348 pHlp->pfnPrintf(pHlp,
1349 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1350 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1351 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1352 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1353 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1354 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1355 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1356 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1357 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1358 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1359 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1360 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1361 ,
1362 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1363 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1364 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1365 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1366 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1367 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1368 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1369 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1370 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1371 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1372 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1373 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1374
1375 pHlp->pfnPrintf(pHlp,
1376 "FPU:\n"
1377 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1378 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1379 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1380 ,
1381 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1382 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1383 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1384 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1385
1386 pHlp->pfnPrintf(pHlp,
1387 "MSR:\n"
1388 "%sEFER =%016RX64\n"
1389 "%sPAT =%016RX64\n"
1390 "%sSTAR =%016RX64\n"
1391 "%sCSTAR =%016RX64\n"
1392 "%sLSTAR =%016RX64\n"
1393 "%sSFMASK =%016RX64\n"
1394 "%sKERNELGSBASE =%016RX64\n",
1395 pszPrefix, pCtx->msrEFER,
1396 pszPrefix, pCtx->msrPAT,
1397 pszPrefix, pCtx->msrSTAR,
1398 pszPrefix, pCtx->msrCSTAR,
1399 pszPrefix, pCtx->msrLSTAR,
1400 pszPrefix, pCtx->msrSFMASK,
1401 pszPrefix, pCtx->msrKERNELGSBASE);
1402 break;
1403 }
1404}
1405
1406
1407/**
1408 * Display all cpu states and any other cpum info.
1409 *
1410 * @param pVM VM Handle.
1411 * @param pHlp The info helper functions.
1412 * @param pszArgs Arguments, ignored.
1413 */
1414static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1415{
1416 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1417 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1418 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1419 cpumR3InfoHost(pVM, pHlp, pszArgs);
1420}
1421
1422
1423/**
1424 * Parses the info argument.
1425 *
1426 * The argument starts with 'verbose', 'terse' or 'default' and then
1427 * continues with the comment string.
1428 *
1429 * @param pszArgs The pointer to the argument string.
1430 * @param penmType Where to store the dump type request.
1431 * @param ppszComment Where to store the pointer to the comment string.
1432 */
1433static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1434{
1435 if (!pszArgs)
1436 {
1437 *penmType = CPUMDUMPTYPE_DEFAULT;
1438 *ppszComment = "";
1439 }
1440 else
1441 {
1442 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1443 {
1444 pszArgs += 5;
1445 *penmType = CPUMDUMPTYPE_VERBOSE;
1446 }
1447 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1448 {
1449 pszArgs += 5;
1450 *penmType = CPUMDUMPTYPE_TERSE;
1451 }
1452 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1453 {
1454 pszArgs += 7;
1455 *penmType = CPUMDUMPTYPE_DEFAULT;
1456 }
1457 else
1458 *penmType = CPUMDUMPTYPE_DEFAULT;
1459 *ppszComment = RTStrStripL(pszArgs);
1460 }
1461}
1462
1463
1464/**
1465 * Display the guest cpu state.
1466 *
1467 * @param pVM VM Handle.
1468 * @param pHlp The info helper functions.
1469 * @param pszArgs Arguments, ignored.
1470 */
1471static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1472{
1473 CPUMDUMPTYPE enmType;
1474 const char *pszComment;
1475 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1476
1477 /* @todo SMP support! */
1478 PVMCPU pVCpu = VMMGetCpu(pVM);
1479 if (!pVCpu)
1480 pVCpu = &pVM->aCpus[0];
1481
1482 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1483
1484 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1485 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1486}
1487
1488
1489/**
1490 * Display the current guest instruction
1491 *
1492 * @param pVM VM Handle.
1493 * @param pHlp The info helper functions.
1494 * @param pszArgs Arguments, ignored.
1495 */
1496static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1497{
1498 char szInstruction[256];
1499 /* @todo SMP support! */
1500 PVMCPU pVCpu = VMMGetCpu(pVM);
1501 if (!pVCpu)
1502 pVCpu = &pVM->aCpus[0];
1503
1504 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1505 if (RT_SUCCESS(rc))
1506 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1507}
1508
1509
1510/**
1511 * Display the hypervisor cpu state.
1512 *
1513 * @param pVM VM Handle.
1514 * @param pHlp The info helper functions.
1515 * @param pszArgs Arguments, ignored.
1516 */
1517static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1518{
1519 CPUMDUMPTYPE enmType;
1520 const char *pszComment;
1521 /* @todo SMP */
1522 PVMCPU pVCpu = &pVM->aCpus[0];
1523
1524 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1525 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1526 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1527 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1528}
1529
1530
1531/**
1532 * Display the host cpu state.
1533 *
1534 * @param pVM VM Handle.
1535 * @param pHlp The info helper functions.
1536 * @param pszArgs Arguments, ignored.
1537 */
1538static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1539{
1540 CPUMDUMPTYPE enmType;
1541 const char *pszComment;
1542 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1543 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1544
1545 /*
1546 * Format the EFLAGS.
1547 */
1548 /* @todo SMP */
1549 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1550#if HC_ARCH_BITS == 32
1551 uint32_t efl = pCtx->eflags.u32;
1552#else
1553 uint64_t efl = pCtx->rflags;
1554#endif
1555 char szEFlags[80];
1556 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1557
1558 /*
1559 * Format the registers.
1560 */
1561#if HC_ARCH_BITS == 32
1562# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1563 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1564# endif
1565 {
1566 pHlp->pfnPrintf(pHlp,
1567 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1568 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1569 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1570 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1571 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1572 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1573 ,
1574 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1575 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1576 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1577 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1578 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1579 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1580 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1581 }
1582# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1583 else
1584# endif
1585#endif
1586#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1587 {
1588 pHlp->pfnPrintf(pHlp,
1589 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1590 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1591 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1592 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1593 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1594 "r14=%016RX64 r15=%016RX64\n"
1595 "iopl=%d %31s\n"
1596 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1597 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1598 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1599 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1600 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1601 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1602 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1603 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1604 ,
1605 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1606 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1607 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1608 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1609 pCtx->r11, pCtx->r12, pCtx->r13,
1610 pCtx->r14, pCtx->r15,
1611 X86_EFL_GET_IOPL(efl), szEFlags,
1612 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1613 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1614 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1615 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1616 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1617 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1618 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1619 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1620 }
1621#endif
1622}
1623
1624
1625/**
1626 * Get L1 cache / TLS associativity.
1627 */
1628static const char *getCacheAss(unsigned u, char *pszBuf)
1629{
1630 if (u == 0)
1631 return "res0 ";
1632 if (u == 1)
1633 return "direct";
1634 if (u >= 256)
1635 return "???";
1636
1637 RTStrPrintf(pszBuf, 16, "%d way", u);
1638 return pszBuf;
1639}
1640
1641
1642/**
1643 * Get L2 cache soociativity.
1644 */
1645const char *getL2CacheAss(unsigned u)
1646{
1647 switch (u)
1648 {
1649 case 0: return "off ";
1650 case 1: return "direct";
1651 case 2: return "2 way ";
1652 case 3: return "res3 ";
1653 case 4: return "4 way ";
1654 case 5: return "res5 ";
1655 case 6: return "8 way "; case 7: return "res7 ";
1656 case 8: return "16 way";
1657 case 9: return "res9 ";
1658 case 10: return "res10 ";
1659 case 11: return "res11 ";
1660 case 12: return "res12 ";
1661 case 13: return "res13 ";
1662 case 14: return "res14 ";
1663 case 15: return "fully ";
1664 default:
1665 return "????";
1666 }
1667}
1668
1669
1670/**
1671 * Display the guest CpuId leaves.
1672 *
1673 * @param pVM VM Handle.
1674 * @param pHlp The info helper functions.
1675 * @param pszArgs "terse", "default" or "verbose".
1676 */
1677static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1678{
1679 /*
1680 * Parse the argument.
1681 */
1682 unsigned iVerbosity = 1;
1683 if (pszArgs)
1684 {
1685 pszArgs = RTStrStripL(pszArgs);
1686 if (!strcmp(pszArgs, "terse"))
1687 iVerbosity--;
1688 else if (!strcmp(pszArgs, "verbose"))
1689 iVerbosity++;
1690 }
1691
1692 /*
1693 * Start cracking.
1694 */
1695 CPUMCPUID Host;
1696 CPUMCPUID Guest;
1697 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1698
1699 pHlp->pfnPrintf(pHlp,
1700 " RAW Standard CPUIDs\n"
1701 " Function eax ebx ecx edx\n");
1702 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1703 {
1704 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1705 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1706
1707 pHlp->pfnPrintf(pHlp,
1708 "Gst: %08x %08x %08x %08x %08x%s\n"
1709 "Hst: %08x %08x %08x %08x\n",
1710 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1711 i <= cStdMax ? "" : "*",
1712 Host.eax, Host.ebx, Host.ecx, Host.edx);
1713 }
1714
1715 /*
1716 * If verbose, decode it.
1717 */
1718 if (iVerbosity)
1719 {
1720 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1721 pHlp->pfnPrintf(pHlp,
1722 "Name: %.04s%.04s%.04s\n"
1723 "Supports: 0-%x\n",
1724 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1725 }
1726
1727 /*
1728 * Get Features.
1729 */
1730 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1731 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1732 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1733 if (cStdMax >= 1 && iVerbosity)
1734 {
1735 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1736 uint32_t uEAX = Guest.eax;
1737
1738 pHlp->pfnPrintf(pHlp,
1739 "Family: %d \tExtended: %d \tEffective: %d\n"
1740 "Model: %d \tExtended: %d \tEffective: %d\n"
1741 "Stepping: %d\n"
1742 "APIC ID: %#04x\n"
1743 "Logical CPUs: %d\n"
1744 "CLFLUSH Size: %d\n"
1745 "Brand ID: %#04x\n",
1746 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1747 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1748 ASMGetCpuStepping(uEAX),
1749 (Guest.ebx >> 24) & 0xff,
1750 (Guest.ebx >> 16) & 0xff,
1751 (Guest.ebx >> 8) & 0xff,
1752 (Guest.ebx >> 0) & 0xff);
1753 if (iVerbosity == 1)
1754 {
1755 uint32_t uEDX = Guest.edx;
1756 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1757 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1758 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1759 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1760 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1761 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1762 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1763 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1764 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1765 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1766 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1767 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1768 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1769 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1770 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1771 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1772 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1773 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1774 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1775 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1776 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1777 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1778 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1779 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1780 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1781 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1782 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1783 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1784 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1785 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1786 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1787 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1788 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1789 pHlp->pfnPrintf(pHlp, "\n");
1790
1791 uint32_t uECX = Guest.ecx;
1792 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1793 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1794 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1795 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1796 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1797 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1798 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1799 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1800 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1801 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1802 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1803 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1804 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1805 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1806 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1807 for (unsigned iBit = 14; iBit < 32; iBit++)
1808 if (uECX & RT_BIT(iBit))
1809 pHlp->pfnPrintf(pHlp, " %d", iBit);
1810 pHlp->pfnPrintf(pHlp, "\n");
1811 }
1812 else
1813 {
1814 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1815
1816 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1817 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1818 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1819 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1820
1821 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1822 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1823 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1824 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1825 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1826 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1827 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1828 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1829 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1830 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1831 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1832 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1833 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1834 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1835 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1836 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1837 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1838 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1839 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1840 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1841 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1842 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1843 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1844 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1845 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1846 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1847 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1848 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1849 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1850 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1851 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1852 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1853 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1854
1855 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1856 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
1857 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
1858 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1859 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1860 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1861 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
1862 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1863 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1864 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1865 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1866 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved2, EcxHost.u2Reserved2);
1867 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1868 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1869 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
1870 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
1871 pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
1872 pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
1873 pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
1874 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
1875 pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
1876 pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
1877 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1878 pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
1879 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
1880 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
1881 }
1882 }
1883 if (cStdMax >= 2 && iVerbosity)
1884 {
1885 /** @todo */
1886 }
1887
1888 /*
1889 * Extended.
1890 * Implemented after AMD specs.
1891 */
1892 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1893
1894 pHlp->pfnPrintf(pHlp,
1895 "\n"
1896 " RAW Extended CPUIDs\n"
1897 " Function eax ebx ecx edx\n");
1898 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1899 {
1900 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1901 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1902
1903 pHlp->pfnPrintf(pHlp,
1904 "Gst: %08x %08x %08x %08x %08x%s\n"
1905 "Hst: %08x %08x %08x %08x\n",
1906 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1907 i <= cExtMax ? "" : "*",
1908 Host.eax, Host.ebx, Host.ecx, Host.edx);
1909 }
1910
1911 /*
1912 * Understandable output
1913 */
1914 if (iVerbosity)
1915 {
1916 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1917 pHlp->pfnPrintf(pHlp,
1918 "Ext Name: %.4s%.4s%.4s\n"
1919 "Ext Supports: 0x80000000-%#010x\n",
1920 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1921 }
1922
1923 if (iVerbosity && cExtMax >= 1)
1924 {
1925 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1926 uint32_t uEAX = Guest.eax;
1927 pHlp->pfnPrintf(pHlp,
1928 "Family: %d \tExtended: %d \tEffective: %d\n"
1929 "Model: %d \tExtended: %d \tEffective: %d\n"
1930 "Stepping: %d\n"
1931 "Brand ID: %#05x\n",
1932 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1933 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1934 ASMGetCpuStepping(uEAX),
1935 Guest.ebx & 0xfff);
1936
1937 if (iVerbosity == 1)
1938 {
1939 uint32_t uEDX = Guest.edx;
1940 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1941 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1942 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1943 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1944 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1945 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1946 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1947 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1948 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1949 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1950 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1951 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1952 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1953 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1954 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1955 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1956 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1957 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1958 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1959 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1960 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1961 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1962 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1963 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1964 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1965 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1966 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1967 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1968 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1969 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1970 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1971 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1972 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1973 pHlp->pfnPrintf(pHlp, "\n");
1974
1975 uint32_t uECX = Guest.ecx;
1976 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1977 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1978 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1979 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1980 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1981 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1982 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1983 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1984 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1985 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1986 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1987 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1988 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1989 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1990 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1991 for (unsigned iBit = 5; iBit < 32; iBit++)
1992 if (uECX & RT_BIT(iBit))
1993 pHlp->pfnPrintf(pHlp, " %d", iBit);
1994 pHlp->pfnPrintf(pHlp, "\n");
1995 }
1996 else
1997 {
1998 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1999
2000 uint32_t uEdxGst = Guest.edx;
2001 uint32_t uEdxHst = Host.edx;
2002 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2003 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2004 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2005 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2006 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2007 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2008 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2009 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2010 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2011 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2012 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2013 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2014 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2015 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2016 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2017 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
2018 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
2019 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
2020 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
2021 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
2022 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
2023 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
2024 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
2025 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
2026 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
2027 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
2028 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
2029 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
2030 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
2031 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
2032 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
2033 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
2034 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
2035
2036 uint32_t uEcxGst = Guest.ecx;
2037 uint32_t uEcxHst = Host.ecx;
2038 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
2039 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
2040 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
2041 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
2042 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
2043 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
2044 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
2045 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
2046 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
2047 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
2048 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
2049 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
2050 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
2051 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
2052 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
2053 }
2054 }
2055
2056 if (iVerbosity && cExtMax >= 2)
2057 {
2058 char szString[4*4*3+1] = {0};
2059 uint32_t *pu32 = (uint32_t *)szString;
2060 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
2061 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
2062 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
2063 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
2064 if (cExtMax >= 3)
2065 {
2066 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
2067 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
2068 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2069 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2070 }
2071 if (cExtMax >= 4)
2072 {
2073 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2074 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2075 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2076 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2077 }
2078 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2079 }
2080
2081 if (iVerbosity && cExtMax >= 5)
2082 {
2083 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2084 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2085 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2086 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2087 char sz1[32];
2088 char sz2[32];
2089
2090 pHlp->pfnPrintf(pHlp,
2091 "TLB 2/4M Instr/Uni: %s %3d entries\n"
2092 "TLB 2/4M Data: %s %3d entries\n",
2093 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2094 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2095 pHlp->pfnPrintf(pHlp,
2096 "TLB 4K Instr/Uni: %s %3d entries\n"
2097 "TLB 4K Data: %s %3d entries\n",
2098 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2099 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2100 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2101 "L1 Instr Cache Lines Per Tag: %d\n"
2102 "L1 Instr Cache Associativity: %s\n"
2103 "L1 Instr Cache Size: %d KB\n",
2104 (uEDX >> 0) & 0xff,
2105 (uEDX >> 8) & 0xff,
2106 getCacheAss((uEDX >> 16) & 0xff, sz1),
2107 (uEDX >> 24) & 0xff);
2108 pHlp->pfnPrintf(pHlp,
2109 "L1 Data Cache Line Size: %d bytes\n"
2110 "L1 Data Cache Lines Per Tag: %d\n"
2111 "L1 Data Cache Associativity: %s\n"
2112 "L1 Data Cache Size: %d KB\n",
2113 (uECX >> 0) & 0xff,
2114 (uECX >> 8) & 0xff,
2115 getCacheAss((uECX >> 16) & 0xff, sz1),
2116 (uECX >> 24) & 0xff);
2117 }
2118
2119 if (iVerbosity && cExtMax >= 6)
2120 {
2121 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2122 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2123 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2124
2125 pHlp->pfnPrintf(pHlp,
2126 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2127 "L2 TLB 2/4M Data: %s %4d entries\n",
2128 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2129 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2130 pHlp->pfnPrintf(pHlp,
2131 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2132 "L2 TLB 4K Data: %s %4d entries\n",
2133 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2134 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2135 pHlp->pfnPrintf(pHlp,
2136 "L2 Cache Line Size: %d bytes\n"
2137 "L2 Cache Lines Per Tag: %d\n"
2138 "L2 Cache Associativity: %s\n"
2139 "L2 Cache Size: %d KB\n",
2140 (uEDX >> 0) & 0xff,
2141 (uEDX >> 8) & 0xf,
2142 getL2CacheAss((uEDX >> 12) & 0xf),
2143 (uEDX >> 16) & 0xffff);
2144 }
2145
2146 if (iVerbosity && cExtMax >= 7)
2147 {
2148 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2149
2150 pHlp->pfnPrintf(pHlp, "APM Features: ");
2151 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2152 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2153 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2154 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2155 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2156 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2157 for (unsigned iBit = 6; iBit < 32; iBit++)
2158 if (uEDX & RT_BIT(iBit))
2159 pHlp->pfnPrintf(pHlp, " %d", iBit);
2160 pHlp->pfnPrintf(pHlp, "\n");
2161 }
2162
2163 if (iVerbosity && cExtMax >= 8)
2164 {
2165 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2166 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2167
2168 pHlp->pfnPrintf(pHlp,
2169 "Physical Address Width: %d bits\n"
2170 "Virtual Address Width: %d bits\n",
2171 (uEAX >> 0) & 0xff,
2172 (uEAX >> 8) & 0xff);
2173 pHlp->pfnPrintf(pHlp,
2174 "Physical Core Count: %d\n",
2175 (uECX >> 0) & 0xff);
2176 }
2177
2178
2179 /*
2180 * Centaur.
2181 */
2182 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2183
2184 pHlp->pfnPrintf(pHlp,
2185 "\n"
2186 " RAW Centaur CPUIDs\n"
2187 " Function eax ebx ecx edx\n");
2188 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2189 {
2190 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2191 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2192
2193 pHlp->pfnPrintf(pHlp,
2194 "Gst: %08x %08x %08x %08x %08x%s\n"
2195 "Hst: %08x %08x %08x %08x\n",
2196 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2197 i <= cCentaurMax ? "" : "*",
2198 Host.eax, Host.ebx, Host.ecx, Host.edx);
2199 }
2200
2201 /*
2202 * Understandable output
2203 */
2204 if (iVerbosity)
2205 {
2206 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2207 pHlp->pfnPrintf(pHlp,
2208 "Centaur Supports: 0xc0000000-%#010x\n",
2209 Guest.eax);
2210 }
2211
2212 if (iVerbosity && cCentaurMax >= 1)
2213 {
2214 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2215 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2216 uint32_t uEdxHst = Host.edx;
2217
2218 if (iVerbosity == 1)
2219 {
2220 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2221 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2222 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2223 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2224 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2225 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2226 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2227 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2228 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2229 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2230 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2231 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2232 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2233 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2234 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2235 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2236 for (unsigned iBit = 14; iBit < 32; iBit++)
2237 if (uEdxGst & RT_BIT(iBit))
2238 pHlp->pfnPrintf(pHlp, " %d", iBit);
2239 pHlp->pfnPrintf(pHlp, "\n");
2240 }
2241 else
2242 {
2243 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2244 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2245 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2246 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2247 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2248 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2249 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2250 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2251 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2252 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2253 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2254 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2255 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2256 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2257 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2258 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2259 for (unsigned iBit = 14; iBit < 32; iBit++)
2260 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2261 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2262 pHlp->pfnPrintf(pHlp, "\n");
2263 }
2264 }
2265}
2266
2267
2268/**
2269 * Structure used when disassembling and instructions in DBGF.
2270 * This is used so the reader function can get the stuff it needs.
2271 */
2272typedef struct CPUMDISASSTATE
2273{
2274 /** Pointer to the CPU structure. */
2275 PDISCPUSTATE pCpu;
2276 /** The VM handle. */
2277 PVM pVM;
2278 /** The VMCPU handle. */
2279 PVMCPU pVCpu;
2280 /** Pointer to the first byte in the segemnt. */
2281 RTGCUINTPTR GCPtrSegBase;
2282 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2283 RTGCUINTPTR GCPtrSegEnd;
2284 /** The size of the segment minus 1. */
2285 RTGCUINTPTR cbSegLimit;
2286 /** Pointer to the current page - R3 Ptr. */
2287 void const *pvPageR3;
2288 /** Pointer to the current page - GC Ptr. */
2289 RTGCPTR pvPageGC;
2290 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2291 PGMPAGEMAPLOCK PageMapLock;
2292 /** Whether the PageMapLock is valid or not. */
2293 bool fLocked;
2294 /** 64 bits mode or not. */
2295 bool f64Bits;
2296} CPUMDISASSTATE, *PCPUMDISASSTATE;
2297
2298
2299/**
2300 * Instruction reader.
2301 *
2302 * @returns VBox status code.
2303 * @param PtrSrc Address to read from.
2304 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2305 * @param pu8Dst Where to store the bytes.
2306 * @param cbRead Number of bytes to read.
2307 * @param uDisCpu Pointer to the disassembler cpu state.
2308 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2309 */
2310static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2311{
2312 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2313 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2314 Assert(cbRead > 0);
2315 for (;;)
2316 {
2317 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2318
2319 /* Need to update the page translation? */
2320 if ( !pState->pvPageR3
2321 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2322 {
2323 int rc = VINF_SUCCESS;
2324
2325 /* translate the address */
2326 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2327 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2328 && !HWACCMIsEnabled(pState->pVM))
2329 {
2330 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2331 if (!pState->pvPageR3)
2332 rc = VERR_INVALID_POINTER;
2333 }
2334 else
2335 {
2336 /* Release mapping lock previously acquired. */
2337 if (pState->fLocked)
2338 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2339 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2340 pState->fLocked = RT_SUCCESS_NP(rc);
2341 }
2342 if (RT_FAILURE(rc))
2343 {
2344 pState->pvPageR3 = NULL;
2345 return rc;
2346 }
2347 }
2348
2349 /* check the segemnt limit */
2350 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2351 return VERR_OUT_OF_SELECTOR_BOUNDS;
2352
2353 /* calc how much we can read */
2354 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2355 if (!pState->f64Bits)
2356 {
2357 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2358 if (cb > cbSeg && cbSeg)
2359 cb = cbSeg;
2360 }
2361 if (cb > cbRead)
2362 cb = cbRead;
2363
2364 /* read and advance */
2365 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2366 cbRead -= cb;
2367 if (!cbRead)
2368 return VINF_SUCCESS;
2369 pu8Dst += cb;
2370 PtrSrc += cb;
2371 }
2372}
2373
2374
2375/**
2376 * Disassemble an instruction and return the information in the provided structure.
2377 *
2378 * @returns VBox status code.
2379 * @param pVM VM Handle
2380 * @param pVCpu VMCPU Handle
2381 * @param pCtx CPU context
2382 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2383 * @param pCpu Disassembly state
2384 * @param pszPrefix String prefix for logging (debug only)
2385 *
2386 */
2387VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2388{
2389 CPUMDISASSTATE State;
2390 int rc;
2391
2392 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2393 State.pCpu = pCpu;
2394 State.pvPageGC = 0;
2395 State.pvPageR3 = NULL;
2396 State.pVM = pVM;
2397 State.pVCpu = pVCpu;
2398 State.fLocked = false;
2399 State.f64Bits = false;
2400
2401 /*
2402 * Get selector information.
2403 */
2404 if ( (pCtx->cr0 & X86_CR0_PE)
2405 && pCtx->eflags.Bits.u1VM == 0)
2406 {
2407 if (CPUMAreHiddenSelRegsValid(pVM))
2408 {
2409 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2410 State.GCPtrSegBase = pCtx->csHid.u64Base;
2411 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2412 State.cbSegLimit = pCtx->csHid.u32Limit;
2413 pCpu->mode = (State.f64Bits)
2414 ? CPUMODE_64BIT
2415 : pCtx->csHid.Attr.n.u1DefBig
2416 ? CPUMODE_32BIT
2417 : CPUMODE_16BIT;
2418 }
2419 else
2420 {
2421 DBGFSELINFO SelInfo;
2422
2423 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2424 if (RT_FAILURE(rc))
2425 {
2426 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2427 return rc;
2428 }
2429
2430 /*
2431 * Validate the selector.
2432 */
2433 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2434 if (RT_FAILURE(rc))
2435 {
2436 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2437 return rc;
2438 }
2439 State.GCPtrSegBase = SelInfo.GCPtrBase;
2440 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2441 State.cbSegLimit = SelInfo.cbLimit;
2442 pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2443 }
2444 }
2445 else
2446 {
2447 /* real or V86 mode */
2448 pCpu->mode = CPUMODE_16BIT;
2449 State.GCPtrSegBase = pCtx->cs * 16;
2450 State.GCPtrSegEnd = 0xFFFFFFFF;
2451 State.cbSegLimit = 0xFFFFFFFF;
2452 }
2453
2454 /*
2455 * Disassemble the instruction.
2456 */
2457 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2458 pCpu->apvUserData[0] = &State;
2459
2460 uint32_t cbInstr;
2461#ifndef LOG_ENABLED
2462 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2463 if (RT_SUCCESS(rc))
2464 {
2465#else
2466 char szOutput[160];
2467 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2468 if (RT_SUCCESS(rc))
2469 {
2470 /* log it */
2471 if (pszPrefix)
2472 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2473 else
2474 Log(("%s", szOutput));
2475#endif
2476 rc = VINF_SUCCESS;
2477 }
2478 else
2479 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2480
2481 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2482 if (State.fLocked)
2483 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2484
2485 return rc;
2486}
2487
2488#ifdef DEBUG
2489
2490/**
2491 * Disassemble an instruction and dump it to the log
2492 *
2493 * @returns VBox status code.
2494 * @param pVM VM Handle
2495 * @param pVCpu VMCPU Handle
2496 * @param pCtx CPU context
2497 * @param pc GC instruction pointer
2498 * @param pszPrefix String prefix for logging
2499 *
2500 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2501 */
2502VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2503{
2504 DISCPUSTATE Cpu;
2505 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2506}
2507
2508
2509/**
2510 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2511 *
2512 * @internal
2513 */
2514VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2515{
2516 /* @todo SMP support!! */
2517 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2518}
2519
2520#endif /* DEBUG */
2521
2522/**
2523 * API for controlling a few of the CPU features found in CR4.
2524 *
2525 * Currently only X86_CR4_TSD is accepted as input.
2526 *
2527 * @returns VBox status code.
2528 *
2529 * @param pVM The VM handle.
2530 * @param fOr The CR4 OR mask.
2531 * @param fAnd The CR4 AND mask.
2532 */
2533VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2534{
2535 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2536 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2537
2538 pVM->cpum.s.CR4.OrMask &= fAnd;
2539 pVM->cpum.s.CR4.OrMask |= fOr;
2540
2541 return VINF_SUCCESS;
2542}
2543
2544
2545/**
2546 * Gets a pointer to the array of standard CPUID leafs.
2547 *
2548 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2549 *
2550 * @returns Pointer to the standard CPUID leafs (read-only).
2551 * @param pVM The VM handle.
2552 * @remark Intended for PATM.
2553 */
2554VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2555{
2556 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2557}
2558
2559
2560/**
2561 * Gets a pointer to the array of extended CPUID leafs.
2562 *
2563 * CPUMGetGuestCpuIdExtMax() give the size of the array.
2564 *
2565 * @returns Pointer to the extended CPUID leafs (read-only).
2566 * @param pVM The VM handle.
2567 * @remark Intended for PATM.
2568 */
2569VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2570{
2571 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2572}
2573
2574
2575/**
2576 * Gets a pointer to the array of centaur CPUID leafs.
2577 *
2578 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2579 *
2580 * @returns Pointer to the centaur CPUID leafs (read-only).
2581 * @param pVM The VM handle.
2582 * @remark Intended for PATM.
2583 */
2584VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2585{
2586 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2587}
2588
2589
2590/**
2591 * Gets a pointer to the default CPUID leaf.
2592 *
2593 * @returns Pointer to the default CPUID leaf (read-only).
2594 * @param pVM The VM handle.
2595 * @remark Intended for PATM.
2596 */
2597VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2598{
2599 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2600}
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