VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 23781

Last change on this file since 23781 was 23758, checked in by vboxsync, 16 years ago

Skeleton code for synthetic cpu handling.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 126.7 KB
Line 
1/* $Id: CPUM.cpp 23758 2009-10-14 12:21:21Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The current saved state version. */
70#ifdef VBOX_WITH_LIVE_MIGRATION
71#define CPUM_SAVED_STATE_VERSION 11
72#else
73#define CPUM_SAVED_STATE_VERSION 10
74#endif
75/** The saved state version of 3.0 and 3.1 trunk before the live migration
76 * changes. */
77#define CPUM_SAVED_STATE_VERSION_VER3_0 10
78/** The saved state version for the 2.1 trunk before the MSR changes. */
79#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
80/** The saved state version of 2.0, used for backwards compatibility. */
81#define CPUM_SAVED_STATE_VERSION_VER2_0 8
82/** The saved state version of 1.6, used for backwards compatability. */
83#define CPUM_SAVED_STATE_VERSION_VER1_6 6
84
85
86/*******************************************************************************
87* Structures and Typedefs *
88*******************************************************************************/
89
90/**
91 * What kind of cpu info dump to perform.
92 */
93typedef enum CPUMDUMPTYPE
94{
95 CPUMDUMPTYPE_TERSE,
96 CPUMDUMPTYPE_DEFAULT,
97 CPUMDUMPTYPE_VERBOSE
98} CPUMDUMPTYPE;
99/** Pointer to a cpu info dump type. */
100typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
101
102
103/*******************************************************************************
104* Internal Functions *
105*******************************************************************************/
106static int cpumR3CpuIdInit(PVM pVM);
107#ifdef VBOX_WITH_LIVE_MIGRATION
108static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
109#endif
110static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
111static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
112static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
115static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
116static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
117static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
118
119
120/**
121 * Initializes the CPUM.
122 *
123 * @returns VBox status code.
124 * @param pVM The VM to operate on.
125 */
126VMMR3DECL(int) CPUMR3Init(PVM pVM)
127{
128 LogFlow(("CPUMR3Init\n"));
129
130 /*
131 * Assert alignment and sizes.
132 */
133 AssertCompileMemberAlignment(VM, cpum.s, 32);
134 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
135 AssertCompileSizeAlignment(CPUMCTX, 64);
136 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
137 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
138 AssertCompileMemberAlignment(VM, cpum, 64);
139 AssertCompileMemberAlignment(VM, aCpus, 64);
140 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
141 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
142
143 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
144 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
145 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
146
147 /* Calculate the offset from CPUMCPU to CPUM. */
148 for (VMCPUID i = 0; i < pVM->cCpus; i++)
149 {
150 PVMCPU pVCpu = &pVM->aCpus[i];
151
152 /*
153 * Setup any fixed pointers and offsets.
154 */
155 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
156 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
157
158 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
159 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
160 }
161
162 /*
163 * Check that the CPU supports the minimum features we require.
164 */
165 if (!ASMHasCpuId())
166 {
167 Log(("The CPU doesn't support CPUID!\n"));
168 return VERR_UNSUPPORTED_CPU;
169 }
170 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
171 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
172
173 /* Setup the CR4 AND and OR masks used in the switcher */
174 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
175 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
176 {
177 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
178 /* No FXSAVE implies no SSE */
179 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
180 pVM->cpum.s.CR4.OrMask = 0;
181 }
182 else
183 {
184 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
185 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
186 }
187
188 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
189 {
190 Log(("The CPU doesn't support MMX!\n"));
191 return VERR_UNSUPPORTED_CPU;
192 }
193 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
194 {
195 Log(("The CPU doesn't support TSC!\n"));
196 return VERR_UNSUPPORTED_CPU;
197 }
198 /* Bogus on AMD? */
199 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
200 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
201
202 /*
203 * Setup hypervisor startup values.
204 */
205
206 /*
207 * Register saved state data item.
208 */
209#ifdef VBOX_WITH_LIVE_MIGRATION
210 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
211 NULL, cpumR3LiveExec, NULL,
212 NULL, cpumR3SaveExec, NULL,
213 NULL, cpumR3LoadExec, NULL);
214#else
215 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
216 NULL, NULL, NULL,
217 NULL, cpumR3SaveExec, NULL,
218 NULL, cpumR3LoadExec, NULL);
219#endif
220 if (RT_FAILURE(rc))
221 return rc;
222
223 /* Query the CPU manufacturer. */
224 uint32_t uEAX, uEBX, uECX, uEDX;
225 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
226 if ( uEAX >= 1
227 && uEBX == X86_CPUID_VENDOR_AMD_EBX
228 && uECX == X86_CPUID_VENDOR_AMD_ECX
229 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
230 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
231 else if ( uEAX >= 1
232 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
233 && uECX == X86_CPUID_VENDOR_INTEL_ECX
234 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
235 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
236 else /** @todo Via */
237 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
238
239 /*
240 * Register info handlers.
241 */
242 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
243 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
244 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
245 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
246 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
247 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
248
249 /*
250 * Initialize the Guest CPU state.
251 */
252 rc = cpumR3CpuIdInit(pVM);
253 if (RT_FAILURE(rc))
254 return rc;
255 CPUMR3Reset(pVM);
256 return VINF_SUCCESS;
257}
258
259
260/**
261 * Initializes the per-VCPU CPUM.
262 *
263 * @returns VBox status code.
264 * @param pVM The VM to operate on.
265 */
266VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
267{
268 LogFlow(("CPUMR3InitCPU\n"));
269 return VINF_SUCCESS;
270}
271
272
273/**
274 * Initializes the emulated CPU's cpuid information.
275 *
276 * @returns VBox status code.
277 * @param pVM The VM to operate on.
278 */
279static int cpumR3CpuIdInit(PVM pVM)
280{
281 PCPUM pCPUM = &pVM->cpum.s;
282 uint32_t i;
283
284 /*
285 * Get the host CPUIDs.
286 */
287 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
288 ASMCpuId_Idx_ECX(i, 0,
289 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
290 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
291 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
292 ASMCpuId(0x80000000 + i,
293 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
294 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
295 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
296 ASMCpuId(0xc0000000 + i,
297 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
298 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
299
300 /*
301 * Only report features we can support.
302 */
303 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
304 | X86_CPUID_FEATURE_EDX_VME
305 | X86_CPUID_FEATURE_EDX_DE
306 | X86_CPUID_FEATURE_EDX_PSE
307 | X86_CPUID_FEATURE_EDX_TSC
308 | X86_CPUID_FEATURE_EDX_MSR
309 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
310 | X86_CPUID_FEATURE_EDX_MCE
311 | X86_CPUID_FEATURE_EDX_CX8
312 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
313 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
314 //| X86_CPUID_FEATURE_EDX_SEP
315 | X86_CPUID_FEATURE_EDX_MTRR
316 | X86_CPUID_FEATURE_EDX_PGE
317 | X86_CPUID_FEATURE_EDX_MCA
318 | X86_CPUID_FEATURE_EDX_CMOV
319 | X86_CPUID_FEATURE_EDX_PAT
320 | X86_CPUID_FEATURE_EDX_PSE36
321 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
322 | X86_CPUID_FEATURE_EDX_CLFSH
323 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
324 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
325 | X86_CPUID_FEATURE_EDX_MMX
326 | X86_CPUID_FEATURE_EDX_FXSR
327 | X86_CPUID_FEATURE_EDX_SSE
328 | X86_CPUID_FEATURE_EDX_SSE2
329 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
330 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
331 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
332 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
333 | 0;
334 pCPUM->aGuestCpuIdStd[1].ecx &= 0
335 | X86_CPUID_FEATURE_ECX_SSE3
336 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
337 | ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
338 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
339 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
340 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
341 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
342 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
343 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
344 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
345 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
346 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
347 /* ECX Bit 21 - x2APIC support - not yet. */
348 // | X86_CPUID_FEATURE_ECX_X2APIC
349 /* ECX Bit 23 - POPCOUNT instruction. */
350 //| X86_CPUID_FEATURE_ECX_POPCOUNT
351 | 0;
352
353 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
354 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
355 | X86_CPUID_AMD_FEATURE_EDX_VME
356 | X86_CPUID_AMD_FEATURE_EDX_DE
357 | X86_CPUID_AMD_FEATURE_EDX_PSE
358 | X86_CPUID_AMD_FEATURE_EDX_TSC
359 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
360 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
361 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
362 | X86_CPUID_AMD_FEATURE_EDX_CX8
363 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
364 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
365 //| X86_CPUID_AMD_FEATURE_EDX_SEP
366 | X86_CPUID_AMD_FEATURE_EDX_MTRR
367 | X86_CPUID_AMD_FEATURE_EDX_PGE
368 | X86_CPUID_AMD_FEATURE_EDX_MCA
369 | X86_CPUID_AMD_FEATURE_EDX_CMOV
370 | X86_CPUID_AMD_FEATURE_EDX_PAT
371 | X86_CPUID_AMD_FEATURE_EDX_PSE36
372 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
373 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
374 | X86_CPUID_AMD_FEATURE_EDX_MMX
375 | X86_CPUID_AMD_FEATURE_EDX_FXSR
376 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
377 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
378 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
379 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
380 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
381 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
382 | 0;
383 pCPUM->aGuestCpuIdExt[1].ecx &= 0
384 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
385 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
386 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
387 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
388 /** Note: This could prevent migration from AMD to Intel CPUs! */
389 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
390 //| X86_CPUID_AMD_FEATURE_ECX_ABM
391 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
392 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
393 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
394 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
395 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
396 //| X86_CPUID_AMD_FEATURE_ECX_WDT
397 | 0;
398
399 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
400 if (pCPUM->fSyntheticCpu)
401 {
402 /* AMD only; shared feature bits are set dynamically. */
403 pCPUM->aGuestCpuIdExt[1].edx = 0;
404 pCPUM->aGuestCpuIdExt[1].ecx = 0;
405
406 /** @todo fill in the rest of the cpu leaves. */
407 }
408
409 /*
410 * Hide HTT, multicode, SMP, whatever.
411 * (APIC-ID := 0 and #LogCpus := 0)
412 */
413 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
414#ifdef VBOX_WITH_MULTI_CORE
415 if (pVM->cCpus > 1)
416 {
417 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
418 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
419 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
420 }
421#endif
422
423 /* Cpuid 2:
424 * Intel: Cache and TLB information
425 * AMD: Reserved
426 * Safe to expose
427 */
428
429 /* Cpuid 3:
430 * Intel: EAX, EBX - reserved
431 * ECX, EDX - Processor Serial Number if available, otherwise reserved
432 * AMD: Reserved
433 * Safe to expose
434 */
435 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
436 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
437
438 /* Cpuid 4:
439 * Intel: Deterministic Cache Parameters Leaf
440 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
441 * AMD: Reserved
442 * Safe to expose, except for EAX:
443 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
444 * Bits 31-26: Maximum number of processor cores in this physical package**
445 * @Note These SMP values are constant regardless of ECX
446 */
447 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
448 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
449#ifdef VBOX_WITH_MULTI_CORE
450 if ( pVM->cCpus > 1
451 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_INTEL)
452 {
453 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
454 /* One logical processor with possibly multiple cores. */
455 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
456 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
457 }
458#endif
459
460 /* Cpuid 5: Monitor/mwait Leaf
461 * Intel: ECX, EDX - reserved
462 * EAX, EBX - Smallest and largest monitor line size
463 * AMD: EDX - reserved
464 * EAX, EBX - Smallest and largest monitor line size
465 * ECX - extensions (ignored for now)
466 * Safe to expose
467 */
468 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
469 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
470
471 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
472
473 /*
474 * Determine the default.
475 *
476 * Intel returns values of the highest standard function, while AMD
477 * returns zeros. VIA on the other hand seems to returning nothing or
478 * perhaps some random garbage, we don't try to duplicate this behavior.
479 */
480 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
481 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
482 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
483
484 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
485 * Safe to pass on to the guest.
486 *
487 * Intel: 0x800000005 reserved
488 * 0x800000006 L2 cache information
489 * AMD: 0x800000005 L1 cache information
490 * 0x800000006 L2/L3 cache information
491 */
492
493 /* Cpuid 0x800000007:
494 * AMD: EAX, EBX, ECX - reserved
495 * EDX: Advanced Power Management Information
496 * Intel: Reserved
497 */
498 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
499 {
500 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
501
502 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
503
504 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
505 {
506 /* Only expose the TSC invariant capability bit to the guest. */
507 pCPUM->aGuestCpuIdExt[7].edx &= 0
508 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
509 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
510 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
511 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
512 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
513 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
514 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
515 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
516#if 1
517 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
518 * that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
519 */
520#else
521 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
522#endif
523 | 0;
524 }
525 else
526 pCPUM->aGuestCpuIdExt[7].edx = 0;
527 }
528
529 /* Cpuid 0x800000008:
530 * AMD: EBX, EDX - reserved
531 * EAX: Virtual/Physical address Size
532 * ECX: Number of cores + APICIdCoreIdSize
533 * Intel: EAX: Virtual/Physical address Size
534 * EBX, ECX, EDX - reserved
535 */
536 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
537 {
538 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
539 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
540 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
541 * NC (0-7) Number of cores; 0 equals 1 core */
542 pCPUM->aGuestCpuIdExt[8].ecx = 0;
543#ifdef VBOX_WITH_MULTI_CORE
544 if ( pVM->cCpus > 1
545 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
546 {
547 /* Legacy method to determine the number of cores. */
548 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
549 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
550
551 }
552#endif
553 }
554
555 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
556 * Limit the number of standard CPUID leafs to 0..2 to prevent NT4 from
557 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
558 * This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
559 * @todo r=bird: The intel docs states that leafs 3 is included, why don't we?
560 */
561 bool fNt4LeafLimit;
562 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "NT4LeafLimit", &fNt4LeafLimit, false);
563 if (fNt4LeafLimit)
564 pCPUM->aGuestCpuIdStd[0].eax = 2;
565
566 /*
567 * Limit it the number of entries and fill the remaining with the defaults.
568 *
569 * The limits are masking off stuff about power saving and similar, this
570 * is perhaps a bit crudely done as there is probably some relatively harmless
571 * info too in these leaves (like words about having a constant TSC).
572 */
573 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
574 pCPUM->aGuestCpuIdStd[0].eax = 5;
575
576 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
577 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
578
579 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
580 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
581 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
582 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
583 : 0;
584 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
585 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
586
587 /*
588 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
589 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
590 * of processors from (cpuid(4).eax >> 26) + 1.
591 */
592 if (pVM->cCpus == 1)
593 pCPUM->aGuestCpuIdStd[4].eax = 0;
594
595 /*
596 * Centaur stuff (VIA).
597 *
598 * The important part here (we think) is to make sure the 0xc0000000
599 * function returns 0xc0000001. As for the features, we don't currently
600 * let on about any of those... 0xc0000002 seems to be some
601 * temperature/hz/++ stuff, include it as well (static).
602 */
603 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
604 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
605 {
606 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
607 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
608 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
609 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
610 i++)
611 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
612 }
613 else
614 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
615 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
616
617
618 /*
619 * Load CPUID overrides from configuration.
620 */
621 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
622 * Overloads the CPUID leaf values. */
623 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
624 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
625 for (i=0;; )
626 {
627 while (cElements-- > 0)
628 {
629 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
630 if (pNode)
631 {
632 uint32_t u32;
633 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
634 if (RT_SUCCESS(rc))
635 pCpuId->eax = u32;
636 else
637 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
638
639 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
640 if (RT_SUCCESS(rc))
641 pCpuId->ebx = u32;
642 else
643 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
644
645 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
646 if (RT_SUCCESS(rc))
647 pCpuId->ecx = u32;
648 else
649 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
650
651 rc = CFGMR3QueryU32(pNode, "edx", &u32);
652 if (RT_SUCCESS(rc))
653 pCpuId->edx = u32;
654 else
655 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
656 }
657 pCpuId++;
658 i++;
659 }
660
661 /* next */
662 if ((i & UINT32_C(0xc0000000)) == 0)
663 {
664 pCpuId = &pCPUM->aGuestCpuIdExt[0];
665 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
666 i = UINT32_C(0x80000000);
667 }
668 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
669 {
670 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
671 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
672 i = UINT32_C(0xc0000000);
673 }
674 else
675 break;
676 }
677
678 /* Check if PAE was explicitely enabled by the user. */
679 bool fEnable = false;
680 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
681 if (RT_SUCCESS(rc) && fEnable)
682 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
683
684 /*
685 * Log the cpuid and we're good.
686 */
687 RTCPUSET OnlineSet;
688 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
689 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
690 LogRel(("************************* CPUID dump ************************\n"));
691 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
692 LogRel(("\n"));
693 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
694 LogRel(("******************** End of CPUID dump **********************\n"));
695 return VINF_SUCCESS;
696}
697
698
699
700
701/**
702 * Applies relocations to data and code managed by this
703 * component. This function will be called at init and
704 * whenever the VMM need to relocate it self inside the GC.
705 *
706 * The CPUM will update the addresses used by the switcher.
707 *
708 * @param pVM The VM.
709 */
710VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
711{
712 LogFlow(("CPUMR3Relocate\n"));
713 for (VMCPUID i = 0; i < pVM->cCpus; i++)
714 {
715 /*
716 * Switcher pointers.
717 */
718 PVMCPU pVCpu = &pVM->aCpus[i];
719 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
720 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
721 }
722}
723
724
725/**
726 * Terminates the CPUM.
727 *
728 * Termination means cleaning up and freeing all resources,
729 * the VM it self is at this point powered off or suspended.
730 *
731 * @returns VBox status code.
732 * @param pVM The VM to operate on.
733 */
734VMMR3DECL(int) CPUMR3Term(PVM pVM)
735{
736 CPUMR3TermCPU(pVM);
737 return 0;
738}
739
740
741/**
742 * Terminates the per-VCPU CPUM.
743 *
744 * Termination means cleaning up and freeing all resources,
745 * the VM it self is at this point powered off or suspended.
746 *
747 * @returns VBox status code.
748 * @param pVM The VM to operate on.
749 */
750VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
751{
752#ifdef VBOX_WITH_CRASHDUMP_MAGIC
753 for (VMCPUID i = 0; i < pVM->cCpus; i++)
754 {
755 PVMCPU pVCpu = &pVM->aCpus[i];
756 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
757
758 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
759 pVCpu->cpum.s.uMagic = 0;
760 pCtx->dr[5] = 0;
761 }
762#endif
763 return 0;
764}
765
766VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
767{
768 /* @todo anything different for VCPU > 0? */
769 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
770
771 /*
772 * Initialize everything to ZERO first.
773 */
774 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
775 memset(pCtx, 0, sizeof(*pCtx));
776 pVCpu->cpum.s.fUseFlags = fUseFlags;
777
778 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
779 pCtx->eip = 0x0000fff0;
780 pCtx->edx = 0x00000600; /* P6 processor */
781 pCtx->eflags.Bits.u1Reserved0 = 1;
782
783 pCtx->cs = 0xf000;
784 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
785 pCtx->csHid.u32Limit = 0x0000ffff;
786 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
787 pCtx->csHid.Attr.n.u1Present = 1;
788 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
789
790 pCtx->dsHid.u32Limit = 0x0000ffff;
791 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
792 pCtx->dsHid.Attr.n.u1Present = 1;
793 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
794
795 pCtx->esHid.u32Limit = 0x0000ffff;
796 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
797 pCtx->esHid.Attr.n.u1Present = 1;
798 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
799
800 pCtx->fsHid.u32Limit = 0x0000ffff;
801 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
802 pCtx->fsHid.Attr.n.u1Present = 1;
803 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
804
805 pCtx->gsHid.u32Limit = 0x0000ffff;
806 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
807 pCtx->gsHid.Attr.n.u1Present = 1;
808 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
809
810 pCtx->ssHid.u32Limit = 0x0000ffff;
811 pCtx->ssHid.Attr.n.u1Present = 1;
812 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
813 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
814
815 pCtx->idtr.cbIdt = 0xffff;
816 pCtx->gdtr.cbGdt = 0xffff;
817
818 pCtx->ldtrHid.u32Limit = 0xffff;
819 pCtx->ldtrHid.Attr.n.u1Present = 1;
820 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
821
822 pCtx->trHid.u32Limit = 0xffff;
823 pCtx->trHid.Attr.n.u1Present = 1;
824 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
825
826 pCtx->dr[6] = X86_DR6_INIT_VAL;
827 pCtx->dr[7] = X86_DR7_INIT_VAL;
828
829 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
830 pCtx->fpu.FCW = 0x37f;
831
832 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
833 pCtx->fpu.MXCSR = 0x1F80;
834
835 /* Init PAT MSR */
836 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
837
838 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
839 * The Intel docs don't mention it.
840 */
841 pCtx->msrEFER = 0;
842}
843
844/**
845 * Resets the CPU.
846 *
847 * @returns VINF_SUCCESS.
848 * @param pVM The VM handle.
849 */
850VMMR3DECL(void) CPUMR3Reset(PVM pVM)
851{
852 for (VMCPUID i = 0; i < pVM->cCpus; i++)
853 {
854 CPUMR3ResetCpu(&pVM->aCpus[i]);
855
856#ifdef VBOX_WITH_CRASHDUMP_MAGIC
857 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
858
859 /* Magic marker for searching in crash dumps. */
860 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
861 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
862 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
863#endif
864 }
865}
866
867#ifdef VBOX_WITH_LIVE_MIGRATION
868
869/**
870 * Called both in pass 0 and the final pass.
871 *
872 * @param pVM The VM handle.
873 * @param pSSM The saved state handle.
874 */
875static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
876{
877 /*
878 * Save all the CPU ID leafs here so we can check them for compatability
879 * upon loading.
880 */
881 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
882 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
883
884 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
885 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
886
887 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
888 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
889
890 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
891
892 /*
893 * Save a good portion of the raw CPU IDs as well as they may come in
894 * handy when validating features for raw mode.
895 */
896 CPUMCPUID aRawStd[8];
897 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
898 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
899 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
900 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
901
902 CPUMCPUID aRawExt[16];
903 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
904 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
905 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
906 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
907}
908
909
910/**
911 * Loads the CPU ID leafs saved by pass 0.
912 *
913 * @returns VBox status code.
914 * @param pVM The VM handle.
915 * @param pSSM The saved state handle.
916 * @param uVersion The format version.
917 */
918static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
919{
920 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
921
922 /*
923 * Load them into stack buffers first.
924 */
925 CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
926 uint32_t cGuestCpuIdStd;
927 int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
928 if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
929 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
930 SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
931
932 CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
933 uint32_t cGuestCpuIdExt;
934 rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
935 if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
936 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
937 SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
938
939 CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
940 uint32_t cGuestCpuIdCentaur;
941 rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
942 if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
943 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
944 SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
945
946 CPUMCPUID GuestCpuIdDef;
947 rc = SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
948 AssertRCReturn(rc, rc);
949
950 CPUMCPUID aRawStd[8];
951 uint32_t cRawStd;
952 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
953 if (cRawStd > RT_ELEMENTS(aRawStd))
954 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
955 SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
956
957 CPUMCPUID aRawExt[16];
958 uint32_t cRawExt;
959 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
960 if (cRawExt > RT_ELEMENTS(aRawExt))
961 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
962 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
963 AssertRCReturn(rc, rc);
964
965 /*
966 * Note that we support restoring less than the current amount of standard
967 * leaves because we've been allowed more is newer version of VBox.
968 *
969 * So, pad new entries with the default.
970 */
971 for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
972 aGuestCpuIdStd[i] = GuestCpuIdDef;
973
974 for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
975 aGuestCpuIdExt[i] = GuestCpuIdDef;
976
977 for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
978 aGuestCpuIdCentaur[i] = GuestCpuIdDef;
979
980 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
981 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
982
983 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
984 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
985
986 /*
987 * Get the raw CPU IDs for the current host.
988 */
989 CPUMCPUID aHostRawStd[8];
990 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
991 ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
992
993 CPUMCPUID aHostRawExt[16];
994 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
995 ASMCpuId(i | UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
996
997 /*
998 * Now for the fun part...
999 */
1000
1001
1002 /*
1003 * We're good, commit the CPU ID leafs.
1004 */
1005 memcmp(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1006 memcmp(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1007 memcmp(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1008 pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1009
1010 return VINF_SUCCESS;
1011}
1012
1013
1014/**
1015 * Pass 0 live exec callback.
1016 *
1017 * @returns VINF_SSM_DONT_CALL_AGAIN.
1018 * @param pVM The VM handle.
1019 * @param pSSM The saved state handle.
1020 * @param uPass The pass (0).
1021 */
1022static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1023{
1024 AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1025 cpumR3SaveCpuId(pVM, pSSM);
1026 return VINF_SSM_DONT_CALL_AGAIN;
1027}
1028
1029#endif /* VBOX_WITH_LIVE_MIGRATION */
1030
1031/**
1032 * Execute state save operation.
1033 *
1034 * @returns VBox status code.
1035 * @param pVM VM Handle.
1036 * @param pSSM SSM operation handle.
1037 */
1038static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1039{
1040 /*
1041 * Save.
1042 */
1043 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1044 {
1045 PVMCPU pVCpu = &pVM->aCpus[i];
1046
1047 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1048 }
1049
1050 SSMR3PutU32(pSSM, pVM->cCpus);
1051 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1052 {
1053 PVMCPU pVCpu = &pVM->aCpus[i];
1054
1055 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1056 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1057 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1058 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1059 }
1060
1061#ifdef VBOX_WITH_LIVE_MIGRATION
1062 cpumR3SaveCpuId(pVM, pSSM);
1063 return VINF_SUCCESS;
1064#else
1065
1066 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1067 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1068
1069 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1070 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1071
1072 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1073 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1074
1075 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1076
1077 /* Add the cpuid for checking that the cpu is unchanged. */
1078 uint32_t au32CpuId[8] = {0};
1079 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1080 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1081 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
1082#endif
1083}
1084
1085
1086/**
1087 * Load a version 1.6 CPUMCTX structure.
1088 *
1089 * @returns VBox status code.
1090 * @param pVM VM Handle.
1091 * @param pCpumctx16 Version 1.6 CPUMCTX
1092 */
1093static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1094{
1095#define CPUMCTX16_LOADREG(RegName) \
1096 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1097
1098#define CPUMCTX16_LOADDRXREG(RegName) \
1099 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1100
1101#define CPUMCTX16_LOADHIDREG(RegName) \
1102 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1103 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1104 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1105
1106#define CPUMCTX16_LOADSEGREG(RegName) \
1107 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1108 CPUMCTX16_LOADHIDREG(RegName);
1109
1110 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1111
1112 CPUMCTX16_LOADREG(rax);
1113 CPUMCTX16_LOADREG(rbx);
1114 CPUMCTX16_LOADREG(rcx);
1115 CPUMCTX16_LOADREG(rdx);
1116 CPUMCTX16_LOADREG(rdi);
1117 CPUMCTX16_LOADREG(rsi);
1118 CPUMCTX16_LOADREG(rbp);
1119 CPUMCTX16_LOADREG(esp);
1120 CPUMCTX16_LOADREG(rip);
1121 CPUMCTX16_LOADREG(rflags);
1122
1123 CPUMCTX16_LOADSEGREG(cs);
1124 CPUMCTX16_LOADSEGREG(ds);
1125 CPUMCTX16_LOADSEGREG(es);
1126 CPUMCTX16_LOADSEGREG(fs);
1127 CPUMCTX16_LOADSEGREG(gs);
1128 CPUMCTX16_LOADSEGREG(ss);
1129
1130 CPUMCTX16_LOADREG(r8);
1131 CPUMCTX16_LOADREG(r9);
1132 CPUMCTX16_LOADREG(r10);
1133 CPUMCTX16_LOADREG(r11);
1134 CPUMCTX16_LOADREG(r12);
1135 CPUMCTX16_LOADREG(r13);
1136 CPUMCTX16_LOADREG(r14);
1137 CPUMCTX16_LOADREG(r15);
1138
1139 CPUMCTX16_LOADREG(cr0);
1140 CPUMCTX16_LOADREG(cr2);
1141 CPUMCTX16_LOADREG(cr3);
1142 CPUMCTX16_LOADREG(cr4);
1143
1144 CPUMCTX16_LOADDRXREG(0);
1145 CPUMCTX16_LOADDRXREG(1);
1146 CPUMCTX16_LOADDRXREG(2);
1147 CPUMCTX16_LOADDRXREG(3);
1148 CPUMCTX16_LOADDRXREG(4);
1149 CPUMCTX16_LOADDRXREG(5);
1150 CPUMCTX16_LOADDRXREG(6);
1151 CPUMCTX16_LOADDRXREG(7);
1152
1153 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
1154 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
1155 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
1156 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
1157
1158 CPUMCTX16_LOADREG(ldtr);
1159 CPUMCTX16_LOADREG(tr);
1160
1161 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
1162
1163 CPUMCTX16_LOADREG(msrEFER);
1164 CPUMCTX16_LOADREG(msrSTAR);
1165 CPUMCTX16_LOADREG(msrPAT);
1166 CPUMCTX16_LOADREG(msrLSTAR);
1167 CPUMCTX16_LOADREG(msrCSTAR);
1168 CPUMCTX16_LOADREG(msrSFMASK);
1169 CPUMCTX16_LOADREG(msrKERNELGSBASE);
1170
1171 CPUMCTX16_LOADHIDREG(ldtr);
1172 CPUMCTX16_LOADHIDREG(tr);
1173
1174#undef CPUMCTX16_LOADSEGREG
1175#undef CPUMCTX16_LOADHIDREG
1176#undef CPUMCTX16_LOADDRXREG
1177#undef CPUMCTX16_LOADREG
1178}
1179
1180
1181/**
1182 * Execute state load operation.
1183 *
1184 * @returns VBox status code.
1185 * @param pVM VM Handle.
1186 * @param pSSM SSM operation handle.
1187 * @param uVersion Data layout version.
1188 * @param uPass The data pass.
1189 */
1190static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1191{
1192 /*
1193 * Validate version.
1194 */
1195 if ( uVersion != CPUM_SAVED_STATE_VERSION
1196 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1197 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1198 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1199 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1200 {
1201 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1202 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1203 }
1204
1205 if (uPass == SSM_PASS_FINAL)
1206 {
1207 /*
1208 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1209 * really old SSM file versions.)
1210 */
1211 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1212 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1213 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1214 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1215
1216 /*
1217 * Restore.
1218 */
1219 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1220 {
1221 PVMCPU pVCpu = &pVM->aCpus[i];
1222 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1223 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1224
1225 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1226 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1227 pVCpu->cpum.s.Hyper.esp = uESP;
1228 }
1229
1230 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1231 {
1232 CPUMCTX_VER1_6 cpumctx16;
1233 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1234 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1235
1236 /* Save the old cpumctx state into the new one. */
1237 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1238
1239 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1240 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1241 }
1242 else
1243 {
1244 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1245 {
1246 uint32_t cCpus;
1247 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1248 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1249 VERR_SSM_UNEXPECTED_DATA);
1250 }
1251 AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1252 || pVM->cCpus == 1,
1253 ("cCpus=%u\n", pVM->cCpus),
1254 VERR_SSM_UNEXPECTED_DATA);
1255
1256 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1257 {
1258 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1259 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1260 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1261 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1262 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1263 }
1264 }
1265 }
1266
1267#ifdef VBOX_WITH_LIVE_MIGRATION
1268 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
1269 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1270
1271 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
1272 * actually required. */
1273#endif
1274
1275 /*
1276 * Restore the CPUID leaves.
1277 *
1278 * Note that we support restoring less than the current amount of standard
1279 * leaves because we've been allowed more is newer version of VBox.
1280 */
1281 uint32_t cElements;
1282 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1283 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1284 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1285 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1286
1287 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1288 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1289 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1290 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1291
1292 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1293 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1294 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1295 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1296
1297 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1298
1299 /*
1300 * Check that the basic cpuid id information is unchanged.
1301 */
1302 /** @todo we should check the 64 bits capabilities too! */
1303 uint32_t au32CpuId[8] = {0};
1304 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1305 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1306 uint32_t au32CpuIdSaved[8];
1307 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1308 if (RT_SUCCESS(rc))
1309 {
1310 /* Ignore CPU stepping. */
1311 au32CpuId[4] &= 0xfffffff0;
1312 au32CpuIdSaved[4] &= 0xfffffff0;
1313
1314 /* Ignore APIC ID (AMD specs). */
1315 au32CpuId[5] &= ~0xff000000;
1316 au32CpuIdSaved[5] &= ~0xff000000;
1317
1318 /* Ignore the number of Logical CPUs (AMD specs). */
1319 au32CpuId[5] &= ~0x00ff0000;
1320 au32CpuIdSaved[5] &= ~0x00ff0000;
1321
1322 /* Ignore some advanced capability bits, that we don't expose to the guest. */
1323 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1324 | X86_CPUID_FEATURE_ECX_VMX
1325 | X86_CPUID_FEATURE_ECX_SMX
1326 | X86_CPUID_FEATURE_ECX_EST
1327 | X86_CPUID_FEATURE_ECX_TM2
1328 | X86_CPUID_FEATURE_ECX_CNTXID
1329 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1330 | X86_CPUID_FEATURE_ECX_PDCM
1331 | X86_CPUID_FEATURE_ECX_DCA
1332 | X86_CPUID_FEATURE_ECX_X2APIC
1333 );
1334 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1335 | X86_CPUID_FEATURE_ECX_VMX
1336 | X86_CPUID_FEATURE_ECX_SMX
1337 | X86_CPUID_FEATURE_ECX_EST
1338 | X86_CPUID_FEATURE_ECX_TM2
1339 | X86_CPUID_FEATURE_ECX_CNTXID
1340 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1341 | X86_CPUID_FEATURE_ECX_PDCM
1342 | X86_CPUID_FEATURE_ECX_DCA
1343 | X86_CPUID_FEATURE_ECX_X2APIC
1344 );
1345
1346 /* Make sure we don't forget to update the masks when enabling
1347 * features in the future.
1348 */
1349 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
1350 ( X86_CPUID_FEATURE_ECX_DTES64
1351 | X86_CPUID_FEATURE_ECX_VMX
1352 | X86_CPUID_FEATURE_ECX_SMX
1353 | X86_CPUID_FEATURE_ECX_EST
1354 | X86_CPUID_FEATURE_ECX_TM2
1355 | X86_CPUID_FEATURE_ECX_CNTXID
1356 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1357 | X86_CPUID_FEATURE_ECX_PDCM
1358 | X86_CPUID_FEATURE_ECX_DCA
1359 | X86_CPUID_FEATURE_ECX_X2APIC
1360 )));
1361 /* do the compare */
1362 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1363 {
1364 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1365 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1366 "Saved=%.*Rhxs\n"
1367 "Real =%.*Rhxs\n",
1368 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1369 sizeof(au32CpuId), au32CpuId));
1370 else
1371 {
1372 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
1373 "Saved=%.*Rhxs\n"
1374 "Real =%.*Rhxs\n",
1375 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1376 sizeof(au32CpuId), au32CpuId));
1377 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1378 }
1379 }
1380 }
1381
1382 return rc;
1383}
1384
1385
1386/**
1387 * Formats the EFLAGS value into mnemonics.
1388 *
1389 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1390 * @param efl The EFLAGS value.
1391 */
1392static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1393{
1394 /*
1395 * Format the flags.
1396 */
1397 static const struct
1398 {
1399 const char *pszSet; const char *pszClear; uint32_t fFlag;
1400 } s_aFlags[] =
1401 {
1402 { "vip",NULL, X86_EFL_VIP },
1403 { "vif",NULL, X86_EFL_VIF },
1404 { "ac", NULL, X86_EFL_AC },
1405 { "vm", NULL, X86_EFL_VM },
1406 { "rf", NULL, X86_EFL_RF },
1407 { "nt", NULL, X86_EFL_NT },
1408 { "ov", "nv", X86_EFL_OF },
1409 { "dn", "up", X86_EFL_DF },
1410 { "ei", "di", X86_EFL_IF },
1411 { "tf", NULL, X86_EFL_TF },
1412 { "nt", "pl", X86_EFL_SF },
1413 { "nz", "zr", X86_EFL_ZF },
1414 { "ac", "na", X86_EFL_AF },
1415 { "po", "pe", X86_EFL_PF },
1416 { "cy", "nc", X86_EFL_CF },
1417 };
1418 char *psz = pszEFlags;
1419 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1420 {
1421 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1422 if (pszAdd)
1423 {
1424 strcpy(psz, pszAdd);
1425 psz += strlen(pszAdd);
1426 *psz++ = ' ';
1427 }
1428 }
1429 psz[-1] = '\0';
1430}
1431
1432
1433/**
1434 * Formats a full register dump.
1435 *
1436 * @param pVM VM Handle.
1437 * @param pCtx The context to format.
1438 * @param pCtxCore The context core to format.
1439 * @param pHlp Output functions.
1440 * @param enmType The dump type.
1441 * @param pszPrefix Register name prefix.
1442 */
1443static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1444{
1445 /*
1446 * Format the EFLAGS.
1447 */
1448 uint32_t efl = pCtxCore->eflags.u32;
1449 char szEFlags[80];
1450 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1451
1452 /*
1453 * Format the registers.
1454 */
1455 switch (enmType)
1456 {
1457 case CPUMDUMPTYPE_TERSE:
1458 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1459 pHlp->pfnPrintf(pHlp,
1460 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1461 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1462 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1463 "%sr14=%016RX64 %sr15=%016RX64\n"
1464 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1465 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1466 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1467 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1468 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1469 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1470 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1471 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1472 else
1473 pHlp->pfnPrintf(pHlp,
1474 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1475 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1476 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1477 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1478 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1479 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1480 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1481 break;
1482
1483 case CPUMDUMPTYPE_DEFAULT:
1484 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1485 pHlp->pfnPrintf(pHlp,
1486 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1487 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1488 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1489 "%sr14=%016RX64 %sr15=%016RX64\n"
1490 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1491 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1492 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1493 ,
1494 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1495 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1496 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1497 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1498 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1499 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1500 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1501 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1502 else
1503 pHlp->pfnPrintf(pHlp,
1504 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1505 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1506 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1507 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1508 ,
1509 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1510 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1511 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1512 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1513 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1514 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1515 break;
1516
1517 case CPUMDUMPTYPE_VERBOSE:
1518 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1519 pHlp->pfnPrintf(pHlp,
1520 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1521 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1522 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1523 "%sr14=%016RX64 %sr15=%016RX64\n"
1524 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1525 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1526 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1527 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1528 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1529 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1530 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1531 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1532 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1533 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1534 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1535 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1536 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1537 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1538 ,
1539 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1540 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1541 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1542 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1543 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1544 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1545 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1546 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1547 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1548 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1549 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1550 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1551 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1552 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1553 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1554 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1555 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1556 else
1557 pHlp->pfnPrintf(pHlp,
1558 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1559 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1560 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1561 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1562 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1563 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1564 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1565 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1566 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1567 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1568 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1569 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1570 ,
1571 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1572 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1573 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1574 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1575 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1576 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1577 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1578 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1579 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1580 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1581 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1582 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1583
1584 pHlp->pfnPrintf(pHlp,
1585 "FPU:\n"
1586 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1587 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1588 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1589 ,
1590 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1591 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1592 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1593 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1594
1595 pHlp->pfnPrintf(pHlp,
1596 "MSR:\n"
1597 "%sEFER =%016RX64\n"
1598 "%sPAT =%016RX64\n"
1599 "%sSTAR =%016RX64\n"
1600 "%sCSTAR =%016RX64\n"
1601 "%sLSTAR =%016RX64\n"
1602 "%sSFMASK =%016RX64\n"
1603 "%sKERNELGSBASE =%016RX64\n",
1604 pszPrefix, pCtx->msrEFER,
1605 pszPrefix, pCtx->msrPAT,
1606 pszPrefix, pCtx->msrSTAR,
1607 pszPrefix, pCtx->msrCSTAR,
1608 pszPrefix, pCtx->msrLSTAR,
1609 pszPrefix, pCtx->msrSFMASK,
1610 pszPrefix, pCtx->msrKERNELGSBASE);
1611 break;
1612 }
1613}
1614
1615
1616/**
1617 * Display all cpu states and any other cpum info.
1618 *
1619 * @param pVM VM Handle.
1620 * @param pHlp The info helper functions.
1621 * @param pszArgs Arguments, ignored.
1622 */
1623static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1624{
1625 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1626 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1627 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1628 cpumR3InfoHost(pVM, pHlp, pszArgs);
1629}
1630
1631
1632/**
1633 * Parses the info argument.
1634 *
1635 * The argument starts with 'verbose', 'terse' or 'default' and then
1636 * continues with the comment string.
1637 *
1638 * @param pszArgs The pointer to the argument string.
1639 * @param penmType Where to store the dump type request.
1640 * @param ppszComment Where to store the pointer to the comment string.
1641 */
1642static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1643{
1644 if (!pszArgs)
1645 {
1646 *penmType = CPUMDUMPTYPE_DEFAULT;
1647 *ppszComment = "";
1648 }
1649 else
1650 {
1651 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1652 {
1653 pszArgs += 5;
1654 *penmType = CPUMDUMPTYPE_VERBOSE;
1655 }
1656 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1657 {
1658 pszArgs += 5;
1659 *penmType = CPUMDUMPTYPE_TERSE;
1660 }
1661 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1662 {
1663 pszArgs += 7;
1664 *penmType = CPUMDUMPTYPE_DEFAULT;
1665 }
1666 else
1667 *penmType = CPUMDUMPTYPE_DEFAULT;
1668 *ppszComment = RTStrStripL(pszArgs);
1669 }
1670}
1671
1672
1673/**
1674 * Display the guest cpu state.
1675 *
1676 * @param pVM VM Handle.
1677 * @param pHlp The info helper functions.
1678 * @param pszArgs Arguments, ignored.
1679 */
1680static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1681{
1682 CPUMDUMPTYPE enmType;
1683 const char *pszComment;
1684 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1685
1686 /* @todo SMP support! */
1687 PVMCPU pVCpu = VMMGetCpu(pVM);
1688 if (!pVCpu)
1689 pVCpu = &pVM->aCpus[0];
1690
1691 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1692
1693 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1694 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1695}
1696
1697
1698/**
1699 * Display the current guest instruction
1700 *
1701 * @param pVM VM Handle.
1702 * @param pHlp The info helper functions.
1703 * @param pszArgs Arguments, ignored.
1704 */
1705static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1706{
1707 char szInstruction[256];
1708 /* @todo SMP support! */
1709 PVMCPU pVCpu = VMMGetCpu(pVM);
1710 if (!pVCpu)
1711 pVCpu = &pVM->aCpus[0];
1712
1713 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1714 if (RT_SUCCESS(rc))
1715 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1716}
1717
1718
1719/**
1720 * Display the hypervisor cpu state.
1721 *
1722 * @param pVM VM Handle.
1723 * @param pHlp The info helper functions.
1724 * @param pszArgs Arguments, ignored.
1725 */
1726static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1727{
1728 CPUMDUMPTYPE enmType;
1729 const char *pszComment;
1730 /* @todo SMP */
1731 PVMCPU pVCpu = &pVM->aCpus[0];
1732
1733 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1734 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1735 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1736 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1737}
1738
1739
1740/**
1741 * Display the host cpu state.
1742 *
1743 * @param pVM VM Handle.
1744 * @param pHlp The info helper functions.
1745 * @param pszArgs Arguments, ignored.
1746 */
1747static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1748{
1749 CPUMDUMPTYPE enmType;
1750 const char *pszComment;
1751 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1752 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1753
1754 /*
1755 * Format the EFLAGS.
1756 */
1757 /* @todo SMP */
1758 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1759#if HC_ARCH_BITS == 32
1760 uint32_t efl = pCtx->eflags.u32;
1761#else
1762 uint64_t efl = pCtx->rflags;
1763#endif
1764 char szEFlags[80];
1765 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1766
1767 /*
1768 * Format the registers.
1769 */
1770#if HC_ARCH_BITS == 32
1771# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1772 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1773# endif
1774 {
1775 pHlp->pfnPrintf(pHlp,
1776 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1777 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1778 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1779 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1780 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1781 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1782 ,
1783 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1784 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1785 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1786 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1787 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1788 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1789 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1790 }
1791# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1792 else
1793# endif
1794#endif
1795#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1796 {
1797 pHlp->pfnPrintf(pHlp,
1798 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1799 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1800 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1801 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1802 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1803 "r14=%016RX64 r15=%016RX64\n"
1804 "iopl=%d %31s\n"
1805 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1806 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1807 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1808 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1809 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1810 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1811 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1812 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1813 ,
1814 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1815 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1816 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1817 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1818 pCtx->r11, pCtx->r12, pCtx->r13,
1819 pCtx->r14, pCtx->r15,
1820 X86_EFL_GET_IOPL(efl), szEFlags,
1821 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1822 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1823 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1824 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1825 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1826 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1827 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1828 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1829 }
1830#endif
1831}
1832
1833
1834/**
1835 * Get L1 cache / TLS associativity.
1836 */
1837static const char *getCacheAss(unsigned u, char *pszBuf)
1838{
1839 if (u == 0)
1840 return "res0 ";
1841 if (u == 1)
1842 return "direct";
1843 if (u >= 256)
1844 return "???";
1845
1846 RTStrPrintf(pszBuf, 16, "%d way", u);
1847 return pszBuf;
1848}
1849
1850
1851/**
1852 * Get L2 cache soociativity.
1853 */
1854const char *getL2CacheAss(unsigned u)
1855{
1856 switch (u)
1857 {
1858 case 0: return "off ";
1859 case 1: return "direct";
1860 case 2: return "2 way ";
1861 case 3: return "res3 ";
1862 case 4: return "4 way ";
1863 case 5: return "res5 ";
1864 case 6: return "8 way "; case 7: return "res7 ";
1865 case 8: return "16 way";
1866 case 9: return "res9 ";
1867 case 10: return "res10 ";
1868 case 11: return "res11 ";
1869 case 12: return "res12 ";
1870 case 13: return "res13 ";
1871 case 14: return "res14 ";
1872 case 15: return "fully ";
1873 default:
1874 return "????";
1875 }
1876}
1877
1878
1879/**
1880 * Display the guest CpuId leaves.
1881 *
1882 * @param pVM VM Handle.
1883 * @param pHlp The info helper functions.
1884 * @param pszArgs "terse", "default" or "verbose".
1885 */
1886static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1887{
1888 /*
1889 * Parse the argument.
1890 */
1891 unsigned iVerbosity = 1;
1892 if (pszArgs)
1893 {
1894 pszArgs = RTStrStripL(pszArgs);
1895 if (!strcmp(pszArgs, "terse"))
1896 iVerbosity--;
1897 else if (!strcmp(pszArgs, "verbose"))
1898 iVerbosity++;
1899 }
1900
1901 /*
1902 * Start cracking.
1903 */
1904 CPUMCPUID Host;
1905 CPUMCPUID Guest;
1906 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1907
1908 pHlp->pfnPrintf(pHlp,
1909 " RAW Standard CPUIDs\n"
1910 " Function eax ebx ecx edx\n");
1911 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1912 {
1913 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1914 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1915
1916 pHlp->pfnPrintf(pHlp,
1917 "Gst: %08x %08x %08x %08x %08x%s\n"
1918 "Hst: %08x %08x %08x %08x\n",
1919 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1920 i <= cStdMax ? "" : "*",
1921 Host.eax, Host.ebx, Host.ecx, Host.edx);
1922 }
1923
1924 /*
1925 * If verbose, decode it.
1926 */
1927 if (iVerbosity)
1928 {
1929 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1930 pHlp->pfnPrintf(pHlp,
1931 "Name: %.04s%.04s%.04s\n"
1932 "Supports: 0-%x\n",
1933 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1934 }
1935
1936 /*
1937 * Get Features.
1938 */
1939 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1940 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1941 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1942 if (cStdMax >= 1 && iVerbosity)
1943 {
1944 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1945 uint32_t uEAX = Guest.eax;
1946
1947 pHlp->pfnPrintf(pHlp,
1948 "Family: %d \tExtended: %d \tEffective: %d\n"
1949 "Model: %d \tExtended: %d \tEffective: %d\n"
1950 "Stepping: %d\n"
1951 "APIC ID: %#04x\n"
1952 "Logical CPUs: %d\n"
1953 "CLFLUSH Size: %d\n"
1954 "Brand ID: %#04x\n",
1955 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1956 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1957 ASMGetCpuStepping(uEAX),
1958 (Guest.ebx >> 24) & 0xff,
1959 (Guest.ebx >> 16) & 0xff,
1960 (Guest.ebx >> 8) & 0xff,
1961 (Guest.ebx >> 0) & 0xff);
1962 if (iVerbosity == 1)
1963 {
1964 uint32_t uEDX = Guest.edx;
1965 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1966 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1967 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1968 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1969 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1970 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1971 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1972 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1973 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1974 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1975 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1976 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1977 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1978 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1979 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1980 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1981 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1982 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1983 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1984 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1985 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1986 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1987 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1988 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1989 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1990 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1991 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1992 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1993 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1994 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1995 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1996 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1997 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1998 pHlp->pfnPrintf(pHlp, "\n");
1999
2000 uint32_t uECX = Guest.ecx;
2001 pHlp->pfnPrintf(pHlp, "Features ECX: ");
2002 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2003 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
2004 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
2005 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2006 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2007 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2008 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
2009 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2010 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2011 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
2012 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2013 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2014 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
2015 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2016 for (unsigned iBit = 14; iBit < 32; iBit++)
2017 if (uECX & RT_BIT(iBit))
2018 pHlp->pfnPrintf(pHlp, " %d", iBit);
2019 pHlp->pfnPrintf(pHlp, "\n");
2020 }
2021 else
2022 {
2023 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2024
2025 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2026 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2027 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2028 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2029
2030 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2031 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2032 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2033 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2034 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2035 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2036 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2037 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2038 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2039 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2040 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2041 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2042 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2043 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2044 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2045 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
2046 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
2047 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
2048 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
2049 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
2050 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
2051 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
2052 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
2053 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
2054 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
2055 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
2056 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
2057 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
2058 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
2059 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
2060 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
2061 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
2062 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
2063
2064 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
2065 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
2066 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
2067 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
2068 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
2069 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
2070 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
2071 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2072 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
2073 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
2074 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
2075 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved2, EcxHost.u2Reserved2);
2076 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
2077 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
2078 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
2079 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
2080 pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
2081 pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
2082 pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
2083 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
2084 pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
2085 pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
2086 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
2087 pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
2088 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
2089 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
2090 }
2091 }
2092 if (cStdMax >= 2 && iVerbosity)
2093 {
2094 /** @todo */
2095 }
2096
2097 /*
2098 * Extended.
2099 * Implemented after AMD specs.
2100 */
2101 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
2102
2103 pHlp->pfnPrintf(pHlp,
2104 "\n"
2105 " RAW Extended CPUIDs\n"
2106 " Function eax ebx ecx edx\n");
2107 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
2108 {
2109 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
2110 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2111
2112 pHlp->pfnPrintf(pHlp,
2113 "Gst: %08x %08x %08x %08x %08x%s\n"
2114 "Hst: %08x %08x %08x %08x\n",
2115 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2116 i <= cExtMax ? "" : "*",
2117 Host.eax, Host.ebx, Host.ecx, Host.edx);
2118 }
2119
2120 /*
2121 * Understandable output
2122 */
2123 if (iVerbosity)
2124 {
2125 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
2126 pHlp->pfnPrintf(pHlp,
2127 "Ext Name: %.4s%.4s%.4s\n"
2128 "Ext Supports: 0x80000000-%#010x\n",
2129 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2130 }
2131
2132 if (iVerbosity && cExtMax >= 1)
2133 {
2134 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
2135 uint32_t uEAX = Guest.eax;
2136 pHlp->pfnPrintf(pHlp,
2137 "Family: %d \tExtended: %d \tEffective: %d\n"
2138 "Model: %d \tExtended: %d \tEffective: %d\n"
2139 "Stepping: %d\n"
2140 "Brand ID: %#05x\n",
2141 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2142 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2143 ASMGetCpuStepping(uEAX),
2144 Guest.ebx & 0xfff);
2145
2146 if (iVerbosity == 1)
2147 {
2148 uint32_t uEDX = Guest.edx;
2149 pHlp->pfnPrintf(pHlp, "Features EDX: ");
2150 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2151 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2152 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2153 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2154 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2155 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2156 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2157 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2158 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2159 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2160 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2161 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
2162 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2163 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2164 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2165 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2166 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2167 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2168 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
2169 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
2170 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
2171 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
2172 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
2173 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2174 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2175 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
2176 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
2177 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
2178 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
2179 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
2180 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
2181 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
2182 pHlp->pfnPrintf(pHlp, "\n");
2183
2184 uint32_t uECX = Guest.ecx;
2185 pHlp->pfnPrintf(pHlp, "Features ECX: ");
2186 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
2187 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
2188 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
2189 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
2190 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
2191 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
2192 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
2193 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
2194 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
2195 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
2196 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
2197 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
2198 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
2199 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
2200 for (unsigned iBit = 5; iBit < 32; iBit++)
2201 if (uECX & RT_BIT(iBit))
2202 pHlp->pfnPrintf(pHlp, " %d", iBit);
2203 pHlp->pfnPrintf(pHlp, "\n");
2204 }
2205 else
2206 {
2207 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2208
2209 uint32_t uEdxGst = Guest.edx;
2210 uint32_t uEdxHst = Host.edx;
2211 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2212 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2213 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2214 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2215 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2216 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2217 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2218 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2219 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2220 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2221 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2222 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2223 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2224 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2225 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2226 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
2227 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
2228 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
2229 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
2230 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
2231 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
2232 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
2233 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
2234 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
2235 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
2236 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
2237 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
2238 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
2239 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
2240 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
2241 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
2242 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
2243 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
2244
2245 uint32_t uEcxGst = Guest.ecx;
2246 uint32_t uEcxHst = Host.ecx;
2247 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
2248 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
2249 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
2250 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
2251 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
2252 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
2253 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
2254 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
2255 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
2256 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
2257 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
2258 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
2259 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
2260 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
2261 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
2262 }
2263 }
2264
2265 if (iVerbosity && cExtMax >= 2)
2266 {
2267 char szString[4*4*3+1] = {0};
2268 uint32_t *pu32 = (uint32_t *)szString;
2269 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
2270 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
2271 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
2272 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
2273 if (cExtMax >= 3)
2274 {
2275 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
2276 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
2277 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2278 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2279 }
2280 if (cExtMax >= 4)
2281 {
2282 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2283 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2284 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2285 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2286 }
2287 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2288 }
2289
2290 if (iVerbosity && cExtMax >= 5)
2291 {
2292 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2293 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2294 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2295 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2296 char sz1[32];
2297 char sz2[32];
2298
2299 pHlp->pfnPrintf(pHlp,
2300 "TLB 2/4M Instr/Uni: %s %3d entries\n"
2301 "TLB 2/4M Data: %s %3d entries\n",
2302 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2303 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2304 pHlp->pfnPrintf(pHlp,
2305 "TLB 4K Instr/Uni: %s %3d entries\n"
2306 "TLB 4K Data: %s %3d entries\n",
2307 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2308 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2309 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2310 "L1 Instr Cache Lines Per Tag: %d\n"
2311 "L1 Instr Cache Associativity: %s\n"
2312 "L1 Instr Cache Size: %d KB\n",
2313 (uEDX >> 0) & 0xff,
2314 (uEDX >> 8) & 0xff,
2315 getCacheAss((uEDX >> 16) & 0xff, sz1),
2316 (uEDX >> 24) & 0xff);
2317 pHlp->pfnPrintf(pHlp,
2318 "L1 Data Cache Line Size: %d bytes\n"
2319 "L1 Data Cache Lines Per Tag: %d\n"
2320 "L1 Data Cache Associativity: %s\n"
2321 "L1 Data Cache Size: %d KB\n",
2322 (uECX >> 0) & 0xff,
2323 (uECX >> 8) & 0xff,
2324 getCacheAss((uECX >> 16) & 0xff, sz1),
2325 (uECX >> 24) & 0xff);
2326 }
2327
2328 if (iVerbosity && cExtMax >= 6)
2329 {
2330 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2331 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2332 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2333
2334 pHlp->pfnPrintf(pHlp,
2335 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2336 "L2 TLB 2/4M Data: %s %4d entries\n",
2337 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2338 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2339 pHlp->pfnPrintf(pHlp,
2340 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2341 "L2 TLB 4K Data: %s %4d entries\n",
2342 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2343 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2344 pHlp->pfnPrintf(pHlp,
2345 "L2 Cache Line Size: %d bytes\n"
2346 "L2 Cache Lines Per Tag: %d\n"
2347 "L2 Cache Associativity: %s\n"
2348 "L2 Cache Size: %d KB\n",
2349 (uEDX >> 0) & 0xff,
2350 (uEDX >> 8) & 0xf,
2351 getL2CacheAss((uEDX >> 12) & 0xf),
2352 (uEDX >> 16) & 0xffff);
2353 }
2354
2355 if (iVerbosity && cExtMax >= 7)
2356 {
2357 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2358
2359 pHlp->pfnPrintf(pHlp, "APM Features: ");
2360 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2361 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2362 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2363 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2364 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2365 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2366 for (unsigned iBit = 6; iBit < 32; iBit++)
2367 if (uEDX & RT_BIT(iBit))
2368 pHlp->pfnPrintf(pHlp, " %d", iBit);
2369 pHlp->pfnPrintf(pHlp, "\n");
2370 }
2371
2372 if (iVerbosity && cExtMax >= 8)
2373 {
2374 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2375 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2376
2377 pHlp->pfnPrintf(pHlp,
2378 "Physical Address Width: %d bits\n"
2379 "Virtual Address Width: %d bits\n",
2380 (uEAX >> 0) & 0xff,
2381 (uEAX >> 8) & 0xff);
2382 pHlp->pfnPrintf(pHlp,
2383 "Physical Core Count: %d\n",
2384 (uECX >> 0) & 0xff);
2385 }
2386
2387
2388 /*
2389 * Centaur.
2390 */
2391 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2392
2393 pHlp->pfnPrintf(pHlp,
2394 "\n"
2395 " RAW Centaur CPUIDs\n"
2396 " Function eax ebx ecx edx\n");
2397 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2398 {
2399 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2400 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2401
2402 pHlp->pfnPrintf(pHlp,
2403 "Gst: %08x %08x %08x %08x %08x%s\n"
2404 "Hst: %08x %08x %08x %08x\n",
2405 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2406 i <= cCentaurMax ? "" : "*",
2407 Host.eax, Host.ebx, Host.ecx, Host.edx);
2408 }
2409
2410 /*
2411 * Understandable output
2412 */
2413 if (iVerbosity)
2414 {
2415 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2416 pHlp->pfnPrintf(pHlp,
2417 "Centaur Supports: 0xc0000000-%#010x\n",
2418 Guest.eax);
2419 }
2420
2421 if (iVerbosity && cCentaurMax >= 1)
2422 {
2423 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2424 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2425 uint32_t uEdxHst = Host.edx;
2426
2427 if (iVerbosity == 1)
2428 {
2429 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2430 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2431 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2432 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2433 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2434 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2435 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2436 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2437 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2438 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2439 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2440 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2441 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2442 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2443 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2444 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2445 for (unsigned iBit = 14; iBit < 32; iBit++)
2446 if (uEdxGst & RT_BIT(iBit))
2447 pHlp->pfnPrintf(pHlp, " %d", iBit);
2448 pHlp->pfnPrintf(pHlp, "\n");
2449 }
2450 else
2451 {
2452 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2453 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2454 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2455 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2456 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2457 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2458 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2459 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2460 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2461 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2462 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2463 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2464 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2465 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2466 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2467 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2468 for (unsigned iBit = 14; iBit < 32; iBit++)
2469 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2470 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2471 pHlp->pfnPrintf(pHlp, "\n");
2472 }
2473 }
2474}
2475
2476
2477/**
2478 * Structure used when disassembling and instructions in DBGF.
2479 * This is used so the reader function can get the stuff it needs.
2480 */
2481typedef struct CPUMDISASSTATE
2482{
2483 /** Pointer to the CPU structure. */
2484 PDISCPUSTATE pCpu;
2485 /** The VM handle. */
2486 PVM pVM;
2487 /** The VMCPU handle. */
2488 PVMCPU pVCpu;
2489 /** Pointer to the first byte in the segemnt. */
2490 RTGCUINTPTR GCPtrSegBase;
2491 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2492 RTGCUINTPTR GCPtrSegEnd;
2493 /** The size of the segment minus 1. */
2494 RTGCUINTPTR cbSegLimit;
2495 /** Pointer to the current page - R3 Ptr. */
2496 void const *pvPageR3;
2497 /** Pointer to the current page - GC Ptr. */
2498 RTGCPTR pvPageGC;
2499 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2500 PGMPAGEMAPLOCK PageMapLock;
2501 /** Whether the PageMapLock is valid or not. */
2502 bool fLocked;
2503 /** 64 bits mode or not. */
2504 bool f64Bits;
2505} CPUMDISASSTATE, *PCPUMDISASSTATE;
2506
2507
2508/**
2509 * Instruction reader.
2510 *
2511 * @returns VBox status code.
2512 * @param PtrSrc Address to read from.
2513 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2514 * @param pu8Dst Where to store the bytes.
2515 * @param cbRead Number of bytes to read.
2516 * @param uDisCpu Pointer to the disassembler cpu state.
2517 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2518 */
2519static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2520{
2521 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2522 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2523 Assert(cbRead > 0);
2524 for (;;)
2525 {
2526 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2527
2528 /* Need to update the page translation? */
2529 if ( !pState->pvPageR3
2530 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2531 {
2532 int rc = VINF_SUCCESS;
2533
2534 /* translate the address */
2535 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2536 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2537 && !HWACCMIsEnabled(pState->pVM))
2538 {
2539 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2540 if (!pState->pvPageR3)
2541 rc = VERR_INVALID_POINTER;
2542 }
2543 else
2544 {
2545 /* Release mapping lock previously acquired. */
2546 if (pState->fLocked)
2547 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2548 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2549 pState->fLocked = RT_SUCCESS_NP(rc);
2550 }
2551 if (RT_FAILURE(rc))
2552 {
2553 pState->pvPageR3 = NULL;
2554 return rc;
2555 }
2556 }
2557
2558 /* check the segemnt limit */
2559 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2560 return VERR_OUT_OF_SELECTOR_BOUNDS;
2561
2562 /* calc how much we can read */
2563 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2564 if (!pState->f64Bits)
2565 {
2566 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2567 if (cb > cbSeg && cbSeg)
2568 cb = cbSeg;
2569 }
2570 if (cb > cbRead)
2571 cb = cbRead;
2572
2573 /* read and advance */
2574 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2575 cbRead -= cb;
2576 if (!cbRead)
2577 return VINF_SUCCESS;
2578 pu8Dst += cb;
2579 PtrSrc += cb;
2580 }
2581}
2582
2583
2584/**
2585 * Disassemble an instruction and return the information in the provided structure.
2586 *
2587 * @returns VBox status code.
2588 * @param pVM VM Handle
2589 * @param pVCpu VMCPU Handle
2590 * @param pCtx CPU context
2591 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2592 * @param pCpu Disassembly state
2593 * @param pszPrefix String prefix for logging (debug only)
2594 *
2595 */
2596VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2597{
2598 CPUMDISASSTATE State;
2599 int rc;
2600
2601 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2602 State.pCpu = pCpu;
2603 State.pvPageGC = 0;
2604 State.pvPageR3 = NULL;
2605 State.pVM = pVM;
2606 State.pVCpu = pVCpu;
2607 State.fLocked = false;
2608 State.f64Bits = false;
2609
2610 /*
2611 * Get selector information.
2612 */
2613 if ( (pCtx->cr0 & X86_CR0_PE)
2614 && pCtx->eflags.Bits.u1VM == 0)
2615 {
2616 if (CPUMAreHiddenSelRegsValid(pVM))
2617 {
2618 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2619 State.GCPtrSegBase = pCtx->csHid.u64Base;
2620 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2621 State.cbSegLimit = pCtx->csHid.u32Limit;
2622 pCpu->mode = (State.f64Bits)
2623 ? CPUMODE_64BIT
2624 : pCtx->csHid.Attr.n.u1DefBig
2625 ? CPUMODE_32BIT
2626 : CPUMODE_16BIT;
2627 }
2628 else
2629 {
2630 DBGFSELINFO SelInfo;
2631
2632 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2633 if (RT_FAILURE(rc))
2634 {
2635 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2636 return rc;
2637 }
2638
2639 /*
2640 * Validate the selector.
2641 */
2642 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2643 if (RT_FAILURE(rc))
2644 {
2645 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2646 return rc;
2647 }
2648 State.GCPtrSegBase = SelInfo.GCPtrBase;
2649 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2650 State.cbSegLimit = SelInfo.cbLimit;
2651 pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2652 }
2653 }
2654 else
2655 {
2656 /* real or V86 mode */
2657 pCpu->mode = CPUMODE_16BIT;
2658 State.GCPtrSegBase = pCtx->cs * 16;
2659 State.GCPtrSegEnd = 0xFFFFFFFF;
2660 State.cbSegLimit = 0xFFFFFFFF;
2661 }
2662
2663 /*
2664 * Disassemble the instruction.
2665 */
2666 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2667 pCpu->apvUserData[0] = &State;
2668
2669 uint32_t cbInstr;
2670#ifndef LOG_ENABLED
2671 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2672 if (RT_SUCCESS(rc))
2673 {
2674#else
2675 char szOutput[160];
2676 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2677 if (RT_SUCCESS(rc))
2678 {
2679 /* log it */
2680 if (pszPrefix)
2681 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2682 else
2683 Log(("%s", szOutput));
2684#endif
2685 rc = VINF_SUCCESS;
2686 }
2687 else
2688 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2689
2690 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2691 if (State.fLocked)
2692 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2693
2694 return rc;
2695}
2696
2697#ifdef DEBUG
2698
2699/**
2700 * Disassemble an instruction and dump it to the log
2701 *
2702 * @returns VBox status code.
2703 * @param pVM VM Handle
2704 * @param pVCpu VMCPU Handle
2705 * @param pCtx CPU context
2706 * @param pc GC instruction pointer
2707 * @param pszPrefix String prefix for logging
2708 *
2709 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2710 */
2711VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2712{
2713 DISCPUSTATE Cpu;
2714 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2715}
2716
2717
2718/**
2719 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2720 *
2721 * @internal
2722 */
2723VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2724{
2725 /* @todo SMP support!! */
2726 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2727}
2728
2729#endif /* DEBUG */
2730
2731/**
2732 * API for controlling a few of the CPU features found in CR4.
2733 *
2734 * Currently only X86_CR4_TSD is accepted as input.
2735 *
2736 * @returns VBox status code.
2737 *
2738 * @param pVM The VM handle.
2739 * @param fOr The CR4 OR mask.
2740 * @param fAnd The CR4 AND mask.
2741 */
2742VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2743{
2744 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2745 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2746
2747 pVM->cpum.s.CR4.OrMask &= fAnd;
2748 pVM->cpum.s.CR4.OrMask |= fOr;
2749
2750 return VINF_SUCCESS;
2751}
2752
2753
2754/**
2755 * Gets a pointer to the array of standard CPUID leafs.
2756 *
2757 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2758 *
2759 * @returns Pointer to the standard CPUID leafs (read-only).
2760 * @param pVM The VM handle.
2761 * @remark Intended for PATM.
2762 */
2763VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2764{
2765 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2766}
2767
2768
2769/**
2770 * Gets a pointer to the array of extended CPUID leafs.
2771 *
2772 * CPUMGetGuestCpuIdExtMax() give the size of the array.
2773 *
2774 * @returns Pointer to the extended CPUID leafs (read-only).
2775 * @param pVM The VM handle.
2776 * @remark Intended for PATM.
2777 */
2778VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2779{
2780 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2781}
2782
2783
2784/**
2785 * Gets a pointer to the array of centaur CPUID leafs.
2786 *
2787 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2788 *
2789 * @returns Pointer to the centaur CPUID leafs (read-only).
2790 * @param pVM The VM handle.
2791 * @remark Intended for PATM.
2792 */
2793VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2794{
2795 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2796}
2797
2798
2799/**
2800 * Gets a pointer to the default CPUID leaf.
2801 *
2802 * @returns Pointer to the default CPUID leaf (read-only).
2803 * @param pVM The VM handle.
2804 * @remark Intended for PATM.
2805 */
2806VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2807{
2808 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2809}
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette