CPUM.cpp@ 24760

Last change on this file since 24760 was 24463, checked in by vboxsync, 15 years ago
CPUM: Enabled the last bit of live migration code.
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1	/* $Id: CPUM.cpp 24463 2009-11-06 16:22:42Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_cpum CPUM - CPU Monitor / Manager
23	*
24	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
25	* also responsible for lazy FPU handling and some of the context loading
26	* in raw mode.
27	*
28	* There are three CPU contexts, the most important one is the guest one (GC).
29	* When running in raw-mode (RC) there is a special hyper context for the VMM
30	* part that floats around inside the guest address space. When running in
31	* raw-mode, CPUM also maintains a host context for saving and restoring
32	* registers accross world switches. This latter is done in cooperation with the
33	* world switcher (@see pg_vmm).
34	*
35	* @see grp_cpum
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_CPUM
42	#include <VBox/cpum.h>
43	#include <VBox/cpumdis.h>
44	#include <VBox/pgm.h>
45	#include <VBox/pdm.h>
46	#include <VBox/mm.h>
47	#include <VBox/selm.h>
48	#include <VBox/dbgf.h>
49	#include <VBox/patm.h>
50	#include <VBox/hwaccm.h>
51	#include <VBox/ssm.h>
52	#include "CPUMInternal.h"
53	#include <VBox/vm.h>
54
55	#include <VBox/param.h>
56	#include <VBox/dis.h>
57	#include <VBox/err.h>
58	#include <VBox/log.h>
59	#include <iprt/assert.h>
60	#include <iprt/asm.h>
61	#include <iprt/string.h>
62	#include <iprt/mp.h>
63	#include <iprt/cpuset.h>
64
65
66	/*******************************************************************************
67	* Defined Constants And Macros *
68	*******************************************************************************/
69	/** The current saved state version. */
70	#define CPUM_SAVED_STATE_VERSION 11
71	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
72	* changes. */
73	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
74	/** The saved state version for the 2.1 trunk before the MSR changes. */
75	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
76	/** The saved state version of 2.0, used for backwards compatibility. */
77	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
78	/** The saved state version of 1.6, used for backwards compatability. */
79	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
80
81
82	/*******************************************************************************
83	* Structures and Typedefs *
84	*******************************************************************************/
85
86	/**
87	* What kind of cpu info dump to perform.
88	*/
89	typedef enum CPUMDUMPTYPE
90	{
91	CPUMDUMPTYPE_TERSE,
92	CPUMDUMPTYPE_DEFAULT,
93	CPUMDUMPTYPE_VERBOSE
94	} CPUMDUMPTYPE;
95	/** Pointer to a cpu info dump type. */
96	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
97
98
99	/*******************************************************************************
100	* Internal Functions *
101	*******************************************************************************/
102	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
103	static int cpumR3CpuIdInit(PVM pVM);
104	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
105	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
106	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
107	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113
114
115	/**
116	* Initializes the CPUM.
117	*
118	* @returns VBox status code.
119	* @param pVM The VM to operate on.
120	*/
121	VMMR3DECL(int) CPUMR3Init(PVM pVM)
122	{
123	LogFlow(("CPUMR3Init\n"));
124
125	/*
126	* Assert alignment and sizes.
127	*/
128	AssertCompileMemberAlignment(VM, cpum.s, 32);
129	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
130	AssertCompileSizeAlignment(CPUMCTX, 64);
131	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
132	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
133	AssertCompileMemberAlignment(VM, cpum, 64);
134	AssertCompileMemberAlignment(VM, aCpus, 64);
135	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
136	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
137
138	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
139	pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
140	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
141
142	/* Calculate the offset from CPUMCPU to CPUM. */
143	for (VMCPUID i = 0; i < pVM->cCpus; i++)
144	{
145	PVMCPU pVCpu = &pVM->aCpus[i];
146
147	/*
148	* Setup any fixed pointers and offsets.
149	*/
150	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
151	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
152
153	pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
154	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
155	}
156
157	/*
158	* Check that the CPU supports the minimum features we require.
159	*/
160	if (!ASMHasCpuId())
161	{
162	Log(("The CPU doesn't support CPUID!\n"));
163	return VERR_UNSUPPORTED_CPU;
164	}
165	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
166	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
167
168	/* Setup the CR4 AND and OR masks used in the switcher */
169	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
170	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
171	{
172	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
173	/* No FXSAVE implies no SSE */
174	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
175	pVM->cpum.s.CR4.OrMask = 0;
176	}
177	else
178	{
179	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
180	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
181	}
182
183	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
184	{
185	Log(("The CPU doesn't support MMX!\n"));
186	return VERR_UNSUPPORTED_CPU;
187	}
188	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
189	{
190	Log(("The CPU doesn't support TSC!\n"));
191	return VERR_UNSUPPORTED_CPU;
192	}
193	/* Bogus on AMD? */
194	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
195	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
196
197	/*
198	* Detech the host CPU vendor.
199	* (The guest CPU vendor is re-detected later on.)
200	*/
201	uint32_t uEAX, uEBX, uECX, uEDX;
202	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
203	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
204	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
205
206	/*
207	* Setup hypervisor startup values.
208	*/
209
210	/*
211	* Register saved state data item.
212	*/
213	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
214	NULL, cpumR3LiveExec, NULL,
215	NULL, cpumR3SaveExec, NULL,
216	NULL, cpumR3LoadExec, NULL);
217	if (RT_FAILURE(rc))
218	return rc;
219
220	/*
221	* Register info handlers.
222	*/
223	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
224	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
225	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
227	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
228	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
229
230	/*
231	* Initialize the Guest CPUID state.
232	*/
233	rc = cpumR3CpuIdInit(pVM);
234	if (RT_FAILURE(rc))
235	return rc;
236	CPUMR3Reset(pVM);
237	return VINF_SUCCESS;
238	}
239
240
241	/**
242	* Initializes the per-VCPU CPUM.
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
248	{
249	LogFlow(("CPUMR3InitCPU\n"));
250	return VINF_SUCCESS;
251	}
252
253
254	/**
255	* Detect the CPU vendor give n the
256	*
257	* @returns The vendor.
258	* @param uEAX EAX from CPUID(0).
259	* @param uEBX EBX from CPUID(0).
260	* @param uECX ECX from CPUID(0).
261	* @param uEDX EDX from CPUID(0).
262	*/
263	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
264	{
265	if ( uEAX >= 1
266	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
267	&& uECX == X86_CPUID_VENDOR_AMD_ECX
268	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
269	return CPUMCPUVENDOR_AMD;
270
271	if ( uEAX >= 1
272	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
273	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
274	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
275	return CPUMCPUVENDOR_INTEL;
276
277	/** @todo detect the other buggers... */
278	return CPUMCPUVENDOR_UNKNOWN;
279	}
280
281
282	/**
283	* Fetches overrides for a CPUID leaf.
284	*
285	* @returns VBox status code.
286	* @param pLeaf The leaf to load the overrides into.
287	* @param pCfgNode The CFGM node containing the overrides
288	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
289	* @param iLeaf The CPUID leaf number.
290	*/
291	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
292	{
293	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
294	if (pLeafNode)
295	{
296	uint32_t u32;
297	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
298	if (RT_SUCCESS(rc))
299	pLeaf->eax = u32;
300	else
301	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
302
303	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
304	if (RT_SUCCESS(rc))
305	pLeaf->ebx = u32;
306	else
307	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
308
309	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
310	if (RT_SUCCESS(rc))
311	pLeaf->ecx = u32;
312	else
313	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
314
315	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
316	if (RT_SUCCESS(rc))
317	pLeaf->edx = u32;
318	else
319	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
320
321	}
322	return VINF_SUCCESS;
323	}
324
325
326	/**
327	* Load the overrides for a set of CPUID leafs.
328	*
329	* @returns VBox status code.
330	* @param paLeafs The leaf array.
331	* @param cLeafs The number of leafs.
332	* @param uStart The start leaf number.
333	* @param pCfgNode The CFGM node containing the overrides
334	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
335	*/
336	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
337	{
338	for (uint32_t i = 0; i < cLeafs; i++)
339	{
340	int rc = cpumR3CpuIdFetchLeafOverride(&paLeafs[i], pCfgNode, uStart + i);
341	if (RT_FAILURE(rc))
342	return rc;
343	}
344
345	return VINF_SUCCESS;
346	}
347
348	/**
349	* Init a set of host CPUID leafs.
350	*
351	* @returns VBox status code.
352	* @param paLeafs The leaf array.
353	* @param cLeafs The number of leafs.
354	* @param uStart The start leaf number.
355	* @param pCfgNode The /CPUM/HostCPUID/ node.
356	*/
357	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
358	{
359	/* Using the ECX variant for all of them can't hurt... */
360	for (uint32_t i = 0; i < cLeafs; i++)
361	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeafs[i].eax, &paLeafs[i].ebx, &paLeafs[i].ecx, &paLeafs[i].edx);
362
363	/* Load CPUID leaf override; we currently don't care if the caller
364	specifies features the host CPU doesn't support. */
365	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeafs, cLeafs, pCfgNode);
366	}
367
368
369	/**
370	* Initializes the emulated CPU's cpuid information.
371	*
372	* @returns VBox status code.
373	* @param pVM The VM to operate on.
374	*/
375	static int cpumR3CpuIdInit(PVM pVM)
376	{
377	PCPUM pCPUM = &pVM->cpum.s;
378	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
379	uint32_t i;
380	int rc;
381
382	/*
383	* Get the host CPUIDs and redetect the guest CPU vendor (could've been overridden).
384	*/
385	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
386	* Overrides the host CPUID leaf values used for calculating the guest CPUID
387	* leafs. This can be used to preserve the CPUID values when moving a VM to
388	* a different machine. Another use is restricting (or extending) the
389	* feature set exposed to the guest. */
390	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
391	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
392	AssertRCReturn(rc, rc);
393	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
394	AssertRCReturn(rc, rc);
395	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
396	AssertRCReturn(rc, rc);
397
398	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
399	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
400
401	/*
402	* Only report features we can support.
403	*/
404	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
405	\| X86_CPUID_FEATURE_EDX_VME
406	\| X86_CPUID_FEATURE_EDX_DE
407	\| X86_CPUID_FEATURE_EDX_PSE
408	\| X86_CPUID_FEATURE_EDX_TSC
409	\| X86_CPUID_FEATURE_EDX_MSR
410	//\| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
411	\| X86_CPUID_FEATURE_EDX_MCE
412	\| X86_CPUID_FEATURE_EDX_CX8
413	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
414	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
415	//\| X86_CPUID_FEATURE_EDX_SEP
416	\| X86_CPUID_FEATURE_EDX_MTRR
417	\| X86_CPUID_FEATURE_EDX_PGE
418	\| X86_CPUID_FEATURE_EDX_MCA
419	\| X86_CPUID_FEATURE_EDX_CMOV
420	\| X86_CPUID_FEATURE_EDX_PAT
421	\| X86_CPUID_FEATURE_EDX_PSE36
422	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
423	\| X86_CPUID_FEATURE_EDX_CLFSH
424	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
425	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
426	\| X86_CPUID_FEATURE_EDX_MMX
427	\| X86_CPUID_FEATURE_EDX_FXSR
428	\| X86_CPUID_FEATURE_EDX_SSE
429	\| X86_CPUID_FEATURE_EDX_SSE2
430	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
431	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
432	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
433	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
434	\| 0;
435	pCPUM->aGuestCpuIdStd[1].ecx &= 0
436	\| X86_CPUID_FEATURE_ECX_SSE3
437	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
438	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
439	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
440	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
441	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
442	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
443	//\| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
444	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
445	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
446	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
447	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
448	/* ECX Bit 21 - x2APIC support - not yet. */
449	// \| X86_CPUID_FEATURE_ECX_X2APIC
450	/* ECX Bit 23 - POPCNT instruction. */
451	//\| X86_CPUID_FEATURE_ECX_POPCNT
452	\| 0;
453
454	/* ASSUMES that this is ALWAYS the AMD define feature set if present. */
455	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
456	\| X86_CPUID_AMD_FEATURE_EDX_VME
457	\| X86_CPUID_AMD_FEATURE_EDX_DE
458	\| X86_CPUID_AMD_FEATURE_EDX_PSE
459	\| X86_CPUID_AMD_FEATURE_EDX_TSC
460	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
461	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
462	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
463	\| X86_CPUID_AMD_FEATURE_EDX_CX8
464	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
465	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
466	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
467	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
468	\| X86_CPUID_AMD_FEATURE_EDX_PGE
469	\| X86_CPUID_AMD_FEATURE_EDX_MCA
470	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
471	\| X86_CPUID_AMD_FEATURE_EDX_PAT
472	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
473	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
474	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
475	\| X86_CPUID_AMD_FEATURE_EDX_MMX
476	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
477	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
478	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
479	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
480	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
481	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
482	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
483	\| 0;
484	pCPUM->aGuestCpuIdExt[1].ecx &= 0
485	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
486	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
487	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
488	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
489	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
490	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
491	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
492	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
493	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
494	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
495	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
496	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
497	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
498	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
499	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
500	\| 0;
501
502	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false); AssertRCReturn(rc, rc);
503	if (pCPUM->fSyntheticCpu)
504	{
505	const char szVendor[13] = "VirtualBox ";
506	const char szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
507
508	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
509
510	/* Limit the nr of standard leaves; 5 for monitor/mwait */
511	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
512
513	/* 0: Vendor */
514	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)szVendor)[0];
515	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)szVendor)[2];
516	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)szVendor)[1];
517
518	/* 1.eax: Version information. family : model : stepping */
519	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
520
521	/* Leaves 2 - 4 are Intel only - zero them out */
522	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
523	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
524	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
525
526	/* Leaf 5 = monitor/mwait */
527
528	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
529	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
530	/* AMD only - set to zero. */
531	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
532
533	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
534	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
535
536	/* 0x800000002-4: Processor Name String Identifier. */
537	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)szProcessor)[0];
538	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)szProcessor)[1];
539	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)szProcessor)[2];
540	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)szProcessor)[3];
541	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)szProcessor)[4];
542	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)szProcessor)[5];
543	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)szProcessor)[6];
544	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)szProcessor)[7];
545	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)szProcessor)[8];
546	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)szProcessor)[9];
547	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)szProcessor)[10];
548	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)szProcessor)[11];
549
550	/* 0x800000005-7 - reserved -> zero */
551	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
552	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
553	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
554
555	/* 0x800000008: only the max virtual and physical address size. */
556	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
557	}
558
559	/*
560	* Hide HTT, multicode, SMP, whatever.
561	* (APIC-ID := 0 and #LogCpus := 0)
562	*/
563	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
564	#ifdef VBOX_WITH_MULTI_CORE
565	if ( pVM->cCpus > 1
566	&& pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC)
567	{
568	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
569	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
570	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
571	}
572	#endif
573
574	/* Cpuid 2:
575	* Intel: Cache and TLB information
576	* AMD: Reserved
577	* Safe to expose
578	*/
579
580	/* Cpuid 3:
581	* Intel: EAX, EBX - reserved
582	* ECX, EDX - Processor Serial Number if available, otherwise reserved
583	* AMD: Reserved
584	* Safe to expose
585	*/
586	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
587	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
588
589	/* Cpuid 4:
590	* Intel: Deterministic Cache Parameters Leaf
591	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
592	* AMD: Reserved
593	* Safe to expose, except for EAX:
594	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
595	* Bits 31-26: Maximum number of processor cores in this physical package**
596	* Note: These SMP values are constant regardless of ECX
597	*/
598	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
599	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
600	#ifdef VBOX_WITH_MULTI_CORE
601	if ( pVM->cCpus > 1
602	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
603	{
604	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
605	/* One logical processor with possibly multiple cores. */
606	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
607	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
608	}
609	#endif
610
611	/* Cpuid 5: Monitor/mwait Leaf
612	* Intel: ECX, EDX - reserved
613	* EAX, EBX - Smallest and largest monitor line size
614	* AMD: EDX - reserved
615	* EAX, EBX - Smallest and largest monitor line size
616	* ECX - extensions (ignored for now)
617	* Safe to expose
618	*/
619	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
620	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
621
622	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
623
624	/*
625	* Determine the default.
626	*
627	* Intel returns values of the highest standard function, while AMD
628	* returns zeros. VIA on the other hand seems to returning nothing or
629	* perhaps some random garbage, we don't try to duplicate this behavior.
630	*/
631	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
632	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
633	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
634
635	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
636	* Safe to pass on to the guest.
637	*
638	* Intel: 0x800000005 reserved
639	* 0x800000006 L2 cache information
640	* AMD: 0x800000005 L1 cache information
641	* 0x800000006 L2/L3 cache information
642	*/
643
644	/* Cpuid 0x800000007:
645	* AMD: EAX, EBX, ECX - reserved
646	* EDX: Advanced Power Management Information
647	* Intel: Reserved
648	*/
649	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
650	{
651	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
652
653	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
654
655	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
656	{
657	/* Only expose the TSC invariant capability bit to the guest. */
658	pCPUM->aGuestCpuIdExt[7].edx &= 0
659	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
660	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
661	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
662	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
663	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
664	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
665	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
666	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
667	#if 1
668	/* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
669	* that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
670	*/
671	#else
672	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
673	#endif
674	\| 0;
675	}
676	else
677	pCPUM->aGuestCpuIdExt[7].edx = 0;
678	}
679
680	/* Cpuid 0x800000008:
681	* AMD: EBX, EDX - reserved
682	* EAX: Virtual/Physical address Size
683	* ECX: Number of cores + APICIdCoreIdSize
684	* Intel: EAX: Virtual/Physical address Size
685	* EBX, ECX, EDX - reserved
686	*/
687	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
688	{
689	/* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
690	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
691	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
692	* NC (0-7) Number of cores; 0 equals 1 core */
693	pCPUM->aGuestCpuIdExt[8].ecx = 0;
694	#ifdef VBOX_WITH_MULTI_CORE
695	if ( pVM->cCpus > 1
696	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
697	{
698	/* Legacy method to determine the number of cores. */
699	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
700	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
701
702	}
703	#endif
704	}
705
706	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
707	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
708	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
709	* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
710	*/
711	bool fNt4LeafLimit;
712	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
713	if (fNt4LeafLimit)
714	pCPUM->aGuestCpuIdStd[0].eax = 3;
715
716	/*
717	* Limit it the number of entries and fill the remaining with the defaults.
718	*
719	* The limits are masking off stuff about power saving and similar, this
720	* is perhaps a bit crudely done as there is probably some relatively harmless
721	* info too in these leaves (like words about having a constant TSC).
722	*/
723	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
724	pCPUM->aGuestCpuIdStd[0].eax = 5;
725
726	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
727	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
728
729	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
730	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
731	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
732	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
733	: 0;
734	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
735	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
736
737	/*
738	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
739	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
740	* of processors from (cpuid(4).eax >> 26) + 1.
741	*/
742	if (pVM->cCpus == 1)
743	pCPUM->aGuestCpuIdStd[4].eax = 0;
744
745	/*
746	* Centaur stuff (VIA).
747	*
748	* The important part here (we think) is to make sure the 0xc0000000
749	* function returns 0xc0000001. As for the features, we don't currently
750	* let on about any of those... 0xc0000002 seems to be some
751	* temperature/hz/++ stuff, include it as well (static).
752	*/
753	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
754	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
755	{
756	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
757	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
758	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
759	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
760	i++)
761	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
762	}
763	else
764	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
765	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
766
767
768	/*
769	* Load CPUID overrides from configuration.
770	* Note: Kind of redundant now, but allows unchanged overrides
771	*/
772	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
773	* Overrides the CPUID leaf values. */
774	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
775	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
776	AssertRCReturn(rc, rc);
777	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
778	AssertRCReturn(rc, rc);
779	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
780	AssertRCReturn(rc, rc);
781
782	/*
783	* Check if PAE was explicitely enabled by the user.
784	*/
785	bool fEnable;
786	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
787	if (fEnable)
788	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
789
790	/*
791	* Log the cpuid and we're good.
792	*/
793	RTCPUSET OnlineSet;
794	LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
795	(int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
796	LogRel(("*********************** CPUID dump **********************\n"));
797	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
798	LogRel(("\n"));
799	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
800	LogRel(("****************** End of CPUID dump ********************\n"));
801	return VINF_SUCCESS;
802	}
803
804
805
806
807	/**
808	* Applies relocations to data and code managed by this
809	* component. This function will be called at init and
810	* whenever the VMM need to relocate it self inside the GC.
811	*
812	* The CPUM will update the addresses used by the switcher.
813	*
814	* @param pVM The VM.
815	*/
816	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
817	{
818	LogFlow(("CPUMR3Relocate\n"));
819	for (VMCPUID i = 0; i < pVM->cCpus; i++)
820	{
821	/*
822	* Switcher pointers.
823	*/
824	PVMCPU pVCpu = &pVM->aCpus[i];
825	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
826	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
827	}
828	}
829
830
831	/**
832	* Terminates the CPUM.
833	*
834	* Termination means cleaning up and freeing all resources,
835	* the VM it self is at this point powered off or suspended.
836	*
837	* @returns VBox status code.
838	* @param pVM The VM to operate on.
839	*/
840	VMMR3DECL(int) CPUMR3Term(PVM pVM)
841	{
842	CPUMR3TermCPU(pVM);
843	return 0;
844	}
845
846
847	/**
848	* Terminates the per-VCPU CPUM.
849	*
850	* Termination means cleaning up and freeing all resources,
851	* the VM it self is at this point powered off or suspended.
852	*
853	* @returns VBox status code.
854	* @param pVM The VM to operate on.
855	*/
856	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
857	{
858	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
859	for (VMCPUID i = 0; i < pVM->cCpus; i++)
860	{
861	PVMCPU pVCpu = &pVM->aCpus[i];
862	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
863
864	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
865	pVCpu->cpum.s.uMagic = 0;
866	pCtx->dr[5] = 0;
867	}
868	#endif
869	return 0;
870	}
871
872	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
873	{
874	/* @todo anything different for VCPU > 0? */
875	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
876
877	/*
878	* Initialize everything to ZERO first.
879	*/
880	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
881	memset(pCtx, 0, sizeof(*pCtx));
882	pVCpu->cpum.s.fUseFlags = fUseFlags;
883
884	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
885	pCtx->eip = 0x0000fff0;
886	pCtx->edx = 0x00000600; /* P6 processor */
887	pCtx->eflags.Bits.u1Reserved0 = 1;
888
889	pCtx->cs = 0xf000;
890	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
891	pCtx->csHid.u32Limit = 0x0000ffff;
892	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
893	pCtx->csHid.Attr.n.u1Present = 1;
894	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
895
896	pCtx->dsHid.u32Limit = 0x0000ffff;
897	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
898	pCtx->dsHid.Attr.n.u1Present = 1;
899	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
900
901	pCtx->esHid.u32Limit = 0x0000ffff;
902	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
903	pCtx->esHid.Attr.n.u1Present = 1;
904	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
905
906	pCtx->fsHid.u32Limit = 0x0000ffff;
907	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
908	pCtx->fsHid.Attr.n.u1Present = 1;
909	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
910
911	pCtx->gsHid.u32Limit = 0x0000ffff;
912	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
913	pCtx->gsHid.Attr.n.u1Present = 1;
914	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
915
916	pCtx->ssHid.u32Limit = 0x0000ffff;
917	pCtx->ssHid.Attr.n.u1Present = 1;
918	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
919	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
920
921	pCtx->idtr.cbIdt = 0xffff;
922	pCtx->gdtr.cbGdt = 0xffff;
923
924	pCtx->ldtrHid.u32Limit = 0xffff;
925	pCtx->ldtrHid.Attr.n.u1Present = 1;
926	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
927
928	pCtx->trHid.u32Limit = 0xffff;
929	pCtx->trHid.Attr.n.u1Present = 1;
930	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
931
932	pCtx->dr[6] = X86_DR6_INIT_VAL;
933	pCtx->dr[7] = X86_DR7_INIT_VAL;
934
935	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
936	pCtx->fpu.FCW = 0x37f;
937
938	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
939	pCtx->fpu.MXCSR = 0x1F80;
940
941	/* Init PAT MSR */
942	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
943
944	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
945	* The Intel docs don't mention it.
946	*/
947	pCtx->msrEFER = 0;
948	}
949
950	/**
951	* Resets the CPU.
952	*
953	* @returns VINF_SUCCESS.
954	* @param pVM The VM handle.
955	*/
956	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
957	{
958	for (VMCPUID i = 0; i < pVM->cCpus; i++)
959	{
960	CPUMR3ResetCpu(&pVM->aCpus[i]);
961
962	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
963	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
964
965	/* Magic marker for searching in crash dumps. */
966	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
967	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
968	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
969	#endif
970	}
971	}
972
973
974	/**
975	* Called both in pass 0 and the final pass.
976	*
977	* @param pVM The VM handle.
978	* @param pSSM The saved state handle.
979	*/
980	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
981	{
982	/*
983	* Save all the CPU ID leaves here so we can check them for compatability
984	* upon loading.
985	*/
986	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
987	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
988
989	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
990	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
991
992	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
993	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
994
995	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
996
997	/*
998	* Save a good portion of the raw CPU IDs as well as they may come in
999	* handy when validating features for raw mode.
1000	*/
1001	CPUMCPUID aRawStd[16];
1002	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1003	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1004	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1005	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1006
1007	CPUMCPUID aRawExt[32];
1008	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1009	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1010	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1011	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1012	}
1013
1014
1015	/**
1016	* Loads the CPU ID leaves saved by pass 0.
1017	*
1018	* @returns VBox status code.
1019	* @param pVM The VM handle.
1020	* @param pSSM The saved state handle.
1021	* @param uVersion The format version.
1022	*/
1023	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1024	{
1025	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1026
1027	/*
1028	* Define a bunch of macros for simplifying the code.
1029	*/
1030	/* Generic expression + failure message. */
1031	#define CPUID_CHECK_RET(expr, fmt) \
1032	do { \
1033	if (!(expr)) \
1034	{ \
1035	char pszMsg = RTStrAPrintf2 fmt; / lack of variadict macros sucks */ \
1036	if (fStrictCpuIdChecks) \
1037	{ \
1038	int rc = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1039	RTStrFree(pszMsg); \
1040	return rc; \
1041	} \
1042	LogRel(("CPUM: %s\n", pszMsg)); \
1043	RTStrFree(pszMsg); \
1044	} \
1045	} while (0)
1046	#define CPUID_CHECK_WRN(expr, fmt) \
1047	do { \
1048	if (!(expr)) \
1049	LogRel(fmt); \
1050	} while (0)
1051
1052	/* For comparing two values and bitch if they differs. */
1053	#define CPUID_CHECK2_RET(what, host, saved) \
1054	do { \
1055	if ((host) != (saved)) \
1056	{ \
1057	if (fStrictCpuIdChecks) \
1058	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1059	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1060	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1061	} \
1062	} while (0)
1063	#define CPUID_CHECK2_WRN(what, host, saved) \
1064	do { \
1065	if ((host) != (saved)) \
1066	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1067	} while (0)
1068
1069	/* For checking raw cpu features (raw mode). */
1070	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1071	do { \
1072	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1073	{ \
1074	if (fStrictCpuIdChecks) \
1075	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1076	N_(#bit " mismatch: host=%d saved=%d"), \
1077	aHostRaw##set [1].reg & (bit), aRaw##set [1].reg & (bit) ); \
1078	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1079	aHostRaw##set [1].reg & (bit), aRaw##set [1].reg & (bit) )); \
1080	} \
1081	} while (0)
1082	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1083	do { \
1084	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1085	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1086	aHostRaw##set [1].reg & (bit), aRaw##set [1].reg & (bit) )); \
1087	} while (0)
1088	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1089
1090	/* For checking guest features. */
1091	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1092	do { \
1093	if ( (aGuestCpuId##set [1].reg & bit) \
1094	&& !(aHostRaw##set [1].reg & bit) \
1095	&& !(aHostOverride##set [1].reg & bit) \
1096	&& !(aGuestOverride##set [1].reg & bit) \
1097	) \
1098	{ \
1099	if (fStrictCpuIdChecks) \
1100	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1101	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1102	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1103	} \
1104	} while (0)
1105	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1106	do { \
1107	if ( (aGuestCpuId##set [1].reg & bit) \
1108	&& !(aHostRaw##set [1].reg & bit) \
1109	&& !(aHostOverride##set [1].reg & bit) \
1110	&& !(aGuestOverride##set [1].reg & bit) \
1111	) \
1112	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1113	} while (0)
1114	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1115	do { \
1116	if ( (aGuestCpuId##set [1].reg & bit) \
1117	&& !(aHostRaw##set [1].reg & bit) \
1118	&& !(aHostOverride##set [1].reg & bit) \
1119	&& !(aGuestOverride##set [1].reg & bit) \
1120	) \
1121	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1122	} while (0)
1123	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1124
1125	/* For checking guest features if AMD guest CPU. */
1126	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1127	do { \
1128	if ( (aGuestCpuId##set [1].reg & bit) \
1129	&& fGuestAmd \
1130	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1131	&& !(aHostOverride##set [1].reg & bit) \
1132	&& !(aGuestOverride##set [1].reg & bit) \
1133	) \
1134	{ \
1135	if (fStrictCpuIdChecks) \
1136	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1137	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1138	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1139	} \
1140	} while (0)
1141	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1142	do { \
1143	if ( (aGuestCpuId##set [1].reg & bit) \
1144	&& fGuestAmd \
1145	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1146	&& !(aHostOverride##set [1].reg & bit) \
1147	&& !(aGuestOverride##set [1].reg & bit) \
1148	) \
1149	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1150	} while (0)
1151	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1152	do { \
1153	if ( (aGuestCpuId##set [1].reg & bit) \
1154	&& fGuestAmd \
1155	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1156	&& !(aHostOverride##set [1].reg & bit) \
1157	&& !(aGuestOverride##set [1].reg & bit) \
1158	) \
1159	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1160	} while (0)
1161	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1162
1163	/* For checking AMD features which have a corresponding bit in the standard
1164	range. (Intel defines very few bits in the extended feature sets.) */
1165	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1166	do { \
1167	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1168	&& !(fHostAmd \
1169	? aHostRawExt[1].reg & (ExtBit) \
1170	: aHostRawStd[1].reg & (StdBit)) \
1171	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1172	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1173	) \
1174	{ \
1175	if (fStrictCpuIdChecks) \
1176	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1177	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1178	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1179	} \
1180	} while (0)
1181	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1182	do { \
1183	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1184	&& !(fHostAmd \
1185	? aHostRawExt[1].reg & (ExtBit) \
1186	: aHostRawStd[1].reg & (StdBit)) \
1187	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1188	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1189	) \
1190	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1191	} while (0)
1192	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1193	do { \
1194	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1195	&& !(fHostAmd \
1196	? aHostRawExt[1].reg & (ExtBit) \
1197	: aHostRawStd[1].reg & (StdBit)) \
1198	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1199	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1200	) \
1201	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1202	} while (0)
1203	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1204
1205	/*
1206	* Load them into stack buffers first.
1207	*/
1208	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1209	uint32_t cGuestCpuIdStd;
1210	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1211	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1212	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1213	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1214
1215	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1216	uint32_t cGuestCpuIdExt;
1217	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1218	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1219	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1220	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1221
1222	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1223	uint32_t cGuestCpuIdCentaur;
1224	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1225	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1226	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1227	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1228
1229	CPUMCPUID GuestCpuIdDef;
1230	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1231	AssertRCReturn(rc, rc);
1232
1233	CPUMCPUID aRawStd[16];
1234	uint32_t cRawStd;
1235	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1236	if (cRawStd > RT_ELEMENTS(aRawStd))
1237	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1238	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1239
1240	CPUMCPUID aRawExt[32];
1241	uint32_t cRawExt;
1242	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1243	if (cRawExt > RT_ELEMENTS(aRawExt))
1244	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1245	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1246	AssertRCReturn(rc, rc);
1247
1248	/*
1249	* Note that we support restoring less than the current amount of standard
1250	* leaves because we've been allowed more is newer version of VBox.
1251	*
1252	* So, pad new entries with the default.
1253	*/
1254	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1255	aGuestCpuIdStd[i] = GuestCpuIdDef;
1256
1257	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1258	aGuestCpuIdExt[i] = GuestCpuIdDef;
1259
1260	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1261	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1262
1263	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1264	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1265
1266	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1267	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1268
1269	/*
1270	* Get the raw CPU IDs for the current host.
1271	*/
1272	CPUMCPUID aHostRawStd[16];
1273	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1274	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1275
1276	CPUMCPUID aHostRawExt[32];
1277	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1278	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1279
1280	/*
1281	* Get the host and guest overrides so we don't reject the state because
1282	* some feature was enabled thru these interfaces.
1283	* Note! We currently only need the feature leafs, so skip rest.
1284	*/
1285	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1286	CPUMCPUID aGuestOverrideStd[2];
1287	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1288	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1289
1290	CPUMCPUID aGuestOverrideExt[2];
1291	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1292	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1293
1294	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1295	CPUMCPUID aHostOverrideStd[2];
1296	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1297	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1298
1299	CPUMCPUID aHostOverrideExt[2];
1300	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1301	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1302
1303	/*
1304	* This can be skipped.
1305	*/
1306	bool fStrictCpuIdChecks;
1307	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, false);
1308
1309
1310
1311	/*
1312	* For raw-mode we'll require that the CPUs are very similar since we don't
1313	* intercept CPUID instructions for user mode applications.
1314	*/
1315	if (!HWACCMIsEnabled(pVM))
1316	{
1317	/* CPUID(0) */
1318	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1319	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1320	&& aHostRawStd[0].edx == aRawStd[0].edx,
1321	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1322	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1323	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1324	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1325	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1326	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1327
1328	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1329
1330	/* CPUID(1).eax */
1331	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1332	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1333	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1334
1335	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1336	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1337	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1338
1339	/* CPUID(1).ecx */
1340	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1341	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1342	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1343	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1344	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1345	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1346	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1347	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1348	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1349	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1350	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1351	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1352	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1353	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1354	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1355	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1356	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1357	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1358	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1359	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1360	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1361	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1362	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1363	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1364	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1365	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1366	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1367	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1368	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1369	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1370	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1371	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1372
1373	/* CPUID(1).edx */
1374	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1375	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1376	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1377	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1378	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1379	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1380	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1381	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1382	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1383	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1384	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1385	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1386	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1387	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1388	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1389	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1390	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1391	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1392	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1393	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1394	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1395	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1396	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1397	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1398	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1399	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1400	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1401	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1402	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1403	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1404	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1405	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1406
1407	/* CPUID(2) - config, mostly about caches. ignore. */
1408	/* CPUID(3) - processor serial number. ignore. */
1409	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1410	/* CPUID(5) - mwait/monitor config. ignore. */
1411	/* CPUID(6) - power management. ignore. */
1412	/* CPUID(7) - ???. ignore. */
1413	/* CPUID(8) - ???. ignore. */
1414	/* CPUID(9) - DCA. ignore for now. */
1415	/* CPUID(a) - PeMo info. ignore for now. */
1416	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1417
1418	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1419	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1420	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1421	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1422	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1423	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1424	{
1425	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1426	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1427	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1428	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1429	}
1430
1431	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1432	Note! Intel have/is marking many of the fields here as reserved. We
1433	will verify them as if it's an AMD CPU. */
1434	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1435	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1436	(N_("Extended leafs was present on saved state host, but is missing on the current\n")));
1437	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1438	{
1439	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1440	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1441	&& aHostRawExt[0].edx == aRawExt[0].edx,
1442	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1443	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1444	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1445	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1446
1447	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1448	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1449	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1450	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1451	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1452	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1453
1454	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1455	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1456	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1457	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1458
1459	/* CPUID(0x80000001).ecx */
1460	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1461	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1462	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1463	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1464	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1465	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1466	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1467	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1468	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1469	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1470	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1471	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1472	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1473	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1474	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1475	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1476	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1477	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1478	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1479	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1480	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1481	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1482	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1483	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1484	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1485	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1486	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1487	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1488	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1489	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1490	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1491	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1492
1493	/* CPUID(0x80000001).edx */
1494	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1495	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1496	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1497	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1498	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1499	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1500	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1501	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1502	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1503	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1504	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1505	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1506	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1507	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1508	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1509	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1510	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1511	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1512	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1513	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1514	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1515	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1516	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1517	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1518	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1519	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1520	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1521	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1522	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1523	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1524	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1525	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1526
1527	/** @todo verify the rest as well. */
1528	}
1529	}
1530
1531
1532
1533	/*
1534	* Verify that we can support the features already exposed to the guest on
1535	* this host.
1536	*
1537	* Most of the features we're emulating requires intercepting instruction
1538	* and doing it the slow way, so there is no need to warn when they aren't
1539	* present in the host CPU. Thus we use IGN instead of EMU on these.
1540	*
1541	* Trailing comments:
1542	* "EMU" - Possible to emulate, could be lots of work and very slow.
1543	* "EMU?" - Can this be emulated?
1544	*/
1545	/* CPUID(1).ecx */
1546	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1547	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1548	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1549	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1550	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1551	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1552	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1553	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1554	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1555	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1556	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1557	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1558	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1559	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1560	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1561	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1562	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1563	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1564	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1565	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1566	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1567	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1568	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1569	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1570	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1571	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1572	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1573	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1574	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1575	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1576	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1577	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1578
1579	/* CPUID(1).edx */
1580	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1581	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1582	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1583	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1584	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1585	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1586	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1587	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1588	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1589	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1590	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1591	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1592	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1593	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1594	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1595	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1596	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1597	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1598	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1599	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1600	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1601	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1602	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1603	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1604	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1605	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1606	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1607	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1608	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1609	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1610	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1611	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1612
1613	/* CPUID(0x80000000). */
1614	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1615	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1616	{
1617	/** @todo deal with no 0x80000001 on the host. */
1618	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1619	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1620
1621	/* CPUID(0x80000001).ecx */
1622	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1623	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1624	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1625	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1626	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1627	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1628	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1629	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1630	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1631	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1632	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1633	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1634	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1635	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1636	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1637	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1638	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1639	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1640	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1641	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1642	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1643	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1644	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1645	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1646	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1647	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1648	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1649	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1650	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1651	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1652	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1653	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1654
1655	/* CPUID(0x80000001).edx */
1656	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1657	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1658	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1659	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1660	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1661	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1662	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1663	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1664	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1665	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1666	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1667	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1668	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1669	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1670	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1671	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1672	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1673	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1674	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1675	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1676	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1677	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1678	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1679	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1680	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1681	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1682	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1683	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1684	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1685	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1686	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1687	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1688	}
1689
1690	/*
1691	* We're good, commit the CPU ID leaves.
1692	*/
1693	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1694	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1695	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1696	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1697
1698	#undef CPUID_CHECK_RET
1699	#undef CPUID_CHECK_WRN
1700	#undef CPUID_CHECK2_RET
1701	#undef CPUID_CHECK2_WRN
1702	#undef CPUID_RAW_FEATURE_RET
1703	#undef CPUID_RAW_FEATURE_WRN
1704	#undef CPUID_RAW_FEATURE_IGN
1705	#undef CPUID_GST_FEATURE_RET
1706	#undef CPUID_GST_FEATURE_WRN
1707	#undef CPUID_GST_FEATURE_EMU
1708	#undef CPUID_GST_FEATURE_IGN
1709	#undef CPUID_GST_FEATURE2_RET
1710	#undef CPUID_GST_FEATURE2_WRN
1711	#undef CPUID_GST_FEATURE2_EMU
1712	#undef CPUID_GST_FEATURE2_IGN
1713	#undef CPUID_GST_AMD_FEATURE_RET
1714	#undef CPUID_GST_AMD_FEATURE_WRN
1715	#undef CPUID_GST_AMD_FEATURE_EMU
1716	#undef CPUID_GST_AMD_FEATURE_IGN
1717
1718	return VINF_SUCCESS;
1719	}
1720
1721
1722	/**
1723	* Pass 0 live exec callback.
1724	*
1725	* @returns VINF_SSM_DONT_CALL_AGAIN.
1726	* @param pVM The VM handle.
1727	* @param pSSM The saved state handle.
1728	* @param uPass The pass (0).
1729	*/
1730	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1731	{
1732	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1733	cpumR3SaveCpuId(pVM, pSSM);
1734	return VINF_SSM_DONT_CALL_AGAIN;
1735	}
1736
1737
1738	/**
1739	* Execute state save operation.
1740	*
1741	* @returns VBox status code.
1742	* @param pVM VM Handle.
1743	* @param pSSM SSM operation handle.
1744	*/
1745	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1746	{
1747	/*
1748	* Save.
1749	*/
1750	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1751	{
1752	PVMCPU pVCpu = &pVM->aCpus[i];
1753
1754	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1755	}
1756
1757	SSMR3PutU32(pSSM, pVM->cCpus);
1758	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1759	{
1760	PVMCPU pVCpu = &pVM->aCpus[i];
1761
1762	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1763	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1764	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1765	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1766	}
1767
1768	cpumR3SaveCpuId(pVM, pSSM);
1769	return VINF_SUCCESS;
1770	}
1771
1772
1773	/**
1774	* Load a version 1.6 CPUMCTX structure.
1775	*
1776	* @returns VBox status code.
1777	* @param pVM VM Handle.
1778	* @param pCpumctx16 Version 1.6 CPUMCTX
1779	*/
1780	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1781	{
1782	#define CPUMCTX16_LOADREG(RegName) \
1783	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1784
1785	#define CPUMCTX16_LOADDRXREG(RegName) \
1786	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1787
1788	#define CPUMCTX16_LOADHIDREG(RegName) \
1789	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1790	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1791	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1792
1793	#define CPUMCTX16_LOADSEGREG(RegName) \
1794	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1795	CPUMCTX16_LOADHIDREG(RegName);
1796
1797	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1798
1799	CPUMCTX16_LOADREG(rax);
1800	CPUMCTX16_LOADREG(rbx);
1801	CPUMCTX16_LOADREG(rcx);
1802	CPUMCTX16_LOADREG(rdx);
1803	CPUMCTX16_LOADREG(rdi);
1804	CPUMCTX16_LOADREG(rsi);
1805	CPUMCTX16_LOADREG(rbp);
1806	CPUMCTX16_LOADREG(esp);
1807	CPUMCTX16_LOADREG(rip);
1808	CPUMCTX16_LOADREG(rflags);
1809
1810	CPUMCTX16_LOADSEGREG(cs);
1811	CPUMCTX16_LOADSEGREG(ds);
1812	CPUMCTX16_LOADSEGREG(es);
1813	CPUMCTX16_LOADSEGREG(fs);
1814	CPUMCTX16_LOADSEGREG(gs);
1815	CPUMCTX16_LOADSEGREG(ss);
1816
1817	CPUMCTX16_LOADREG(r8);
1818	CPUMCTX16_LOADREG(r9);
1819	CPUMCTX16_LOADREG(r10);
1820	CPUMCTX16_LOADREG(r11);
1821	CPUMCTX16_LOADREG(r12);
1822	CPUMCTX16_LOADREG(r13);
1823	CPUMCTX16_LOADREG(r14);
1824	CPUMCTX16_LOADREG(r15);
1825
1826	CPUMCTX16_LOADREG(cr0);
1827	CPUMCTX16_LOADREG(cr2);
1828	CPUMCTX16_LOADREG(cr3);
1829	CPUMCTX16_LOADREG(cr4);
1830
1831	CPUMCTX16_LOADDRXREG(0);
1832	CPUMCTX16_LOADDRXREG(1);
1833	CPUMCTX16_LOADDRXREG(2);
1834	CPUMCTX16_LOADDRXREG(3);
1835	CPUMCTX16_LOADDRXREG(4);
1836	CPUMCTX16_LOADDRXREG(5);
1837	CPUMCTX16_LOADDRXREG(6);
1838	CPUMCTX16_LOADDRXREG(7);
1839
1840	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
1841	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
1842	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
1843	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
1844
1845	CPUMCTX16_LOADREG(ldtr);
1846	CPUMCTX16_LOADREG(tr);
1847
1848	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
1849
1850	CPUMCTX16_LOADREG(msrEFER);
1851	CPUMCTX16_LOADREG(msrSTAR);
1852	CPUMCTX16_LOADREG(msrPAT);
1853	CPUMCTX16_LOADREG(msrLSTAR);
1854	CPUMCTX16_LOADREG(msrCSTAR);
1855	CPUMCTX16_LOADREG(msrSFMASK);
1856	CPUMCTX16_LOADREG(msrKERNELGSBASE);
1857
1858	CPUMCTX16_LOADHIDREG(ldtr);
1859	CPUMCTX16_LOADHIDREG(tr);
1860
1861	#undef CPUMCTX16_LOADSEGREG
1862	#undef CPUMCTX16_LOADHIDREG
1863	#undef CPUMCTX16_LOADDRXREG
1864	#undef CPUMCTX16_LOADREG
1865	}
1866
1867
1868	/**
1869	* Execute state load operation.
1870	*
1871	* @returns VBox status code.
1872	* @param pVM VM Handle.
1873	* @param pSSM SSM operation handle.
1874	* @param uVersion Data layout version.
1875	* @param uPass The data pass.
1876	*/
1877	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1878	{
1879	/*
1880	* Validate version.
1881	*/
1882	if ( uVersion != CPUM_SAVED_STATE_VERSION
1883	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1884	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1885	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1886	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1887	{
1888	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1889	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1890	}
1891
1892	if (uPass == SSM_PASS_FINAL)
1893	{
1894	/*
1895	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1896	* really old SSM file versions.)
1897	*/
1898	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1899	SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1900	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1901	SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1902
1903	/*
1904	* Restore.
1905	*/
1906	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1907	{
1908	PVMCPU pVCpu = &pVM->aCpus[i];
1909	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1910	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1911
1912	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1913	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1914	pVCpu->cpum.s.Hyper.esp = uESP;
1915	}
1916
1917	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1918	{
1919	CPUMCTX_VER1_6 cpumctx16;
1920	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1921	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1922
1923	/* Save the old cpumctx state into the new one. */
1924	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1925
1926	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1927	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1928	}
1929	else
1930	{
1931	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1932	{
1933	uint32_t cCpus;
1934	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1935	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1936	VERR_SSM_UNEXPECTED_DATA);
1937	}
1938	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1939	\|\| pVM->cCpus == 1,
1940	("cCpus=%u\n", pVM->cCpus),
1941	VERR_SSM_UNEXPECTED_DATA);
1942
1943	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1944	{
1945	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1946	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1947	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1948	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1949	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1950	}
1951	}
1952	}
1953
1954	/*
1955	* Guest CPUIDs.
1956	*/
1957	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
1958	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1959
1960	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
1961	* actually required. */
1962
1963	/*
1964	* Restore the CPUID leaves.
1965	*
1966	* Note that we support restoring less than the current amount of standard
1967	* leaves because we've been allowed more is newer version of VBox.
1968	*/
1969	uint32_t cElements;
1970	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1971	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1972	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1973	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1974
1975	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1976	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1977	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1978	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1979
1980	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1981	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1982	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1983	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1984
1985	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1986
1987	/*
1988	* Check that the basic cpuid id information is unchanged.
1989	*/
1990	/** @todo we should check the 64 bits capabilities too! */
1991	uint32_t au32CpuId[8] = {0};
1992	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1993	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1994	uint32_t au32CpuIdSaved[8];
1995	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1996	if (RT_SUCCESS(rc))
1997	{
1998	/* Ignore CPU stepping. */
1999	au32CpuId[4] &= 0xfffffff0;
2000	au32CpuIdSaved[4] &= 0xfffffff0;
2001
2002	/* Ignore APIC ID (AMD specs). */
2003	au32CpuId[5] &= ~0xff000000;
2004	au32CpuIdSaved[5] &= ~0xff000000;
2005
2006	/* Ignore the number of Logical CPUs (AMD specs). */
2007	au32CpuId[5] &= ~0x00ff0000;
2008	au32CpuIdSaved[5] &= ~0x00ff0000;
2009
2010	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2011	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2012	\| X86_CPUID_FEATURE_ECX_VMX
2013	\| X86_CPUID_FEATURE_ECX_SMX
2014	\| X86_CPUID_FEATURE_ECX_EST
2015	\| X86_CPUID_FEATURE_ECX_TM2
2016	\| X86_CPUID_FEATURE_ECX_CNTXID
2017	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2018	\| X86_CPUID_FEATURE_ECX_PDCM
2019	\| X86_CPUID_FEATURE_ECX_DCA
2020	\| X86_CPUID_FEATURE_ECX_X2APIC
2021	);
2022	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2023	\| X86_CPUID_FEATURE_ECX_VMX
2024	\| X86_CPUID_FEATURE_ECX_SMX
2025	\| X86_CPUID_FEATURE_ECX_EST
2026	\| X86_CPUID_FEATURE_ECX_TM2
2027	\| X86_CPUID_FEATURE_ECX_CNTXID
2028	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2029	\| X86_CPUID_FEATURE_ECX_PDCM
2030	\| X86_CPUID_FEATURE_ECX_DCA
2031	\| X86_CPUID_FEATURE_ECX_X2APIC
2032	);
2033
2034	/* Make sure we don't forget to update the masks when enabling
2035	* features in the future.
2036	*/
2037	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2038	( X86_CPUID_FEATURE_ECX_DTES64
2039	\| X86_CPUID_FEATURE_ECX_VMX
2040	\| X86_CPUID_FEATURE_ECX_SMX
2041	\| X86_CPUID_FEATURE_ECX_EST
2042	\| X86_CPUID_FEATURE_ECX_TM2
2043	\| X86_CPUID_FEATURE_ECX_CNTXID
2044	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2045	\| X86_CPUID_FEATURE_ECX_PDCM
2046	\| X86_CPUID_FEATURE_ECX_DCA
2047	\| X86_CPUID_FEATURE_ECX_X2APIC
2048	)));
2049	/* do the compare */
2050	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2051	{
2052	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2053	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2054	"Saved=%.*Rhxs\n"
2055	"Real =%.*Rhxs\n",
2056	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2057	sizeof(au32CpuId), au32CpuId));
2058	else
2059	{
2060	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2061	"Saved=%.*Rhxs\n"
2062	"Real =%.*Rhxs\n",
2063	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2064	sizeof(au32CpuId), au32CpuId));
2065	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2066	}
2067	}
2068	}
2069
2070	return rc;
2071	}
2072
2073
2074	/**
2075	* Formats the EFLAGS value into mnemonics.
2076	*
2077	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2078	* @param efl The EFLAGS value.
2079	*/
2080	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2081	{
2082	/*
2083	* Format the flags.
2084	*/
2085	static const struct
2086	{
2087	const char pszSet; const char pszClear; uint32_t fFlag;
2088	} s_aFlags[] =
2089	{
2090	{ "vip",NULL, X86_EFL_VIP },
2091	{ "vif",NULL, X86_EFL_VIF },
2092	{ "ac", NULL, X86_EFL_AC },
2093	{ "vm", NULL, X86_EFL_VM },
2094	{ "rf", NULL, X86_EFL_RF },
2095	{ "nt", NULL, X86_EFL_NT },
2096	{ "ov", "nv", X86_EFL_OF },
2097	{ "dn", "up", X86_EFL_DF },
2098	{ "ei", "di", X86_EFL_IF },
2099	{ "tf", NULL, X86_EFL_TF },
2100	{ "nt", "pl", X86_EFL_SF },
2101	{ "nz", "zr", X86_EFL_ZF },
2102	{ "ac", "na", X86_EFL_AF },
2103	{ "po", "pe", X86_EFL_PF },
2104	{ "cy", "nc", X86_EFL_CF },
2105	};
2106	char *psz = pszEFlags;
2107	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2108	{
2109	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2110	if (pszAdd)
2111	{
2112	strcpy(psz, pszAdd);
2113	psz += strlen(pszAdd);
2114	*psz++ = ' ';
2115	}
2116	}
2117	psz[-1] = '\0';
2118	}
2119
2120
2121	/**
2122	* Formats a full register dump.
2123	*
2124	* @param pVM VM Handle.
2125	* @param pCtx The context to format.
2126	* @param pCtxCore The context core to format.
2127	* @param pHlp Output functions.
2128	* @param enmType The dump type.
2129	* @param pszPrefix Register name prefix.
2130	*/
2131	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2132	{
2133	/*
2134	* Format the EFLAGS.
2135	*/
2136	uint32_t efl = pCtxCore->eflags.u32;
2137	char szEFlags[80];
2138	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2139
2140	/*
2141	* Format the registers.
2142	*/
2143	switch (enmType)
2144	{
2145	case CPUMDUMPTYPE_TERSE:
2146	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2147	pHlp->pfnPrintf(pHlp,
2148	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2149	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2150	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2151	"%sr14=%016RX64 %sr15=%016RX64\n"
2152	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2153	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2154	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2155	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2156	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2157	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2158	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2159	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2160	else
2161	pHlp->pfnPrintf(pHlp,
2162	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2163	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2164	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2165	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2166	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2167	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2168	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2169	break;
2170
2171	case CPUMDUMPTYPE_DEFAULT:
2172	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2173	pHlp->pfnPrintf(pHlp,
2174	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2175	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2176	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2177	"%sr14=%016RX64 %sr15=%016RX64\n"
2178	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2179	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2180	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2181	,
2182	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2183	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2184	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2185	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2186	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2187	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2188	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2189	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2190	else
2191	pHlp->pfnPrintf(pHlp,
2192	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2193	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2194	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2195	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2196	,
2197	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2198	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2199	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2200	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2201	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2202	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2203	break;
2204
2205	case CPUMDUMPTYPE_VERBOSE:
2206	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2207	pHlp->pfnPrintf(pHlp,
2208	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2209	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2210	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2211	"%sr14=%016RX64 %sr15=%016RX64\n"
2212	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2213	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2214	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2215	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2216	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2217	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2218	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2219	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2220	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2221	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2222	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2223	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2224	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2225	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2226	,
2227	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2228	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2229	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2230	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2231	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2232	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2233	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2234	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2235	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2236	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2237	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2238	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2239	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2240	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2241	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2242	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2243	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2244	else
2245	pHlp->pfnPrintf(pHlp,
2246	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2247	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2248	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2249	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2250	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2251	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2252	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2253	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2254	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2255	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2256	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2257	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2258	,
2259	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2260	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2261	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2262	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2263	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2264	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2265	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2266	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2267	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2268	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2269	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2270	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2271
2272	pHlp->pfnPrintf(pHlp,
2273	"FPU:\n"
2274	"%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
2275	"%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
2276	"%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2277	,
2278	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
2279	pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2280	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
2281	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
2282
2283	pHlp->pfnPrintf(pHlp,
2284	"MSR:\n"
2285	"%sEFER =%016RX64\n"
2286	"%sPAT =%016RX64\n"
2287	"%sSTAR =%016RX64\n"
2288	"%sCSTAR =%016RX64\n"
2289	"%sLSTAR =%016RX64\n"
2290	"%sSFMASK =%016RX64\n"
2291	"%sKERNELGSBASE =%016RX64\n",
2292	pszPrefix, pCtx->msrEFER,
2293	pszPrefix, pCtx->msrPAT,
2294	pszPrefix, pCtx->msrSTAR,
2295	pszPrefix, pCtx->msrCSTAR,
2296	pszPrefix, pCtx->msrLSTAR,
2297	pszPrefix, pCtx->msrSFMASK,
2298	pszPrefix, pCtx->msrKERNELGSBASE);
2299	break;
2300	}
2301	}
2302
2303
2304	/**
2305	* Display all cpu states and any other cpum info.
2306	*
2307	* @param pVM VM Handle.
2308	* @param pHlp The info helper functions.
2309	* @param pszArgs Arguments, ignored.
2310	*/
2311	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2312	{
2313	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2314	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2315	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2316	cpumR3InfoHost(pVM, pHlp, pszArgs);
2317	}
2318
2319
2320	/**
2321	* Parses the info argument.
2322	*
2323	* The argument starts with 'verbose', 'terse' or 'default' and then
2324	* continues with the comment string.
2325	*
2326	* @param pszArgs The pointer to the argument string.
2327	* @param penmType Where to store the dump type request.
2328	* @param ppszComment Where to store the pointer to the comment string.
2329	*/
2330	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2331	{
2332	if (!pszArgs)
2333	{
2334	*penmType = CPUMDUMPTYPE_DEFAULT;
2335	*ppszComment = "";
2336	}
2337	else
2338	{
2339	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2340	{
2341	pszArgs += 5;
2342	*penmType = CPUMDUMPTYPE_VERBOSE;
2343	}
2344	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2345	{
2346	pszArgs += 5;
2347	*penmType = CPUMDUMPTYPE_TERSE;
2348	}
2349	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2350	{
2351	pszArgs += 7;
2352	*penmType = CPUMDUMPTYPE_DEFAULT;
2353	}
2354	else
2355	*penmType = CPUMDUMPTYPE_DEFAULT;
2356	*ppszComment = RTStrStripL(pszArgs);
2357	}
2358	}
2359
2360
2361	/**
2362	* Display the guest cpu state.
2363	*
2364	* @param pVM VM Handle.
2365	* @param pHlp The info helper functions.
2366	* @param pszArgs Arguments, ignored.
2367	*/
2368	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2369	{
2370	CPUMDUMPTYPE enmType;
2371	const char *pszComment;
2372	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2373
2374	/* @todo SMP support! */
2375	PVMCPU pVCpu = VMMGetCpu(pVM);
2376	if (!pVCpu)
2377	pVCpu = &pVM->aCpus[0];
2378
2379	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2380
2381	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2382	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2383	}
2384
2385
2386	/**
2387	* Display the current guest instruction
2388	*
2389	* @param pVM VM Handle.
2390	* @param pHlp The info helper functions.
2391	* @param pszArgs Arguments, ignored.
2392	*/
2393	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2394	{
2395	char szInstruction[256];
2396	/* @todo SMP support! */
2397	PVMCPU pVCpu = VMMGetCpu(pVM);
2398	if (!pVCpu)
2399	pVCpu = &pVM->aCpus[0];
2400
2401	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2402	if (RT_SUCCESS(rc))
2403	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2404	}
2405
2406
2407	/**
2408	* Display the hypervisor cpu state.
2409	*
2410	* @param pVM VM Handle.
2411	* @param pHlp The info helper functions.
2412	* @param pszArgs Arguments, ignored.
2413	*/
2414	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2415	{
2416	CPUMDUMPTYPE enmType;
2417	const char *pszComment;
2418	/* @todo SMP */
2419	PVMCPU pVCpu = &pVM->aCpus[0];
2420
2421	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2422	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2423	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2424	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2425	}
2426
2427
2428	/**
2429	* Display the host cpu state.
2430	*
2431	* @param pVM VM Handle.
2432	* @param pHlp The info helper functions.
2433	* @param pszArgs Arguments, ignored.
2434	*/
2435	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2436	{
2437	CPUMDUMPTYPE enmType;
2438	const char *pszComment;
2439	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2440	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2441
2442	/*
2443	* Format the EFLAGS.
2444	*/
2445	/* @todo SMP */
2446	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2447	#if HC_ARCH_BITS == 32
2448	uint32_t efl = pCtx->eflags.u32;
2449	#else
2450	uint64_t efl = pCtx->rflags;
2451	#endif
2452	char szEFlags[80];
2453	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2454
2455	/*
2456	* Format the registers.
2457	*/
2458	#if HC_ARCH_BITS == 32
2459	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2460	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2461	# endif
2462	{
2463	pHlp->pfnPrintf(pHlp,
2464	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2465	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2466	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2467	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2468	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2469	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2470	,
2471	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2472	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2473	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2474	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2475	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2476	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2477	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2478	}
2479	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2480	else
2481	# endif
2482	#endif
2483	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2484	{
2485	pHlp->pfnPrintf(pHlp,
2486	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2487	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2488	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2489	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2490	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2491	"r14=%016RX64 r15=%016RX64\n"
2492	"iopl=%d %31s\n"
2493	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2494	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2495	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2496	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2497	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2498	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2499	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2500	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2501	,
2502	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2503	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2504	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2505	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2506	pCtx->r11, pCtx->r12, pCtx->r13,
2507	pCtx->r14, pCtx->r15,
2508	X86_EFL_GET_IOPL(efl), szEFlags,
2509	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2510	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2511	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2512	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2513	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2514	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2515	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2516	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2517	}
2518	#endif
2519	}
2520
2521
2522	/**
2523	* Get L1 cache / TLS associativity.
2524	*/
2525	static const char getCacheAss(unsigned u, char pszBuf)
2526	{
2527	if (u == 0)
2528	return "res0 ";
2529	if (u == 1)
2530	return "direct";
2531	if (u >= 256)
2532	return "???";
2533
2534	RTStrPrintf(pszBuf, 16, "%d way", u);
2535	return pszBuf;
2536	}
2537
2538
2539	/**
2540	* Get L2 cache soociativity.
2541	*/
2542	const char *getL2CacheAss(unsigned u)
2543	{
2544	switch (u)
2545	{
2546	case 0: return "off ";
2547	case 1: return "direct";
2548	case 2: return "2 way ";
2549	case 3: return "res3 ";
2550	case 4: return "4 way ";
2551	case 5: return "res5 ";
2552	case 6: return "8 way "; case 7: return "res7 ";
2553	case 8: return "16 way";
2554	case 9: return "res9 ";
2555	case 10: return "res10 ";
2556	case 11: return "res11 ";
2557	case 12: return "res12 ";
2558	case 13: return "res13 ";
2559	case 14: return "res14 ";
2560	case 15: return "fully ";
2561	default:
2562	return "????";
2563	}
2564	}
2565
2566
2567	/**
2568	* Display the guest CpuId leaves.
2569	*
2570	* @param pVM VM Handle.
2571	* @param pHlp The info helper functions.
2572	* @param pszArgs "terse", "default" or "verbose".
2573	*/
2574	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2575	{
2576	/*
2577	* Parse the argument.
2578	*/
2579	unsigned iVerbosity = 1;
2580	if (pszArgs)
2581	{
2582	pszArgs = RTStrStripL(pszArgs);
2583	if (!strcmp(pszArgs, "terse"))
2584	iVerbosity--;
2585	else if (!strcmp(pszArgs, "verbose"))
2586	iVerbosity++;
2587	}
2588
2589	/*
2590	* Start cracking.
2591	*/
2592	CPUMCPUID Host;
2593	CPUMCPUID Guest;
2594	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2595
2596	pHlp->pfnPrintf(pHlp,
2597	" RAW Standard CPUIDs\n"
2598	" Function eax ebx ecx edx\n");
2599	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2600	{
2601	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2602	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2603
2604	pHlp->pfnPrintf(pHlp,
2605	"Gst: %08x %08x %08x %08x %08x%s\n"
2606	"Hst: %08x %08x %08x %08x\n",
2607	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2608	i <= cStdMax ? "" : "*",
2609	Host.eax, Host.ebx, Host.ecx, Host.edx);
2610	}
2611
2612	/*
2613	* If verbose, decode it.
2614	*/
2615	if (iVerbosity)
2616	{
2617	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2618	pHlp->pfnPrintf(pHlp,
2619	"Name: %.04s%.04s%.04s\n"
2620	"Supports: 0-%x\n",
2621	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2622	}
2623
2624	/*
2625	* Get Features.
2626	*/
2627	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2628	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2629	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2630	if (cStdMax >= 1 && iVerbosity)
2631	{
2632	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2633	uint32_t uEAX = Guest.eax;
2634
2635	pHlp->pfnPrintf(pHlp,
2636	"Family: %d \tExtended: %d \tEffective: %d\n"
2637	"Model: %d \tExtended: %d \tEffective: %d\n"
2638	"Stepping: %d\n"
2639	"Type: %d\n"
2640	"APIC ID: %#04x\n"
2641	"Logical CPUs: %d\n"
2642	"CLFLUSH Size: %d\n"
2643	"Brand ID: %#04x\n",
2644	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2645	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2646	ASMGetCpuStepping(uEAX),
2647	(uEAX >> 12) & 3,
2648	(Guest.ebx >> 24) & 0xff,
2649	(Guest.ebx >> 16) & 0xff,
2650	(Guest.ebx >> 8) & 0xff,
2651	(Guest.ebx >> 0) & 0xff);
2652	if (iVerbosity == 1)
2653	{
2654	uint32_t uEDX = Guest.edx;
2655	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2656	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2657	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2658	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2659	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2660	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2661	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2662	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2663	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2664	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2665	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2666	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2667	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2668	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2669	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2670	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2671	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2672	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2673	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2674	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2675	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2676	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2677	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2678	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2679	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2680	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2681	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2682	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2683	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2684	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2685	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2686	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2687	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2688	pHlp->pfnPrintf(pHlp, "\n");
2689
2690	uint32_t uECX = Guest.ecx;
2691	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2692	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2693	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2694	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2695	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2696	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2697	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2698	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2699	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2700	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2701	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2702	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2703	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2704	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2705	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2706	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2707	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2708	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2709	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " 17");
2710	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2711	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4_1");
2712	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4_2");
2713	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2714	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2715	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2716	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " 24");
2717	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2718	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2719	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2720	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2721	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2722	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2723	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2724	pHlp->pfnPrintf(pHlp, "\n");
2725	}
2726	else
2727	{
2728	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2729
2730	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2731	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2732	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2733	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2734
2735	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2736	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2737	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2738	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2739	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2740	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2741	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2742	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2743	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2744	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2745	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2746	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2747	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2748	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2749	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2750	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
2751	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
2752	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
2753	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
2754	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
2755	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
2756	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
2757	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
2758	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
2759	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
2760	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
2761	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
2762	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
2763	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
2764	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
2765	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
2766	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
2767	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
2768
2769	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
2770	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
2771	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
2772	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
2773	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
2774	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
2775	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
2776	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2777	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
2778	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
2779	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
2780	pHlp->pfnPrintf(pHlp, "FMA = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
2781	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
2782	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
2783	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
2784	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
2785	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
2786	pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
2787	pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
2788	pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
2789	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
2790	pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
2791	pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
2792	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
2793	pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
2794	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
2795	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
2796	}
2797	}
2798	if (cStdMax >= 2 && iVerbosity)
2799	{
2800	/** @todo */
2801	}
2802
2803	/*
2804	* Extended.
2805	* Implemented after AMD specs.
2806	*/
2807	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
2808
2809	pHlp->pfnPrintf(pHlp,
2810	"\n"
2811	" RAW Extended CPUIDs\n"
2812	" Function eax ebx ecx edx\n");
2813	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
2814	{
2815	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
2816	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2817
2818	pHlp->pfnPrintf(pHlp,
2819	"Gst: %08x %08x %08x %08x %08x%s\n"
2820	"Hst: %08x %08x %08x %08x\n",
2821	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2822	i <= cExtMax ? "" : "*",
2823	Host.eax, Host.ebx, Host.ecx, Host.edx);
2824	}
2825
2826	/*
2827	* Understandable output
2828	*/
2829	if (iVerbosity)
2830	{
2831	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
2832	pHlp->pfnPrintf(pHlp,
2833	"Ext Name: %.4s%.4s%.4s\n"
2834	"Ext Supports: 0x80000000-%#010x\n",
2835	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2836	}
2837
2838	if (iVerbosity && cExtMax >= 1)
2839	{
2840	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
2841	uint32_t uEAX = Guest.eax;
2842	pHlp->pfnPrintf(pHlp,
2843	"Family: %d \tExtended: %d \tEffective: %d\n"
2844	"Model: %d \tExtended: %d \tEffective: %d\n"
2845	"Stepping: %d\n"
2846	"Brand ID: %#05x\n",
2847	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2848	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2849	ASMGetCpuStepping(uEAX),
2850	Guest.ebx & 0xfff);
2851
2852	if (iVerbosity == 1)
2853	{
2854	uint32_t uEDX = Guest.edx;
2855	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2856	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2857	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2858	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2859	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2860	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2861	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2862	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2863	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2864	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2865	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2866	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2867	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
2868	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2869	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2870	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2871	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2872	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2873	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2874	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
2875	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
2876	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
2877	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
2878	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
2879	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2880	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2881	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
2882	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
2883	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
2884	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
2885	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
2886	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
2887	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
2888	pHlp->pfnPrintf(pHlp, "\n");
2889
2890	uint32_t uECX = Guest.ecx;
2891	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2892	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
2893	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
2894	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
2895	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
2896	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
2897	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
2898	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
2899	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
2900	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
2901	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
2902	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
2903	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
2904	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
2905	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
2906	for (unsigned iBit = 5; iBit < 32; iBit++)
2907	if (uECX & RT_BIT(iBit))
2908	pHlp->pfnPrintf(pHlp, " %d", iBit);
2909	pHlp->pfnPrintf(pHlp, "\n");
2910	}
2911	else
2912	{
2913	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2914
2915	uint32_t uEdxGst = Guest.edx;
2916	uint32_t uEdxHst = Host.edx;
2917	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2918	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2919	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2920	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2921	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2922	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2923	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2924	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2925	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2926	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2927	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2928	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2929	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2930	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2931	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2932	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
2933	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
2934	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
2935	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
2936	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
2937	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
2938	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
2939	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
2940	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
2941	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
2942	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
2943	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
2944	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
2945	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
2946	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
2947	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
2948	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
2949	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
2950
2951	uint32_t uEcxGst = Guest.ecx;
2952	uint32_t uEcxHst = Host.ecx;
2953	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
2954	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
2955	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
2956	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
2957	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
2958	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
2959	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
2960	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
2961	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
2962	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
2963	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
2964	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
2965	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
2966	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
2967	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
2968	}
2969	}
2970
2971	if (iVerbosity && cExtMax >= 2)
2972	{
2973	char szString[443+1] = {0};
2974	uint32_t pu32 = (uint32_t )szString;
2975	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
2976	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
2977	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
2978	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
2979	if (cExtMax >= 3)
2980	{
2981	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
2982	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
2983	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2984	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2985	}
2986	if (cExtMax >= 4)
2987	{
2988	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2989	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2990	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2991	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2992	}
2993	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2994	}
2995
2996	if (iVerbosity && cExtMax >= 5)
2997	{
2998	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2999	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3000	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3001	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3002	char sz1[32];
3003	char sz2[32];
3004
3005	pHlp->pfnPrintf(pHlp,
3006	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3007	"TLB 2/4M Data: %s %3d entries\n",
3008	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3009	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3010	pHlp->pfnPrintf(pHlp,
3011	"TLB 4K Instr/Uni: %s %3d entries\n"
3012	"TLB 4K Data: %s %3d entries\n",
3013	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3014	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3015	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3016	"L1 Instr Cache Lines Per Tag: %d\n"
3017	"L1 Instr Cache Associativity: %s\n"
3018	"L1 Instr Cache Size: %d KB\n",
3019	(uEDX >> 0) & 0xff,
3020	(uEDX >> 8) & 0xff,
3021	getCacheAss((uEDX >> 16) & 0xff, sz1),
3022	(uEDX >> 24) & 0xff);
3023	pHlp->pfnPrintf(pHlp,
3024	"L1 Data Cache Line Size: %d bytes\n"
3025	"L1 Data Cache Lines Per Tag: %d\n"
3026	"L1 Data Cache Associativity: %s\n"
3027	"L1 Data Cache Size: %d KB\n",
3028	(uECX >> 0) & 0xff,
3029	(uECX >> 8) & 0xff,
3030	getCacheAss((uECX >> 16) & 0xff, sz1),
3031	(uECX >> 24) & 0xff);
3032	}
3033
3034	if (iVerbosity && cExtMax >= 6)
3035	{
3036	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3037	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3038	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3039
3040	pHlp->pfnPrintf(pHlp,
3041	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3042	"L2 TLB 2/4M Data: %s %4d entries\n",
3043	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3044	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3045	pHlp->pfnPrintf(pHlp,
3046	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3047	"L2 TLB 4K Data: %s %4d entries\n",
3048	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3049	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3050	pHlp->pfnPrintf(pHlp,
3051	"L2 Cache Line Size: %d bytes\n"
3052	"L2 Cache Lines Per Tag: %d\n"
3053	"L2 Cache Associativity: %s\n"
3054	"L2 Cache Size: %d KB\n",
3055	(uEDX >> 0) & 0xff,
3056	(uEDX >> 8) & 0xf,
3057	getL2CacheAss((uEDX >> 12) & 0xf),
3058	(uEDX >> 16) & 0xffff);
3059	}
3060
3061	if (iVerbosity && cExtMax >= 7)
3062	{
3063	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3064
3065	pHlp->pfnPrintf(pHlp, "APM Features: ");
3066	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3067	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3068	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3069	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3070	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3071	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3072	for (unsigned iBit = 6; iBit < 32; iBit++)
3073	if (uEDX & RT_BIT(iBit))
3074	pHlp->pfnPrintf(pHlp, " %d", iBit);
3075	pHlp->pfnPrintf(pHlp, "\n");
3076	}
3077
3078	if (iVerbosity && cExtMax >= 8)
3079	{
3080	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3081	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3082
3083	pHlp->pfnPrintf(pHlp,
3084	"Physical Address Width: %d bits\n"
3085	"Virtual Address Width: %d bits\n",
3086	(uEAX >> 0) & 0xff,
3087	(uEAX >> 8) & 0xff);
3088	pHlp->pfnPrintf(pHlp,
3089	"Physical Core Count: %d\n",
3090	(uECX >> 0) & 0xff);
3091	}
3092
3093
3094	/*
3095	* Centaur.
3096	*/
3097	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3098
3099	pHlp->pfnPrintf(pHlp,
3100	"\n"
3101	" RAW Centaur CPUIDs\n"
3102	" Function eax ebx ecx edx\n");
3103	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3104	{
3105	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3106	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3107
3108	pHlp->pfnPrintf(pHlp,
3109	"Gst: %08x %08x %08x %08x %08x%s\n"
3110	"Hst: %08x %08x %08x %08x\n",
3111	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3112	i <= cCentaurMax ? "" : "*",
3113	Host.eax, Host.ebx, Host.ecx, Host.edx);
3114	}
3115
3116	/*
3117	* Understandable output
3118	*/
3119	if (iVerbosity)
3120	{
3121	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3122	pHlp->pfnPrintf(pHlp,
3123	"Centaur Supports: 0xc0000000-%#010x\n",
3124	Guest.eax);
3125	}
3126
3127	if (iVerbosity && cCentaurMax >= 1)
3128	{
3129	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3130	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3131	uint32_t uEdxHst = Host.edx;
3132
3133	if (iVerbosity == 1)
3134	{
3135	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3136	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3137	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3138	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3139	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3140	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3141	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3142	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3143	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3144	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3145	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3146	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3147	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3148	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3149	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3150	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3151	for (unsigned iBit = 14; iBit < 32; iBit++)
3152	if (uEdxGst & RT_BIT(iBit))
3153	pHlp->pfnPrintf(pHlp, " %d", iBit);
3154	pHlp->pfnPrintf(pHlp, "\n");
3155	}
3156	else
3157	{
3158	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3159	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3160	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3161	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3162	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3163	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3164	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3165	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3166	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3167	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3168	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3169	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3170	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3171	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3172	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3173	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3174	for (unsigned iBit = 14; iBit < 32; iBit++)
3175	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3176	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3177	pHlp->pfnPrintf(pHlp, "\n");
3178	}
3179	}
3180	}
3181
3182
3183	/**
3184	* Structure used when disassembling and instructions in DBGF.
3185	* This is used so the reader function can get the stuff it needs.
3186	*/
3187	typedef struct CPUMDISASSTATE
3188	{
3189	/** Pointer to the CPU structure. */
3190	PDISCPUSTATE pCpu;
3191	/** The VM handle. */
3192	PVM pVM;
3193	/** The VMCPU handle. */
3194	PVMCPU pVCpu;
3195	/** Pointer to the first byte in the segemnt. */
3196	RTGCUINTPTR GCPtrSegBase;
3197	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3198	RTGCUINTPTR GCPtrSegEnd;
3199	/** The size of the segment minus 1. */
3200	RTGCUINTPTR cbSegLimit;
3201	/** Pointer to the current page - R3 Ptr. */
3202	void const *pvPageR3;
3203	/** Pointer to the current page - GC Ptr. */
3204	RTGCPTR pvPageGC;
3205	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3206	PGMPAGEMAPLOCK PageMapLock;
3207	/** Whether the PageMapLock is valid or not. */
3208	bool fLocked;
3209	/** 64 bits mode or not. */
3210	bool f64Bits;
3211	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3212
3213
3214	/**
3215	* Instruction reader.
3216	*
3217	* @returns VBox status code.
3218	* @param PtrSrc Address to read from.
3219	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3220	* @param pu8Dst Where to store the bytes.
3221	* @param cbRead Number of bytes to read.
3222	* @param uDisCpu Pointer to the disassembler cpu state.
3223	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3224	*/
3225	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3226	{
3227	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3228	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3229	Assert(cbRead > 0);
3230	for (;;)
3231	{
3232	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3233
3234	/* Need to update the page translation? */
3235	if ( !pState->pvPageR3
3236	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3237	{
3238	int rc = VINF_SUCCESS;
3239
3240	/* translate the address */
3241	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3242	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3243	&& !HWACCMIsEnabled(pState->pVM))
3244	{
3245	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3246	if (!pState->pvPageR3)
3247	rc = VERR_INVALID_POINTER;
3248	}
3249	else
3250	{
3251	/* Release mapping lock previously acquired. */
3252	if (pState->fLocked)
3253	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3254	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3255	pState->fLocked = RT_SUCCESS_NP(rc);
3256	}
3257	if (RT_FAILURE(rc))
3258	{
3259	pState->pvPageR3 = NULL;
3260	return rc;
3261	}
3262	}
3263
3264	/* check the segemnt limit */
3265	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3266	return VERR_OUT_OF_SELECTOR_BOUNDS;
3267
3268	/* calc how much we can read */
3269	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3270	if (!pState->f64Bits)
3271	{
3272	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3273	if (cb > cbSeg && cbSeg)
3274	cb = cbSeg;
3275	}
3276	if (cb > cbRead)
3277	cb = cbRead;
3278
3279	/* read and advance */
3280	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3281	cbRead -= cb;
3282	if (!cbRead)
3283	return VINF_SUCCESS;
3284	pu8Dst += cb;
3285	PtrSrc += cb;
3286	}
3287	}
3288
3289
3290	/**
3291	* Disassemble an instruction and return the information in the provided structure.
3292	*
3293	* @returns VBox status code.
3294	* @param pVM VM Handle
3295	* @param pVCpu VMCPU Handle
3296	* @param pCtx CPU context
3297	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3298	* @param pCpu Disassembly state
3299	* @param pszPrefix String prefix for logging (debug only)
3300	*
3301	*/
3302	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3303	{
3304	CPUMDISASSTATE State;
3305	int rc;
3306
3307	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3308	State.pCpu = pCpu;
3309	State.pvPageGC = 0;
3310	State.pvPageR3 = NULL;
3311	State.pVM = pVM;
3312	State.pVCpu = pVCpu;
3313	State.fLocked = false;
3314	State.f64Bits = false;
3315
3316	/*
3317	* Get selector information.
3318	*/
3319	if ( (pCtx->cr0 & X86_CR0_PE)
3320	&& pCtx->eflags.Bits.u1VM == 0)
3321	{
3322	if (CPUMAreHiddenSelRegsValid(pVM))
3323	{
3324	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3325	State.GCPtrSegBase = pCtx->csHid.u64Base;
3326	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3327	State.cbSegLimit = pCtx->csHid.u32Limit;
3328	pCpu->mode = (State.f64Bits)
3329	? CPUMODE_64BIT
3330	: pCtx->csHid.Attr.n.u1DefBig
3331	? CPUMODE_32BIT
3332	: CPUMODE_16BIT;
3333	}
3334	else
3335	{
3336	DBGFSELINFO SelInfo;
3337
3338	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3339	if (RT_FAILURE(rc))
3340	{
3341	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3342	return rc;
3343	}
3344
3345	/*
3346	* Validate the selector.
3347	*/
3348	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3349	if (RT_FAILURE(rc))
3350	{
3351	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3352	return rc;
3353	}
3354	State.GCPtrSegBase = SelInfo.GCPtrBase;
3355	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3356	State.cbSegLimit = SelInfo.cbLimit;
3357	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3358	}
3359	}
3360	else
3361	{
3362	/* real or V86 mode */
3363	pCpu->mode = CPUMODE_16BIT;
3364	State.GCPtrSegBase = pCtx->cs * 16;
3365	State.GCPtrSegEnd = 0xFFFFFFFF;
3366	State.cbSegLimit = 0xFFFFFFFF;
3367	}
3368
3369	/*
3370	* Disassemble the instruction.
3371	*/
3372	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3373	pCpu->apvUserData[0] = &State;
3374
3375	uint32_t cbInstr;
3376	#ifndef LOG_ENABLED
3377	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3378	if (RT_SUCCESS(rc))
3379	{
3380	#else
3381	char szOutput[160];
3382	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3383	if (RT_SUCCESS(rc))
3384	{
3385	/* log it */
3386	if (pszPrefix)
3387	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3388	else
3389	Log(("%s", szOutput));
3390	#endif
3391	rc = VINF_SUCCESS;
3392	}
3393	else
3394	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3395
3396	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3397	if (State.fLocked)
3398	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3399
3400	return rc;
3401	}
3402
3403	#ifdef DEBUG
3404
3405	/**
3406	* Disassemble an instruction and dump it to the log
3407	*
3408	* @returns VBox status code.
3409	* @param pVM VM Handle
3410	* @param pVCpu VMCPU Handle
3411	* @param pCtx CPU context
3412	* @param pc GC instruction pointer
3413	* @param pszPrefix String prefix for logging
3414	*
3415	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3416	*/
3417	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3418	{
3419	DISCPUSTATE Cpu;
3420	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3421	}
3422
3423
3424	/**
3425	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3426	*
3427	* @internal
3428	*/
3429	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3430	{
3431	/* @todo SMP support!! */
3432	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3433	}
3434
3435	#endif /* DEBUG */
3436
3437	/**
3438	* API for controlling a few of the CPU features found in CR4.
3439	*
3440	* Currently only X86_CR4_TSD is accepted as input.
3441	*
3442	* @returns VBox status code.
3443	*
3444	* @param pVM The VM handle.
3445	* @param fOr The CR4 OR mask.
3446	* @param fAnd The CR4 AND mask.
3447	*/
3448	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3449	{
3450	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3451	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3452
3453	pVM->cpum.s.CR4.OrMask &= fAnd;
3454	pVM->cpum.s.CR4.OrMask \|= fOr;
3455
3456	return VINF_SUCCESS;
3457	}
3458
3459
3460	/**
3461	* Gets a pointer to the array of standard CPUID leaves.
3462	*
3463	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3464	*
3465	* @returns Pointer to the standard CPUID leaves (read-only).
3466	* @param pVM The VM handle.
3467	* @remark Intended for PATM.
3468	*/
3469	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3470	{
3471	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3472	}
3473
3474
3475	/**
3476	* Gets a pointer to the array of extended CPUID leaves.
3477	*
3478	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3479	*
3480	* @returns Pointer to the extended CPUID leaves (read-only).
3481	* @param pVM The VM handle.
3482	* @remark Intended for PATM.
3483	*/
3484	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3485	{
3486	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3487	}
3488
3489
3490	/**
3491	* Gets a pointer to the array of centaur CPUID leaves.
3492	*
3493	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3494	*
3495	* @returns Pointer to the centaur CPUID leaves (read-only).
3496	* @param pVM The VM handle.
3497	* @remark Intended for PATM.
3498	*/
3499	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3500	{
3501	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3502	}
3503
3504
3505	/**
3506	* Gets a pointer to the default CPUID leaf.
3507	*
3508	* @returns Pointer to the default CPUID leaf (read-only).
3509	* @param pVM The VM handle.
3510	* @remark Intended for PATM.
3511	*/
3512	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3513	{
3514	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3515	}

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 24760

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