CPUM.cpp@ 27264

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1	/* $Id: CPUM.cpp 26992 2010-03-03 14:21:20Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_cpum CPUM - CPU Monitor / Manager
23	*
24	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
25	* also responsible for lazy FPU handling and some of the context loading
26	* in raw mode.
27	*
28	* There are three CPU contexts, the most important one is the guest one (GC).
29	* When running in raw-mode (RC) there is a special hyper context for the VMM
30	* part that floats around inside the guest address space. When running in
31	* raw-mode, CPUM also maintains a host context for saving and restoring
32	* registers accross world switches. This latter is done in cooperation with the
33	* world switcher (@see pg_vmm).
34	*
35	* @see grp_cpum
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_CPUM
42	#include <VBox/cpum.h>
43	#include <VBox/cpumdis.h>
44	#include <VBox/pgm.h>
45	#include <VBox/mm.h>
46	#include <VBox/selm.h>
47	#include <VBox/dbgf.h>
48	#include <VBox/patm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/ssm.h>
51	#include "CPUMInternal.h"
52	#include <VBox/vm.h>
53
54	#include <VBox/param.h>
55	#include <VBox/dis.h>
56	#include <VBox/err.h>
57	#include <VBox/log.h>
58	#include <iprt/assert.h>
59	#include <iprt/asm.h>
60	#include <iprt/string.h>
61	#include <iprt/mp.h>
62	#include <iprt/cpuset.h>
63
64
65	/*******************************************************************************
66	* Defined Constants And Macros *
67	*******************************************************************************/
68	/** The current saved state version. */
69	#define CPUM_SAVED_STATE_VERSION 11
70	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
71	* changes. */
72	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
73	/** The saved state version for the 2.1 trunk before the MSR changes. */
74	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
75	/** The saved state version of 2.0, used for backwards compatibility. */
76	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
77	/** The saved state version of 1.6, used for backwards compatability. */
78	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
79
80
81	/*******************************************************************************
82	* Structures and Typedefs *
83	*******************************************************************************/
84
85	/**
86	* What kind of cpu info dump to perform.
87	*/
88	typedef enum CPUMDUMPTYPE
89	{
90	CPUMDUMPTYPE_TERSE,
91	CPUMDUMPTYPE_DEFAULT,
92	CPUMDUMPTYPE_VERBOSE
93	} CPUMDUMPTYPE;
94	/** Pointer to a cpu info dump type. */
95	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
96
97
98	/*******************************************************************************
99	* Internal Functions *
100	*******************************************************************************/
101	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
102	static int cpumR3CpuIdInit(PVM pVM);
103	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
104	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
106	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
107	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
108	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114
115
116	/**
117	* Initializes the CPUM.
118	*
119	* @returns VBox status code.
120	* @param pVM The VM to operate on.
121	*/
122	VMMR3DECL(int) CPUMR3Init(PVM pVM)
123	{
124	LogFlow(("CPUMR3Init\n"));
125
126	/*
127	* Assert alignment and sizes.
128	*/
129	AssertCompileMemberAlignment(VM, cpum.s, 32);
130	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
131	AssertCompileSizeAlignment(CPUMCTX, 64);
132	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
133	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
134	AssertCompileMemberAlignment(VM, cpum, 64);
135	AssertCompileMemberAlignment(VM, aCpus, 64);
136	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
137	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
138
139	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
140	pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
141	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
142
143	/* Calculate the offset from CPUMCPU to CPUM. */
144	for (VMCPUID i = 0; i < pVM->cCpus; i++)
145	{
146	PVMCPU pVCpu = &pVM->aCpus[i];
147
148	/*
149	* Setup any fixed pointers and offsets.
150	*/
151	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
152	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
153
154	pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
155	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
156	}
157
158	/*
159	* Check that the CPU supports the minimum features we require.
160	*/
161	if (!ASMHasCpuId())
162	{
163	Log(("The CPU doesn't support CPUID!\n"));
164	return VERR_UNSUPPORTED_CPU;
165	}
166	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
167	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
168
169	/* Setup the CR4 AND and OR masks used in the switcher */
170	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
171	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
172	{
173	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
174	/* No FXSAVE implies no SSE */
175	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
176	pVM->cpum.s.CR4.OrMask = 0;
177	}
178	else
179	{
180	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
181	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
182	}
183
184	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
185	{
186	Log(("The CPU doesn't support MMX!\n"));
187	return VERR_UNSUPPORTED_CPU;
188	}
189	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
190	{
191	Log(("The CPU doesn't support TSC!\n"));
192	return VERR_UNSUPPORTED_CPU;
193	}
194	/* Bogus on AMD? */
195	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
196	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
197
198	/*
199	* Detech the host CPU vendor.
200	* (The guest CPU vendor is re-detected later on.)
201	*/
202	uint32_t uEAX, uEBX, uECX, uEDX;
203	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
204	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
205	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
206
207	/*
208	* Setup hypervisor startup values.
209	*/
210
211	/*
212	* Register saved state data item.
213	*/
214	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
215	NULL, cpumR3LiveExec, NULL,
216	NULL, cpumR3SaveExec, NULL,
217	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
218	if (RT_FAILURE(rc))
219	return rc;
220
221	/*
222	* Register info handlers.
223	*/
224	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
225	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
227	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
228	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
229	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
230
231	/*
232	* Initialize the Guest CPUID state.
233	*/
234	rc = cpumR3CpuIdInit(pVM);
235	if (RT_FAILURE(rc))
236	return rc;
237	CPUMR3Reset(pVM);
238	return VINF_SUCCESS;
239	}
240
241
242	/**
243	* Initializes the per-VCPU CPUM.
244	*
245	* @returns VBox status code.
246	* @param pVM The VM to operate on.
247	*/
248	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
249	{
250	LogFlow(("CPUMR3InitCPU\n"));
251	return VINF_SUCCESS;
252	}
253
254
255	/**
256	* Detect the CPU vendor give n the
257	*
258	* @returns The vendor.
259	* @param uEAX EAX from CPUID(0).
260	* @param uEBX EBX from CPUID(0).
261	* @param uECX ECX from CPUID(0).
262	* @param uEDX EDX from CPUID(0).
263	*/
264	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
265	{
266	if ( uEAX >= 1
267	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
268	&& uECX == X86_CPUID_VENDOR_AMD_ECX
269	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
270	return CPUMCPUVENDOR_AMD;
271
272	if ( uEAX >= 1
273	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
274	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
275	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
276	return CPUMCPUVENDOR_INTEL;
277
278	/** @todo detect the other buggers... */
279	return CPUMCPUVENDOR_UNKNOWN;
280	}
281
282
283	/**
284	* Fetches overrides for a CPUID leaf.
285	*
286	* @returns VBox status code.
287	* @param pLeaf The leaf to load the overrides into.
288	* @param pCfgNode The CFGM node containing the overrides
289	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
290	* @param iLeaf The CPUID leaf number.
291	*/
292	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
293	{
294	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
295	if (pLeafNode)
296	{
297	uint32_t u32;
298	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
299	if (RT_SUCCESS(rc))
300	pLeaf->eax = u32;
301	else
302	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
303
304	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
305	if (RT_SUCCESS(rc))
306	pLeaf->ebx = u32;
307	else
308	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
309
310	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
311	if (RT_SUCCESS(rc))
312	pLeaf->ecx = u32;
313	else
314	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
315
316	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
317	if (RT_SUCCESS(rc))
318	pLeaf->edx = u32;
319	else
320	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
321
322	}
323	return VINF_SUCCESS;
324	}
325
326
327	/**
328	* Load the overrides for a set of CPUID leafs.
329	*
330	* @returns VBox status code.
331	* @param paLeafs The leaf array.
332	* @param cLeafs The number of leafs.
333	* @param uStart The start leaf number.
334	* @param pCfgNode The CFGM node containing the overrides
335	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
336	*/
337	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
338	{
339	for (uint32_t i = 0; i < cLeafs; i++)
340	{
341	int rc = cpumR3CpuIdFetchLeafOverride(&paLeafs[i], pCfgNode, uStart + i);
342	if (RT_FAILURE(rc))
343	return rc;
344	}
345
346	return VINF_SUCCESS;
347	}
348
349	/**
350	* Init a set of host CPUID leafs.
351	*
352	* @returns VBox status code.
353	* @param paLeafs The leaf array.
354	* @param cLeafs The number of leafs.
355	* @param uStart The start leaf number.
356	* @param pCfgNode The /CPUM/HostCPUID/ node.
357	*/
358	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
359	{
360	/* Using the ECX variant for all of them can't hurt... */
361	for (uint32_t i = 0; i < cLeafs; i++)
362	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeafs[i].eax, &paLeafs[i].ebx, &paLeafs[i].ecx, &paLeafs[i].edx);
363
364	/* Load CPUID leaf override; we currently don't care if the caller
365	specifies features the host CPU doesn't support. */
366	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeafs, cLeafs, pCfgNode);
367	}
368
369
370	/**
371	* Initializes the emulated CPU's cpuid information.
372	*
373	* @returns VBox status code.
374	* @param pVM The VM to operate on.
375	*/
376	static int cpumR3CpuIdInit(PVM pVM)
377	{
378	PCPUM pCPUM = &pVM->cpum.s;
379	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
380	uint32_t i;
381	int rc;
382
383	/*
384	* Get the host CPUIDs and redetect the guest CPU vendor (could've been overridden).
385	*/
386	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
387	* Overrides the host CPUID leaf values used for calculating the guest CPUID
388	* leafs. This can be used to preserve the CPUID values when moving a VM to
389	* a different machine. Another use is restricting (or extending) the
390	* feature set exposed to the guest. */
391	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
392	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
393	AssertRCReturn(rc, rc);
394	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
395	AssertRCReturn(rc, rc);
396	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
397	AssertRCReturn(rc, rc);
398
399	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
400	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
401
402	/*
403	* Only report features we can support.
404	*/
405	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
406	\| X86_CPUID_FEATURE_EDX_VME
407	\| X86_CPUID_FEATURE_EDX_DE
408	\| X86_CPUID_FEATURE_EDX_PSE
409	\| X86_CPUID_FEATURE_EDX_TSC
410	\| X86_CPUID_FEATURE_EDX_MSR
411	//\| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
412	\| X86_CPUID_FEATURE_EDX_MCE
413	\| X86_CPUID_FEATURE_EDX_CX8
414	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
415	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
416	//\| X86_CPUID_FEATURE_EDX_SEP
417	\| X86_CPUID_FEATURE_EDX_MTRR
418	\| X86_CPUID_FEATURE_EDX_PGE
419	\| X86_CPUID_FEATURE_EDX_MCA
420	\| X86_CPUID_FEATURE_EDX_CMOV
421	\| X86_CPUID_FEATURE_EDX_PAT
422	\| X86_CPUID_FEATURE_EDX_PSE36
423	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
424	\| X86_CPUID_FEATURE_EDX_CLFSH
425	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
426	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
427	\| X86_CPUID_FEATURE_EDX_MMX
428	\| X86_CPUID_FEATURE_EDX_FXSR
429	\| X86_CPUID_FEATURE_EDX_SSE
430	\| X86_CPUID_FEATURE_EDX_SSE2
431	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
432	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
433	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
434	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
435	\| 0;
436	pCPUM->aGuestCpuIdStd[1].ecx &= 0
437	\| X86_CPUID_FEATURE_ECX_SSE3
438	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
439	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
440	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
441	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
442	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
443	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
444	\| X86_CPUID_FEATURE_ECX_SSSE3
445	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
446	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
447	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
448	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
449	/* ECX Bit 21 - x2APIC support - not yet. */
450	// \| X86_CPUID_FEATURE_ECX_X2APIC
451	/* ECX Bit 23 - POPCNT instruction. */
452	//\| X86_CPUID_FEATURE_ECX_POPCNT
453	\| 0;
454
455	/* ASSUMES that this is ALWAYS the AMD define feature set if present. */
456	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
457	\| X86_CPUID_AMD_FEATURE_EDX_VME
458	\| X86_CPUID_AMD_FEATURE_EDX_DE
459	\| X86_CPUID_AMD_FEATURE_EDX_PSE
460	\| X86_CPUID_AMD_FEATURE_EDX_TSC
461	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
462	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
463	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
464	\| X86_CPUID_AMD_FEATURE_EDX_CX8
465	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
466	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
467	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
468	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
469	\| X86_CPUID_AMD_FEATURE_EDX_PGE
470	\| X86_CPUID_AMD_FEATURE_EDX_MCA
471	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
472	\| X86_CPUID_AMD_FEATURE_EDX_PAT
473	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
474	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
475	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
476	\| X86_CPUID_AMD_FEATURE_EDX_MMX
477	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
478	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
479	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
480	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
481	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
482	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
483	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
484	\| 0;
485	pCPUM->aGuestCpuIdExt[1].ecx &= 0
486	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
487	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
488	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
489	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
490	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
491	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
492	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
493	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
494	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
495	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
496	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
497	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
498	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
499	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
500	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
501	\| 0;
502
503	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false); AssertRCReturn(rc, rc);
504	if (pCPUM->fSyntheticCpu)
505	{
506	const char szVendor[13] = "VirtualBox ";
507	const char szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
508
509	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
510
511	/* Limit the nr of standard leaves; 5 for monitor/mwait */
512	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
513
514	/* 0: Vendor */
515	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)szVendor)[0];
516	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)szVendor)[2];
517	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)szVendor)[1];
518
519	/* 1.eax: Version information. family : model : stepping */
520	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
521
522	/* Leaves 2 - 4 are Intel only - zero them out */
523	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
524	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
525	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
526
527	/* Leaf 5 = monitor/mwait */
528
529	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
530	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
531	/* AMD only - set to zero. */
532	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
533
534	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
535	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
536
537	/* 0x800000002-4: Processor Name String Identifier. */
538	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)szProcessor)[0];
539	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)szProcessor)[1];
540	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)szProcessor)[2];
541	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)szProcessor)[3];
542	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)szProcessor)[4];
543	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)szProcessor)[5];
544	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)szProcessor)[6];
545	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)szProcessor)[7];
546	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)szProcessor)[8];
547	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)szProcessor)[9];
548	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)szProcessor)[10];
549	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)szProcessor)[11];
550
551	/* 0x800000005-7 - reserved -> zero */
552	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
553	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
554	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
555
556	/* 0x800000008: only the max virtual and physical address size. */
557	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
558	}
559
560	/*
561	* Hide HTT, multicode, SMP, whatever.
562	* (APIC-ID := 0 and #LogCpus := 0)
563	*/
564	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
565	#ifdef VBOX_WITH_MULTI_CORE
566	if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
567	&& pVM->cCpus > 1)
568	{
569	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
570	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
571	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
572	}
573	#endif
574
575	/* Cpuid 2:
576	* Intel: Cache and TLB information
577	* AMD: Reserved
578	* Safe to expose
579	*/
580
581	/* Cpuid 3:
582	* Intel: EAX, EBX - reserved
583	* ECX, EDX - Processor Serial Number if available, otherwise reserved
584	* AMD: Reserved
585	* Safe to expose
586	*/
587	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
588	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
589
590	/* Cpuid 4:
591	* Intel: Deterministic Cache Parameters Leaf
592	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
593	* AMD: Reserved
594	* Safe to expose, except for EAX:
595	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
596	* Bits 31-26: Maximum number of processor cores in this physical package**
597	* Note: These SMP values are constant regardless of ECX
598	*/
599	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
600	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
601	#ifdef VBOX_WITH_MULTI_CORE
602	if ( pVM->cCpus > 1
603	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
604	{
605	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
606	/* One logical processor with possibly multiple cores. */
607	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
608	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
609	}
610	#endif
611
612	/* Cpuid 5: Monitor/mwait Leaf
613	* Intel: ECX, EDX - reserved
614	* EAX, EBX - Smallest and largest monitor line size
615	* AMD: EDX - reserved
616	* EAX, EBX - Smallest and largest monitor line size
617	* ECX - extensions (ignored for now)
618	* Safe to expose
619	*/
620	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
621	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
622
623	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
624	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
625	* Expose MWAIT extended features to the guest.
626	* For now we expose just MWAIT break on interrupt feature (bit 1)
627	*/
628	bool fMWaitExtensions;
629	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
630	if (fMWaitExtensions)
631	pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
632
633	/*
634	* Determine the default.
635	*
636	* Intel returns values of the highest standard function, while AMD
637	* returns zeros. VIA on the other hand seems to returning nothing or
638	* perhaps some random garbage, we don't try to duplicate this behavior.
639	*/
640	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
641	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
642	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
643
644	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
645	* Safe to pass on to the guest.
646	*
647	* Intel: 0x800000005 reserved
648	* 0x800000006 L2 cache information
649	* AMD: 0x800000005 L1 cache information
650	* 0x800000006 L2/L3 cache information
651	*/
652
653	/* Cpuid 0x800000007:
654	* AMD: EAX, EBX, ECX - reserved
655	* EDX: Advanced Power Management Information
656	* Intel: Reserved
657	*/
658	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
659	{
660	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
661
662	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
663
664	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
665	{
666	/* Only expose the TSC invariant capability bit to the guest. */
667	pCPUM->aGuestCpuIdExt[7].edx &= 0
668	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
669	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
670	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
671	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
672	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
673	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
674	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
675	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
676	#if 1
677	/* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
678	* that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
679	*/
680	#else
681	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
682	#endif
683	\| 0;
684	}
685	else
686	pCPUM->aGuestCpuIdExt[7].edx = 0;
687	}
688
689	/* Cpuid 0x800000008:
690	* AMD: EBX, EDX - reserved
691	* EAX: Virtual/Physical address Size
692	* ECX: Number of cores + APICIdCoreIdSize
693	* Intel: EAX: Virtual/Physical address Size
694	* EBX, ECX, EDX - reserved
695	*/
696	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
697	{
698	/* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
699	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
700	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
701	* NC (0-7) Number of cores; 0 equals 1 core */
702	pCPUM->aGuestCpuIdExt[8].ecx = 0;
703	#ifdef VBOX_WITH_MULTI_CORE
704	if ( pVM->cCpus > 1
705	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
706	{
707	/* Legacy method to determine the number of cores. */
708	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
709	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
710
711	}
712	#endif
713	}
714
715	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
716	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
717	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
718	* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
719	*/
720	bool fNt4LeafLimit;
721	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
722	if (fNt4LeafLimit)
723	pCPUM->aGuestCpuIdStd[0].eax = 3;
724
725	/*
726	* Limit it the number of entries and fill the remaining with the defaults.
727	*
728	* The limits are masking off stuff about power saving and similar, this
729	* is perhaps a bit crudely done as there is probably some relatively harmless
730	* info too in these leaves (like words about having a constant TSC).
731	*/
732	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
733	pCPUM->aGuestCpuIdStd[0].eax = 5;
734
735	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
736	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
737
738	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
739	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
740	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
741	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
742	: 0;
743	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
744	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
745
746	/*
747	* Centaur stuff (VIA).
748	*
749	* The important part here (we think) is to make sure the 0xc0000000
750	* function returns 0xc0000001. As for the features, we don't currently
751	* let on about any of those... 0xc0000002 seems to be some
752	* temperature/hz/++ stuff, include it as well (static).
753	*/
754	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
755	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
756	{
757	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
758	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
759	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
760	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
761	i++)
762	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
763	}
764	else
765	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
766	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
767
768
769	/*
770	* Load CPUID overrides from configuration.
771	* Note: Kind of redundant now, but allows unchanged overrides
772	*/
773	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
774	* Overrides the CPUID leaf values. */
775	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
776	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
777	AssertRCReturn(rc, rc);
778	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
779	AssertRCReturn(rc, rc);
780	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
781	AssertRCReturn(rc, rc);
782
783	/*
784	* Check if PAE was explicitely enabled by the user.
785	*/
786	bool fEnable;
787	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
788	if (fEnable)
789	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
790
791	/*
792	* Log the cpuid and we're good.
793	*/
794	RTCPUSET OnlineSet;
795	LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
796	(int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
797	LogRel(("*********************** CPUID dump **********************\n"));
798	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
799	LogRel(("\n"));
800	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
801	LogRel(("****************** End of CPUID dump ********************\n"));
802	return VINF_SUCCESS;
803	}
804
805
806
807
808	/**
809	* Applies relocations to data and code managed by this
810	* component. This function will be called at init and
811	* whenever the VMM need to relocate it self inside the GC.
812	*
813	* The CPUM will update the addresses used by the switcher.
814	*
815	* @param pVM The VM.
816	*/
817	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
818	{
819	LogFlow(("CPUMR3Relocate\n"));
820	for (VMCPUID i = 0; i < pVM->cCpus; i++)
821	{
822	/*
823	* Switcher pointers.
824	*/
825	PVMCPU pVCpu = &pVM->aCpus[i];
826	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
827	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
828
829	}
830	}
831
832
833	/**
834	* Apply late CPUM property changes based on the fHWVirtEx setting
835	*
836	* @param pVM The VM to operate on.
837	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
838	*/
839	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
840	{
841	/*
842	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
843	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
844	* of processors from (cpuid(4).eax >> 26) + 1.
845	*
846	* Note: this code is obsolete, but let's keep it here for reference.
847	* Purpose is valid when we artifically cap the max std id to less than 4.
848	*/
849	if (!fHWVirtExEnabled)
850	{
851	Assert(pVM->cpum.s.aGuestCpuIdStd[4].eax == 0);
852	pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
853	}
854	}
855
856	/**
857	* Terminates the CPUM.
858	*
859	* Termination means cleaning up and freeing all resources,
860	* the VM it self is at this point powered off or suspended.
861	*
862	* @returns VBox status code.
863	* @param pVM The VM to operate on.
864	*/
865	VMMR3DECL(int) CPUMR3Term(PVM pVM)
866	{
867	CPUMR3TermCPU(pVM);
868	return 0;
869	}
870
871
872	/**
873	* Terminates the per-VCPU CPUM.
874	*
875	* Termination means cleaning up and freeing all resources,
876	* the VM it self is at this point powered off or suspended.
877	*
878	* @returns VBox status code.
879	* @param pVM The VM to operate on.
880	*/
881	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
882	{
883	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
884	for (VMCPUID i = 0; i < pVM->cCpus; i++)
885	{
886	PVMCPU pVCpu = &pVM->aCpus[i];
887	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
888
889	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
890	pVCpu->cpum.s.uMagic = 0;
891	pCtx->dr[5] = 0;
892	}
893	#endif
894	return 0;
895	}
896
897
898	/**
899	* Resets a virtual CPU.
900	*
901	* Used by CPUMR3Reset and CPU hot plugging.
902	*
903	* @param pVCpu The virtual CPU handle.
904	*/
905	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
906	{
907	/** @todo anything different for VCPU > 0? */
908	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
909
910	/*
911	* Initialize everything to ZERO first.
912	*/
913	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
914	memset(pCtx, 0, sizeof(*pCtx));
915	pVCpu->cpum.s.fUseFlags = fUseFlags;
916
917	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
918	pCtx->eip = 0x0000fff0;
919	pCtx->edx = 0x00000600; /* P6 processor */
920	pCtx->eflags.Bits.u1Reserved0 = 1;
921
922	pCtx->cs = 0xf000;
923	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
924	pCtx->csHid.u32Limit = 0x0000ffff;
925	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
926	pCtx->csHid.Attr.n.u1Present = 1;
927	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
928
929	pCtx->dsHid.u32Limit = 0x0000ffff;
930	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
931	pCtx->dsHid.Attr.n.u1Present = 1;
932	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
933
934	pCtx->esHid.u32Limit = 0x0000ffff;
935	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
936	pCtx->esHid.Attr.n.u1Present = 1;
937	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
938
939	pCtx->fsHid.u32Limit = 0x0000ffff;
940	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
941	pCtx->fsHid.Attr.n.u1Present = 1;
942	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
943
944	pCtx->gsHid.u32Limit = 0x0000ffff;
945	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
946	pCtx->gsHid.Attr.n.u1Present = 1;
947	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
948
949	pCtx->ssHid.u32Limit = 0x0000ffff;
950	pCtx->ssHid.Attr.n.u1Present = 1;
951	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
952	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
953
954	pCtx->idtr.cbIdt = 0xffff;
955	pCtx->gdtr.cbGdt = 0xffff;
956
957	pCtx->ldtrHid.u32Limit = 0xffff;
958	pCtx->ldtrHid.Attr.n.u1Present = 1;
959	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
960
961	pCtx->trHid.u32Limit = 0xffff;
962	pCtx->trHid.Attr.n.u1Present = 1;
963	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
964
965	pCtx->dr[6] = X86_DR6_INIT_VAL;
966	pCtx->dr[7] = X86_DR7_INIT_VAL;
967
968	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
969	pCtx->fpu.FCW = 0x37f;
970
971	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
972	pCtx->fpu.MXCSR = 0x1F80;
973
974	/* Init PAT MSR */
975	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
976
977	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
978	* The Intel docs don't mention it.
979	*/
980	pCtx->msrEFER = 0;
981	}
982
983
984	/**
985	* Resets the CPU.
986	*
987	* @returns VINF_SUCCESS.
988	* @param pVM The VM handle.
989	*/
990	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
991	{
992	for (VMCPUID i = 0; i < pVM->cCpus; i++)
993	{
994	CPUMR3ResetCpu(&pVM->aCpus[i]);
995
996	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
997	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
998
999	/* Magic marker for searching in crash dumps. */
1000	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1001	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1002	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1003	#endif
1004	}
1005	}
1006
1007
1008	/**
1009	* Called both in pass 0 and the final pass.
1010	*
1011	* @param pVM The VM handle.
1012	* @param pSSM The saved state handle.
1013	*/
1014	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1015	{
1016	/*
1017	* Save all the CPU ID leaves here so we can check them for compatability
1018	* upon loading.
1019	*/
1020	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1021	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1022
1023	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1024	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1025
1026	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1027	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1028
1029	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1030
1031	/*
1032	* Save a good portion of the raw CPU IDs as well as they may come in
1033	* handy when validating features for raw mode.
1034	*/
1035	CPUMCPUID aRawStd[16];
1036	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1037	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1038	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1039	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1040
1041	CPUMCPUID aRawExt[32];
1042	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1043	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1044	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1045	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1046	}
1047
1048
1049	/**
1050	* Loads the CPU ID leaves saved by pass 0.
1051	*
1052	* @returns VBox status code.
1053	* @param pVM The VM handle.
1054	* @param pSSM The saved state handle.
1055	* @param uVersion The format version.
1056	*/
1057	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1058	{
1059	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1060
1061	/*
1062	* Define a bunch of macros for simplifying the code.
1063	*/
1064	/* Generic expression + failure message. */
1065	#define CPUID_CHECK_RET(expr, fmt) \
1066	do { \
1067	if (!(expr)) \
1068	{ \
1069	char pszMsg = RTStrAPrintf2 fmt; / lack of variadict macros sucks */ \
1070	if (fStrictCpuIdChecks) \
1071	{ \
1072	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1073	RTStrFree(pszMsg); \
1074	return rcCpuid; \
1075	} \
1076	LogRel(("CPUM: %s\n", pszMsg)); \
1077	RTStrFree(pszMsg); \
1078	} \
1079	} while (0)
1080	#define CPUID_CHECK_WRN(expr, fmt) \
1081	do { \
1082	if (!(expr)) \
1083	LogRel(fmt); \
1084	} while (0)
1085
1086	/* For comparing two values and bitch if they differs. */
1087	#define CPUID_CHECK2_RET(what, host, saved) \
1088	do { \
1089	if ((host) != (saved)) \
1090	{ \
1091	if (fStrictCpuIdChecks) \
1092	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1093	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1094	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1095	} \
1096	} while (0)
1097	#define CPUID_CHECK2_WRN(what, host, saved) \
1098	do { \
1099	if ((host) != (saved)) \
1100	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1101	} while (0)
1102
1103	/* For checking raw cpu features (raw mode). */
1104	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1105	do { \
1106	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1107	{ \
1108	if (fStrictCpuIdChecks) \
1109	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1110	N_(#bit " mismatch: host=%d saved=%d"), \
1111	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1112	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1113	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1114	} \
1115	} while (0)
1116	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1117	do { \
1118	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1119	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1120	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1121	} while (0)
1122	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1123
1124	/* For checking guest features. */
1125	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1126	do { \
1127	if ( (aGuestCpuId##set [1].reg & bit) \
1128	&& !(aHostRaw##set [1].reg & bit) \
1129	&& !(aHostOverride##set [1].reg & bit) \
1130	&& !(aGuestOverride##set [1].reg & bit) \
1131	) \
1132	{ \
1133	if (fStrictCpuIdChecks) \
1134	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1135	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1136	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1137	} \
1138	} while (0)
1139	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1140	do { \
1141	if ( (aGuestCpuId##set [1].reg & bit) \
1142	&& !(aHostRaw##set [1].reg & bit) \
1143	&& !(aHostOverride##set [1].reg & bit) \
1144	&& !(aGuestOverride##set [1].reg & bit) \
1145	) \
1146	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1147	} while (0)
1148	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1149	do { \
1150	if ( (aGuestCpuId##set [1].reg & bit) \
1151	&& !(aHostRaw##set [1].reg & bit) \
1152	&& !(aHostOverride##set [1].reg & bit) \
1153	&& !(aGuestOverride##set [1].reg & bit) \
1154	) \
1155	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1156	} while (0)
1157	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1158
1159	/* For checking guest features if AMD guest CPU. */
1160	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1161	do { \
1162	if ( (aGuestCpuId##set [1].reg & bit) \
1163	&& fGuestAmd \
1164	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1165	&& !(aHostOverride##set [1].reg & bit) \
1166	&& !(aGuestOverride##set [1].reg & bit) \
1167	) \
1168	{ \
1169	if (fStrictCpuIdChecks) \
1170	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1171	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1172	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1173	} \
1174	} while (0)
1175	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1176	do { \
1177	if ( (aGuestCpuId##set [1].reg & bit) \
1178	&& fGuestAmd \
1179	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1180	&& !(aHostOverride##set [1].reg & bit) \
1181	&& !(aGuestOverride##set [1].reg & bit) \
1182	) \
1183	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1184	} while (0)
1185	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1186	do { \
1187	if ( (aGuestCpuId##set [1].reg & bit) \
1188	&& fGuestAmd \
1189	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1190	&& !(aHostOverride##set [1].reg & bit) \
1191	&& !(aGuestOverride##set [1].reg & bit) \
1192	) \
1193	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1194	} while (0)
1195	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1196
1197	/* For checking AMD features which have a corresponding bit in the standard
1198	range. (Intel defines very few bits in the extended feature sets.) */
1199	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1200	do { \
1201	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1202	&& !(fHostAmd \
1203	? aHostRawExt[1].reg & (ExtBit) \
1204	: aHostRawStd[1].reg & (StdBit)) \
1205	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1206	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1207	) \
1208	{ \
1209	if (fStrictCpuIdChecks) \
1210	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1211	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1212	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1213	} \
1214	} while (0)
1215	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1216	do { \
1217	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1218	&& !(fHostAmd \
1219	? aHostRawExt[1].reg & (ExtBit) \
1220	: aHostRawStd[1].reg & (StdBit)) \
1221	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1222	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1223	) \
1224	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1225	} while (0)
1226	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1227	do { \
1228	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1229	&& !(fHostAmd \
1230	? aHostRawExt[1].reg & (ExtBit) \
1231	: aHostRawStd[1].reg & (StdBit)) \
1232	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1233	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1234	) \
1235	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1236	} while (0)
1237	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1238
1239	/*
1240	* Load them into stack buffers first.
1241	*/
1242	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1243	uint32_t cGuestCpuIdStd;
1244	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1245	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1246	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1247	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1248
1249	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1250	uint32_t cGuestCpuIdExt;
1251	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1252	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1253	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1254	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1255
1256	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1257	uint32_t cGuestCpuIdCentaur;
1258	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1259	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1260	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1261	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1262
1263	CPUMCPUID GuestCpuIdDef;
1264	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1265	AssertRCReturn(rc, rc);
1266
1267	CPUMCPUID aRawStd[16];
1268	uint32_t cRawStd;
1269	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1270	if (cRawStd > RT_ELEMENTS(aRawStd))
1271	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1272	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1273
1274	CPUMCPUID aRawExt[32];
1275	uint32_t cRawExt;
1276	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1277	if (cRawExt > RT_ELEMENTS(aRawExt))
1278	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1279	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1280	AssertRCReturn(rc, rc);
1281
1282	/*
1283	* Note that we support restoring less than the current amount of standard
1284	* leaves because we've been allowed more is newer version of VBox.
1285	*
1286	* So, pad new entries with the default.
1287	*/
1288	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1289	aGuestCpuIdStd[i] = GuestCpuIdDef;
1290
1291	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1292	aGuestCpuIdExt[i] = GuestCpuIdDef;
1293
1294	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1295	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1296
1297	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1298	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1299
1300	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1301	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1302
1303	/*
1304	* Get the raw CPU IDs for the current host.
1305	*/
1306	CPUMCPUID aHostRawStd[16];
1307	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1308	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1309
1310	CPUMCPUID aHostRawExt[32];
1311	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1312	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1313
1314	/*
1315	* Get the host and guest overrides so we don't reject the state because
1316	* some feature was enabled thru these interfaces.
1317	* Note! We currently only need the feature leafs, so skip rest.
1318	*/
1319	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1320	CPUMCPUID aGuestOverrideStd[2];
1321	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1322	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1323
1324	CPUMCPUID aGuestOverrideExt[2];
1325	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1326	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1327
1328	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1329	CPUMCPUID aHostOverrideStd[2];
1330	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1331	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1332
1333	CPUMCPUID aHostOverrideExt[2];
1334	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1335	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1336
1337	/*
1338	* This can be skipped.
1339	*/
1340	bool fStrictCpuIdChecks;
1341	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1342
1343
1344
1345	/*
1346	* For raw-mode we'll require that the CPUs are very similar since we don't
1347	* intercept CPUID instructions for user mode applications.
1348	*/
1349	if (!HWACCMIsEnabled(pVM))
1350	{
1351	/* CPUID(0) */
1352	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1353	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1354	&& aHostRawStd[0].edx == aRawStd[0].edx,
1355	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1356	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1357	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1358	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1359	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1360	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1361
1362	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1363
1364	/* CPUID(1).eax */
1365	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1366	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1367	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1368
1369	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1370	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1371	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1372
1373	/* CPUID(1).ecx */
1374	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1375	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1376	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1377	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1378	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1379	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1380	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1381	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1382	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1383	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1384	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1385	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1386	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1387	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1388	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1389	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1390	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1391	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1392	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1393	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1394	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1395	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1396	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1397	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1398	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1399	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1400	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1401	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1402	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1403	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1404	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1405	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1406
1407	/* CPUID(1).edx */
1408	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1409	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1410	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1411	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1412	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1413	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1414	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1415	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1416	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1417	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1418	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1419	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1420	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1421	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1422	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1423	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1424	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1425	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1426	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1427	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1428	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1429	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1430	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1431	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1432	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1433	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1434	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1435	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1436	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1437	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1438	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1439	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1440
1441	/* CPUID(2) - config, mostly about caches. ignore. */
1442	/* CPUID(3) - processor serial number. ignore. */
1443	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1444	/* CPUID(5) - mwait/monitor config. ignore. */
1445	/* CPUID(6) - power management. ignore. */
1446	/* CPUID(7) - ???. ignore. */
1447	/* CPUID(8) - ???. ignore. */
1448	/* CPUID(9) - DCA. ignore for now. */
1449	/* CPUID(a) - PeMo info. ignore for now. */
1450	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1451
1452	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1453	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1454	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1455	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1456	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1457	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1458	{
1459	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1460	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1461	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1462	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1463	}
1464
1465	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1466	Note! Intel have/is marking many of the fields here as reserved. We
1467	will verify them as if it's an AMD CPU. */
1468	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1469	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1470	(N_("Extended leafs was present on saved state host, but is missing on the current\n")));
1471	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1472	{
1473	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1474	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1475	&& aHostRawExt[0].edx == aRawExt[0].edx,
1476	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1477	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1478	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1479	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1480
1481	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1482	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1483	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1484	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1485	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1486	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1487
1488	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1489	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1490	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1491	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1492
1493	/* CPUID(0x80000001).ecx */
1494	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1495	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1496	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1497	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1498	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1499	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1500	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1501	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1502	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1503	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1504	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1505	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1506	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1507	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1508	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1509	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1510	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1511	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1512	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1513	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1514	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1515	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1516	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1517	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1518	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1519	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1520	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1521	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1522	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1523	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1524	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1525	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1526
1527	/* CPUID(0x80000001).edx */
1528	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1529	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1530	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1531	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1532	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1533	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1534	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1535	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1536	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1537	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1538	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1539	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1540	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1541	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1542	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1543	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1544	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1545	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1546	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1547	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1548	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1549	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1550	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1551	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1552	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1553	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1554	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1555	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1556	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1557	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1558	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1559	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1560
1561	/** @todo verify the rest as well. */
1562	}
1563	}
1564
1565
1566
1567	/*
1568	* Verify that we can support the features already exposed to the guest on
1569	* this host.
1570	*
1571	* Most of the features we're emulating requires intercepting instruction
1572	* and doing it the slow way, so there is no need to warn when they aren't
1573	* present in the host CPU. Thus we use IGN instead of EMU on these.
1574	*
1575	* Trailing comments:
1576	* "EMU" - Possible to emulate, could be lots of work and very slow.
1577	* "EMU?" - Can this be emulated?
1578	*/
1579	/* CPUID(1).ecx */
1580	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1581	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1582	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1583	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1584	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1585	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1586	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1587	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1588	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1589	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1590	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1591	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1592	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1593	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1594	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1595	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1596	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1597	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1598	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1599	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1600	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1601	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1602	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1603	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1604	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1605	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1606	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1607	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1608	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1609	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1610	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1611	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1612
1613	/* CPUID(1).edx */
1614	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1615	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1616	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1617	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1618	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1619	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1620	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1621	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1622	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1623	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1624	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1625	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1626	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1627	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1628	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1629	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1630	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1631	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1632	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1633	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1634	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1635	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1636	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1637	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1638	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1639	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1640	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1641	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1642	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1643	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1644	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1645	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1646
1647	/* CPUID(0x80000000). */
1648	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1649	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1650	{
1651	/** @todo deal with no 0x80000001 on the host. */
1652	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1653	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1654
1655	/* CPUID(0x80000001).ecx */
1656	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1657	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1658	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1659	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1660	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1661	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1662	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1663	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1664	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1665	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1666	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1667	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1668	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1669	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1670	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1671	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1672	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1673	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1674	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1675	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1676	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1677	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1678	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1679	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1680	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1681	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1682	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1683	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1684	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1685	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1686	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1687	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1688
1689	/* CPUID(0x80000001).edx */
1690	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1691	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1692	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1693	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1694	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1695	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1696	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1697	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1698	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1699	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1700	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1701	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1702	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1703	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1704	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1705	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1706	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1707	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1708	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1709	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1710	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1711	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1712	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1713	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1714	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1715	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1716	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1717	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1718	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1719	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1720	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1721	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1722	}
1723
1724	/*
1725	* We're good, commit the CPU ID leaves.
1726	*/
1727	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1728	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1729	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1730	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1731
1732	#undef CPUID_CHECK_RET
1733	#undef CPUID_CHECK_WRN
1734	#undef CPUID_CHECK2_RET
1735	#undef CPUID_CHECK2_WRN
1736	#undef CPUID_RAW_FEATURE_RET
1737	#undef CPUID_RAW_FEATURE_WRN
1738	#undef CPUID_RAW_FEATURE_IGN
1739	#undef CPUID_GST_FEATURE_RET
1740	#undef CPUID_GST_FEATURE_WRN
1741	#undef CPUID_GST_FEATURE_EMU
1742	#undef CPUID_GST_FEATURE_IGN
1743	#undef CPUID_GST_FEATURE2_RET
1744	#undef CPUID_GST_FEATURE2_WRN
1745	#undef CPUID_GST_FEATURE2_EMU
1746	#undef CPUID_GST_FEATURE2_IGN
1747	#undef CPUID_GST_AMD_FEATURE_RET
1748	#undef CPUID_GST_AMD_FEATURE_WRN
1749	#undef CPUID_GST_AMD_FEATURE_EMU
1750	#undef CPUID_GST_AMD_FEATURE_IGN
1751
1752	return VINF_SUCCESS;
1753	}
1754
1755
1756	/**
1757	* Pass 0 live exec callback.
1758	*
1759	* @returns VINF_SSM_DONT_CALL_AGAIN.
1760	* @param pVM The VM handle.
1761	* @param pSSM The saved state handle.
1762	* @param uPass The pass (0).
1763	*/
1764	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1765	{
1766	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1767	cpumR3SaveCpuId(pVM, pSSM);
1768	return VINF_SSM_DONT_CALL_AGAIN;
1769	}
1770
1771
1772	/**
1773	* Execute state save operation.
1774	*
1775	* @returns VBox status code.
1776	* @param pVM VM Handle.
1777	* @param pSSM SSM operation handle.
1778	*/
1779	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1780	{
1781	/*
1782	* Save.
1783	*/
1784	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1785	{
1786	PVMCPU pVCpu = &pVM->aCpus[i];
1787
1788	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1789	}
1790
1791	SSMR3PutU32(pSSM, pVM->cCpus);
1792	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1793	{
1794	PVMCPU pVCpu = &pVM->aCpus[i];
1795
1796	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1797	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1798	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1799	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1800	}
1801
1802	cpumR3SaveCpuId(pVM, pSSM);
1803	return VINF_SUCCESS;
1804	}
1805
1806
1807	/**
1808	* Load a version 1.6 CPUMCTX structure.
1809	*
1810	* @returns VBox status code.
1811	* @param pVM VM Handle.
1812	* @param pCpumctx16 Version 1.6 CPUMCTX
1813	*/
1814	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1815	{
1816	#define CPUMCTX16_LOADREG(RegName) \
1817	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1818
1819	#define CPUMCTX16_LOADDRXREG(RegName) \
1820	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1821
1822	#define CPUMCTX16_LOADHIDREG(RegName) \
1823	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1824	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1825	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1826
1827	#define CPUMCTX16_LOADSEGREG(RegName) \
1828	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1829	CPUMCTX16_LOADHIDREG(RegName);
1830
1831	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1832
1833	CPUMCTX16_LOADREG(rax);
1834	CPUMCTX16_LOADREG(rbx);
1835	CPUMCTX16_LOADREG(rcx);
1836	CPUMCTX16_LOADREG(rdx);
1837	CPUMCTX16_LOADREG(rdi);
1838	CPUMCTX16_LOADREG(rsi);
1839	CPUMCTX16_LOADREG(rbp);
1840	CPUMCTX16_LOADREG(esp);
1841	CPUMCTX16_LOADREG(rip);
1842	CPUMCTX16_LOADREG(rflags);
1843
1844	CPUMCTX16_LOADSEGREG(cs);
1845	CPUMCTX16_LOADSEGREG(ds);
1846	CPUMCTX16_LOADSEGREG(es);
1847	CPUMCTX16_LOADSEGREG(fs);
1848	CPUMCTX16_LOADSEGREG(gs);
1849	CPUMCTX16_LOADSEGREG(ss);
1850
1851	CPUMCTX16_LOADREG(r8);
1852	CPUMCTX16_LOADREG(r9);
1853	CPUMCTX16_LOADREG(r10);
1854	CPUMCTX16_LOADREG(r11);
1855	CPUMCTX16_LOADREG(r12);
1856	CPUMCTX16_LOADREG(r13);
1857	CPUMCTX16_LOADREG(r14);
1858	CPUMCTX16_LOADREG(r15);
1859
1860	CPUMCTX16_LOADREG(cr0);
1861	CPUMCTX16_LOADREG(cr2);
1862	CPUMCTX16_LOADREG(cr3);
1863	CPUMCTX16_LOADREG(cr4);
1864
1865	CPUMCTX16_LOADDRXREG(0);
1866	CPUMCTX16_LOADDRXREG(1);
1867	CPUMCTX16_LOADDRXREG(2);
1868	CPUMCTX16_LOADDRXREG(3);
1869	CPUMCTX16_LOADDRXREG(4);
1870	CPUMCTX16_LOADDRXREG(5);
1871	CPUMCTX16_LOADDRXREG(6);
1872	CPUMCTX16_LOADDRXREG(7);
1873
1874	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
1875	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
1876	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
1877	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
1878
1879	CPUMCTX16_LOADREG(ldtr);
1880	CPUMCTX16_LOADREG(tr);
1881
1882	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
1883
1884	CPUMCTX16_LOADREG(msrEFER);
1885	CPUMCTX16_LOADREG(msrSTAR);
1886	CPUMCTX16_LOADREG(msrPAT);
1887	CPUMCTX16_LOADREG(msrLSTAR);
1888	CPUMCTX16_LOADREG(msrCSTAR);
1889	CPUMCTX16_LOADREG(msrSFMASK);
1890	CPUMCTX16_LOADREG(msrKERNELGSBASE);
1891
1892	CPUMCTX16_LOADHIDREG(ldtr);
1893	CPUMCTX16_LOADHIDREG(tr);
1894
1895	#undef CPUMCTX16_LOADSEGREG
1896	#undef CPUMCTX16_LOADHIDREG
1897	#undef CPUMCTX16_LOADDRXREG
1898	#undef CPUMCTX16_LOADREG
1899	}
1900
1901
1902	/**
1903	* @copydoc FNSSMINTLOADPREP
1904	*/
1905	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1906	{
1907	pVM->cpum.s.fPendingRestore = true;
1908	return VINF_SUCCESS;
1909	}
1910
1911
1912	/**
1913	* @copydoc FNSSMINTLOADEXEC
1914	*/
1915	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1916	{
1917	/*
1918	* Validate version.
1919	*/
1920	if ( uVersion != CPUM_SAVED_STATE_VERSION
1921	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1922	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1923	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1924	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1925	{
1926	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1927	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1928	}
1929
1930	if (uPass == SSM_PASS_FINAL)
1931	{
1932	/*
1933	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1934	* really old SSM file versions.)
1935	*/
1936	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1937	SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1938	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1939	SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1940
1941	/*
1942	* Restore.
1943	*/
1944	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1945	{
1946	PVMCPU pVCpu = &pVM->aCpus[i];
1947	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1948	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1949
1950	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1951	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1952	pVCpu->cpum.s.Hyper.esp = uESP;
1953	}
1954
1955	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1956	{
1957	CPUMCTX_VER1_6 cpumctx16;
1958	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1959	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1960
1961	/* Save the old cpumctx state into the new one. */
1962	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1963
1964	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1965	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1966	}
1967	else
1968	{
1969	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1970	{
1971	uint32_t cCpus;
1972	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1973	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1974	VERR_SSM_UNEXPECTED_DATA);
1975	}
1976	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1977	\|\| pVM->cCpus == 1,
1978	("cCpus=%u\n", pVM->cCpus),
1979	VERR_SSM_UNEXPECTED_DATA);
1980
1981	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1982	{
1983	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1984	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1985	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1986	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1987	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1988	}
1989	}
1990	}
1991
1992	pVM->cpum.s.fPendingRestore = false;
1993
1994	/*
1995	* Guest CPUIDs.
1996	*/
1997	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
1998	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1999
2000	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2001	* actually required. */
2002
2003	/*
2004	* Restore the CPUID leaves.
2005	*
2006	* Note that we support restoring less than the current amount of standard
2007	* leaves because we've been allowed more is newer version of VBox.
2008	*/
2009	uint32_t cElements;
2010	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2011	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2012	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2013	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2014
2015	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2016	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2017	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2018	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2019
2020	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2021	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2022	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2023	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2024
2025	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2026
2027	/*
2028	* Check that the basic cpuid id information is unchanged.
2029	*/
2030	/** @todo we should check the 64 bits capabilities too! */
2031	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2032	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2033	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2034	uint32_t au32CpuIdSaved[8];
2035	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2036	if (RT_SUCCESS(rc))
2037	{
2038	/* Ignore CPU stepping. */
2039	au32CpuId[4] &= 0xfffffff0;
2040	au32CpuIdSaved[4] &= 0xfffffff0;
2041
2042	/* Ignore APIC ID (AMD specs). */
2043	au32CpuId[5] &= ~0xff000000;
2044	au32CpuIdSaved[5] &= ~0xff000000;
2045
2046	/* Ignore the number of Logical CPUs (AMD specs). */
2047	au32CpuId[5] &= ~0x00ff0000;
2048	au32CpuIdSaved[5] &= ~0x00ff0000;
2049
2050	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2051	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2052	\| X86_CPUID_FEATURE_ECX_VMX
2053	\| X86_CPUID_FEATURE_ECX_SMX
2054	\| X86_CPUID_FEATURE_ECX_EST
2055	\| X86_CPUID_FEATURE_ECX_TM2
2056	\| X86_CPUID_FEATURE_ECX_CNTXID
2057	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2058	\| X86_CPUID_FEATURE_ECX_PDCM
2059	\| X86_CPUID_FEATURE_ECX_DCA
2060	\| X86_CPUID_FEATURE_ECX_X2APIC
2061	);
2062	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2063	\| X86_CPUID_FEATURE_ECX_VMX
2064	\| X86_CPUID_FEATURE_ECX_SMX
2065	\| X86_CPUID_FEATURE_ECX_EST
2066	\| X86_CPUID_FEATURE_ECX_TM2
2067	\| X86_CPUID_FEATURE_ECX_CNTXID
2068	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2069	\| X86_CPUID_FEATURE_ECX_PDCM
2070	\| X86_CPUID_FEATURE_ECX_DCA
2071	\| X86_CPUID_FEATURE_ECX_X2APIC
2072	);
2073
2074	/* Make sure we don't forget to update the masks when enabling
2075	* features in the future.
2076	*/
2077	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2078	( X86_CPUID_FEATURE_ECX_DTES64
2079	\| X86_CPUID_FEATURE_ECX_VMX
2080	\| X86_CPUID_FEATURE_ECX_SMX
2081	\| X86_CPUID_FEATURE_ECX_EST
2082	\| X86_CPUID_FEATURE_ECX_TM2
2083	\| X86_CPUID_FEATURE_ECX_CNTXID
2084	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2085	\| X86_CPUID_FEATURE_ECX_PDCM
2086	\| X86_CPUID_FEATURE_ECX_DCA
2087	\| X86_CPUID_FEATURE_ECX_X2APIC
2088	)));
2089	/* do the compare */
2090	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2091	{
2092	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2093	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2094	"Saved=%.*Rhxs\n"
2095	"Real =%.*Rhxs\n",
2096	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2097	sizeof(au32CpuId), au32CpuId));
2098	else
2099	{
2100	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2101	"Saved=%.*Rhxs\n"
2102	"Real =%.*Rhxs\n",
2103	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2104	sizeof(au32CpuId), au32CpuId));
2105	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2106	}
2107	}
2108	}
2109
2110	return rc;
2111	}
2112
2113
2114	/**
2115	* @copydoc FNSSMINTLOADPREP
2116	*/
2117	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2118	{
2119	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2120	return VINF_SUCCESS;
2121
2122	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2123	if (pVM->cpum.s.fPendingRestore)
2124	{
2125	LogRel(("CPUM: Missing state!\n"));
2126	return VERR_INTERNAL_ERROR_2;
2127	}
2128
2129	return VINF_SUCCESS;
2130	}
2131
2132
2133	/**
2134	* Checks if the CPUM state restore is still pending.
2135	*
2136	* @returns true / false.
2137	* @param pVM The VM handle.
2138	*/
2139	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2140	{
2141	return pVM->cpum.s.fPendingRestore;
2142	}
2143
2144
2145	/**
2146	* Formats the EFLAGS value into mnemonics.
2147	*
2148	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2149	* @param efl The EFLAGS value.
2150	*/
2151	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2152	{
2153	/*
2154	* Format the flags.
2155	*/
2156	static const struct
2157	{
2158	const char pszSet; const char pszClear; uint32_t fFlag;
2159	} s_aFlags[] =
2160	{
2161	{ "vip",NULL, X86_EFL_VIP },
2162	{ "vif",NULL, X86_EFL_VIF },
2163	{ "ac", NULL, X86_EFL_AC },
2164	{ "vm", NULL, X86_EFL_VM },
2165	{ "rf", NULL, X86_EFL_RF },
2166	{ "nt", NULL, X86_EFL_NT },
2167	{ "ov", "nv", X86_EFL_OF },
2168	{ "dn", "up", X86_EFL_DF },
2169	{ "ei", "di", X86_EFL_IF },
2170	{ "tf", NULL, X86_EFL_TF },
2171	{ "nt", "pl", X86_EFL_SF },
2172	{ "nz", "zr", X86_EFL_ZF },
2173	{ "ac", "na", X86_EFL_AF },
2174	{ "po", "pe", X86_EFL_PF },
2175	{ "cy", "nc", X86_EFL_CF },
2176	};
2177	char *psz = pszEFlags;
2178	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2179	{
2180	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2181	if (pszAdd)
2182	{
2183	strcpy(psz, pszAdd);
2184	psz += strlen(pszAdd);
2185	*psz++ = ' ';
2186	}
2187	}
2188	psz[-1] = '\0';
2189	}
2190
2191
2192	/**
2193	* Formats a full register dump.
2194	*
2195	* @param pVM VM Handle.
2196	* @param pCtx The context to format.
2197	* @param pCtxCore The context core to format.
2198	* @param pHlp Output functions.
2199	* @param enmType The dump type.
2200	* @param pszPrefix Register name prefix.
2201	*/
2202	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2203	{
2204	/*
2205	* Format the EFLAGS.
2206	*/
2207	uint32_t efl = pCtxCore->eflags.u32;
2208	char szEFlags[80];
2209	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2210
2211	/*
2212	* Format the registers.
2213	*/
2214	switch (enmType)
2215	{
2216	case CPUMDUMPTYPE_TERSE:
2217	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2218	pHlp->pfnPrintf(pHlp,
2219	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2220	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2221	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2222	"%sr14=%016RX64 %sr15=%016RX64\n"
2223	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2224	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2225	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2226	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2227	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2228	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2229	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2230	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2231	else
2232	pHlp->pfnPrintf(pHlp,
2233	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2234	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2235	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2236	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2237	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2238	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2239	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2240	break;
2241
2242	case CPUMDUMPTYPE_DEFAULT:
2243	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2244	pHlp->pfnPrintf(pHlp,
2245	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2246	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2247	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2248	"%sr14=%016RX64 %sr15=%016RX64\n"
2249	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2250	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2251	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2252	,
2253	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2254	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2255	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2256	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2257	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2258	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2259	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2260	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2261	else
2262	pHlp->pfnPrintf(pHlp,
2263	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2264	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2265	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2266	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2267	,
2268	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2269	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2270	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2271	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2272	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2273	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2274	break;
2275
2276	case CPUMDUMPTYPE_VERBOSE:
2277	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2278	pHlp->pfnPrintf(pHlp,
2279	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2280	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2281	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2282	"%sr14=%016RX64 %sr15=%016RX64\n"
2283	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2284	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2285	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2286	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2287	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2288	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2289	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2290	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2291	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2292	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2293	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2294	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2295	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2296	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2297	,
2298	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2299	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2300	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2301	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2302	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2303	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2304	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2305	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2306	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2307	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2308	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2309	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2310	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2311	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2312	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2313	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2314	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2315	else
2316	pHlp->pfnPrintf(pHlp,
2317	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2318	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2319	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2320	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2321	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2322	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2323	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2324	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2325	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2326	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2327	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2328	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2329	,
2330	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2331	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2332	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2333	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2334	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2335	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2336	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2337	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2338	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2339	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2340	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2341	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2342
2343	pHlp->pfnPrintf(pHlp,
2344	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2345	"%sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2346	,
2347	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2348	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2349	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2350	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2351	);
2352	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2353	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2354	{
2355	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2356	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2357	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2358	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2359	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2360	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2361	/** @todo This isn't entirenly correct and needs more work! */
2362	pHlp->pfnPrintf(pHlp,
2363	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2364	pszPrefix, iST, pszPrefix, iFPR,
2365	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2366	uTag, chSign, iInteger, u64Fraction, uExponent);
2367	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2368	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2369	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2370	else
2371	pHlp->pfnPrintf(pHlp, "\n");
2372	}
2373	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2374	pHlp->pfnPrintf(pHlp,
2375	iXMM & 1
2376	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2377	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2378	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2379	pCtx->fpu.aXMM[iXMM].au32[3],
2380	pCtx->fpu.aXMM[iXMM].au32[2],
2381	pCtx->fpu.aXMM[iXMM].au32[1],
2382	pCtx->fpu.aXMM[iXMM].au32[0]);
2383	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2384	if (pCtx->fpu.au32RsrvdRest[i])
2385	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2386	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2387
2388	pHlp->pfnPrintf(pHlp,
2389	"%sEFER =%016RX64\n"
2390	"%sPAT =%016RX64\n"
2391	"%sSTAR =%016RX64\n"
2392	"%sCSTAR =%016RX64\n"
2393	"%sLSTAR =%016RX64\n"
2394	"%sSFMASK =%016RX64\n"
2395	"%sKERNELGSBASE =%016RX64\n",
2396	pszPrefix, pCtx->msrEFER,
2397	pszPrefix, pCtx->msrPAT,
2398	pszPrefix, pCtx->msrSTAR,
2399	pszPrefix, pCtx->msrCSTAR,
2400	pszPrefix, pCtx->msrLSTAR,
2401	pszPrefix, pCtx->msrSFMASK,
2402	pszPrefix, pCtx->msrKERNELGSBASE);
2403	break;
2404	}
2405	}
2406
2407
2408	/**
2409	* Display all cpu states and any other cpum info.
2410	*
2411	* @param pVM VM Handle.
2412	* @param pHlp The info helper functions.
2413	* @param pszArgs Arguments, ignored.
2414	*/
2415	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2416	{
2417	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2418	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2419	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2420	cpumR3InfoHost(pVM, pHlp, pszArgs);
2421	}
2422
2423
2424	/**
2425	* Parses the info argument.
2426	*
2427	* The argument starts with 'verbose', 'terse' or 'default' and then
2428	* continues with the comment string.
2429	*
2430	* @param pszArgs The pointer to the argument string.
2431	* @param penmType Where to store the dump type request.
2432	* @param ppszComment Where to store the pointer to the comment string.
2433	*/
2434	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2435	{
2436	if (!pszArgs)
2437	{
2438	*penmType = CPUMDUMPTYPE_DEFAULT;
2439	*ppszComment = "";
2440	}
2441	else
2442	{
2443	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2444	{
2445	pszArgs += 5;
2446	*penmType = CPUMDUMPTYPE_VERBOSE;
2447	}
2448	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2449	{
2450	pszArgs += 5;
2451	*penmType = CPUMDUMPTYPE_TERSE;
2452	}
2453	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2454	{
2455	pszArgs += 7;
2456	*penmType = CPUMDUMPTYPE_DEFAULT;
2457	}
2458	else
2459	*penmType = CPUMDUMPTYPE_DEFAULT;
2460	*ppszComment = RTStrStripL(pszArgs);
2461	}
2462	}
2463
2464
2465	/**
2466	* Display the guest cpu state.
2467	*
2468	* @param pVM VM Handle.
2469	* @param pHlp The info helper functions.
2470	* @param pszArgs Arguments, ignored.
2471	*/
2472	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2473	{
2474	CPUMDUMPTYPE enmType;
2475	const char *pszComment;
2476	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2477
2478	/* @todo SMP support! */
2479	PVMCPU pVCpu = VMMGetCpu(pVM);
2480	if (!pVCpu)
2481	pVCpu = &pVM->aCpus[0];
2482
2483	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2484
2485	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2486	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2487	}
2488
2489
2490	/**
2491	* Display the current guest instruction
2492	*
2493	* @param pVM VM Handle.
2494	* @param pHlp The info helper functions.
2495	* @param pszArgs Arguments, ignored.
2496	*/
2497	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2498	{
2499	char szInstruction[256];
2500	/* @todo SMP support! */
2501	PVMCPU pVCpu = VMMGetCpu(pVM);
2502	if (!pVCpu)
2503	pVCpu = &pVM->aCpus[0];
2504
2505	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2506	if (RT_SUCCESS(rc))
2507	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2508	}
2509
2510
2511	/**
2512	* Display the hypervisor cpu state.
2513	*
2514	* @param pVM VM Handle.
2515	* @param pHlp The info helper functions.
2516	* @param pszArgs Arguments, ignored.
2517	*/
2518	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2519	{
2520	CPUMDUMPTYPE enmType;
2521	const char *pszComment;
2522	/* @todo SMP */
2523	PVMCPU pVCpu = &pVM->aCpus[0];
2524
2525	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2526	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2527	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2528	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2529	}
2530
2531
2532	/**
2533	* Display the host cpu state.
2534	*
2535	* @param pVM VM Handle.
2536	* @param pHlp The info helper functions.
2537	* @param pszArgs Arguments, ignored.
2538	*/
2539	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2540	{
2541	CPUMDUMPTYPE enmType;
2542	const char *pszComment;
2543	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2544	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2545
2546	/*
2547	* Format the EFLAGS.
2548	*/
2549	/* @todo SMP */
2550	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2551	#if HC_ARCH_BITS == 32
2552	uint32_t efl = pCtx->eflags.u32;
2553	#else
2554	uint64_t efl = pCtx->rflags;
2555	#endif
2556	char szEFlags[80];
2557	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2558
2559	/*
2560	* Format the registers.
2561	*/
2562	#if HC_ARCH_BITS == 32
2563	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2564	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2565	# endif
2566	{
2567	pHlp->pfnPrintf(pHlp,
2568	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2569	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2570	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2571	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2572	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2573	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2574	,
2575	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2576	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2577	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2578	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2579	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2580	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2581	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2582	}
2583	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2584	else
2585	# endif
2586	#endif
2587	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2588	{
2589	pHlp->pfnPrintf(pHlp,
2590	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2591	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2592	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2593	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2594	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2595	"r14=%016RX64 r15=%016RX64\n"
2596	"iopl=%d %31s\n"
2597	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2598	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2599	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2600	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2601	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2602	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2603	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2604	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2605	,
2606	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2607	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2608	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2609	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2610	pCtx->r11, pCtx->r12, pCtx->r13,
2611	pCtx->r14, pCtx->r15,
2612	X86_EFL_GET_IOPL(efl), szEFlags,
2613	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2614	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2615	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2616	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2617	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2618	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2619	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2620	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2621	}
2622	#endif
2623	}
2624
2625
2626	/**
2627	* Get L1 cache / TLS associativity.
2628	*/
2629	static const char getCacheAss(unsigned u, char pszBuf)
2630	{
2631	if (u == 0)
2632	return "res0 ";
2633	if (u == 1)
2634	return "direct";
2635	if (u >= 256)
2636	return "???";
2637
2638	RTStrPrintf(pszBuf, 16, "%d way", u);
2639	return pszBuf;
2640	}
2641
2642
2643	/**
2644	* Get L2 cache soociativity.
2645	*/
2646	const char *getL2CacheAss(unsigned u)
2647	{
2648	switch (u)
2649	{
2650	case 0: return "off ";
2651	case 1: return "direct";
2652	case 2: return "2 way ";
2653	case 3: return "res3 ";
2654	case 4: return "4 way ";
2655	case 5: return "res5 ";
2656	case 6: return "8 way "; case 7: return "res7 ";
2657	case 8: return "16 way";
2658	case 9: return "res9 ";
2659	case 10: return "res10 ";
2660	case 11: return "res11 ";
2661	case 12: return "res12 ";
2662	case 13: return "res13 ";
2663	case 14: return "res14 ";
2664	case 15: return "fully ";
2665	default:
2666	return "????";
2667	}
2668	}
2669
2670
2671	/**
2672	* Display the guest CpuId leaves.
2673	*
2674	* @param pVM VM Handle.
2675	* @param pHlp The info helper functions.
2676	* @param pszArgs "terse", "default" or "verbose".
2677	*/
2678	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2679	{
2680	/*
2681	* Parse the argument.
2682	*/
2683	unsigned iVerbosity = 1;
2684	if (pszArgs)
2685	{
2686	pszArgs = RTStrStripL(pszArgs);
2687	if (!strcmp(pszArgs, "terse"))
2688	iVerbosity--;
2689	else if (!strcmp(pszArgs, "verbose"))
2690	iVerbosity++;
2691	}
2692
2693	/*
2694	* Start cracking.
2695	*/
2696	CPUMCPUID Host;
2697	CPUMCPUID Guest;
2698	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2699
2700	pHlp->pfnPrintf(pHlp,
2701	" RAW Standard CPUIDs\n"
2702	" Function eax ebx ecx edx\n");
2703	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2704	{
2705	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2706	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2707
2708	pHlp->pfnPrintf(pHlp,
2709	"Gst: %08x %08x %08x %08x %08x%s\n"
2710	"Hst: %08x %08x %08x %08x\n",
2711	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2712	i <= cStdMax ? "" : "*",
2713	Host.eax, Host.ebx, Host.ecx, Host.edx);
2714	}
2715
2716	/*
2717	* If verbose, decode it.
2718	*/
2719	if (iVerbosity)
2720	{
2721	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2722	pHlp->pfnPrintf(pHlp,
2723	"Name: %.04s%.04s%.04s\n"
2724	"Supports: 0-%x\n",
2725	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2726	}
2727
2728	/*
2729	* Get Features.
2730	*/
2731	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2732	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2733	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2734	if (cStdMax >= 1 && iVerbosity)
2735	{
2736	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2737	uint32_t uEAX = Guest.eax;
2738
2739	pHlp->pfnPrintf(pHlp,
2740	"Family: %d \tExtended: %d \tEffective: %d\n"
2741	"Model: %d \tExtended: %d \tEffective: %d\n"
2742	"Stepping: %d\n"
2743	"Type: %d\n"
2744	"APIC ID: %#04x\n"
2745	"Logical CPUs: %d\n"
2746	"CLFLUSH Size: %d\n"
2747	"Brand ID: %#04x\n",
2748	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2749	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2750	ASMGetCpuStepping(uEAX),
2751	(uEAX >> 12) & 3,
2752	(Guest.ebx >> 24) & 0xff,
2753	(Guest.ebx >> 16) & 0xff,
2754	(Guest.ebx >> 8) & 0xff,
2755	(Guest.ebx >> 0) & 0xff);
2756	if (iVerbosity == 1)
2757	{
2758	uint32_t uEDX = Guest.edx;
2759	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2760	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2761	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2762	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2763	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2764	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2765	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2766	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2767	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2768	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2769	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2770	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2771	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2772	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2773	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2774	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2775	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2776	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2777	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2778	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2779	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2780	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2781	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2782	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2783	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2784	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2785	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2786	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2787	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2788	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2789	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2790	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2791	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2792	pHlp->pfnPrintf(pHlp, "\n");
2793
2794	uint32_t uECX = Guest.ecx;
2795	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2796	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2797	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2798	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2799	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2800	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2801	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2802	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2803	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2804	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2805	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2806	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2807	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2808	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2809	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2810	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2811	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2812	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2813	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " 17");
2814	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2815	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4_1");
2816	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4_2");
2817	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2818	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2819	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2820	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " 24");
2821	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2822	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2823	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2824	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2825	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2826	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2827	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2828	pHlp->pfnPrintf(pHlp, "\n");
2829	}
2830	else
2831	{
2832	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2833
2834	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2835	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2836	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2837	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2838
2839	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2840	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2841	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2842	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2843	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2844	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2845	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2846	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2847	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2848	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2849	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2850	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2851	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2852	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2853	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2854	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
2855	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
2856	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
2857	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
2858	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
2859	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
2860	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
2861	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
2862	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
2863	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
2864	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
2865	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
2866	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
2867	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
2868	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
2869	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
2870	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
2871	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
2872
2873	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
2874	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
2875	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
2876	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
2877	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
2878	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
2879	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
2880	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2881	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
2882	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
2883	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
2884	pHlp->pfnPrintf(pHlp, "FMA = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
2885	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
2886	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
2887	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
2888	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
2889	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
2890	pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
2891	pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
2892	pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
2893	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
2894	pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
2895	pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
2896	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
2897	pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
2898	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
2899	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
2900	}
2901	}
2902	if (cStdMax >= 2 && iVerbosity)
2903	{
2904	/** @todo */
2905	}
2906
2907	/*
2908	* Extended.
2909	* Implemented after AMD specs.
2910	*/
2911	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
2912
2913	pHlp->pfnPrintf(pHlp,
2914	"\n"
2915	" RAW Extended CPUIDs\n"
2916	" Function eax ebx ecx edx\n");
2917	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
2918	{
2919	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
2920	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2921
2922	pHlp->pfnPrintf(pHlp,
2923	"Gst: %08x %08x %08x %08x %08x%s\n"
2924	"Hst: %08x %08x %08x %08x\n",
2925	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2926	i <= cExtMax ? "" : "*",
2927	Host.eax, Host.ebx, Host.ecx, Host.edx);
2928	}
2929
2930	/*
2931	* Understandable output
2932	*/
2933	if (iVerbosity)
2934	{
2935	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
2936	pHlp->pfnPrintf(pHlp,
2937	"Ext Name: %.4s%.4s%.4s\n"
2938	"Ext Supports: 0x80000000-%#010x\n",
2939	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2940	}
2941
2942	if (iVerbosity && cExtMax >= 1)
2943	{
2944	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
2945	uint32_t uEAX = Guest.eax;
2946	pHlp->pfnPrintf(pHlp,
2947	"Family: %d \tExtended: %d \tEffective: %d\n"
2948	"Model: %d \tExtended: %d \tEffective: %d\n"
2949	"Stepping: %d\n"
2950	"Brand ID: %#05x\n",
2951	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2952	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2953	ASMGetCpuStepping(uEAX),
2954	Guest.ebx & 0xfff);
2955
2956	if (iVerbosity == 1)
2957	{
2958	uint32_t uEDX = Guest.edx;
2959	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2960	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2961	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2962	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2963	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2964	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2965	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2966	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2967	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2968	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2969	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2970	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2971	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
2972	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2973	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2974	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2975	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2976	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2977	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2978	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
2979	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
2980	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
2981	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
2982	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
2983	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2984	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2985	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
2986	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
2987	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
2988	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
2989	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
2990	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
2991	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
2992	pHlp->pfnPrintf(pHlp, "\n");
2993
2994	uint32_t uECX = Guest.ecx;
2995	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2996	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
2997	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
2998	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
2999	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3000	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3001	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3002	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3003	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3004	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3005	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3006	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3007	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3008	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3009	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3010	for (unsigned iBit = 5; iBit < 32; iBit++)
3011	if (uECX & RT_BIT(iBit))
3012	pHlp->pfnPrintf(pHlp, " %d", iBit);
3013	pHlp->pfnPrintf(pHlp, "\n");
3014	}
3015	else
3016	{
3017	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3018
3019	uint32_t uEdxGst = Guest.edx;
3020	uint32_t uEdxHst = Host.edx;
3021	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3022	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3023	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3024	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3025	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3026	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3027	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3028	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3029	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3030	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3031	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3032	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3033	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3034	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3035	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3036	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3037	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3038	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3039	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3040	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3041	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3042	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3043	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3044	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3045	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3046	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3047	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3048	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3049	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3050	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3051	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3052	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3053	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3054
3055	uint32_t uEcxGst = Guest.ecx;
3056	uint32_t uEcxHst = Host.ecx;
3057	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3058	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3059	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3060	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3061	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3062	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3063	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3064	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3065	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3066	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3067	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3068	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3069	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3070	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3071	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3072	}
3073	}
3074
3075	if (iVerbosity && cExtMax >= 2)
3076	{
3077	char szString[443+1] = {0};
3078	uint32_t pu32 = (uint32_t )szString;
3079	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3080	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3081	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3082	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3083	if (cExtMax >= 3)
3084	{
3085	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3086	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3087	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3088	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3089	}
3090	if (cExtMax >= 4)
3091	{
3092	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3093	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3094	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3095	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3096	}
3097	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3098	}
3099
3100	if (iVerbosity && cExtMax >= 5)
3101	{
3102	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3103	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3104	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3105	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3106	char sz1[32];
3107	char sz2[32];
3108
3109	pHlp->pfnPrintf(pHlp,
3110	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3111	"TLB 2/4M Data: %s %3d entries\n",
3112	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3113	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3114	pHlp->pfnPrintf(pHlp,
3115	"TLB 4K Instr/Uni: %s %3d entries\n"
3116	"TLB 4K Data: %s %3d entries\n",
3117	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3118	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3119	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3120	"L1 Instr Cache Lines Per Tag: %d\n"
3121	"L1 Instr Cache Associativity: %s\n"
3122	"L1 Instr Cache Size: %d KB\n",
3123	(uEDX >> 0) & 0xff,
3124	(uEDX >> 8) & 0xff,
3125	getCacheAss((uEDX >> 16) & 0xff, sz1),
3126	(uEDX >> 24) & 0xff);
3127	pHlp->pfnPrintf(pHlp,
3128	"L1 Data Cache Line Size: %d bytes\n"
3129	"L1 Data Cache Lines Per Tag: %d\n"
3130	"L1 Data Cache Associativity: %s\n"
3131	"L1 Data Cache Size: %d KB\n",
3132	(uECX >> 0) & 0xff,
3133	(uECX >> 8) & 0xff,
3134	getCacheAss((uECX >> 16) & 0xff, sz1),
3135	(uECX >> 24) & 0xff);
3136	}
3137
3138	if (iVerbosity && cExtMax >= 6)
3139	{
3140	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3141	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3142	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3143
3144	pHlp->pfnPrintf(pHlp,
3145	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3146	"L2 TLB 2/4M Data: %s %4d entries\n",
3147	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3148	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3149	pHlp->pfnPrintf(pHlp,
3150	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3151	"L2 TLB 4K Data: %s %4d entries\n",
3152	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3153	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3154	pHlp->pfnPrintf(pHlp,
3155	"L2 Cache Line Size: %d bytes\n"
3156	"L2 Cache Lines Per Tag: %d\n"
3157	"L2 Cache Associativity: %s\n"
3158	"L2 Cache Size: %d KB\n",
3159	(uEDX >> 0) & 0xff,
3160	(uEDX >> 8) & 0xf,
3161	getL2CacheAss((uEDX >> 12) & 0xf),
3162	(uEDX >> 16) & 0xffff);
3163	}
3164
3165	if (iVerbosity && cExtMax >= 7)
3166	{
3167	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3168
3169	pHlp->pfnPrintf(pHlp, "APM Features: ");
3170	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3171	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3172	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3173	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3174	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3175	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3176	for (unsigned iBit = 6; iBit < 32; iBit++)
3177	if (uEDX & RT_BIT(iBit))
3178	pHlp->pfnPrintf(pHlp, " %d", iBit);
3179	pHlp->pfnPrintf(pHlp, "\n");
3180	}
3181
3182	if (iVerbosity && cExtMax >= 8)
3183	{
3184	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3185	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3186
3187	pHlp->pfnPrintf(pHlp,
3188	"Physical Address Width: %d bits\n"
3189	"Virtual Address Width: %d bits\n",
3190	(uEAX >> 0) & 0xff,
3191	(uEAX >> 8) & 0xff);
3192	pHlp->pfnPrintf(pHlp,
3193	"Physical Core Count: %d\n",
3194	(uECX >> 0) & 0xff);
3195	}
3196
3197
3198	/*
3199	* Centaur.
3200	*/
3201	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3202
3203	pHlp->pfnPrintf(pHlp,
3204	"\n"
3205	" RAW Centaur CPUIDs\n"
3206	" Function eax ebx ecx edx\n");
3207	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3208	{
3209	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3210	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3211
3212	pHlp->pfnPrintf(pHlp,
3213	"Gst: %08x %08x %08x %08x %08x%s\n"
3214	"Hst: %08x %08x %08x %08x\n",
3215	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3216	i <= cCentaurMax ? "" : "*",
3217	Host.eax, Host.ebx, Host.ecx, Host.edx);
3218	}
3219
3220	/*
3221	* Understandable output
3222	*/
3223	if (iVerbosity)
3224	{
3225	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3226	pHlp->pfnPrintf(pHlp,
3227	"Centaur Supports: 0xc0000000-%#010x\n",
3228	Guest.eax);
3229	}
3230
3231	if (iVerbosity && cCentaurMax >= 1)
3232	{
3233	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3234	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3235	uint32_t uEdxHst = Host.edx;
3236
3237	if (iVerbosity == 1)
3238	{
3239	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3240	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3241	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3242	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3243	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3244	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3245	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3246	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3247	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3248	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3249	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3250	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3251	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3252	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3253	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3254	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3255	for (unsigned iBit = 14; iBit < 32; iBit++)
3256	if (uEdxGst & RT_BIT(iBit))
3257	pHlp->pfnPrintf(pHlp, " %d", iBit);
3258	pHlp->pfnPrintf(pHlp, "\n");
3259	}
3260	else
3261	{
3262	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3263	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3264	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3265	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3266	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3267	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3268	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3269	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3270	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3271	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3272	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3273	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3274	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3275	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3276	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3277	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3278	for (unsigned iBit = 14; iBit < 32; iBit++)
3279	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3280	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3281	pHlp->pfnPrintf(pHlp, "\n");
3282	}
3283	}
3284	}
3285
3286
3287	/**
3288	* Structure used when disassembling and instructions in DBGF.
3289	* This is used so the reader function can get the stuff it needs.
3290	*/
3291	typedef struct CPUMDISASSTATE
3292	{
3293	/** Pointer to the CPU structure. */
3294	PDISCPUSTATE pCpu;
3295	/** The VM handle. */
3296	PVM pVM;
3297	/** The VMCPU handle. */
3298	PVMCPU pVCpu;
3299	/** Pointer to the first byte in the segemnt. */
3300	RTGCUINTPTR GCPtrSegBase;
3301	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3302	RTGCUINTPTR GCPtrSegEnd;
3303	/** The size of the segment minus 1. */
3304	RTGCUINTPTR cbSegLimit;
3305	/** Pointer to the current page - R3 Ptr. */
3306	void const *pvPageR3;
3307	/** Pointer to the current page - GC Ptr. */
3308	RTGCPTR pvPageGC;
3309	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3310	PGMPAGEMAPLOCK PageMapLock;
3311	/** Whether the PageMapLock is valid or not. */
3312	bool fLocked;
3313	/** 64 bits mode or not. */
3314	bool f64Bits;
3315	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3316
3317
3318	/**
3319	* Instruction reader.
3320	*
3321	* @returns VBox status code.
3322	* @param PtrSrc Address to read from.
3323	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3324	* @param pu8Dst Where to store the bytes.
3325	* @param cbRead Number of bytes to read.
3326	* @param uDisCpu Pointer to the disassembler cpu state.
3327	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3328	*/
3329	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3330	{
3331	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3332	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3333	Assert(cbRead > 0);
3334	for (;;)
3335	{
3336	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3337
3338	/* Need to update the page translation? */
3339	if ( !pState->pvPageR3
3340	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3341	{
3342	int rc = VINF_SUCCESS;
3343
3344	/* translate the address */
3345	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3346	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3347	&& !HWACCMIsEnabled(pState->pVM))
3348	{
3349	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3350	if (!pState->pvPageR3)
3351	rc = VERR_INVALID_POINTER;
3352	}
3353	else
3354	{
3355	/* Release mapping lock previously acquired. */
3356	if (pState->fLocked)
3357	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3358	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3359	pState->fLocked = RT_SUCCESS_NP(rc);
3360	}
3361	if (RT_FAILURE(rc))
3362	{
3363	pState->pvPageR3 = NULL;
3364	return rc;
3365	}
3366	}
3367
3368	/* check the segemnt limit */
3369	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3370	return VERR_OUT_OF_SELECTOR_BOUNDS;
3371
3372	/* calc how much we can read */
3373	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3374	if (!pState->f64Bits)
3375	{
3376	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3377	if (cb > cbSeg && cbSeg)
3378	cb = cbSeg;
3379	}
3380	if (cb > cbRead)
3381	cb = cbRead;
3382
3383	/* read and advance */
3384	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3385	cbRead -= cb;
3386	if (!cbRead)
3387	return VINF_SUCCESS;
3388	pu8Dst += cb;
3389	PtrSrc += cb;
3390	}
3391	}
3392
3393
3394	/**
3395	* Disassemble an instruction and return the information in the provided structure.
3396	*
3397	* @returns VBox status code.
3398	* @param pVM VM Handle
3399	* @param pVCpu VMCPU Handle
3400	* @param pCtx CPU context
3401	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3402	* @param pCpu Disassembly state
3403	* @param pszPrefix String prefix for logging (debug only)
3404	*
3405	*/
3406	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3407	{
3408	CPUMDISASSTATE State;
3409	int rc;
3410
3411	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3412	State.pCpu = pCpu;
3413	State.pvPageGC = 0;
3414	State.pvPageR3 = NULL;
3415	State.pVM = pVM;
3416	State.pVCpu = pVCpu;
3417	State.fLocked = false;
3418	State.f64Bits = false;
3419
3420	/*
3421	* Get selector information.
3422	*/
3423	if ( (pCtx->cr0 & X86_CR0_PE)
3424	&& pCtx->eflags.Bits.u1VM == 0)
3425	{
3426	if (CPUMAreHiddenSelRegsValid(pVM))
3427	{
3428	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3429	State.GCPtrSegBase = pCtx->csHid.u64Base;
3430	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3431	State.cbSegLimit = pCtx->csHid.u32Limit;
3432	pCpu->mode = (State.f64Bits)
3433	? CPUMODE_64BIT
3434	: pCtx->csHid.Attr.n.u1DefBig
3435	? CPUMODE_32BIT
3436	: CPUMODE_16BIT;
3437	}
3438	else
3439	{
3440	DBGFSELINFO SelInfo;
3441
3442	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3443	if (RT_FAILURE(rc))
3444	{
3445	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3446	return rc;
3447	}
3448
3449	/*
3450	* Validate the selector.
3451	*/
3452	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3453	if (RT_FAILURE(rc))
3454	{
3455	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3456	return rc;
3457	}
3458	State.GCPtrSegBase = SelInfo.GCPtrBase;
3459	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3460	State.cbSegLimit = SelInfo.cbLimit;
3461	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3462	}
3463	}
3464	else
3465	{
3466	/* real or V86 mode */
3467	pCpu->mode = CPUMODE_16BIT;
3468	State.GCPtrSegBase = pCtx->cs * 16;
3469	State.GCPtrSegEnd = 0xFFFFFFFF;
3470	State.cbSegLimit = 0xFFFFFFFF;
3471	}
3472
3473	/*
3474	* Disassemble the instruction.
3475	*/
3476	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3477	pCpu->apvUserData[0] = &State;
3478
3479	uint32_t cbInstr;
3480	#ifndef LOG_ENABLED
3481	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3482	if (RT_SUCCESS(rc))
3483	{
3484	#else
3485	char szOutput[160];
3486	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3487	if (RT_SUCCESS(rc))
3488	{
3489	/* log it */
3490	if (pszPrefix)
3491	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3492	else
3493	Log(("%s", szOutput));
3494	#endif
3495	rc = VINF_SUCCESS;
3496	}
3497	else
3498	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3499
3500	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3501	if (State.fLocked)
3502	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3503
3504	return rc;
3505	}
3506
3507	#ifdef DEBUG
3508
3509	/**
3510	* Disassemble an instruction and dump it to the log
3511	*
3512	* @returns VBox status code.
3513	* @param pVM VM Handle
3514	* @param pVCpu VMCPU Handle
3515	* @param pCtx CPU context
3516	* @param pc GC instruction pointer
3517	* @param pszPrefix String prefix for logging
3518	*
3519	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3520	*/
3521	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3522	{
3523	DISCPUSTATE Cpu;
3524	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3525	}
3526
3527
3528	/**
3529	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3530	*
3531	* @internal
3532	*/
3533	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3534	{
3535	/** @todo SMP support!! */
3536	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3537	}
3538
3539	#endif /* DEBUG */
3540
3541	/**
3542	* API for controlling a few of the CPU features found in CR4.
3543	*
3544	* Currently only X86_CR4_TSD is accepted as input.
3545	*
3546	* @returns VBox status code.
3547	*
3548	* @param pVM The VM handle.
3549	* @param fOr The CR4 OR mask.
3550	* @param fAnd The CR4 AND mask.
3551	*/
3552	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3553	{
3554	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3555	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3556
3557	pVM->cpum.s.CR4.OrMask &= fAnd;
3558	pVM->cpum.s.CR4.OrMask \|= fOr;
3559
3560	return VINF_SUCCESS;
3561	}
3562
3563
3564	/**
3565	* Gets a pointer to the array of standard CPUID leaves.
3566	*
3567	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3568	*
3569	* @returns Pointer to the standard CPUID leaves (read-only).
3570	* @param pVM The VM handle.
3571	* @remark Intended for PATM.
3572	*/
3573	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3574	{
3575	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3576	}
3577
3578
3579	/**
3580	* Gets a pointer to the array of extended CPUID leaves.
3581	*
3582	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3583	*
3584	* @returns Pointer to the extended CPUID leaves (read-only).
3585	* @param pVM The VM handle.
3586	* @remark Intended for PATM.
3587	*/
3588	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3589	{
3590	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3591	}
3592
3593
3594	/**
3595	* Gets a pointer to the array of centaur CPUID leaves.
3596	*
3597	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3598	*
3599	* @returns Pointer to the centaur CPUID leaves (read-only).
3600	* @param pVM The VM handle.
3601	* @remark Intended for PATM.
3602	*/
3603	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3604	{
3605	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3606	}
3607
3608
3609	/**
3610	* Gets a pointer to the default CPUID leaf.
3611	*
3612	* @returns Pointer to the default CPUID leaf (read-only).
3613	* @param pVM The VM handle.
3614	* @remark Intended for PATM.
3615	*/
3616	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3617	{
3618	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3619	}

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 27264

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