CPUM.cpp@ 28112

Last change on this file since 28112 was 27306, checked in by vboxsync, 15 years ago
CPUM: expose EDX of leaf 5 too, contains MWAIT C-states
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1	/* $Id: CPUM.cpp 27306 2010-03-11 20:44:52Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_cpum CPUM - CPU Monitor / Manager
23	*
24	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
25	* also responsible for lazy FPU handling and some of the context loading
26	* in raw mode.
27	*
28	* There are three CPU contexts, the most important one is the guest one (GC).
29	* When running in raw-mode (RC) there is a special hyper context for the VMM
30	* part that floats around inside the guest address space. When running in
31	* raw-mode, CPUM also maintains a host context for saving and restoring
32	* registers accross world switches. This latter is done in cooperation with the
33	* world switcher (@see pg_vmm).
34	*
35	* @see grp_cpum
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_CPUM
42	#include <VBox/cpum.h>
43	#include <VBox/cpumdis.h>
44	#include <VBox/pgm.h>
45	#include <VBox/mm.h>
46	#include <VBox/selm.h>
47	#include <VBox/dbgf.h>
48	#include <VBox/patm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/ssm.h>
51	#include "CPUMInternal.h"
52	#include <VBox/vm.h>
53
54	#include <VBox/param.h>
55	#include <VBox/dis.h>
56	#include <VBox/err.h>
57	#include <VBox/log.h>
58	#include <iprt/assert.h>
59	#include <iprt/asm.h>
60	#include <iprt/string.h>
61	#include <iprt/mp.h>
62	#include <iprt/cpuset.h>
63
64
65	/*******************************************************************************
66	* Defined Constants And Macros *
67	*******************************************************************************/
68	/** The current saved state version. */
69	#define CPUM_SAVED_STATE_VERSION 11
70	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
71	* changes. */
72	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
73	/** The saved state version for the 2.1 trunk before the MSR changes. */
74	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
75	/** The saved state version of 2.0, used for backwards compatibility. */
76	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
77	/** The saved state version of 1.6, used for backwards compatability. */
78	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
79
80
81	/*******************************************************************************
82	* Structures and Typedefs *
83	*******************************************************************************/
84
85	/**
86	* What kind of cpu info dump to perform.
87	*/
88	typedef enum CPUMDUMPTYPE
89	{
90	CPUMDUMPTYPE_TERSE,
91	CPUMDUMPTYPE_DEFAULT,
92	CPUMDUMPTYPE_VERBOSE
93	} CPUMDUMPTYPE;
94	/** Pointer to a cpu info dump type. */
95	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
96
97
98	/*******************************************************************************
99	* Internal Functions *
100	*******************************************************************************/
101	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
102	static int cpumR3CpuIdInit(PVM pVM);
103	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
104	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
106	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
107	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
108	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114
115
116	/**
117	* Initializes the CPUM.
118	*
119	* @returns VBox status code.
120	* @param pVM The VM to operate on.
121	*/
122	VMMR3DECL(int) CPUMR3Init(PVM pVM)
123	{
124	LogFlow(("CPUMR3Init\n"));
125
126	/*
127	* Assert alignment and sizes.
128	*/
129	AssertCompileMemberAlignment(VM, cpum.s, 32);
130	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
131	AssertCompileSizeAlignment(CPUMCTX, 64);
132	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
133	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
134	AssertCompileMemberAlignment(VM, cpum, 64);
135	AssertCompileMemberAlignment(VM, aCpus, 64);
136	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
137	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
138
139	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
140	pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
141	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
142
143	/* Calculate the offset from CPUMCPU to CPUM. */
144	for (VMCPUID i = 0; i < pVM->cCpus; i++)
145	{
146	PVMCPU pVCpu = &pVM->aCpus[i];
147
148	/*
149	* Setup any fixed pointers and offsets.
150	*/
151	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
152	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
153
154	pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
155	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
156	}
157
158	/*
159	* Check that the CPU supports the minimum features we require.
160	*/
161	if (!ASMHasCpuId())
162	{
163	Log(("The CPU doesn't support CPUID!\n"));
164	return VERR_UNSUPPORTED_CPU;
165	}
166	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
167	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
168
169	/* Setup the CR4 AND and OR masks used in the switcher */
170	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
171	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
172	{
173	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
174	/* No FXSAVE implies no SSE */
175	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
176	pVM->cpum.s.CR4.OrMask = 0;
177	}
178	else
179	{
180	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
181	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
182	}
183
184	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
185	{
186	Log(("The CPU doesn't support MMX!\n"));
187	return VERR_UNSUPPORTED_CPU;
188	}
189	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
190	{
191	Log(("The CPU doesn't support TSC!\n"));
192	return VERR_UNSUPPORTED_CPU;
193	}
194	/* Bogus on AMD? */
195	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
196	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
197
198	/*
199	* Detech the host CPU vendor.
200	* (The guest CPU vendor is re-detected later on.)
201	*/
202	uint32_t uEAX, uEBX, uECX, uEDX;
203	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
204	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
205	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
206
207	/*
208	* Setup hypervisor startup values.
209	*/
210
211	/*
212	* Register saved state data item.
213	*/
214	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
215	NULL, cpumR3LiveExec, NULL,
216	NULL, cpumR3SaveExec, NULL,
217	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
218	if (RT_FAILURE(rc))
219	return rc;
220
221	/*
222	* Register info handlers.
223	*/
224	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
225	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
227	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
228	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
229	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
230
231	/*
232	* Initialize the Guest CPUID state.
233	*/
234	rc = cpumR3CpuIdInit(pVM);
235	if (RT_FAILURE(rc))
236	return rc;
237	CPUMR3Reset(pVM);
238	return VINF_SUCCESS;
239	}
240
241
242	/**
243	* Initializes the per-VCPU CPUM.
244	*
245	* @returns VBox status code.
246	* @param pVM The VM to operate on.
247	*/
248	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
249	{
250	LogFlow(("CPUMR3InitCPU\n"));
251	return VINF_SUCCESS;
252	}
253
254
255	/**
256	* Detect the CPU vendor give n the
257	*
258	* @returns The vendor.
259	* @param uEAX EAX from CPUID(0).
260	* @param uEBX EBX from CPUID(0).
261	* @param uECX ECX from CPUID(0).
262	* @param uEDX EDX from CPUID(0).
263	*/
264	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
265	{
266	if ( uEAX >= 1
267	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
268	&& uECX == X86_CPUID_VENDOR_AMD_ECX
269	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
270	return CPUMCPUVENDOR_AMD;
271
272	if ( uEAX >= 1
273	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
274	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
275	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
276	return CPUMCPUVENDOR_INTEL;
277
278	/** @todo detect the other buggers... */
279	return CPUMCPUVENDOR_UNKNOWN;
280	}
281
282
283	/**
284	* Fetches overrides for a CPUID leaf.
285	*
286	* @returns VBox status code.
287	* @param pLeaf The leaf to load the overrides into.
288	* @param pCfgNode The CFGM node containing the overrides
289	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
290	* @param iLeaf The CPUID leaf number.
291	*/
292	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
293	{
294	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
295	if (pLeafNode)
296	{
297	uint32_t u32;
298	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
299	if (RT_SUCCESS(rc))
300	pLeaf->eax = u32;
301	else
302	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
303
304	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
305	if (RT_SUCCESS(rc))
306	pLeaf->ebx = u32;
307	else
308	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
309
310	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
311	if (RT_SUCCESS(rc))
312	pLeaf->ecx = u32;
313	else
314	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
315
316	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
317	if (RT_SUCCESS(rc))
318	pLeaf->edx = u32;
319	else
320	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
321
322	}
323	return VINF_SUCCESS;
324	}
325
326
327	/**
328	* Load the overrides for a set of CPUID leafs.
329	*
330	* @returns VBox status code.
331	* @param paLeafs The leaf array.
332	* @param cLeafs The number of leafs.
333	* @param uStart The start leaf number.
334	* @param pCfgNode The CFGM node containing the overrides
335	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
336	*/
337	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
338	{
339	for (uint32_t i = 0; i < cLeafs; i++)
340	{
341	int rc = cpumR3CpuIdFetchLeafOverride(&paLeafs[i], pCfgNode, uStart + i);
342	if (RT_FAILURE(rc))
343	return rc;
344	}
345
346	return VINF_SUCCESS;
347	}
348
349	/**
350	* Init a set of host CPUID leafs.
351	*
352	* @returns VBox status code.
353	* @param paLeafs The leaf array.
354	* @param cLeafs The number of leafs.
355	* @param uStart The start leaf number.
356	* @param pCfgNode The /CPUM/HostCPUID/ node.
357	*/
358	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
359	{
360	/* Using the ECX variant for all of them can't hurt... */
361	for (uint32_t i = 0; i < cLeafs; i++)
362	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeafs[i].eax, &paLeafs[i].ebx, &paLeafs[i].ecx, &paLeafs[i].edx);
363
364	/* Load CPUID leaf override; we currently don't care if the caller
365	specifies features the host CPU doesn't support. */
366	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeafs, cLeafs, pCfgNode);
367	}
368
369
370	/**
371	* Initializes the emulated CPU's cpuid information.
372	*
373	* @returns VBox status code.
374	* @param pVM The VM to operate on.
375	*/
376	static int cpumR3CpuIdInit(PVM pVM)
377	{
378	PCPUM pCPUM = &pVM->cpum.s;
379	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
380	uint32_t i;
381	int rc;
382
383	/*
384	* Get the host CPUIDs and redetect the guest CPU vendor (could've been overridden).
385	*/
386	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
387	* Overrides the host CPUID leaf values used for calculating the guest CPUID
388	* leafs. This can be used to preserve the CPUID values when moving a VM to
389	* a different machine. Another use is restricting (or extending) the
390	* feature set exposed to the guest. */
391	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
392	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
393	AssertRCReturn(rc, rc);
394	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
395	AssertRCReturn(rc, rc);
396	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
397	AssertRCReturn(rc, rc);
398
399	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
400	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
401
402	/*
403	* Only report features we can support.
404	*/
405	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
406	\| X86_CPUID_FEATURE_EDX_VME
407	\| X86_CPUID_FEATURE_EDX_DE
408	\| X86_CPUID_FEATURE_EDX_PSE
409	\| X86_CPUID_FEATURE_EDX_TSC
410	\| X86_CPUID_FEATURE_EDX_MSR
411	//\| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
412	\| X86_CPUID_FEATURE_EDX_MCE
413	\| X86_CPUID_FEATURE_EDX_CX8
414	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
415	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
416	//\| X86_CPUID_FEATURE_EDX_SEP
417	\| X86_CPUID_FEATURE_EDX_MTRR
418	\| X86_CPUID_FEATURE_EDX_PGE
419	\| X86_CPUID_FEATURE_EDX_MCA
420	\| X86_CPUID_FEATURE_EDX_CMOV
421	\| X86_CPUID_FEATURE_EDX_PAT
422	\| X86_CPUID_FEATURE_EDX_PSE36
423	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
424	\| X86_CPUID_FEATURE_EDX_CLFSH
425	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
426	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
427	\| X86_CPUID_FEATURE_EDX_MMX
428	\| X86_CPUID_FEATURE_EDX_FXSR
429	\| X86_CPUID_FEATURE_EDX_SSE
430	\| X86_CPUID_FEATURE_EDX_SSE2
431	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
432	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
433	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
434	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
435	\| 0;
436	pCPUM->aGuestCpuIdStd[1].ecx &= 0
437	\| X86_CPUID_FEATURE_ECX_SSE3
438	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
439	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
440	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
441	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
442	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
443	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
444	\| X86_CPUID_FEATURE_ECX_SSSE3
445	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
446	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
447	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
448	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
449	/* ECX Bit 21 - x2APIC support - not yet. */
450	// \| X86_CPUID_FEATURE_ECX_X2APIC
451	/* ECX Bit 23 - POPCNT instruction. */
452	//\| X86_CPUID_FEATURE_ECX_POPCNT
453	\| 0;
454
455	/* ASSUMES that this is ALWAYS the AMD define feature set if present. */
456	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
457	\| X86_CPUID_AMD_FEATURE_EDX_VME
458	\| X86_CPUID_AMD_FEATURE_EDX_DE
459	\| X86_CPUID_AMD_FEATURE_EDX_PSE
460	\| X86_CPUID_AMD_FEATURE_EDX_TSC
461	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
462	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
463	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
464	\| X86_CPUID_AMD_FEATURE_EDX_CX8
465	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
466	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
467	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
468	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
469	\| X86_CPUID_AMD_FEATURE_EDX_PGE
470	\| X86_CPUID_AMD_FEATURE_EDX_MCA
471	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
472	\| X86_CPUID_AMD_FEATURE_EDX_PAT
473	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
474	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
475	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
476	\| X86_CPUID_AMD_FEATURE_EDX_MMX
477	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
478	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
479	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
480	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
481	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
482	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
483	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
484	\| 0;
485	pCPUM->aGuestCpuIdExt[1].ecx &= 0
486	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
487	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
488	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
489	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
490	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
491	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
492	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
493	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
494	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
495	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
496	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
497	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
498	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
499	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
500	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
501	\| 0;
502
503	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false); AssertRCReturn(rc, rc);
504	if (pCPUM->fSyntheticCpu)
505	{
506	const char szVendor[13] = "VirtualBox ";
507	const char szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
508
509	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
510
511	/* Limit the nr of standard leaves; 5 for monitor/mwait */
512	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
513
514	/* 0: Vendor */
515	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)szVendor)[0];
516	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)szVendor)[2];
517	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)szVendor)[1];
518
519	/* 1.eax: Version information. family : model : stepping */
520	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
521
522	/* Leaves 2 - 4 are Intel only - zero them out */
523	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
524	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
525	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
526
527	/* Leaf 5 = monitor/mwait */
528
529	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
530	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
531	/* AMD only - set to zero. */
532	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
533
534	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
535	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
536
537	/* 0x800000002-4: Processor Name String Identifier. */
538	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)szProcessor)[0];
539	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)szProcessor)[1];
540	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)szProcessor)[2];
541	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)szProcessor)[3];
542	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)szProcessor)[4];
543	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)szProcessor)[5];
544	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)szProcessor)[6];
545	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)szProcessor)[7];
546	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)szProcessor)[8];
547	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)szProcessor)[9];
548	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)szProcessor)[10];
549	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)szProcessor)[11];
550
551	/* 0x800000005-7 - reserved -> zero */
552	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
553	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
554	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
555
556	/* 0x800000008: only the max virtual and physical address size. */
557	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
558	}
559
560	/*
561	* Hide HTT, multicode, SMP, whatever.
562	* (APIC-ID := 0 and #LogCpus := 0)
563	*/
564	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
565	#ifdef VBOX_WITH_MULTI_CORE
566	if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
567	&& pVM->cCpus > 1)
568	{
569	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
570	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
571	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
572	}
573	#endif
574
575	/* Cpuid 2:
576	* Intel: Cache and TLB information
577	* AMD: Reserved
578	* Safe to expose
579	*/
580
581	/* Cpuid 3:
582	* Intel: EAX, EBX - reserved
583	* ECX, EDX - Processor Serial Number if available, otherwise reserved
584	* AMD: Reserved
585	* Safe to expose
586	*/
587	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
588	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
589
590	/* Cpuid 4:
591	* Intel: Deterministic Cache Parameters Leaf
592	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
593	* AMD: Reserved
594	* Safe to expose, except for EAX:
595	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
596	* Bits 31-26: Maximum number of processor cores in this physical package**
597	* Note: These SMP values are constant regardless of ECX
598	*/
599	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
600	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
601	#ifdef VBOX_WITH_MULTI_CORE
602	if ( pVM->cCpus > 1
603	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
604	{
605	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
606	/* One logical processor with possibly multiple cores. */
607	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
608	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
609	}
610	#endif
611
612	/* Cpuid 5: Monitor/mwait Leaf
613	* Intel: ECX, EDX - reserved
614	* EAX, EBX - Smallest and largest monitor line size
615	* AMD: EDX - reserved
616	* EAX, EBX - Smallest and largest monitor line size
617	* ECX - extensions (ignored for now)
618	* Safe to expose
619	*/
620	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
621	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
622
623	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
624	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
625	* Expose MWAIT extended features to the guest.
626	* For now we expose just MWAIT break on interrupt feature (bit 1)
627	*/
628	bool fMWaitExtensions;
629	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
630	if (fMWaitExtensions)
631	{
632	pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
633	/* @todo: for now we just expose host's MWAIT C-states, although conceptually
634	it shall be part of our power management virtualization model */
635	#if 0
636	/* MWAIT sub C-states */
637	pCPUM->aGuestCpuIdStd[5].edx =
638	(0 << 0) /* 0 in C0 */ \|
639	(2 << 4) /* 2 in C1 */ \|
640	(2 << 8) /* 2 in C2 */ \|
641	(2 << 12) /* 2 in C3 */ \|
642	(0 << 16) /* 0 in C4 */
643	;
644	#endif
645	}
646	else
647	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
648
649	/*
650	* Determine the default.
651	*
652	* Intel returns values of the highest standard function, while AMD
653	* returns zeros. VIA on the other hand seems to returning nothing or
654	* perhaps some random garbage, we don't try to duplicate this behavior.
655	*/
656	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
657	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
658	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
659
660	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
661	* Safe to pass on to the guest.
662	*
663	* Intel: 0x800000005 reserved
664	* 0x800000006 L2 cache information
665	* AMD: 0x800000005 L1 cache information
666	* 0x800000006 L2/L3 cache information
667	*/
668
669	/* Cpuid 0x800000007:
670	* AMD: EAX, EBX, ECX - reserved
671	* EDX: Advanced Power Management Information
672	* Intel: Reserved
673	*/
674	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
675	{
676	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
677
678	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
679
680	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
681	{
682	/* Only expose the TSC invariant capability bit to the guest. */
683	pCPUM->aGuestCpuIdExt[7].edx &= 0
684	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
685	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
686	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
687	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
688	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
689	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
690	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
691	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
692	#if 1
693	/* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
694	* that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
695	*/
696	#else
697	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
698	#endif
699	\| 0;
700	}
701	else
702	pCPUM->aGuestCpuIdExt[7].edx = 0;
703	}
704
705	/* Cpuid 0x800000008:
706	* AMD: EBX, EDX - reserved
707	* EAX: Virtual/Physical address Size
708	* ECX: Number of cores + APICIdCoreIdSize
709	* Intel: EAX: Virtual/Physical address Size
710	* EBX, ECX, EDX - reserved
711	*/
712	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
713	{
714	/* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
715	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
716	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
717	* NC (0-7) Number of cores; 0 equals 1 core */
718	pCPUM->aGuestCpuIdExt[8].ecx = 0;
719	#ifdef VBOX_WITH_MULTI_CORE
720	if ( pVM->cCpus > 1
721	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
722	{
723	/* Legacy method to determine the number of cores. */
724	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
725	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
726
727	}
728	#endif
729	}
730
731	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
732	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
733	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
734	* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
735	*/
736	bool fNt4LeafLimit;
737	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
738	if (fNt4LeafLimit)
739	pCPUM->aGuestCpuIdStd[0].eax = 3;
740
741	/*
742	* Limit it the number of entries and fill the remaining with the defaults.
743	*
744	* The limits are masking off stuff about power saving and similar, this
745	* is perhaps a bit crudely done as there is probably some relatively harmless
746	* info too in these leaves (like words about having a constant TSC).
747	*/
748	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
749	pCPUM->aGuestCpuIdStd[0].eax = 5;
750
751	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
752	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
753
754	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
755	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
756	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
757	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
758	: 0;
759	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
760	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
761
762	/*
763	* Centaur stuff (VIA).
764	*
765	* The important part here (we think) is to make sure the 0xc0000000
766	* function returns 0xc0000001. As for the features, we don't currently
767	* let on about any of those... 0xc0000002 seems to be some
768	* temperature/hz/++ stuff, include it as well (static).
769	*/
770	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
771	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
772	{
773	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
774	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
775	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
776	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
777	i++)
778	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
779	}
780	else
781	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
782	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
783
784
785	/*
786	* Load CPUID overrides from configuration.
787	* Note: Kind of redundant now, but allows unchanged overrides
788	*/
789	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
790	* Overrides the CPUID leaf values. */
791	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
792	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
793	AssertRCReturn(rc, rc);
794	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
795	AssertRCReturn(rc, rc);
796	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
797	AssertRCReturn(rc, rc);
798
799	/*
800	* Check if PAE was explicitely enabled by the user.
801	*/
802	bool fEnable;
803	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
804	if (fEnable)
805	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
806
807	/*
808	* Log the cpuid and we're good.
809	*/
810	RTCPUSET OnlineSet;
811	LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
812	(int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
813	LogRel(("*********************** CPUID dump **********************\n"));
814	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
815	LogRel(("\n"));
816	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
817	LogRel(("****************** End of CPUID dump ********************\n"));
818	return VINF_SUCCESS;
819	}
820
821
822
823
824	/**
825	* Applies relocations to data and code managed by this
826	* component. This function will be called at init and
827	* whenever the VMM need to relocate it self inside the GC.
828	*
829	* The CPUM will update the addresses used by the switcher.
830	*
831	* @param pVM The VM.
832	*/
833	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
834	{
835	LogFlow(("CPUMR3Relocate\n"));
836	for (VMCPUID i = 0; i < pVM->cCpus; i++)
837	{
838	/*
839	* Switcher pointers.
840	*/
841	PVMCPU pVCpu = &pVM->aCpus[i];
842	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
843	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
844
845	}
846	}
847
848
849	/**
850	* Apply late CPUM property changes based on the fHWVirtEx setting
851	*
852	* @param pVM The VM to operate on.
853	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
854	*/
855	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
856	{
857	/*
858	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
859	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
860	* of processors from (cpuid(4).eax >> 26) + 1.
861	*
862	* Note: this code is obsolete, but let's keep it here for reference.
863	* Purpose is valid when we artifically cap the max std id to less than 4.
864	*/
865	if (!fHWVirtExEnabled)
866	{
867	Assert(pVM->cpum.s.aGuestCpuIdStd[4].eax == 0);
868	pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
869	}
870	}
871
872	/**
873	* Terminates the CPUM.
874	*
875	* Termination means cleaning up and freeing all resources,
876	* the VM it self is at this point powered off or suspended.
877	*
878	* @returns VBox status code.
879	* @param pVM The VM to operate on.
880	*/
881	VMMR3DECL(int) CPUMR3Term(PVM pVM)
882	{
883	CPUMR3TermCPU(pVM);
884	return 0;
885	}
886
887
888	/**
889	* Terminates the per-VCPU CPUM.
890	*
891	* Termination means cleaning up and freeing all resources,
892	* the VM it self is at this point powered off or suspended.
893	*
894	* @returns VBox status code.
895	* @param pVM The VM to operate on.
896	*/
897	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
898	{
899	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
900	for (VMCPUID i = 0; i < pVM->cCpus; i++)
901	{
902	PVMCPU pVCpu = &pVM->aCpus[i];
903	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
904
905	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
906	pVCpu->cpum.s.uMagic = 0;
907	pCtx->dr[5] = 0;
908	}
909	#endif
910	return 0;
911	}
912
913
914	/**
915	* Resets a virtual CPU.
916	*
917	* Used by CPUMR3Reset and CPU hot plugging.
918	*
919	* @param pVCpu The virtual CPU handle.
920	*/
921	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
922	{
923	/** @todo anything different for VCPU > 0? */
924	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
925
926	/*
927	* Initialize everything to ZERO first.
928	*/
929	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
930	memset(pCtx, 0, sizeof(*pCtx));
931	pVCpu->cpum.s.fUseFlags = fUseFlags;
932
933	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
934	pCtx->eip = 0x0000fff0;
935	pCtx->edx = 0x00000600; /* P6 processor */
936	pCtx->eflags.Bits.u1Reserved0 = 1;
937
938	pCtx->cs = 0xf000;
939	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
940	pCtx->csHid.u32Limit = 0x0000ffff;
941	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
942	pCtx->csHid.Attr.n.u1Present = 1;
943	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
944
945	pCtx->dsHid.u32Limit = 0x0000ffff;
946	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
947	pCtx->dsHid.Attr.n.u1Present = 1;
948	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
949
950	pCtx->esHid.u32Limit = 0x0000ffff;
951	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
952	pCtx->esHid.Attr.n.u1Present = 1;
953	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
954
955	pCtx->fsHid.u32Limit = 0x0000ffff;
956	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
957	pCtx->fsHid.Attr.n.u1Present = 1;
958	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
959
960	pCtx->gsHid.u32Limit = 0x0000ffff;
961	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
962	pCtx->gsHid.Attr.n.u1Present = 1;
963	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
964
965	pCtx->ssHid.u32Limit = 0x0000ffff;
966	pCtx->ssHid.Attr.n.u1Present = 1;
967	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
968	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
969
970	pCtx->idtr.cbIdt = 0xffff;
971	pCtx->gdtr.cbGdt = 0xffff;
972
973	pCtx->ldtrHid.u32Limit = 0xffff;
974	pCtx->ldtrHid.Attr.n.u1Present = 1;
975	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
976
977	pCtx->trHid.u32Limit = 0xffff;
978	pCtx->trHid.Attr.n.u1Present = 1;
979	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
980
981	pCtx->dr[6] = X86_DR6_INIT_VAL;
982	pCtx->dr[7] = X86_DR7_INIT_VAL;
983
984	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
985	pCtx->fpu.FCW = 0x37f;
986
987	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
988	pCtx->fpu.MXCSR = 0x1F80;
989
990	/* Init PAT MSR */
991	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
992
993	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
994	* The Intel docs don't mention it.
995	*/
996	pCtx->msrEFER = 0;
997	}
998
999
1000	/**
1001	* Resets the CPU.
1002	*
1003	* @returns VINF_SUCCESS.
1004	* @param pVM The VM handle.
1005	*/
1006	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1007	{
1008	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1009	{
1010	CPUMR3ResetCpu(&pVM->aCpus[i]);
1011
1012	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1013	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1014
1015	/* Magic marker for searching in crash dumps. */
1016	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1017	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1018	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1019	#endif
1020	}
1021	}
1022
1023
1024	/**
1025	* Called both in pass 0 and the final pass.
1026	*
1027	* @param pVM The VM handle.
1028	* @param pSSM The saved state handle.
1029	*/
1030	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1031	{
1032	/*
1033	* Save all the CPU ID leaves here so we can check them for compatability
1034	* upon loading.
1035	*/
1036	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1037	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1038
1039	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1040	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1041
1042	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1043	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1044
1045	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1046
1047	/*
1048	* Save a good portion of the raw CPU IDs as well as they may come in
1049	* handy when validating features for raw mode.
1050	*/
1051	CPUMCPUID aRawStd[16];
1052	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1053	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1054	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1055	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1056
1057	CPUMCPUID aRawExt[32];
1058	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1059	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1060	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1061	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1062	}
1063
1064
1065	/**
1066	* Loads the CPU ID leaves saved by pass 0.
1067	*
1068	* @returns VBox status code.
1069	* @param pVM The VM handle.
1070	* @param pSSM The saved state handle.
1071	* @param uVersion The format version.
1072	*/
1073	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1074	{
1075	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1076
1077	/*
1078	* Define a bunch of macros for simplifying the code.
1079	*/
1080	/* Generic expression + failure message. */
1081	#define CPUID_CHECK_RET(expr, fmt) \
1082	do { \
1083	if (!(expr)) \
1084	{ \
1085	char pszMsg = RTStrAPrintf2 fmt; / lack of variadict macros sucks */ \
1086	if (fStrictCpuIdChecks) \
1087	{ \
1088	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1089	RTStrFree(pszMsg); \
1090	return rcCpuid; \
1091	} \
1092	LogRel(("CPUM: %s\n", pszMsg)); \
1093	RTStrFree(pszMsg); \
1094	} \
1095	} while (0)
1096	#define CPUID_CHECK_WRN(expr, fmt) \
1097	do { \
1098	if (!(expr)) \
1099	LogRel(fmt); \
1100	} while (0)
1101
1102	/* For comparing two values and bitch if they differs. */
1103	#define CPUID_CHECK2_RET(what, host, saved) \
1104	do { \
1105	if ((host) != (saved)) \
1106	{ \
1107	if (fStrictCpuIdChecks) \
1108	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1109	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1110	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1111	} \
1112	} while (0)
1113	#define CPUID_CHECK2_WRN(what, host, saved) \
1114	do { \
1115	if ((host) != (saved)) \
1116	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1117	} while (0)
1118
1119	/* For checking raw cpu features (raw mode). */
1120	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1121	do { \
1122	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1123	{ \
1124	if (fStrictCpuIdChecks) \
1125	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1126	N_(#bit " mismatch: host=%d saved=%d"), \
1127	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1128	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1129	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1130	} \
1131	} while (0)
1132	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1133	do { \
1134	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1135	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1136	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1137	} while (0)
1138	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1139
1140	/* For checking guest features. */
1141	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1142	do { \
1143	if ( (aGuestCpuId##set [1].reg & bit) \
1144	&& !(aHostRaw##set [1].reg & bit) \
1145	&& !(aHostOverride##set [1].reg & bit) \
1146	&& !(aGuestOverride##set [1].reg & bit) \
1147	) \
1148	{ \
1149	if (fStrictCpuIdChecks) \
1150	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1151	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1152	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1153	} \
1154	} while (0)
1155	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1156	do { \
1157	if ( (aGuestCpuId##set [1].reg & bit) \
1158	&& !(aHostRaw##set [1].reg & bit) \
1159	&& !(aHostOverride##set [1].reg & bit) \
1160	&& !(aGuestOverride##set [1].reg & bit) \
1161	) \
1162	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1163	} while (0)
1164	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1165	do { \
1166	if ( (aGuestCpuId##set [1].reg & bit) \
1167	&& !(aHostRaw##set [1].reg & bit) \
1168	&& !(aHostOverride##set [1].reg & bit) \
1169	&& !(aGuestOverride##set [1].reg & bit) \
1170	) \
1171	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1172	} while (0)
1173	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1174
1175	/* For checking guest features if AMD guest CPU. */
1176	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1177	do { \
1178	if ( (aGuestCpuId##set [1].reg & bit) \
1179	&& fGuestAmd \
1180	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1181	&& !(aHostOverride##set [1].reg & bit) \
1182	&& !(aGuestOverride##set [1].reg & bit) \
1183	) \
1184	{ \
1185	if (fStrictCpuIdChecks) \
1186	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1187	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1188	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1189	} \
1190	} while (0)
1191	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1192	do { \
1193	if ( (aGuestCpuId##set [1].reg & bit) \
1194	&& fGuestAmd \
1195	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1196	&& !(aHostOverride##set [1].reg & bit) \
1197	&& !(aGuestOverride##set [1].reg & bit) \
1198	) \
1199	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1200	} while (0)
1201	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1202	do { \
1203	if ( (aGuestCpuId##set [1].reg & bit) \
1204	&& fGuestAmd \
1205	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1206	&& !(aHostOverride##set [1].reg & bit) \
1207	&& !(aGuestOverride##set [1].reg & bit) \
1208	) \
1209	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1210	} while (0)
1211	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1212
1213	/* For checking AMD features which have a corresponding bit in the standard
1214	range. (Intel defines very few bits in the extended feature sets.) */
1215	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1216	do { \
1217	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1218	&& !(fHostAmd \
1219	? aHostRawExt[1].reg & (ExtBit) \
1220	: aHostRawStd[1].reg & (StdBit)) \
1221	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1222	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1223	) \
1224	{ \
1225	if (fStrictCpuIdChecks) \
1226	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1227	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1228	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1229	} \
1230	} while (0)
1231	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1232	do { \
1233	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1234	&& !(fHostAmd \
1235	? aHostRawExt[1].reg & (ExtBit) \
1236	: aHostRawStd[1].reg & (StdBit)) \
1237	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1238	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1239	) \
1240	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1241	} while (0)
1242	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1243	do { \
1244	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1245	&& !(fHostAmd \
1246	? aHostRawExt[1].reg & (ExtBit) \
1247	: aHostRawStd[1].reg & (StdBit)) \
1248	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1249	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1250	) \
1251	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1252	} while (0)
1253	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1254
1255	/*
1256	* Load them into stack buffers first.
1257	*/
1258	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1259	uint32_t cGuestCpuIdStd;
1260	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1261	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1262	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1263	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1264
1265	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1266	uint32_t cGuestCpuIdExt;
1267	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1268	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1269	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1270	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1271
1272	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1273	uint32_t cGuestCpuIdCentaur;
1274	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1275	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1276	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1277	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1278
1279	CPUMCPUID GuestCpuIdDef;
1280	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1281	AssertRCReturn(rc, rc);
1282
1283	CPUMCPUID aRawStd[16];
1284	uint32_t cRawStd;
1285	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1286	if (cRawStd > RT_ELEMENTS(aRawStd))
1287	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1288	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1289
1290	CPUMCPUID aRawExt[32];
1291	uint32_t cRawExt;
1292	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1293	if (cRawExt > RT_ELEMENTS(aRawExt))
1294	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1295	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1296	AssertRCReturn(rc, rc);
1297
1298	/*
1299	* Note that we support restoring less than the current amount of standard
1300	* leaves because we've been allowed more is newer version of VBox.
1301	*
1302	* So, pad new entries with the default.
1303	*/
1304	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1305	aGuestCpuIdStd[i] = GuestCpuIdDef;
1306
1307	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1308	aGuestCpuIdExt[i] = GuestCpuIdDef;
1309
1310	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1311	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1312
1313	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1314	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1315
1316	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1317	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1318
1319	/*
1320	* Get the raw CPU IDs for the current host.
1321	*/
1322	CPUMCPUID aHostRawStd[16];
1323	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1324	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1325
1326	CPUMCPUID aHostRawExt[32];
1327	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1328	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1329
1330	/*
1331	* Get the host and guest overrides so we don't reject the state because
1332	* some feature was enabled thru these interfaces.
1333	* Note! We currently only need the feature leafs, so skip rest.
1334	*/
1335	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1336	CPUMCPUID aGuestOverrideStd[2];
1337	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1338	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1339
1340	CPUMCPUID aGuestOverrideExt[2];
1341	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1342	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1343
1344	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1345	CPUMCPUID aHostOverrideStd[2];
1346	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1347	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1348
1349	CPUMCPUID aHostOverrideExt[2];
1350	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1351	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1352
1353	/*
1354	* This can be skipped.
1355	*/
1356	bool fStrictCpuIdChecks;
1357	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1358
1359
1360
1361	/*
1362	* For raw-mode we'll require that the CPUs are very similar since we don't
1363	* intercept CPUID instructions for user mode applications.
1364	*/
1365	if (!HWACCMIsEnabled(pVM))
1366	{
1367	/* CPUID(0) */
1368	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1369	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1370	&& aHostRawStd[0].edx == aRawStd[0].edx,
1371	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1372	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1373	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1374	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1375	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1376	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1377
1378	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1379
1380	/* CPUID(1).eax */
1381	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1382	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1383	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1384
1385	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1386	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1387	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1388
1389	/* CPUID(1).ecx */
1390	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1391	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1392	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1393	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1394	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1395	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1396	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1397	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1398	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1399	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1400	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1401	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1402	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1403	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1404	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1405	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1406	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1407	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1408	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1409	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1410	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1411	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1412	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1413	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1414	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1415	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1416	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1417	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1418	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1419	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1420	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1421	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1422
1423	/* CPUID(1).edx */
1424	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1425	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1426	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1427	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1428	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1429	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1430	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1431	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1432	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1433	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1434	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1435	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1436	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1437	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1438	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1439	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1440	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1441	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1442	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1443	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1444	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1445	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1446	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1447	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1448	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1449	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1450	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1451	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1452	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1453	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1454	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1455	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1456
1457	/* CPUID(2) - config, mostly about caches. ignore. */
1458	/* CPUID(3) - processor serial number. ignore. */
1459	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1460	/* CPUID(5) - mwait/monitor config. ignore. */
1461	/* CPUID(6) - power management. ignore. */
1462	/* CPUID(7) - ???. ignore. */
1463	/* CPUID(8) - ???. ignore. */
1464	/* CPUID(9) - DCA. ignore for now. */
1465	/* CPUID(a) - PeMo info. ignore for now. */
1466	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1467
1468	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1469	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1470	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1471	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1472	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1473	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1474	{
1475	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1476	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1477	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1478	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1479	}
1480
1481	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1482	Note! Intel have/is marking many of the fields here as reserved. We
1483	will verify them as if it's an AMD CPU. */
1484	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1485	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1486	(N_("Extended leafs was present on saved state host, but is missing on the current\n")));
1487	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1488	{
1489	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1490	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1491	&& aHostRawExt[0].edx == aRawExt[0].edx,
1492	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1493	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1494	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1495	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1496
1497	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1498	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1499	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1500	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1501	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1502	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1503
1504	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1505	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1506	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1507	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1508
1509	/* CPUID(0x80000001).ecx */
1510	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1511	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1512	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1513	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1514	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1515	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1516	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1517	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1518	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1519	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1520	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1521	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1522	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1523	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1524	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1525	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1526	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1527	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1528	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1529	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1530	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1531	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1532	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1533	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1534	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1535	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1536	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1537	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1538	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1539	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1540	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1541	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1542
1543	/* CPUID(0x80000001).edx */
1544	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1545	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1546	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1547	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1548	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1549	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1550	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1551	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1552	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1553	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1554	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1555	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1556	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1557	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1558	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1559	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1560	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1561	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1562	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1563	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1564	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1565	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1566	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1567	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1568	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1569	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1570	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1571	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1572	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1573	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1574	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1575	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1576
1577	/** @todo verify the rest as well. */
1578	}
1579	}
1580
1581
1582
1583	/*
1584	* Verify that we can support the features already exposed to the guest on
1585	* this host.
1586	*
1587	* Most of the features we're emulating requires intercepting instruction
1588	* and doing it the slow way, so there is no need to warn when they aren't
1589	* present in the host CPU. Thus we use IGN instead of EMU on these.
1590	*
1591	* Trailing comments:
1592	* "EMU" - Possible to emulate, could be lots of work and very slow.
1593	* "EMU?" - Can this be emulated?
1594	*/
1595	/* CPUID(1).ecx */
1596	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1597	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1598	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1599	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1600	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1601	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1602	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1603	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1604	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1605	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1606	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1607	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1608	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1609	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1610	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1611	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1612	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1613	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1614	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1615	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1616	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1617	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1618	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1619	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1620	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1621	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1622	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1623	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1624	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1625	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1626	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1627	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1628
1629	/* CPUID(1).edx */
1630	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1631	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1632	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1633	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1634	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1635	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1636	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1637	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1638	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1639	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1640	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1641	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1642	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1643	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1644	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1645	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1646	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1647	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1648	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1649	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1650	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1651	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1652	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1653	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1654	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1655	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1656	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1657	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1658	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1659	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1660	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1661	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1662
1663	/* CPUID(0x80000000). */
1664	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1665	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1666	{
1667	/** @todo deal with no 0x80000001 on the host. */
1668	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1669	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1670
1671	/* CPUID(0x80000001).ecx */
1672	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1673	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1674	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1675	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1676	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1677	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1678	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1679	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1680	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1681	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1682	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1683	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1684	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1685	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1686	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1687	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1688	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1689	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1690	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1691	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1692	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1693	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1694	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1695	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1696	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1697	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1698	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1699	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1700	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1701	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1702	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1703	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1704
1705	/* CPUID(0x80000001).edx */
1706	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1707	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1708	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1709	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1710	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1711	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1712	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1713	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1714	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1715	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1716	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1717	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1718	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1719	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1720	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1721	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1722	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1723	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1724	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1725	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1726	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1727	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1728	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1729	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1730	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1731	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1732	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1733	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1734	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1735	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1736	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1737	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1738	}
1739
1740	/*
1741	* We're good, commit the CPU ID leaves.
1742	*/
1743	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1744	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1745	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1746	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1747
1748	#undef CPUID_CHECK_RET
1749	#undef CPUID_CHECK_WRN
1750	#undef CPUID_CHECK2_RET
1751	#undef CPUID_CHECK2_WRN
1752	#undef CPUID_RAW_FEATURE_RET
1753	#undef CPUID_RAW_FEATURE_WRN
1754	#undef CPUID_RAW_FEATURE_IGN
1755	#undef CPUID_GST_FEATURE_RET
1756	#undef CPUID_GST_FEATURE_WRN
1757	#undef CPUID_GST_FEATURE_EMU
1758	#undef CPUID_GST_FEATURE_IGN
1759	#undef CPUID_GST_FEATURE2_RET
1760	#undef CPUID_GST_FEATURE2_WRN
1761	#undef CPUID_GST_FEATURE2_EMU
1762	#undef CPUID_GST_FEATURE2_IGN
1763	#undef CPUID_GST_AMD_FEATURE_RET
1764	#undef CPUID_GST_AMD_FEATURE_WRN
1765	#undef CPUID_GST_AMD_FEATURE_EMU
1766	#undef CPUID_GST_AMD_FEATURE_IGN
1767
1768	return VINF_SUCCESS;
1769	}
1770
1771
1772	/**
1773	* Pass 0 live exec callback.
1774	*
1775	* @returns VINF_SSM_DONT_CALL_AGAIN.
1776	* @param pVM The VM handle.
1777	* @param pSSM The saved state handle.
1778	* @param uPass The pass (0).
1779	*/
1780	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1781	{
1782	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1783	cpumR3SaveCpuId(pVM, pSSM);
1784	return VINF_SSM_DONT_CALL_AGAIN;
1785	}
1786
1787
1788	/**
1789	* Execute state save operation.
1790	*
1791	* @returns VBox status code.
1792	* @param pVM VM Handle.
1793	* @param pSSM SSM operation handle.
1794	*/
1795	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1796	{
1797	/*
1798	* Save.
1799	*/
1800	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1801	{
1802	PVMCPU pVCpu = &pVM->aCpus[i];
1803
1804	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1805	}
1806
1807	SSMR3PutU32(pSSM, pVM->cCpus);
1808	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1809	{
1810	PVMCPU pVCpu = &pVM->aCpus[i];
1811
1812	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1813	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1814	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1815	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1816	}
1817
1818	cpumR3SaveCpuId(pVM, pSSM);
1819	return VINF_SUCCESS;
1820	}
1821
1822
1823	/**
1824	* Load a version 1.6 CPUMCTX structure.
1825	*
1826	* @returns VBox status code.
1827	* @param pVM VM Handle.
1828	* @param pCpumctx16 Version 1.6 CPUMCTX
1829	*/
1830	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1831	{
1832	#define CPUMCTX16_LOADREG(RegName) \
1833	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1834
1835	#define CPUMCTX16_LOADDRXREG(RegName) \
1836	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1837
1838	#define CPUMCTX16_LOADHIDREG(RegName) \
1839	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1840	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1841	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1842
1843	#define CPUMCTX16_LOADSEGREG(RegName) \
1844	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1845	CPUMCTX16_LOADHIDREG(RegName);
1846
1847	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1848
1849	CPUMCTX16_LOADREG(rax);
1850	CPUMCTX16_LOADREG(rbx);
1851	CPUMCTX16_LOADREG(rcx);
1852	CPUMCTX16_LOADREG(rdx);
1853	CPUMCTX16_LOADREG(rdi);
1854	CPUMCTX16_LOADREG(rsi);
1855	CPUMCTX16_LOADREG(rbp);
1856	CPUMCTX16_LOADREG(esp);
1857	CPUMCTX16_LOADREG(rip);
1858	CPUMCTX16_LOADREG(rflags);
1859
1860	CPUMCTX16_LOADSEGREG(cs);
1861	CPUMCTX16_LOADSEGREG(ds);
1862	CPUMCTX16_LOADSEGREG(es);
1863	CPUMCTX16_LOADSEGREG(fs);
1864	CPUMCTX16_LOADSEGREG(gs);
1865	CPUMCTX16_LOADSEGREG(ss);
1866
1867	CPUMCTX16_LOADREG(r8);
1868	CPUMCTX16_LOADREG(r9);
1869	CPUMCTX16_LOADREG(r10);
1870	CPUMCTX16_LOADREG(r11);
1871	CPUMCTX16_LOADREG(r12);
1872	CPUMCTX16_LOADREG(r13);
1873	CPUMCTX16_LOADREG(r14);
1874	CPUMCTX16_LOADREG(r15);
1875
1876	CPUMCTX16_LOADREG(cr0);
1877	CPUMCTX16_LOADREG(cr2);
1878	CPUMCTX16_LOADREG(cr3);
1879	CPUMCTX16_LOADREG(cr4);
1880
1881	CPUMCTX16_LOADDRXREG(0);
1882	CPUMCTX16_LOADDRXREG(1);
1883	CPUMCTX16_LOADDRXREG(2);
1884	CPUMCTX16_LOADDRXREG(3);
1885	CPUMCTX16_LOADDRXREG(4);
1886	CPUMCTX16_LOADDRXREG(5);
1887	CPUMCTX16_LOADDRXREG(6);
1888	CPUMCTX16_LOADDRXREG(7);
1889
1890	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
1891	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
1892	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
1893	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
1894
1895	CPUMCTX16_LOADREG(ldtr);
1896	CPUMCTX16_LOADREG(tr);
1897
1898	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
1899
1900	CPUMCTX16_LOADREG(msrEFER);
1901	CPUMCTX16_LOADREG(msrSTAR);
1902	CPUMCTX16_LOADREG(msrPAT);
1903	CPUMCTX16_LOADREG(msrLSTAR);
1904	CPUMCTX16_LOADREG(msrCSTAR);
1905	CPUMCTX16_LOADREG(msrSFMASK);
1906	CPUMCTX16_LOADREG(msrKERNELGSBASE);
1907
1908	CPUMCTX16_LOADHIDREG(ldtr);
1909	CPUMCTX16_LOADHIDREG(tr);
1910
1911	#undef CPUMCTX16_LOADSEGREG
1912	#undef CPUMCTX16_LOADHIDREG
1913	#undef CPUMCTX16_LOADDRXREG
1914	#undef CPUMCTX16_LOADREG
1915	}
1916
1917
1918	/**
1919	* @copydoc FNSSMINTLOADPREP
1920	*/
1921	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1922	{
1923	pVM->cpum.s.fPendingRestore = true;
1924	return VINF_SUCCESS;
1925	}
1926
1927
1928	/**
1929	* @copydoc FNSSMINTLOADEXEC
1930	*/
1931	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1932	{
1933	/*
1934	* Validate version.
1935	*/
1936	if ( uVersion != CPUM_SAVED_STATE_VERSION
1937	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1938	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1939	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1940	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1941	{
1942	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1943	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1944	}
1945
1946	if (uPass == SSM_PASS_FINAL)
1947	{
1948	/*
1949	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1950	* really old SSM file versions.)
1951	*/
1952	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1953	SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1954	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1955	SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1956
1957	/*
1958	* Restore.
1959	*/
1960	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1961	{
1962	PVMCPU pVCpu = &pVM->aCpus[i];
1963	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1964	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1965
1966	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1967	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1968	pVCpu->cpum.s.Hyper.esp = uESP;
1969	}
1970
1971	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1972	{
1973	CPUMCTX_VER1_6 cpumctx16;
1974	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1975	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1976
1977	/* Save the old cpumctx state into the new one. */
1978	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1979
1980	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1981	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1982	}
1983	else
1984	{
1985	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1986	{
1987	uint32_t cCpus;
1988	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1989	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1990	VERR_SSM_UNEXPECTED_DATA);
1991	}
1992	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1993	\|\| pVM->cCpus == 1,
1994	("cCpus=%u\n", pVM->cCpus),
1995	VERR_SSM_UNEXPECTED_DATA);
1996
1997	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1998	{
1999	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
2000	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
2001	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
2002	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2003	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
2004	}
2005	}
2006	}
2007
2008	pVM->cpum.s.fPendingRestore = false;
2009
2010	/*
2011	* Guest CPUIDs.
2012	*/
2013	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2014	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2015
2016	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2017	* actually required. */
2018
2019	/*
2020	* Restore the CPUID leaves.
2021	*
2022	* Note that we support restoring less than the current amount of standard
2023	* leaves because we've been allowed more is newer version of VBox.
2024	*/
2025	uint32_t cElements;
2026	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2027	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2028	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2029	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2030
2031	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2032	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2033	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2034	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2035
2036	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2037	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2038	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2039	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2040
2041	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2042
2043	/*
2044	* Check that the basic cpuid id information is unchanged.
2045	*/
2046	/** @todo we should check the 64 bits capabilities too! */
2047	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2048	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2049	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2050	uint32_t au32CpuIdSaved[8];
2051	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2052	if (RT_SUCCESS(rc))
2053	{
2054	/* Ignore CPU stepping. */
2055	au32CpuId[4] &= 0xfffffff0;
2056	au32CpuIdSaved[4] &= 0xfffffff0;
2057
2058	/* Ignore APIC ID (AMD specs). */
2059	au32CpuId[5] &= ~0xff000000;
2060	au32CpuIdSaved[5] &= ~0xff000000;
2061
2062	/* Ignore the number of Logical CPUs (AMD specs). */
2063	au32CpuId[5] &= ~0x00ff0000;
2064	au32CpuIdSaved[5] &= ~0x00ff0000;
2065
2066	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2067	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2068	\| X86_CPUID_FEATURE_ECX_VMX
2069	\| X86_CPUID_FEATURE_ECX_SMX
2070	\| X86_CPUID_FEATURE_ECX_EST
2071	\| X86_CPUID_FEATURE_ECX_TM2
2072	\| X86_CPUID_FEATURE_ECX_CNTXID
2073	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2074	\| X86_CPUID_FEATURE_ECX_PDCM
2075	\| X86_CPUID_FEATURE_ECX_DCA
2076	\| X86_CPUID_FEATURE_ECX_X2APIC
2077	);
2078	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2079	\| X86_CPUID_FEATURE_ECX_VMX
2080	\| X86_CPUID_FEATURE_ECX_SMX
2081	\| X86_CPUID_FEATURE_ECX_EST
2082	\| X86_CPUID_FEATURE_ECX_TM2
2083	\| X86_CPUID_FEATURE_ECX_CNTXID
2084	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2085	\| X86_CPUID_FEATURE_ECX_PDCM
2086	\| X86_CPUID_FEATURE_ECX_DCA
2087	\| X86_CPUID_FEATURE_ECX_X2APIC
2088	);
2089
2090	/* Make sure we don't forget to update the masks when enabling
2091	* features in the future.
2092	*/
2093	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2094	( X86_CPUID_FEATURE_ECX_DTES64
2095	\| X86_CPUID_FEATURE_ECX_VMX
2096	\| X86_CPUID_FEATURE_ECX_SMX
2097	\| X86_CPUID_FEATURE_ECX_EST
2098	\| X86_CPUID_FEATURE_ECX_TM2
2099	\| X86_CPUID_FEATURE_ECX_CNTXID
2100	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2101	\| X86_CPUID_FEATURE_ECX_PDCM
2102	\| X86_CPUID_FEATURE_ECX_DCA
2103	\| X86_CPUID_FEATURE_ECX_X2APIC
2104	)));
2105	/* do the compare */
2106	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2107	{
2108	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2109	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2110	"Saved=%.*Rhxs\n"
2111	"Real =%.*Rhxs\n",
2112	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2113	sizeof(au32CpuId), au32CpuId));
2114	else
2115	{
2116	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2117	"Saved=%.*Rhxs\n"
2118	"Real =%.*Rhxs\n",
2119	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2120	sizeof(au32CpuId), au32CpuId));
2121	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2122	}
2123	}
2124	}
2125
2126	return rc;
2127	}
2128
2129
2130	/**
2131	* @copydoc FNSSMINTLOADPREP
2132	*/
2133	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2134	{
2135	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2136	return VINF_SUCCESS;
2137
2138	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2139	if (pVM->cpum.s.fPendingRestore)
2140	{
2141	LogRel(("CPUM: Missing state!\n"));
2142	return VERR_INTERNAL_ERROR_2;
2143	}
2144
2145	return VINF_SUCCESS;
2146	}
2147
2148
2149	/**
2150	* Checks if the CPUM state restore is still pending.
2151	*
2152	* @returns true / false.
2153	* @param pVM The VM handle.
2154	*/
2155	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2156	{
2157	return pVM->cpum.s.fPendingRestore;
2158	}
2159
2160
2161	/**
2162	* Formats the EFLAGS value into mnemonics.
2163	*
2164	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2165	* @param efl The EFLAGS value.
2166	*/
2167	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2168	{
2169	/*
2170	* Format the flags.
2171	*/
2172	static const struct
2173	{
2174	const char pszSet; const char pszClear; uint32_t fFlag;
2175	} s_aFlags[] =
2176	{
2177	{ "vip",NULL, X86_EFL_VIP },
2178	{ "vif",NULL, X86_EFL_VIF },
2179	{ "ac", NULL, X86_EFL_AC },
2180	{ "vm", NULL, X86_EFL_VM },
2181	{ "rf", NULL, X86_EFL_RF },
2182	{ "nt", NULL, X86_EFL_NT },
2183	{ "ov", "nv", X86_EFL_OF },
2184	{ "dn", "up", X86_EFL_DF },
2185	{ "ei", "di", X86_EFL_IF },
2186	{ "tf", NULL, X86_EFL_TF },
2187	{ "nt", "pl", X86_EFL_SF },
2188	{ "nz", "zr", X86_EFL_ZF },
2189	{ "ac", "na", X86_EFL_AF },
2190	{ "po", "pe", X86_EFL_PF },
2191	{ "cy", "nc", X86_EFL_CF },
2192	};
2193	char *psz = pszEFlags;
2194	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2195	{
2196	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2197	if (pszAdd)
2198	{
2199	strcpy(psz, pszAdd);
2200	psz += strlen(pszAdd);
2201	*psz++ = ' ';
2202	}
2203	}
2204	psz[-1] = '\0';
2205	}
2206
2207
2208	/**
2209	* Formats a full register dump.
2210	*
2211	* @param pVM VM Handle.
2212	* @param pCtx The context to format.
2213	* @param pCtxCore The context core to format.
2214	* @param pHlp Output functions.
2215	* @param enmType The dump type.
2216	* @param pszPrefix Register name prefix.
2217	*/
2218	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2219	{
2220	/*
2221	* Format the EFLAGS.
2222	*/
2223	uint32_t efl = pCtxCore->eflags.u32;
2224	char szEFlags[80];
2225	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2226
2227	/*
2228	* Format the registers.
2229	*/
2230	switch (enmType)
2231	{
2232	case CPUMDUMPTYPE_TERSE:
2233	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2234	pHlp->pfnPrintf(pHlp,
2235	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2236	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2237	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2238	"%sr14=%016RX64 %sr15=%016RX64\n"
2239	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2240	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2241	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2242	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2243	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2244	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2245	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2246	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2247	else
2248	pHlp->pfnPrintf(pHlp,
2249	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2250	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2251	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2252	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2253	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2254	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2255	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2256	break;
2257
2258	case CPUMDUMPTYPE_DEFAULT:
2259	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2260	pHlp->pfnPrintf(pHlp,
2261	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2262	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2263	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2264	"%sr14=%016RX64 %sr15=%016RX64\n"
2265	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2266	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2267	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2268	,
2269	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2270	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2271	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2272	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2273	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2274	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2275	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2276	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2277	else
2278	pHlp->pfnPrintf(pHlp,
2279	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2280	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2281	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2282	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2283	,
2284	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2285	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2286	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2287	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2288	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2289	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2290	break;
2291
2292	case CPUMDUMPTYPE_VERBOSE:
2293	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2294	pHlp->pfnPrintf(pHlp,
2295	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2296	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2297	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2298	"%sr14=%016RX64 %sr15=%016RX64\n"
2299	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2300	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2301	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2302	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2303	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2304	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2305	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2306	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2307	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2308	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2309	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2310	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2311	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2312	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2313	,
2314	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2315	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2316	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2317	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2318	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2319	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2320	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2321	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2322	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2323	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2324	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2325	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2326	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2327	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2328	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2329	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2330	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2331	else
2332	pHlp->pfnPrintf(pHlp,
2333	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2334	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2335	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2336	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2337	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2338	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2339	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2340	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2341	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2342	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2343	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2344	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2345	,
2346	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2347	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2348	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2349	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2350	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2351	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2352	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2353	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2354	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2355	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2356	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2357	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2358
2359	pHlp->pfnPrintf(pHlp,
2360	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2361	"%sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2362	,
2363	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2364	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2365	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2366	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2367	);
2368	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2369	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2370	{
2371	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2372	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2373	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2374	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2375	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2376	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2377	/** @todo This isn't entirenly correct and needs more work! */
2378	pHlp->pfnPrintf(pHlp,
2379	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2380	pszPrefix, iST, pszPrefix, iFPR,
2381	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2382	uTag, chSign, iInteger, u64Fraction, uExponent);
2383	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2384	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2385	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2386	else
2387	pHlp->pfnPrintf(pHlp, "\n");
2388	}
2389	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2390	pHlp->pfnPrintf(pHlp,
2391	iXMM & 1
2392	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2393	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2394	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2395	pCtx->fpu.aXMM[iXMM].au32[3],
2396	pCtx->fpu.aXMM[iXMM].au32[2],
2397	pCtx->fpu.aXMM[iXMM].au32[1],
2398	pCtx->fpu.aXMM[iXMM].au32[0]);
2399	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2400	if (pCtx->fpu.au32RsrvdRest[i])
2401	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2402	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2403
2404	pHlp->pfnPrintf(pHlp,
2405	"%sEFER =%016RX64\n"
2406	"%sPAT =%016RX64\n"
2407	"%sSTAR =%016RX64\n"
2408	"%sCSTAR =%016RX64\n"
2409	"%sLSTAR =%016RX64\n"
2410	"%sSFMASK =%016RX64\n"
2411	"%sKERNELGSBASE =%016RX64\n",
2412	pszPrefix, pCtx->msrEFER,
2413	pszPrefix, pCtx->msrPAT,
2414	pszPrefix, pCtx->msrSTAR,
2415	pszPrefix, pCtx->msrCSTAR,
2416	pszPrefix, pCtx->msrLSTAR,
2417	pszPrefix, pCtx->msrSFMASK,
2418	pszPrefix, pCtx->msrKERNELGSBASE);
2419	break;
2420	}
2421	}
2422
2423
2424	/**
2425	* Display all cpu states and any other cpum info.
2426	*
2427	* @param pVM VM Handle.
2428	* @param pHlp The info helper functions.
2429	* @param pszArgs Arguments, ignored.
2430	*/
2431	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2432	{
2433	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2434	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2435	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2436	cpumR3InfoHost(pVM, pHlp, pszArgs);
2437	}
2438
2439
2440	/**
2441	* Parses the info argument.
2442	*
2443	* The argument starts with 'verbose', 'terse' or 'default' and then
2444	* continues with the comment string.
2445	*
2446	* @param pszArgs The pointer to the argument string.
2447	* @param penmType Where to store the dump type request.
2448	* @param ppszComment Where to store the pointer to the comment string.
2449	*/
2450	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2451	{
2452	if (!pszArgs)
2453	{
2454	*penmType = CPUMDUMPTYPE_DEFAULT;
2455	*ppszComment = "";
2456	}
2457	else
2458	{
2459	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2460	{
2461	pszArgs += 5;
2462	*penmType = CPUMDUMPTYPE_VERBOSE;
2463	}
2464	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2465	{
2466	pszArgs += 5;
2467	*penmType = CPUMDUMPTYPE_TERSE;
2468	}
2469	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2470	{
2471	pszArgs += 7;
2472	*penmType = CPUMDUMPTYPE_DEFAULT;
2473	}
2474	else
2475	*penmType = CPUMDUMPTYPE_DEFAULT;
2476	*ppszComment = RTStrStripL(pszArgs);
2477	}
2478	}
2479
2480
2481	/**
2482	* Display the guest cpu state.
2483	*
2484	* @param pVM VM Handle.
2485	* @param pHlp The info helper functions.
2486	* @param pszArgs Arguments, ignored.
2487	*/
2488	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2489	{
2490	CPUMDUMPTYPE enmType;
2491	const char *pszComment;
2492	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2493
2494	/* @todo SMP support! */
2495	PVMCPU pVCpu = VMMGetCpu(pVM);
2496	if (!pVCpu)
2497	pVCpu = &pVM->aCpus[0];
2498
2499	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2500
2501	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2502	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2503	}
2504
2505
2506	/**
2507	* Display the current guest instruction
2508	*
2509	* @param pVM VM Handle.
2510	* @param pHlp The info helper functions.
2511	* @param pszArgs Arguments, ignored.
2512	*/
2513	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2514	{
2515	char szInstruction[256];
2516	/* @todo SMP support! */
2517	PVMCPU pVCpu = VMMGetCpu(pVM);
2518	if (!pVCpu)
2519	pVCpu = &pVM->aCpus[0];
2520
2521	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2522	if (RT_SUCCESS(rc))
2523	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2524	}
2525
2526
2527	/**
2528	* Display the hypervisor cpu state.
2529	*
2530	* @param pVM VM Handle.
2531	* @param pHlp The info helper functions.
2532	* @param pszArgs Arguments, ignored.
2533	*/
2534	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2535	{
2536	CPUMDUMPTYPE enmType;
2537	const char *pszComment;
2538	/* @todo SMP */
2539	PVMCPU pVCpu = &pVM->aCpus[0];
2540
2541	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2542	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2543	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2544	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2545	}
2546
2547
2548	/**
2549	* Display the host cpu state.
2550	*
2551	* @param pVM VM Handle.
2552	* @param pHlp The info helper functions.
2553	* @param pszArgs Arguments, ignored.
2554	*/
2555	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2556	{
2557	CPUMDUMPTYPE enmType;
2558	const char *pszComment;
2559	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2560	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2561
2562	/*
2563	* Format the EFLAGS.
2564	*/
2565	/* @todo SMP */
2566	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2567	#if HC_ARCH_BITS == 32
2568	uint32_t efl = pCtx->eflags.u32;
2569	#else
2570	uint64_t efl = pCtx->rflags;
2571	#endif
2572	char szEFlags[80];
2573	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2574
2575	/*
2576	* Format the registers.
2577	*/
2578	#if HC_ARCH_BITS == 32
2579	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2580	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2581	# endif
2582	{
2583	pHlp->pfnPrintf(pHlp,
2584	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2585	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2586	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2587	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2588	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2589	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2590	,
2591	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2592	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2593	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2594	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2595	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2596	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2597	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2598	}
2599	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2600	else
2601	# endif
2602	#endif
2603	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2604	{
2605	pHlp->pfnPrintf(pHlp,
2606	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2607	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2608	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2609	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2610	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2611	"r14=%016RX64 r15=%016RX64\n"
2612	"iopl=%d %31s\n"
2613	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2614	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2615	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2616	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2617	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2618	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2619	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2620	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2621	,
2622	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2623	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2624	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2625	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2626	pCtx->r11, pCtx->r12, pCtx->r13,
2627	pCtx->r14, pCtx->r15,
2628	X86_EFL_GET_IOPL(efl), szEFlags,
2629	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2630	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2631	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2632	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2633	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2634	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2635	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2636	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2637	}
2638	#endif
2639	}
2640
2641
2642	/**
2643	* Get L1 cache / TLS associativity.
2644	*/
2645	static const char getCacheAss(unsigned u, char pszBuf)
2646	{
2647	if (u == 0)
2648	return "res0 ";
2649	if (u == 1)
2650	return "direct";
2651	if (u >= 256)
2652	return "???";
2653
2654	RTStrPrintf(pszBuf, 16, "%d way", u);
2655	return pszBuf;
2656	}
2657
2658
2659	/**
2660	* Get L2 cache soociativity.
2661	*/
2662	const char *getL2CacheAss(unsigned u)
2663	{
2664	switch (u)
2665	{
2666	case 0: return "off ";
2667	case 1: return "direct";
2668	case 2: return "2 way ";
2669	case 3: return "res3 ";
2670	case 4: return "4 way ";
2671	case 5: return "res5 ";
2672	case 6: return "8 way "; case 7: return "res7 ";
2673	case 8: return "16 way";
2674	case 9: return "res9 ";
2675	case 10: return "res10 ";
2676	case 11: return "res11 ";
2677	case 12: return "res12 ";
2678	case 13: return "res13 ";
2679	case 14: return "res14 ";
2680	case 15: return "fully ";
2681	default:
2682	return "????";
2683	}
2684	}
2685
2686
2687	/**
2688	* Display the guest CpuId leaves.
2689	*
2690	* @param pVM VM Handle.
2691	* @param pHlp The info helper functions.
2692	* @param pszArgs "terse", "default" or "verbose".
2693	*/
2694	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2695	{
2696	/*
2697	* Parse the argument.
2698	*/
2699	unsigned iVerbosity = 1;
2700	if (pszArgs)
2701	{
2702	pszArgs = RTStrStripL(pszArgs);
2703	if (!strcmp(pszArgs, "terse"))
2704	iVerbosity--;
2705	else if (!strcmp(pszArgs, "verbose"))
2706	iVerbosity++;
2707	}
2708
2709	/*
2710	* Start cracking.
2711	*/
2712	CPUMCPUID Host;
2713	CPUMCPUID Guest;
2714	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2715
2716	pHlp->pfnPrintf(pHlp,
2717	" RAW Standard CPUIDs\n"
2718	" Function eax ebx ecx edx\n");
2719	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2720	{
2721	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2722	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2723
2724	pHlp->pfnPrintf(pHlp,
2725	"Gst: %08x %08x %08x %08x %08x%s\n"
2726	"Hst: %08x %08x %08x %08x\n",
2727	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2728	i <= cStdMax ? "" : "*",
2729	Host.eax, Host.ebx, Host.ecx, Host.edx);
2730	}
2731
2732	/*
2733	* If verbose, decode it.
2734	*/
2735	if (iVerbosity)
2736	{
2737	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2738	pHlp->pfnPrintf(pHlp,
2739	"Name: %.04s%.04s%.04s\n"
2740	"Supports: 0-%x\n",
2741	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2742	}
2743
2744	/*
2745	* Get Features.
2746	*/
2747	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2748	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2749	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2750	if (cStdMax >= 1 && iVerbosity)
2751	{
2752	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2753	uint32_t uEAX = Guest.eax;
2754
2755	pHlp->pfnPrintf(pHlp,
2756	"Family: %d \tExtended: %d \tEffective: %d\n"
2757	"Model: %d \tExtended: %d \tEffective: %d\n"
2758	"Stepping: %d\n"
2759	"Type: %d\n"
2760	"APIC ID: %#04x\n"
2761	"Logical CPUs: %d\n"
2762	"CLFLUSH Size: %d\n"
2763	"Brand ID: %#04x\n",
2764	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2765	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2766	ASMGetCpuStepping(uEAX),
2767	(uEAX >> 12) & 3,
2768	(Guest.ebx >> 24) & 0xff,
2769	(Guest.ebx >> 16) & 0xff,
2770	(Guest.ebx >> 8) & 0xff,
2771	(Guest.ebx >> 0) & 0xff);
2772	if (iVerbosity == 1)
2773	{
2774	uint32_t uEDX = Guest.edx;
2775	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2776	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2777	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2778	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2779	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2780	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2781	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2782	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2783	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2784	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2785	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2786	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2787	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2788	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2789	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2790	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2791	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2792	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2793	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2794	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2795	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2796	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2797	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2798	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2799	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2800	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2801	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2802	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2803	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2804	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2805	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2806	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2807	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2808	pHlp->pfnPrintf(pHlp, "\n");
2809
2810	uint32_t uECX = Guest.ecx;
2811	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2812	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2813	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2814	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2815	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2816	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2817	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2818	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2819	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2820	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2821	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2822	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2823	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2824	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2825	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2826	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2827	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2828	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2829	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " 17");
2830	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2831	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4_1");
2832	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4_2");
2833	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2834	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2835	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2836	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " 24");
2837	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2838	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2839	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2840	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2841	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2842	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2843	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2844	pHlp->pfnPrintf(pHlp, "\n");
2845	}
2846	else
2847	{
2848	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2849
2850	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2851	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2852	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2853	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2854
2855	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2856	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2857	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2858	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2859	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2860	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2861	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2862	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2863	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2864	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2865	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2866	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2867	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2868	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2869	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2870	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
2871	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
2872	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
2873	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
2874	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
2875	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
2876	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
2877	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
2878	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
2879	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
2880	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
2881	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
2882	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
2883	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
2884	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
2885	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
2886	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
2887	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
2888
2889	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
2890	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
2891	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
2892	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
2893	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
2894	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
2895	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
2896	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2897	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
2898	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
2899	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
2900	pHlp->pfnPrintf(pHlp, "FMA = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
2901	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
2902	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
2903	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
2904	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
2905	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
2906	pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
2907	pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
2908	pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
2909	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
2910	pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
2911	pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
2912	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
2913	pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
2914	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
2915	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
2916	}
2917	}
2918	if (cStdMax >= 2 && iVerbosity)
2919	{
2920	/** @todo */
2921	}
2922
2923	/*
2924	* Extended.
2925	* Implemented after AMD specs.
2926	*/
2927	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
2928
2929	pHlp->pfnPrintf(pHlp,
2930	"\n"
2931	" RAW Extended CPUIDs\n"
2932	" Function eax ebx ecx edx\n");
2933	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
2934	{
2935	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
2936	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2937
2938	pHlp->pfnPrintf(pHlp,
2939	"Gst: %08x %08x %08x %08x %08x%s\n"
2940	"Hst: %08x %08x %08x %08x\n",
2941	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2942	i <= cExtMax ? "" : "*",
2943	Host.eax, Host.ebx, Host.ecx, Host.edx);
2944	}
2945
2946	/*
2947	* Understandable output
2948	*/
2949	if (iVerbosity)
2950	{
2951	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
2952	pHlp->pfnPrintf(pHlp,
2953	"Ext Name: %.4s%.4s%.4s\n"
2954	"Ext Supports: 0x80000000-%#010x\n",
2955	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2956	}
2957
2958	if (iVerbosity && cExtMax >= 1)
2959	{
2960	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
2961	uint32_t uEAX = Guest.eax;
2962	pHlp->pfnPrintf(pHlp,
2963	"Family: %d \tExtended: %d \tEffective: %d\n"
2964	"Model: %d \tExtended: %d \tEffective: %d\n"
2965	"Stepping: %d\n"
2966	"Brand ID: %#05x\n",
2967	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2968	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2969	ASMGetCpuStepping(uEAX),
2970	Guest.ebx & 0xfff);
2971
2972	if (iVerbosity == 1)
2973	{
2974	uint32_t uEDX = Guest.edx;
2975	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2976	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2977	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2978	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2979	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2980	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2981	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2982	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2983	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2984	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2985	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2986	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2987	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
2988	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2989	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2990	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2991	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2992	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2993	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2994	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
2995	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
2996	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
2997	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
2998	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
2999	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3000	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3001	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3002	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3003	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3004	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3005	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3006	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3007	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3008	pHlp->pfnPrintf(pHlp, "\n");
3009
3010	uint32_t uECX = Guest.ecx;
3011	pHlp->pfnPrintf(pHlp, "Features ECX: ");
3012	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3013	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3014	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3015	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3016	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3017	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3018	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3019	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3020	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3021	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3022	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3023	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3024	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3025	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3026	for (unsigned iBit = 5; iBit < 32; iBit++)
3027	if (uECX & RT_BIT(iBit))
3028	pHlp->pfnPrintf(pHlp, " %d", iBit);
3029	pHlp->pfnPrintf(pHlp, "\n");
3030	}
3031	else
3032	{
3033	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3034
3035	uint32_t uEdxGst = Guest.edx;
3036	uint32_t uEdxHst = Host.edx;
3037	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3038	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3039	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3040	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3041	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3042	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3043	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3044	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3045	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3046	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3047	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3048	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3049	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3050	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3051	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3052	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3053	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3054	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3055	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3056	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3057	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3058	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3059	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3060	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3061	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3062	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3063	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3064	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3065	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3066	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3067	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3068	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3069	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3070
3071	uint32_t uEcxGst = Guest.ecx;
3072	uint32_t uEcxHst = Host.ecx;
3073	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3074	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3075	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3076	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3077	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3078	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3079	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3080	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3081	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3082	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3083	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3084	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3085	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3086	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3087	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3088	}
3089	}
3090
3091	if (iVerbosity && cExtMax >= 2)
3092	{
3093	char szString[443+1] = {0};
3094	uint32_t pu32 = (uint32_t )szString;
3095	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3096	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3097	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3098	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3099	if (cExtMax >= 3)
3100	{
3101	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3102	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3103	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3104	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3105	}
3106	if (cExtMax >= 4)
3107	{
3108	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3109	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3110	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3111	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3112	}
3113	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3114	}
3115
3116	if (iVerbosity && cExtMax >= 5)
3117	{
3118	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3119	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3120	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3121	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3122	char sz1[32];
3123	char sz2[32];
3124
3125	pHlp->pfnPrintf(pHlp,
3126	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3127	"TLB 2/4M Data: %s %3d entries\n",
3128	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3129	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3130	pHlp->pfnPrintf(pHlp,
3131	"TLB 4K Instr/Uni: %s %3d entries\n"
3132	"TLB 4K Data: %s %3d entries\n",
3133	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3134	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3135	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3136	"L1 Instr Cache Lines Per Tag: %d\n"
3137	"L1 Instr Cache Associativity: %s\n"
3138	"L1 Instr Cache Size: %d KB\n",
3139	(uEDX >> 0) & 0xff,
3140	(uEDX >> 8) & 0xff,
3141	getCacheAss((uEDX >> 16) & 0xff, sz1),
3142	(uEDX >> 24) & 0xff);
3143	pHlp->pfnPrintf(pHlp,
3144	"L1 Data Cache Line Size: %d bytes\n"
3145	"L1 Data Cache Lines Per Tag: %d\n"
3146	"L1 Data Cache Associativity: %s\n"
3147	"L1 Data Cache Size: %d KB\n",
3148	(uECX >> 0) & 0xff,
3149	(uECX >> 8) & 0xff,
3150	getCacheAss((uECX >> 16) & 0xff, sz1),
3151	(uECX >> 24) & 0xff);
3152	}
3153
3154	if (iVerbosity && cExtMax >= 6)
3155	{
3156	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3157	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3158	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3159
3160	pHlp->pfnPrintf(pHlp,
3161	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3162	"L2 TLB 2/4M Data: %s %4d entries\n",
3163	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3164	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3165	pHlp->pfnPrintf(pHlp,
3166	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3167	"L2 TLB 4K Data: %s %4d entries\n",
3168	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3169	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3170	pHlp->pfnPrintf(pHlp,
3171	"L2 Cache Line Size: %d bytes\n"
3172	"L2 Cache Lines Per Tag: %d\n"
3173	"L2 Cache Associativity: %s\n"
3174	"L2 Cache Size: %d KB\n",
3175	(uEDX >> 0) & 0xff,
3176	(uEDX >> 8) & 0xf,
3177	getL2CacheAss((uEDX >> 12) & 0xf),
3178	(uEDX >> 16) & 0xffff);
3179	}
3180
3181	if (iVerbosity && cExtMax >= 7)
3182	{
3183	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3184
3185	pHlp->pfnPrintf(pHlp, "APM Features: ");
3186	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3187	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3188	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3189	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3190	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3191	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3192	for (unsigned iBit = 6; iBit < 32; iBit++)
3193	if (uEDX & RT_BIT(iBit))
3194	pHlp->pfnPrintf(pHlp, " %d", iBit);
3195	pHlp->pfnPrintf(pHlp, "\n");
3196	}
3197
3198	if (iVerbosity && cExtMax >= 8)
3199	{
3200	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3201	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3202
3203	pHlp->pfnPrintf(pHlp,
3204	"Physical Address Width: %d bits\n"
3205	"Virtual Address Width: %d bits\n",
3206	(uEAX >> 0) & 0xff,
3207	(uEAX >> 8) & 0xff);
3208	pHlp->pfnPrintf(pHlp,
3209	"Physical Core Count: %d\n",
3210	(uECX >> 0) & 0xff);
3211	}
3212
3213
3214	/*
3215	* Centaur.
3216	*/
3217	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3218
3219	pHlp->pfnPrintf(pHlp,
3220	"\n"
3221	" RAW Centaur CPUIDs\n"
3222	" Function eax ebx ecx edx\n");
3223	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3224	{
3225	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3226	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3227
3228	pHlp->pfnPrintf(pHlp,
3229	"Gst: %08x %08x %08x %08x %08x%s\n"
3230	"Hst: %08x %08x %08x %08x\n",
3231	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3232	i <= cCentaurMax ? "" : "*",
3233	Host.eax, Host.ebx, Host.ecx, Host.edx);
3234	}
3235
3236	/*
3237	* Understandable output
3238	*/
3239	if (iVerbosity)
3240	{
3241	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3242	pHlp->pfnPrintf(pHlp,
3243	"Centaur Supports: 0xc0000000-%#010x\n",
3244	Guest.eax);
3245	}
3246
3247	if (iVerbosity && cCentaurMax >= 1)
3248	{
3249	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3250	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3251	uint32_t uEdxHst = Host.edx;
3252
3253	if (iVerbosity == 1)
3254	{
3255	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3256	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3257	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3258	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3259	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3260	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3261	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3262	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3263	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3264	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3265	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3266	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3267	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3268	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3269	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3270	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3271	for (unsigned iBit = 14; iBit < 32; iBit++)
3272	if (uEdxGst & RT_BIT(iBit))
3273	pHlp->pfnPrintf(pHlp, " %d", iBit);
3274	pHlp->pfnPrintf(pHlp, "\n");
3275	}
3276	else
3277	{
3278	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3279	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3280	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3281	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3282	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3283	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3284	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3285	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3286	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3287	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3288	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3289	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3290	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3291	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3292	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3293	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3294	for (unsigned iBit = 14; iBit < 32; iBit++)
3295	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3296	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3297	pHlp->pfnPrintf(pHlp, "\n");
3298	}
3299	}
3300	}
3301
3302
3303	/**
3304	* Structure used when disassembling and instructions in DBGF.
3305	* This is used so the reader function can get the stuff it needs.
3306	*/
3307	typedef struct CPUMDISASSTATE
3308	{
3309	/** Pointer to the CPU structure. */
3310	PDISCPUSTATE pCpu;
3311	/** The VM handle. */
3312	PVM pVM;
3313	/** The VMCPU handle. */
3314	PVMCPU pVCpu;
3315	/** Pointer to the first byte in the segemnt. */
3316	RTGCUINTPTR GCPtrSegBase;
3317	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3318	RTGCUINTPTR GCPtrSegEnd;
3319	/** The size of the segment minus 1. */
3320	RTGCUINTPTR cbSegLimit;
3321	/** Pointer to the current page - R3 Ptr. */
3322	void const *pvPageR3;
3323	/** Pointer to the current page - GC Ptr. */
3324	RTGCPTR pvPageGC;
3325	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3326	PGMPAGEMAPLOCK PageMapLock;
3327	/** Whether the PageMapLock is valid or not. */
3328	bool fLocked;
3329	/** 64 bits mode or not. */
3330	bool f64Bits;
3331	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3332
3333
3334	/**
3335	* Instruction reader.
3336	*
3337	* @returns VBox status code.
3338	* @param PtrSrc Address to read from.
3339	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3340	* @param pu8Dst Where to store the bytes.
3341	* @param cbRead Number of bytes to read.
3342	* @param uDisCpu Pointer to the disassembler cpu state.
3343	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3344	*/
3345	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3346	{
3347	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3348	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3349	Assert(cbRead > 0);
3350	for (;;)
3351	{
3352	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3353
3354	/* Need to update the page translation? */
3355	if ( !pState->pvPageR3
3356	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3357	{
3358	int rc = VINF_SUCCESS;
3359
3360	/* translate the address */
3361	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3362	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3363	&& !HWACCMIsEnabled(pState->pVM))
3364	{
3365	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3366	if (!pState->pvPageR3)
3367	rc = VERR_INVALID_POINTER;
3368	}
3369	else
3370	{
3371	/* Release mapping lock previously acquired. */
3372	if (pState->fLocked)
3373	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3374	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3375	pState->fLocked = RT_SUCCESS_NP(rc);
3376	}
3377	if (RT_FAILURE(rc))
3378	{
3379	pState->pvPageR3 = NULL;
3380	return rc;
3381	}
3382	}
3383
3384	/* check the segemnt limit */
3385	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3386	return VERR_OUT_OF_SELECTOR_BOUNDS;
3387
3388	/* calc how much we can read */
3389	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3390	if (!pState->f64Bits)
3391	{
3392	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3393	if (cb > cbSeg && cbSeg)
3394	cb = cbSeg;
3395	}
3396	if (cb > cbRead)
3397	cb = cbRead;
3398
3399	/* read and advance */
3400	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3401	cbRead -= cb;
3402	if (!cbRead)
3403	return VINF_SUCCESS;
3404	pu8Dst += cb;
3405	PtrSrc += cb;
3406	}
3407	}
3408
3409
3410	/**
3411	* Disassemble an instruction and return the information in the provided structure.
3412	*
3413	* @returns VBox status code.
3414	* @param pVM VM Handle
3415	* @param pVCpu VMCPU Handle
3416	* @param pCtx CPU context
3417	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3418	* @param pCpu Disassembly state
3419	* @param pszPrefix String prefix for logging (debug only)
3420	*
3421	*/
3422	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3423	{
3424	CPUMDISASSTATE State;
3425	int rc;
3426
3427	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3428	State.pCpu = pCpu;
3429	State.pvPageGC = 0;
3430	State.pvPageR3 = NULL;
3431	State.pVM = pVM;
3432	State.pVCpu = pVCpu;
3433	State.fLocked = false;
3434	State.f64Bits = false;
3435
3436	/*
3437	* Get selector information.
3438	*/
3439	if ( (pCtx->cr0 & X86_CR0_PE)
3440	&& pCtx->eflags.Bits.u1VM == 0)
3441	{
3442	if (CPUMAreHiddenSelRegsValid(pVM))
3443	{
3444	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3445	State.GCPtrSegBase = pCtx->csHid.u64Base;
3446	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3447	State.cbSegLimit = pCtx->csHid.u32Limit;
3448	pCpu->mode = (State.f64Bits)
3449	? CPUMODE_64BIT
3450	: pCtx->csHid.Attr.n.u1DefBig
3451	? CPUMODE_32BIT
3452	: CPUMODE_16BIT;
3453	}
3454	else
3455	{
3456	DBGFSELINFO SelInfo;
3457
3458	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3459	if (RT_FAILURE(rc))
3460	{
3461	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3462	return rc;
3463	}
3464
3465	/*
3466	* Validate the selector.
3467	*/
3468	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3469	if (RT_FAILURE(rc))
3470	{
3471	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3472	return rc;
3473	}
3474	State.GCPtrSegBase = SelInfo.GCPtrBase;
3475	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3476	State.cbSegLimit = SelInfo.cbLimit;
3477	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3478	}
3479	}
3480	else
3481	{
3482	/* real or V86 mode */
3483	pCpu->mode = CPUMODE_16BIT;
3484	State.GCPtrSegBase = pCtx->cs * 16;
3485	State.GCPtrSegEnd = 0xFFFFFFFF;
3486	State.cbSegLimit = 0xFFFFFFFF;
3487	}
3488
3489	/*
3490	* Disassemble the instruction.
3491	*/
3492	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3493	pCpu->apvUserData[0] = &State;
3494
3495	uint32_t cbInstr;
3496	#ifndef LOG_ENABLED
3497	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3498	if (RT_SUCCESS(rc))
3499	{
3500	#else
3501	char szOutput[160];
3502	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3503	if (RT_SUCCESS(rc))
3504	{
3505	/* log it */
3506	if (pszPrefix)
3507	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3508	else
3509	Log(("%s", szOutput));
3510	#endif
3511	rc = VINF_SUCCESS;
3512	}
3513	else
3514	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3515
3516	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3517	if (State.fLocked)
3518	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3519
3520	return rc;
3521	}
3522
3523	#ifdef DEBUG
3524
3525	/**
3526	* Disassemble an instruction and dump it to the log
3527	*
3528	* @returns VBox status code.
3529	* @param pVM VM Handle
3530	* @param pVCpu VMCPU Handle
3531	* @param pCtx CPU context
3532	* @param pc GC instruction pointer
3533	* @param pszPrefix String prefix for logging
3534	*
3535	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3536	*/
3537	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3538	{
3539	DISCPUSTATE Cpu;
3540	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3541	}
3542
3543
3544	/**
3545	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3546	*
3547	* @internal
3548	*/
3549	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3550	{
3551	/** @todo SMP support!! */
3552	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3553	}
3554
3555	#endif /* DEBUG */
3556
3557	/**
3558	* API for controlling a few of the CPU features found in CR4.
3559	*
3560	* Currently only X86_CR4_TSD is accepted as input.
3561	*
3562	* @returns VBox status code.
3563	*
3564	* @param pVM The VM handle.
3565	* @param fOr The CR4 OR mask.
3566	* @param fAnd The CR4 AND mask.
3567	*/
3568	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3569	{
3570	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3571	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3572
3573	pVM->cpum.s.CR4.OrMask &= fAnd;
3574	pVM->cpum.s.CR4.OrMask \|= fOr;
3575
3576	return VINF_SUCCESS;
3577	}
3578
3579
3580	/**
3581	* Gets a pointer to the array of standard CPUID leaves.
3582	*
3583	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3584	*
3585	* @returns Pointer to the standard CPUID leaves (read-only).
3586	* @param pVM The VM handle.
3587	* @remark Intended for PATM.
3588	*/
3589	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3590	{
3591	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3592	}
3593
3594
3595	/**
3596	* Gets a pointer to the array of extended CPUID leaves.
3597	*
3598	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3599	*
3600	* @returns Pointer to the extended CPUID leaves (read-only).
3601	* @param pVM The VM handle.
3602	* @remark Intended for PATM.
3603	*/
3604	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3605	{
3606	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3607	}
3608
3609
3610	/**
3611	* Gets a pointer to the array of centaur CPUID leaves.
3612	*
3613	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3614	*
3615	* @returns Pointer to the centaur CPUID leaves (read-only).
3616	* @param pVM The VM handle.
3617	* @remark Intended for PATM.
3618	*/
3619	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3620	{
3621	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3622	}
3623
3624
3625	/**
3626	* Gets a pointer to the default CPUID leaf.
3627	*
3628	* @returns Pointer to the default CPUID leaf (read-only).
3629	* @param pVM The VM handle.
3630	* @remark Intended for PATM.
3631	*/
3632	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3633	{
3634	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3635	}

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 28112

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