CPUM.cpp@ 30978

Last change on this file since 30978 was 30861, checked in by vboxsync, 14 years ago
VMM,REM: Replumbled the MSR updating and reading so that PGM can easily be notified when EFER.NXE changes.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 187.5 KB

Line
1	/* $Id: CPUM.cpp 30861 2010-07-15 18:09:29Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers accross world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*/
33
34	/*******************************************************************************
35	* Header Files *
36	*******************************************************************************/
37	#define LOG_GROUP LOG_GROUP_CPUM
38	#include <VBox/cpum.h>
39	#include <VBox/cpumdis.h>
40	#include <VBox/pgm.h>
41	#include <VBox/mm.h>
42	#include <VBox/selm.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/patm.h>
45	#include <VBox/hwaccm.h>
46	#include <VBox/ssm.h>
47	#include "CPUMInternal.h"
48	#include <VBox/vm.h>
49
50	#include <VBox/param.h>
51	#include <VBox/dis.h>
52	#include <VBox/err.h>
53	#include <VBox/log.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm-amd64-x86.h>
56	#include <iprt/string.h>
57	#include <iprt/mp.h>
58	#include <iprt/cpuset.h>
59	#include <include/internal/pgm.h>
60
61	/*******************************************************************************
62	* Defined Constants And Macros *
63	*******************************************************************************/
64	/** The current saved state version. */
65	#define CPUM_SAVED_STATE_VERSION 12
66	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
67	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
68	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
69	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
70	* changes. */
71	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
72	/** The saved state version for the 2.1 trunk before the MSR changes. */
73	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
74	/** The saved state version of 2.0, used for backwards compatibility. */
75	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
76	/** The saved state version of 1.6, used for backwards compatability. */
77	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
78
79
80	/*******************************************************************************
81	* Structures and Typedefs *
82	*******************************************************************************/
83
84	/**
85	* What kind of cpu info dump to perform.
86	*/
87	typedef enum CPUMDUMPTYPE
88	{
89	CPUMDUMPTYPE_TERSE,
90	CPUMDUMPTYPE_DEFAULT,
91	CPUMDUMPTYPE_VERBOSE
92	} CPUMDUMPTYPE;
93	/** Pointer to a cpu info dump type. */
94	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97	/*******************************************************************************
98	* Internal Functions *
99	*******************************************************************************/
100	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
101	static int cpumR3CpuIdInit(PVM pVM);
102	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
103	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
104	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
106	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
107	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113
114
115	/**
116	* Initializes the CPUM.
117	*
118	* @returns VBox status code.
119	* @param pVM The VM to operate on.
120	*/
121	VMMR3DECL(int) CPUMR3Init(PVM pVM)
122	{
123	LogFlow(("CPUMR3Init\n"));
124
125	/*
126	* Assert alignment and sizes.
127	*/
128	AssertCompileMemberAlignment(VM, cpum.s, 32);
129	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
130	AssertCompileSizeAlignment(CPUMCTX, 64);
131	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
132	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
133	AssertCompileMemberAlignment(VM, cpum, 64);
134	AssertCompileMemberAlignment(VM, aCpus, 64);
135	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
136	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
137
138	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
139	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
140	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
141
142	/* Calculate the offset from CPUMCPU to CPUM. */
143	for (VMCPUID i = 0; i < pVM->cCpus; i++)
144	{
145	PVMCPU pVCpu = &pVM->aCpus[i];
146
147	/*
148	* Setup any fixed pointers and offsets.
149	*/
150	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
151	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
152
153	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
154	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
155	}
156
157	/*
158	* Check that the CPU supports the minimum features we require.
159	*/
160	if (!ASMHasCpuId())
161	{
162	Log(("The CPU doesn't support CPUID!\n"));
163	return VERR_UNSUPPORTED_CPU;
164	}
165	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
166	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
167
168	/* Setup the CR4 AND and OR masks used in the switcher */
169	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
170	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
171	{
172	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
173	/* No FXSAVE implies no SSE */
174	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
175	pVM->cpum.s.CR4.OrMask = 0;
176	}
177	else
178	{
179	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
180	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
181	}
182
183	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
184	{
185	Log(("The CPU doesn't support MMX!\n"));
186	return VERR_UNSUPPORTED_CPU;
187	}
188	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
189	{
190	Log(("The CPU doesn't support TSC!\n"));
191	return VERR_UNSUPPORTED_CPU;
192	}
193	/* Bogus on AMD? */
194	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
195	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
196
197	/*
198	* Detech the host CPU vendor.
199	* (The guest CPU vendor is re-detected later on.)
200	*/
201	uint32_t uEAX, uEBX, uECX, uEDX;
202	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
203	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
204	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
205
206	/*
207	* Setup hypervisor startup values.
208	*/
209
210	/*
211	* Register saved state data item.
212	*/
213	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
214	NULL, cpumR3LiveExec, NULL,
215	NULL, cpumR3SaveExec, NULL,
216	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
217	if (RT_FAILURE(rc))
218	return rc;
219
220	/*
221	* Register info handlers.
222	*/
223	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
224	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
225	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
227	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
228	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
229
230	/*
231	* Initialize the Guest CPUID state.
232	*/
233	rc = cpumR3CpuIdInit(pVM);
234	if (RT_FAILURE(rc))
235	return rc;
236	CPUMR3Reset(pVM);
237	return VINF_SUCCESS;
238	}
239
240
241	/**
242	* Initializes the per-VCPU CPUM.
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
248	{
249	LogFlow(("CPUMR3InitCPU\n"));
250	return VINF_SUCCESS;
251	}
252
253
254	/**
255	* Detect the CPU vendor give n the
256	*
257	* @returns The vendor.
258	* @param uEAX EAX from CPUID(0).
259	* @param uEBX EBX from CPUID(0).
260	* @param uECX ECX from CPUID(0).
261	* @param uEDX EDX from CPUID(0).
262	*/
263	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
264	{
265	if ( uEAX >= 1
266	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
267	&& uECX == X86_CPUID_VENDOR_AMD_ECX
268	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
269	return CPUMCPUVENDOR_AMD;
270
271	if ( uEAX >= 1
272	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
273	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
274	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
275	return CPUMCPUVENDOR_INTEL;
276
277	/** @todo detect the other buggers... */
278	return CPUMCPUVENDOR_UNKNOWN;
279	}
280
281
282	/**
283	* Fetches overrides for a CPUID leaf.
284	*
285	* @returns VBox status code.
286	* @param pLeaf The leaf to load the overrides into.
287	* @param pCfgNode The CFGM node containing the overrides
288	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
289	* @param iLeaf The CPUID leaf number.
290	*/
291	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
292	{
293	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
294	if (pLeafNode)
295	{
296	uint32_t u32;
297	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
298	if (RT_SUCCESS(rc))
299	pLeaf->eax = u32;
300	else
301	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
302
303	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
304	if (RT_SUCCESS(rc))
305	pLeaf->ebx = u32;
306	else
307	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
308
309	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
310	if (RT_SUCCESS(rc))
311	pLeaf->ecx = u32;
312	else
313	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
314
315	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
316	if (RT_SUCCESS(rc))
317	pLeaf->edx = u32;
318	else
319	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
320
321	}
322	return VINF_SUCCESS;
323	}
324
325
326	/**
327	* Load the overrides for a set of CPUID leaves.
328	*
329	* @returns VBox status code.
330	* @param paLeaves The leaf array.
331	* @param cLeaves The number of leaves.
332	* @param uStart The start leaf number.
333	* @param pCfgNode The CFGM node containing the overrides
334	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
335	*/
336	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
337	{
338	for (uint32_t i = 0; i < cLeaves; i++)
339	{
340	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
341	if (RT_FAILURE(rc))
342	return rc;
343	}
344
345	return VINF_SUCCESS;
346	}
347
348	/**
349	* Init a set of host CPUID leaves.
350	*
351	* @returns VBox status code.
352	* @param paLeaves The leaf array.
353	* @param cLeaves The number of leaves.
354	* @param uStart The start leaf number.
355	* @param pCfgNode The /CPUM/HostCPUID/ node.
356	*/
357	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
358	{
359	/* Using the ECX variant for all of them can't hurt... */
360	for (uint32_t i = 0; i < cLeaves; i++)
361	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
362
363	/* Load CPUID leaf override; we currently don't care if the user
364	specifies features the host CPU doesn't support. */
365	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
366	}
367
368
369	/**
370	* Initializes the emulated CPU's cpuid information.
371	*
372	* @returns VBox status code.
373	* @param pVM The VM to operate on.
374	*/
375	static int cpumR3CpuIdInit(PVM pVM)
376	{
377	PCPUM pCPUM = &pVM->cpum.s;
378	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
379	uint32_t i;
380	int rc;
381
382	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
383	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
384	{ \
385	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
386	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
387	}
388	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
389	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
390	{ \
391	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
392	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
393	}
394
395	/*
396	* Read the configuration.
397	*/
398	/** @cfgm{CPUM/SyntheticCpu, boolean, false}
399	* Enables the Synthetic CPU. The Vendor ID and Processor Name are
400	* completely overridden by VirtualBox custom strings. Some
401	* CPUID information is withheld, like the cache info. */
402	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
403	AssertRCReturn(rc, rc);
404
405	/** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
406	* When non-zero CPUID features that could cause portability issues will be
407	* stripped. The higher the value the more features gets stripped. Higher
408	* values should only be used when older CPUs are involved since it may
409	* harm performance and maybe also cause problems with specific guests. */
410	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
411	AssertRCReturn(rc, rc);
412
413	AssertLogRelReturn(!pCPUM->fSyntheticCpu \|\| !pCPUM->u8PortableCpuIdLevel, VERR_INTERNAL_ERROR_2);
414
415	/*
416	* Get the host CPUID leaves and redetect the guest CPU vendor (could've
417	* been overridden).
418	*/
419	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
420	* Overrides the host CPUID leaf values used for calculating the guest CPUID
421	* leaves. This can be used to preserve the CPUID values when moving a VM
422	* to a different machine. Another use is restricting (or extending) the
423	* feature set exposed to the guest. */
424	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
425	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
426	AssertRCReturn(rc, rc);
427	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
428	AssertRCReturn(rc, rc);
429	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
430	AssertRCReturn(rc, rc);
431
432	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
433	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
434
435	/*
436	* Determine the default leaf.
437	*
438	* Intel returns values of the highest standard function, while AMD
439	* returns zeros. VIA on the other hand seems to returning nothing or
440	* perhaps some random garbage, we don't try to duplicate this behavior.
441	*/
442	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
443	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
444	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
445
446
447	/* Cpuid 1 & 0x80000001:
448	* Only report features we can support.
449	*
450	* Note! When enabling new features the Synthetic CPU and Portable CPUID
451	* options may require adjusting (i.e. stripping what was enabled).
452	*/
453	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
454	\| X86_CPUID_FEATURE_EDX_VME
455	\| X86_CPUID_FEATURE_EDX_DE
456	\| X86_CPUID_FEATURE_EDX_PSE
457	\| X86_CPUID_FEATURE_EDX_TSC
458	\| X86_CPUID_FEATURE_EDX_MSR
459	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
460	\| X86_CPUID_FEATURE_EDX_MCE
461	\| X86_CPUID_FEATURE_EDX_CX8
462	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
463	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
464	//\| X86_CPUID_FEATURE_EDX_SEP
465	\| X86_CPUID_FEATURE_EDX_MTRR
466	\| X86_CPUID_FEATURE_EDX_PGE
467	\| X86_CPUID_FEATURE_EDX_MCA
468	\| X86_CPUID_FEATURE_EDX_CMOV
469	\| X86_CPUID_FEATURE_EDX_PAT
470	\| X86_CPUID_FEATURE_EDX_PSE36
471	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
472	\| X86_CPUID_FEATURE_EDX_CLFSH
473	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
474	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
475	\| X86_CPUID_FEATURE_EDX_MMX
476	\| X86_CPUID_FEATURE_EDX_FXSR
477	\| X86_CPUID_FEATURE_EDX_SSE
478	\| X86_CPUID_FEATURE_EDX_SSE2
479	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
480	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
481	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
482	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
483	\| 0;
484	pCPUM->aGuestCpuIdStd[1].ecx &= 0
485	\| X86_CPUID_FEATURE_ECX_SSE3
486	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
487	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
488	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
489	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
490	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
491	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
492	\| X86_CPUID_FEATURE_ECX_SSSE3
493	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
494	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
495	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
496	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
497	/* ECX Bit 21 - x2APIC support - not yet. */
498	// \| X86_CPUID_FEATURE_ECX_X2APIC
499	/* ECX Bit 23 - POPCNT instruction. */
500	//\| X86_CPUID_FEATURE_ECX_POPCNT
501	\| 0;
502	if (pCPUM->u8PortableCpuIdLevel > 0)
503	{
504	PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
505	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
506	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
507	PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
508	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
509	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
510	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
511
512	Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
513	\| X86_CPUID_FEATURE_EDX_PSN
514	\| X86_CPUID_FEATURE_EDX_DS
515	\| X86_CPUID_FEATURE_EDX_ACPI
516	\| X86_CPUID_FEATURE_EDX_SS
517	\| X86_CPUID_FEATURE_EDX_TM
518	\| X86_CPUID_FEATURE_EDX_PBE
519	)));
520	Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
521	\| X86_CPUID_FEATURE_ECX_DTES64
522	\| X86_CPUID_FEATURE_ECX_CPLDS
523	\| X86_CPUID_FEATURE_ECX_VMX
524	\| X86_CPUID_FEATURE_ECX_SMX
525	\| X86_CPUID_FEATURE_ECX_EST
526	\| X86_CPUID_FEATURE_ECX_TM2
527	\| X86_CPUID_FEATURE_ECX_CNTXID
528	\| X86_CPUID_FEATURE_ECX_FMA
529	\| X86_CPUID_FEATURE_ECX_CX16
530	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
531	\| X86_CPUID_FEATURE_ECX_PDCM
532	\| X86_CPUID_FEATURE_ECX_DCA
533	\| X86_CPUID_FEATURE_ECX_MOVBE
534	\| X86_CPUID_FEATURE_ECX_AES
535	\| X86_CPUID_FEATURE_ECX_POPCNT
536	\| X86_CPUID_FEATURE_ECX_XSAVE
537	\| X86_CPUID_FEATURE_ECX_OSXSAVE
538	\| X86_CPUID_FEATURE_ECX_AVX
539	)));
540	}
541
542	/* Cpuid 0x80000001:
543	* Only report features we can support.
544	*
545	* Note! When enabling new features the Synthetic CPU and Portable CPUID
546	* options may require adjusting (i.e. stripping what was enabled).
547	*
548	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
549	*/
550	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
551	\| X86_CPUID_AMD_FEATURE_EDX_VME
552	\| X86_CPUID_AMD_FEATURE_EDX_DE
553	\| X86_CPUID_AMD_FEATURE_EDX_PSE
554	\| X86_CPUID_AMD_FEATURE_EDX_TSC
555	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
556	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
557	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
558	\| X86_CPUID_AMD_FEATURE_EDX_CX8
559	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
560	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
561	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
562	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
563	\| X86_CPUID_AMD_FEATURE_EDX_PGE
564	\| X86_CPUID_AMD_FEATURE_EDX_MCA
565	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
566	\| X86_CPUID_AMD_FEATURE_EDX_PAT
567	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
568	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
569	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
570	\| X86_CPUID_AMD_FEATURE_EDX_MMX
571	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
572	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
573	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
574	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
575	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
576	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
577	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
578	\| 0;
579	pCPUM->aGuestCpuIdExt[1].ecx &= 0
580	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
581	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
582	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
583	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
584	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
585	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
586	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
587	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
588	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
589	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
590	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
591	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
592	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
593	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
594	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
595	\| 0;
596	if (pCPUM->u8PortableCpuIdLevel > 0)
597	{
598	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
599	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
600	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
601	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
602	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
603	PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
604	PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
605
606	Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
607	\| X86_CPUID_AMD_FEATURE_ECX_SVM
608	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
609	\| X86_CPUID_AMD_FEATURE_ECX_CR8L
610	\| X86_CPUID_AMD_FEATURE_ECX_ABM
611	\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
612	\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
613	\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
614	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
615	\| X86_CPUID_AMD_FEATURE_ECX_IBS
616	\| X86_CPUID_AMD_FEATURE_ECX_SSE5
617	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
618	\| X86_CPUID_AMD_FEATURE_ECX_WDT
619	\| UINT32_C(0xffffc000)
620	)));
621	Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
622	\| X86_CPUID_AMD_FEATURE_EDX_SEP
623	\| RT_BIT(18)
624	\| RT_BIT(19)
625	\| RT_BIT(21)
626	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
627	\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
628	\| RT_BIT(28)
629	)));
630	}
631
632	/*
633	* Apply the Synthetic CPU modifications. (TODO: move this up)
634	*/
635	if (pCPUM->fSyntheticCpu)
636	{
637	static const char s_szVendor[13] = "VirtualBox ";
638	static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
639
640	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
641
642	/* Limit the nr of standard leaves; 5 for monitor/mwait */
643	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
644
645	/* 0: Vendor */
646	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
647	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
648	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
649
650	/* 1.eax: Version information. family : model : stepping */
651	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
652
653	/* Leaves 2 - 4 are Intel only - zero them out */
654	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
655	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
656	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
657
658	/* Leaf 5 = monitor/mwait */
659
660	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
661	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
662	/* AMD only - set to zero. */
663	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
664
665	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
666	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
667
668	/* 0x800000002-4: Processor Name String Identifier. */
669	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
670	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
671	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
672	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
673	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
674	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
675	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
676	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
677	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
678	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
679	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
680	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
681
682	/* 0x800000005-7 - reserved -> zero */
683	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
684	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
685	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
686
687	/* 0x800000008: only the max virtual and physical address size. */
688	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
689	}
690
691	/*
692	* Hide HTT, multicode, SMP, whatever.
693	* (APIC-ID := 0 and #LogCpus := 0)
694	*/
695	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
696	#ifdef VBOX_WITH_MULTI_CORE
697	if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
698	&& pVM->cCpus > 1)
699	{
700	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
701	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
702	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
703	}
704	#endif
705
706	/* Cpuid 2:
707	* Intel: Cache and TLB information
708	* AMD: Reserved
709	* Safe to expose; restrict the number of calls to 1 for the portable case.
710	*/
711	if ( pCPUM->u8PortableCpuIdLevel > 0
712	&& pCPUM->aGuestCpuIdStd[0].eax >= 2
713	&& (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
714	{
715	LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
716	pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
717	}
718
719	/* Cpuid 3:
720	* Intel: EAX, EBX - reserved (transmeta uses these)
721	* ECX, EDX - Processor Serial Number if available, otherwise reserved
722	* AMD: Reserved
723	* Safe to expose
724	*/
725	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
726	{
727	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
728	if (pCPUM->u8PortableCpuIdLevel > 0)
729	pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
730	}
731
732	/* Cpuid 4:
733	* Intel: Deterministic Cache Parameters Leaf
734	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
735	* AMD: Reserved
736	* Safe to expose, except for EAX:
737	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
738	* Bits 31-26: Maximum number of processor cores in this physical package**
739	* Note: These SMP values are constant regardless of ECX
740	*/
741	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
742	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
743	#ifdef VBOX_WITH_MULTI_CORE
744	if ( pVM->cCpus > 1
745	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
746	{
747	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
748	/* One logical processor with possibly multiple cores. */
749	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
750	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
751	}
752	#endif
753
754	/* Cpuid 5: Monitor/mwait Leaf
755	* Intel: ECX, EDX - reserved
756	* EAX, EBX - Smallest and largest monitor line size
757	* AMD: EDX - reserved
758	* EAX, EBX - Smallest and largest monitor line size
759	* ECX - extensions (ignored for now)
760	* Safe to expose
761	*/
762	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
763	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
764
765	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
766	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
767	* Expose MWAIT extended features to the guest. For now we expose
768	* just MWAIT break on interrupt feature (bit 1).
769	*/
770	bool fMWaitExtensions;
771	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
772	if (fMWaitExtensions)
773	{
774	pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
775	/* @todo: for now we just expose host's MWAIT C-states, although conceptually
776	it shall be part of our power management virtualization model */
777	#if 0
778	/* MWAIT sub C-states */
779	pCPUM->aGuestCpuIdStd[5].edx =
780	(0 << 0) /* 0 in C0 */ \|
781	(2 << 4) /* 2 in C1 */ \|
782	(2 << 8) /* 2 in C2 */ \|
783	(2 << 12) /* 2 in C3 */ \|
784	(0 << 16) /* 0 in C4 */
785	;
786	#endif
787	}
788	else
789	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
790
791	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
792	* Safe to pass on to the guest.
793	*
794	* Intel: 0x800000005 reserved
795	* 0x800000006 L2 cache information
796	* AMD: 0x800000005 L1 cache information
797	* 0x800000006 L2/L3 cache information
798	*/
799
800	/* Cpuid 0x800000007:
801	* AMD: EAX, EBX, ECX - reserved
802	* EDX: Advanced Power Management Information
803	* Intel: Reserved
804	*/
805	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
806	{
807	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
808
809	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
810
811	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
812	{
813	/* Only expose the TSC invariant capability bit to the guest. */
814	pCPUM->aGuestCpuIdExt[7].edx &= 0
815	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
816	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
817	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
818	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
819	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
820	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
821	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
822	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
823	#if 0 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
824	* Linux kernels blindly assume that the AMD performance counters work
825	* if this is set for 64 bits guests. (Can't really find a CPUID feature
826	* bit for them though.) */
827	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
828	#endif
829	\| 0;
830	}
831	else
832	pCPUM->aGuestCpuIdExt[7].edx = 0;
833	}
834
835	/* Cpuid 0x800000008:
836	* AMD: EBX, EDX - reserved
837	* EAX: Virtual/Physical/Guest address Size
838	* ECX: Number of cores + APICIdCoreIdSize
839	* Intel: EAX: Virtual/Physical address Size
840	* EBX, ECX, EDX - reserved
841	*/
842	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
843	{
844	/* Only expose the virtual and physical address sizes to the guest. */
845	pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
846	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
847	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
848	* NC (0-7) Number of cores; 0 equals 1 core */
849	pCPUM->aGuestCpuIdExt[8].ecx = 0;
850	#ifdef VBOX_WITH_MULTI_CORE
851	if ( pVM->cCpus > 1
852	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
853	{
854	/* Legacy method to determine the number of cores. */
855	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
856	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
857
858	}
859	#endif
860	}
861
862	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
863	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
864	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
865	* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
866	*/
867	bool fNt4LeafLimit;
868	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
869	if (fNt4LeafLimit)
870	pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
871
872	/*
873	* Limit it the number of entries and fill the remaining with the defaults.
874	*
875	* The limits are masking off stuff about power saving and similar, this
876	* is perhaps a bit crudely done as there is probably some relatively harmless
877	* info too in these leaves (like words about having a constant TSC).
878	*/
879	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
880	pCPUM->aGuestCpuIdStd[0].eax = 5;
881	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
882	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
883
884	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
885	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
886	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
887	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
888	: 0;
889	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
890	i++)
891	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
892
893	/*
894	* Centaur stuff (VIA).
895	*
896	* The important part here (we think) is to make sure the 0xc0000000
897	* function returns 0xc0000001. As for the features, we don't currently
898	* let on about any of those... 0xc0000002 seems to be some
899	* temperature/hz/++ stuff, include it as well (static).
900	*/
901	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
902	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
903	{
904	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
905	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
906	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
907	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
908	i++)
909	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
910	}
911	else
912	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
913	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
914
915
916	/*
917	* Load CPUID overrides from configuration.
918	* Note: Kind of redundant now, but allows unchanged overrides
919	*/
920	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
921	* Overrides the CPUID leaf values. */
922	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
923	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
924	AssertRCReturn(rc, rc);
925	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
926	AssertRCReturn(rc, rc);
927	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
928	AssertRCReturn(rc, rc);
929
930	/*
931	* Check if PAE was explicitely enabled by the user.
932	*/
933	bool fEnable;
934	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
935	if (fEnable)
936	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
937
938	/*
939	* Log the cpuid and we're good.
940	*/
941	RTCPUSET OnlineSet;
942	LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
943	(int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
944	LogRel(("*********************** CPUID dump **********************\n"));
945	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
946	LogRel(("\n"));
947	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
948	LogRel(("****************** End of CPUID dump ********************\n"));
949
950	#undef PORTABLE_DISABLE_FEATURE_BIT
951	#undef PORTABLE_CLEAR_BITS_WHEN
952
953	return VINF_SUCCESS;
954	}
955
956
957	/**
958	* Applies relocations to data and code managed by this
959	* component. This function will be called at init and
960	* whenever the VMM need to relocate it self inside the GC.
961	*
962	* The CPUM will update the addresses used by the switcher.
963	*
964	* @param pVM The VM.
965	*/
966	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
967	{
968	LogFlow(("CPUMR3Relocate\n"));
969	for (VMCPUID i = 0; i < pVM->cCpus; i++)
970	{
971	/*
972	* Switcher pointers.
973	*/
974	PVMCPU pVCpu = &pVM->aCpus[i];
975	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
976	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
977
978	}
979	}
980
981
982	/**
983	* Apply late CPUM property changes based on the fHWVirtEx setting
984	*
985	* @param pVM The VM to operate on.
986	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
987	*/
988	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
989	{
990	/*
991	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
992	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
993	* of processors from (cpuid(4).eax >> 26) + 1.
994	*
995	* Note: this code is obsolete, but let's keep it here for reference.
996	* Purpose is valid when we artifically cap the max std id to less than 4.
997	*/
998	if (!fHWVirtExEnabled)
999	{
1000	Assert(pVM->cpum.s.aGuestCpuIdStd[4].eax == 0);
1001	pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1002	}
1003	}
1004
1005	/**
1006	* Terminates the CPUM.
1007	*
1008	* Termination means cleaning up and freeing all resources,
1009	* the VM it self is at this point powered off or suspended.
1010	*
1011	* @returns VBox status code.
1012	* @param pVM The VM to operate on.
1013	*/
1014	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1015	{
1016	CPUMR3TermCPU(pVM);
1017	return 0;
1018	}
1019
1020
1021	/**
1022	* Terminates the per-VCPU CPUM.
1023	*
1024	* Termination means cleaning up and freeing all resources,
1025	* the VM it self is at this point powered off or suspended.
1026	*
1027	* @returns VBox status code.
1028	* @param pVM The VM to operate on.
1029	*/
1030	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
1031	{
1032	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1033	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1034	{
1035	PVMCPU pVCpu = &pVM->aCpus[i];
1036	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1037
1038	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1039	pVCpu->cpum.s.uMagic = 0;
1040	pCtx->dr[5] = 0;
1041	}
1042	#endif
1043	return 0;
1044	}
1045
1046
1047	/**
1048	* Resets a virtual CPU.
1049	*
1050	* Used by CPUMR3Reset and CPU hot plugging.
1051	*
1052	* @param pVCpu The virtual CPU handle.
1053	*/
1054	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1055	{
1056	/** @todo anything different for VCPU > 0? */
1057	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1058
1059	/*
1060	* Initialize everything to ZERO first.
1061	*/
1062	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1063	memset(pCtx, 0, sizeof(*pCtx));
1064	pVCpu->cpum.s.fUseFlags = fUseFlags;
1065
1066	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1067	pCtx->eip = 0x0000fff0;
1068	pCtx->edx = 0x00000600; /* P6 processor */
1069	pCtx->eflags.Bits.u1Reserved0 = 1;
1070
1071	pCtx->cs = 0xf000;
1072	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
1073	pCtx->csHid.u32Limit = 0x0000ffff;
1074	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
1075	pCtx->csHid.Attr.n.u1Present = 1;
1076	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
1077
1078	pCtx->dsHid.u32Limit = 0x0000ffff;
1079	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
1080	pCtx->dsHid.Attr.n.u1Present = 1;
1081	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1082
1083	pCtx->esHid.u32Limit = 0x0000ffff;
1084	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
1085	pCtx->esHid.Attr.n.u1Present = 1;
1086	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1087
1088	pCtx->fsHid.u32Limit = 0x0000ffff;
1089	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
1090	pCtx->fsHid.Attr.n.u1Present = 1;
1091	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1092
1093	pCtx->gsHid.u32Limit = 0x0000ffff;
1094	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
1095	pCtx->gsHid.Attr.n.u1Present = 1;
1096	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1097
1098	pCtx->ssHid.u32Limit = 0x0000ffff;
1099	pCtx->ssHid.Attr.n.u1Present = 1;
1100	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
1101	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1102
1103	pCtx->idtr.cbIdt = 0xffff;
1104	pCtx->gdtr.cbGdt = 0xffff;
1105
1106	pCtx->ldtrHid.u32Limit = 0xffff;
1107	pCtx->ldtrHid.Attr.n.u1Present = 1;
1108	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1109
1110	pCtx->trHid.u32Limit = 0xffff;
1111	pCtx->trHid.Attr.n.u1Present = 1;
1112	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
1113
1114	pCtx->dr[6] = X86_DR6_INIT_VAL;
1115	pCtx->dr[7] = X86_DR7_INIT_VAL;
1116
1117	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
1118	pCtx->fpu.FCW = 0x37f;
1119
1120	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
1121	pCtx->fpu.MXCSR = 0x1F80;
1122
1123	/* Init PAT MSR */
1124	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1125
1126	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1127	* The Intel docs don't mention it.
1128	*/
1129	pCtx->msrEFER = 0;
1130	}
1131
1132
1133	/**
1134	* Resets the CPU.
1135	*
1136	* @returns VINF_SUCCESS.
1137	* @param pVM The VM handle.
1138	*/
1139	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1140	{
1141	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1142	{
1143	CPUMR3ResetCpu(&pVM->aCpus[i]);
1144
1145	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1146	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1147
1148	/* Magic marker for searching in crash dumps. */
1149	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1150	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1151	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1152	#endif
1153	}
1154	}
1155
1156
1157	/**
1158	* Called both in pass 0 and the final pass.
1159	*
1160	* @param pVM The VM handle.
1161	* @param pSSM The saved state handle.
1162	*/
1163	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1164	{
1165	/*
1166	* Save all the CPU ID leaves here so we can check them for compatability
1167	* upon loading.
1168	*/
1169	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1170	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1171
1172	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1173	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1174
1175	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1176	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1177
1178	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1179
1180	/*
1181	* Save a good portion of the raw CPU IDs as well as they may come in
1182	* handy when validating features for raw mode.
1183	*/
1184	CPUMCPUID aRawStd[16];
1185	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1186	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1187	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1188	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1189
1190	CPUMCPUID aRawExt[32];
1191	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1192	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1193	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1194	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1195	}
1196
1197
1198	/**
1199	* Loads the CPU ID leaves saved by pass 0.
1200	*
1201	* @returns VBox status code.
1202	* @param pVM The VM handle.
1203	* @param pSSM The saved state handle.
1204	* @param uVersion The format version.
1205	*/
1206	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1207	{
1208	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1209
1210	/*
1211	* Define a bunch of macros for simplifying the code.
1212	*/
1213	/* Generic expression + failure message. */
1214	#define CPUID_CHECK_RET(expr, fmt) \
1215	do { \
1216	if (!(expr)) \
1217	{ \
1218	char pszMsg = RTStrAPrintf2 fmt; / lack of variadict macros sucks */ \
1219	if (fStrictCpuIdChecks) \
1220	{ \
1221	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1222	RTStrFree(pszMsg); \
1223	return rcCpuid; \
1224	} \
1225	LogRel(("CPUM: %s\n", pszMsg)); \
1226	RTStrFree(pszMsg); \
1227	} \
1228	} while (0)
1229	#define CPUID_CHECK_WRN(expr, fmt) \
1230	do { \
1231	if (!(expr)) \
1232	LogRel(fmt); \
1233	} while (0)
1234
1235	/* For comparing two values and bitch if they differs. */
1236	#define CPUID_CHECK2_RET(what, host, saved) \
1237	do { \
1238	if ((host) != (saved)) \
1239	{ \
1240	if (fStrictCpuIdChecks) \
1241	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1242	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1243	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1244	} \
1245	} while (0)
1246	#define CPUID_CHECK2_WRN(what, host, saved) \
1247	do { \
1248	if ((host) != (saved)) \
1249	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1250	} while (0)
1251
1252	/* For checking raw cpu features (raw mode). */
1253	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1254	do { \
1255	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1256	{ \
1257	if (fStrictCpuIdChecks) \
1258	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1259	N_(#bit " mismatch: host=%d saved=%d"), \
1260	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1261	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1262	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1263	} \
1264	} while (0)
1265	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1266	do { \
1267	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1268	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1269	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1270	} while (0)
1271	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1272
1273	/* For checking guest features. */
1274	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1275	do { \
1276	if ( (aGuestCpuId##set [1].reg & bit) \
1277	&& !(aHostRaw##set [1].reg & bit) \
1278	&& !(aHostOverride##set [1].reg & bit) \
1279	&& !(aGuestOverride##set [1].reg & bit) \
1280	) \
1281	{ \
1282	if (fStrictCpuIdChecks) \
1283	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1284	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1285	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1286	} \
1287	} while (0)
1288	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1289	do { \
1290	if ( (aGuestCpuId##set [1].reg & bit) \
1291	&& !(aHostRaw##set [1].reg & bit) \
1292	&& !(aHostOverride##set [1].reg & bit) \
1293	&& !(aGuestOverride##set [1].reg & bit) \
1294	) \
1295	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1296	} while (0)
1297	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1298	do { \
1299	if ( (aGuestCpuId##set [1].reg & bit) \
1300	&& !(aHostRaw##set [1].reg & bit) \
1301	&& !(aHostOverride##set [1].reg & bit) \
1302	&& !(aGuestOverride##set [1].reg & bit) \
1303	) \
1304	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1305	} while (0)
1306	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1307
1308	/* For checking guest features if AMD guest CPU. */
1309	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1310	do { \
1311	if ( (aGuestCpuId##set [1].reg & bit) \
1312	&& fGuestAmd \
1313	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1314	&& !(aHostOverride##set [1].reg & bit) \
1315	&& !(aGuestOverride##set [1].reg & bit) \
1316	) \
1317	{ \
1318	if (fStrictCpuIdChecks) \
1319	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1320	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1321	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1322	} \
1323	} while (0)
1324	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1325	do { \
1326	if ( (aGuestCpuId##set [1].reg & bit) \
1327	&& fGuestAmd \
1328	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1329	&& !(aHostOverride##set [1].reg & bit) \
1330	&& !(aGuestOverride##set [1].reg & bit) \
1331	) \
1332	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1333	} while (0)
1334	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1335	do { \
1336	if ( (aGuestCpuId##set [1].reg & bit) \
1337	&& fGuestAmd \
1338	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1339	&& !(aHostOverride##set [1].reg & bit) \
1340	&& !(aGuestOverride##set [1].reg & bit) \
1341	) \
1342	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1343	} while (0)
1344	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1345
1346	/* For checking AMD features which have a corresponding bit in the standard
1347	range. (Intel defines very few bits in the extended feature sets.) */
1348	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1349	do { \
1350	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1351	&& !(fHostAmd \
1352	? aHostRawExt[1].reg & (ExtBit) \
1353	: aHostRawStd[1].reg & (StdBit)) \
1354	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1355	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1356	) \
1357	{ \
1358	if (fStrictCpuIdChecks) \
1359	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1360	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1361	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1362	} \
1363	} while (0)
1364	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1365	do { \
1366	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1367	&& !(fHostAmd \
1368	? aHostRawExt[1].reg & (ExtBit) \
1369	: aHostRawStd[1].reg & (StdBit)) \
1370	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1371	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1372	) \
1373	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1374	} while (0)
1375	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1376	do { \
1377	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1378	&& !(fHostAmd \
1379	? aHostRawExt[1].reg & (ExtBit) \
1380	: aHostRawStd[1].reg & (StdBit)) \
1381	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1382	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1383	) \
1384	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1385	} while (0)
1386	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1387
1388	/*
1389	* Load them into stack buffers first.
1390	*/
1391	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1392	uint32_t cGuestCpuIdStd;
1393	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1394	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1395	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1396	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1397
1398	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1399	uint32_t cGuestCpuIdExt;
1400	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1401	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1402	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1403	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1404
1405	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1406	uint32_t cGuestCpuIdCentaur;
1407	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1408	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1409	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1410	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1411
1412	CPUMCPUID GuestCpuIdDef;
1413	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1414	AssertRCReturn(rc, rc);
1415
1416	CPUMCPUID aRawStd[16];
1417	uint32_t cRawStd;
1418	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1419	if (cRawStd > RT_ELEMENTS(aRawStd))
1420	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1421	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1422
1423	CPUMCPUID aRawExt[32];
1424	uint32_t cRawExt;
1425	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1426	if (cRawExt > RT_ELEMENTS(aRawExt))
1427	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1428	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1429	AssertRCReturn(rc, rc);
1430
1431	/*
1432	* Note that we support restoring less than the current amount of standard
1433	* leaves because we've been allowed more is newer version of VBox.
1434	*
1435	* So, pad new entries with the default.
1436	*/
1437	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1438	aGuestCpuIdStd[i] = GuestCpuIdDef;
1439
1440	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1441	aGuestCpuIdExt[i] = GuestCpuIdDef;
1442
1443	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1444	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1445
1446	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1447	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1448
1449	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1450	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1451
1452	/*
1453	* Get the raw CPU IDs for the current host.
1454	*/
1455	CPUMCPUID aHostRawStd[16];
1456	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1457	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1458
1459	CPUMCPUID aHostRawExt[32];
1460	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1461	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1462
1463	/*
1464	* Get the host and guest overrides so we don't reject the state because
1465	* some feature was enabled thru these interfaces.
1466	* Note! We currently only need the feature leaves, so skip rest.
1467	*/
1468	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1469	CPUMCPUID aGuestOverrideStd[2];
1470	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1471	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1472
1473	CPUMCPUID aGuestOverrideExt[2];
1474	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1475	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1476
1477	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1478	CPUMCPUID aHostOverrideStd[2];
1479	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1480	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1481
1482	CPUMCPUID aHostOverrideExt[2];
1483	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1484	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1485
1486	/*
1487	* This can be skipped.
1488	*/
1489	bool fStrictCpuIdChecks;
1490	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1491
1492
1493
1494	/*
1495	* For raw-mode we'll require that the CPUs are very similar since we don't
1496	* intercept CPUID instructions for user mode applications.
1497	*/
1498	if (!HWACCMIsEnabled(pVM))
1499	{
1500	/* CPUID(0) */
1501	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1502	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1503	&& aHostRawStd[0].edx == aRawStd[0].edx,
1504	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1505	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1506	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1507	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1508	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1509	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1510
1511	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1512
1513	/* CPUID(1).eax */
1514	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1515	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1516	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1517
1518	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1519	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1520	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1521
1522	/* CPUID(1).ecx */
1523	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1524	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1525	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1526	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1527	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1528	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1529	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1530	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1531	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1532	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1533	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1534	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1535	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1536	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1537	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1538	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1539	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1540	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1541	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1542	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1543	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1544	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1545	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1546	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1547	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1548	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1549	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1550	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1551	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1552	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1553	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1554	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1555
1556	/* CPUID(1).edx */
1557	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1558	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1559	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1560	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1561	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1562	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1563	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1564	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1565	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1566	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1567	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1568	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1569	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1570	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1571	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1572	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1573	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1574	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1575	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1576	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1577	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1578	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1579	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1580	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1581	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1582	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1583	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1584	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1585	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1586	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1587	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1588	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1589
1590	/* CPUID(2) - config, mostly about caches. ignore. */
1591	/* CPUID(3) - processor serial number. ignore. */
1592	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1593	/* CPUID(5) - mwait/monitor config. ignore. */
1594	/* CPUID(6) - power management. ignore. */
1595	/* CPUID(7) - ???. ignore. */
1596	/* CPUID(8) - ???. ignore. */
1597	/* CPUID(9) - DCA. ignore for now. */
1598	/* CPUID(a) - PeMo info. ignore for now. */
1599	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1600
1601	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1602	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1603	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1604	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1605	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1606	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1607	{
1608	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1609	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1610	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1611	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1612	}
1613
1614	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1615	Note! Intel have/is marking many of the fields here as reserved. We
1616	will verify them as if it's an AMD CPU. */
1617	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1618	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1619	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
1620	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1621	{
1622	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1623	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1624	&& aHostRawExt[0].edx == aRawExt[0].edx,
1625	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1626	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1627	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1628	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1629
1630	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1631	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1632	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1633	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1634	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1635	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1636
1637	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1638	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1639	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1640	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1641
1642	/* CPUID(0x80000001).ecx */
1643	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1644	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1645	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1646	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1647	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1648	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1649	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1650	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1651	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1652	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1653	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1654	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1655	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1656	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1657	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1658	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1659	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1660	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1661	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1662	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1663	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1664	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1665	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1666	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1667	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1668	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1669	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1670	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1671	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1672	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1673	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1674	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1675
1676	/* CPUID(0x80000001).edx */
1677	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1678	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1679	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1680	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1681	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1682	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1683	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1684	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1685	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1686	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1687	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1688	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1689	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1690	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1691	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1692	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1693	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1694	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1695	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1696	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1697	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1698	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1699	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1700	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1701	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1702	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1703	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1704	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1705	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1706	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1707	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1708	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1709
1710	/** @todo verify the rest as well. */
1711	}
1712	}
1713
1714
1715
1716	/*
1717	* Verify that we can support the features already exposed to the guest on
1718	* this host.
1719	*
1720	* Most of the features we're emulating requires intercepting instruction
1721	* and doing it the slow way, so there is no need to warn when they aren't
1722	* present in the host CPU. Thus we use IGN instead of EMU on these.
1723	*
1724	* Trailing comments:
1725	* "EMU" - Possible to emulate, could be lots of work and very slow.
1726	* "EMU?" - Can this be emulated?
1727	*/
1728	/* CPUID(1).ecx */
1729	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1730	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1731	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1732	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1733	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1734	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1735	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1736	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1737	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1738	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1739	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1740	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1741	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1742	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1743	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1744	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1745	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1746	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1747	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1748	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1749	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1750	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1751	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1752	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1753	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1754	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1755	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1756	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1757	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1758	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1759	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1760	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1761
1762	/* CPUID(1).edx */
1763	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1764	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1765	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1766	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1767	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1768	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1769	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1770	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1771	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1772	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1773	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1774	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1775	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1776	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1777	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1778	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1779	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1780	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1781	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1782	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1783	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1784	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1785	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1786	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1787	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1788	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1789	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1790	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1791	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1792	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1793	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1794	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1795
1796	/* CPUID(0x80000000). */
1797	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1798	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1799	{
1800	/** @todo deal with no 0x80000001 on the host. */
1801	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1802	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1803
1804	/* CPUID(0x80000001).ecx */
1805	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1806	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1807	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1808	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1809	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1810	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1811	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1812	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1813	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1814	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1815	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1816	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1817	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1818	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1819	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1820	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1821	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1822	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1823	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1824	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1825	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1826	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1827	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1828	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1829	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1830	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1831	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1832	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1833	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1834	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1835	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1836	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1837
1838	/* CPUID(0x80000001).edx */
1839	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1840	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1841	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1842	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1843	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1844	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1845	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1846	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1847	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1848	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1849	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1850	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1851	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1852	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1853	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1854	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1855	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1856	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1857	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1858	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1859	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1860	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1861	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1862	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1863	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1864	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1865	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1866	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1867	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1868	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1869	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1870	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1871	}
1872
1873	/*
1874	* We're good, commit the CPU ID leaves.
1875	*/
1876	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1877	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1878	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1879	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1880
1881	#undef CPUID_CHECK_RET
1882	#undef CPUID_CHECK_WRN
1883	#undef CPUID_CHECK2_RET
1884	#undef CPUID_CHECK2_WRN
1885	#undef CPUID_RAW_FEATURE_RET
1886	#undef CPUID_RAW_FEATURE_WRN
1887	#undef CPUID_RAW_FEATURE_IGN
1888	#undef CPUID_GST_FEATURE_RET
1889	#undef CPUID_GST_FEATURE_WRN
1890	#undef CPUID_GST_FEATURE_EMU
1891	#undef CPUID_GST_FEATURE_IGN
1892	#undef CPUID_GST_FEATURE2_RET
1893	#undef CPUID_GST_FEATURE2_WRN
1894	#undef CPUID_GST_FEATURE2_EMU
1895	#undef CPUID_GST_FEATURE2_IGN
1896	#undef CPUID_GST_AMD_FEATURE_RET
1897	#undef CPUID_GST_AMD_FEATURE_WRN
1898	#undef CPUID_GST_AMD_FEATURE_EMU
1899	#undef CPUID_GST_AMD_FEATURE_IGN
1900
1901	return VINF_SUCCESS;
1902	}
1903
1904
1905	/**
1906	* Pass 0 live exec callback.
1907	*
1908	* @returns VINF_SSM_DONT_CALL_AGAIN.
1909	* @param pVM The VM handle.
1910	* @param pSSM The saved state handle.
1911	* @param uPass The pass (0).
1912	*/
1913	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1914	{
1915	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1916	cpumR3SaveCpuId(pVM, pSSM);
1917	return VINF_SSM_DONT_CALL_AGAIN;
1918	}
1919
1920
1921	/**
1922	* Execute state save operation.
1923	*
1924	* @returns VBox status code.
1925	* @param pVM VM Handle.
1926	* @param pSSM SSM operation handle.
1927	*/
1928	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1929	{
1930	/*
1931	* Save.
1932	*/
1933	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1934	{
1935	PVMCPU pVCpu = &pVM->aCpus[i];
1936
1937	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1938	}
1939
1940	SSMR3PutU32(pSSM, pVM->cCpus);
1941	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1942	{
1943	PVMCPU pVCpu = &pVM->aCpus[i];
1944
1945	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1946	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1947	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1948	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1949	}
1950
1951	cpumR3SaveCpuId(pVM, pSSM);
1952	return VINF_SUCCESS;
1953	}
1954
1955
1956	/**
1957	* Load a version 1.6 CPUMCTX structure.
1958	*
1959	* @returns VBox status code.
1960	* @param pVM VM Handle.
1961	* @param pCpumctx16 Version 1.6 CPUMCTX
1962	*/
1963	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1964	{
1965	#define CPUMCTX16_LOADREG(RegName) \
1966	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1967
1968	#define CPUMCTX16_LOADDRXREG(RegName) \
1969	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1970
1971	#define CPUMCTX16_LOADHIDREG(RegName) \
1972	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1973	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1974	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1975
1976	#define CPUMCTX16_LOADSEGREG(RegName) \
1977	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1978	CPUMCTX16_LOADHIDREG(RegName);
1979
1980	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1981
1982	CPUMCTX16_LOADREG(rax);
1983	CPUMCTX16_LOADREG(rbx);
1984	CPUMCTX16_LOADREG(rcx);
1985	CPUMCTX16_LOADREG(rdx);
1986	CPUMCTX16_LOADREG(rdi);
1987	CPUMCTX16_LOADREG(rsi);
1988	CPUMCTX16_LOADREG(rbp);
1989	CPUMCTX16_LOADREG(esp);
1990	CPUMCTX16_LOADREG(rip);
1991	CPUMCTX16_LOADREG(rflags);
1992
1993	CPUMCTX16_LOADSEGREG(cs);
1994	CPUMCTX16_LOADSEGREG(ds);
1995	CPUMCTX16_LOADSEGREG(es);
1996	CPUMCTX16_LOADSEGREG(fs);
1997	CPUMCTX16_LOADSEGREG(gs);
1998	CPUMCTX16_LOADSEGREG(ss);
1999
2000	CPUMCTX16_LOADREG(r8);
2001	CPUMCTX16_LOADREG(r9);
2002	CPUMCTX16_LOADREG(r10);
2003	CPUMCTX16_LOADREG(r11);
2004	CPUMCTX16_LOADREG(r12);
2005	CPUMCTX16_LOADREG(r13);
2006	CPUMCTX16_LOADREG(r14);
2007	CPUMCTX16_LOADREG(r15);
2008
2009	CPUMCTX16_LOADREG(cr0);
2010	CPUMCTX16_LOADREG(cr2);
2011	CPUMCTX16_LOADREG(cr3);
2012	CPUMCTX16_LOADREG(cr4);
2013
2014	CPUMCTX16_LOADDRXREG(0);
2015	CPUMCTX16_LOADDRXREG(1);
2016	CPUMCTX16_LOADDRXREG(2);
2017	CPUMCTX16_LOADDRXREG(3);
2018	CPUMCTX16_LOADDRXREG(4);
2019	CPUMCTX16_LOADDRXREG(5);
2020	CPUMCTX16_LOADDRXREG(6);
2021	CPUMCTX16_LOADDRXREG(7);
2022
2023	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
2024	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
2025	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
2026	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
2027
2028	CPUMCTX16_LOADREG(ldtr);
2029	CPUMCTX16_LOADREG(tr);
2030
2031	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
2032
2033	CPUMCTX16_LOADREG(msrEFER);
2034	CPUMCTX16_LOADREG(msrSTAR);
2035	CPUMCTX16_LOADREG(msrPAT);
2036	CPUMCTX16_LOADREG(msrLSTAR);
2037	CPUMCTX16_LOADREG(msrCSTAR);
2038	CPUMCTX16_LOADREG(msrSFMASK);
2039	CPUMCTX16_LOADREG(msrKERNELGSBASE);
2040
2041	CPUMCTX16_LOADHIDREG(ldtr);
2042	CPUMCTX16_LOADHIDREG(tr);
2043
2044	#undef CPUMCTX16_LOADSEGREG
2045	#undef CPUMCTX16_LOADHIDREG
2046	#undef CPUMCTX16_LOADDRXREG
2047	#undef CPUMCTX16_LOADREG
2048	}
2049
2050
2051	/**
2052	* @copydoc FNSSMINTLOADPREP
2053	*/
2054	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2055	{
2056	pVM->cpum.s.fPendingRestore = true;
2057	return VINF_SUCCESS;
2058	}
2059
2060
2061	/**
2062	* @copydoc FNSSMINTLOADEXEC
2063	*/
2064	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2065	{
2066	/*
2067	* Validate version.
2068	*/
2069	if ( uVersion != CPUM_SAVED_STATE_VERSION
2070	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2071	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2072	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2073	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2074	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2075	{
2076	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2077	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2078	}
2079
2080	if (uPass == SSM_PASS_FINAL)
2081	{
2082	/*
2083	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2084	* really old SSM file versions.)
2085	*/
2086	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2087	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2088	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2089	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2090
2091	/*
2092	* Restore.
2093	*/
2094	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2095	{
2096	PVMCPU pVCpu = &pVM->aCpus[i];
2097	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2098	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
2099
2100	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
2101	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2102	pVCpu->cpum.s.Hyper.esp = uESP;
2103	}
2104
2105	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2106	{
2107	CPUMCTX_VER1_6 cpumctx16;
2108	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
2109	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
2110
2111	/* Save the old cpumctx state into the new one. */
2112	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
2113
2114	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
2115	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
2116	}
2117	else
2118	{
2119	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2120	{
2121	uint32_t cCpus;
2122	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2123	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2124	VERR_SSM_UNEXPECTED_DATA);
2125	}
2126	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2127	\|\| pVM->cCpus == 1,
2128	("cCpus=%u\n", pVM->cCpus),
2129	VERR_SSM_UNEXPECTED_DATA);
2130
2131	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2132	{
2133	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
2134	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
2135	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
2136	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2137	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
2138	}
2139	}
2140
2141	/* Older states does not set CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID for
2142	raw-mode guest, so we have to do it ourselves. */
2143	if ( uVersion <= CPUM_SAVED_STATE_VERSION_VER3_2
2144	&& !HWACCMIsEnabled(pVM))
2145	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2146	pVM->aCpus[iCpu].cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2147	}
2148
2149	pVM->cpum.s.fPendingRestore = false;
2150
2151	/*
2152	* Guest CPUIDs.
2153	*/
2154	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2155	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2156
2157	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2158	* actually required. */
2159
2160	/*
2161	* Restore the CPUID leaves.
2162	*
2163	* Note that we support restoring less than the current amount of standard
2164	* leaves because we've been allowed more is newer version of VBox.
2165	*/
2166	uint32_t cElements;
2167	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2168	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2169	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2170	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2171
2172	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2173	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2174	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2175	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2176
2177	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2178	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2179	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2180	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2181
2182	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2183
2184	/*
2185	* Check that the basic cpuid id information is unchanged.
2186	*/
2187	/** @todo we should check the 64 bits capabilities too! */
2188	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2189	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2190	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2191	uint32_t au32CpuIdSaved[8];
2192	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2193	if (RT_SUCCESS(rc))
2194	{
2195	/* Ignore CPU stepping. */
2196	au32CpuId[4] &= 0xfffffff0;
2197	au32CpuIdSaved[4] &= 0xfffffff0;
2198
2199	/* Ignore APIC ID (AMD specs). */
2200	au32CpuId[5] &= ~0xff000000;
2201	au32CpuIdSaved[5] &= ~0xff000000;
2202
2203	/* Ignore the number of Logical CPUs (AMD specs). */
2204	au32CpuId[5] &= ~0x00ff0000;
2205	au32CpuIdSaved[5] &= ~0x00ff0000;
2206
2207	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2208	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2209	\| X86_CPUID_FEATURE_ECX_VMX
2210	\| X86_CPUID_FEATURE_ECX_SMX
2211	\| X86_CPUID_FEATURE_ECX_EST
2212	\| X86_CPUID_FEATURE_ECX_TM2
2213	\| X86_CPUID_FEATURE_ECX_CNTXID
2214	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2215	\| X86_CPUID_FEATURE_ECX_PDCM
2216	\| X86_CPUID_FEATURE_ECX_DCA
2217	\| X86_CPUID_FEATURE_ECX_X2APIC
2218	);
2219	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2220	\| X86_CPUID_FEATURE_ECX_VMX
2221	\| X86_CPUID_FEATURE_ECX_SMX
2222	\| X86_CPUID_FEATURE_ECX_EST
2223	\| X86_CPUID_FEATURE_ECX_TM2
2224	\| X86_CPUID_FEATURE_ECX_CNTXID
2225	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2226	\| X86_CPUID_FEATURE_ECX_PDCM
2227	\| X86_CPUID_FEATURE_ECX_DCA
2228	\| X86_CPUID_FEATURE_ECX_X2APIC
2229	);
2230
2231	/* Make sure we don't forget to update the masks when enabling
2232	* features in the future.
2233	*/
2234	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2235	( X86_CPUID_FEATURE_ECX_DTES64
2236	\| X86_CPUID_FEATURE_ECX_VMX
2237	\| X86_CPUID_FEATURE_ECX_SMX
2238	\| X86_CPUID_FEATURE_ECX_EST
2239	\| X86_CPUID_FEATURE_ECX_TM2
2240	\| X86_CPUID_FEATURE_ECX_CNTXID
2241	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2242	\| X86_CPUID_FEATURE_ECX_PDCM
2243	\| X86_CPUID_FEATURE_ECX_DCA
2244	\| X86_CPUID_FEATURE_ECX_X2APIC
2245	)));
2246	/* do the compare */
2247	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2248	{
2249	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2250	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2251	"Saved=%.*Rhxs\n"
2252	"Real =%.*Rhxs\n",
2253	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2254	sizeof(au32CpuId), au32CpuId));
2255	else
2256	{
2257	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2258	"Saved=%.*Rhxs\n"
2259	"Real =%.*Rhxs\n",
2260	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2261	sizeof(au32CpuId), au32CpuId));
2262	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2263	}
2264	}
2265	}
2266
2267	return rc;
2268	}
2269
2270
2271	/**
2272	* @copydoc FNSSMINTLOADPREP
2273	*/
2274	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2275	{
2276	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2277	return VINF_SUCCESS;
2278
2279	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2280	if (pVM->cpum.s.fPendingRestore)
2281	{
2282	LogRel(("CPUM: Missing state!\n"));
2283	return VERR_INTERNAL_ERROR_2;
2284	}
2285
2286	/* Notify PGM of the NXE states in case they've changed. */
2287	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2288	PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2289	return VINF_SUCCESS;
2290	}
2291
2292
2293	/**
2294	* Checks if the CPUM state restore is still pending.
2295	*
2296	* @returns true / false.
2297	* @param pVM The VM handle.
2298	*/
2299	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2300	{
2301	return pVM->cpum.s.fPendingRestore;
2302	}
2303
2304
2305	/**
2306	* Formats the EFLAGS value into mnemonics.
2307	*
2308	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2309	* @param efl The EFLAGS value.
2310	*/
2311	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2312	{
2313	/*
2314	* Format the flags.
2315	*/
2316	static const struct
2317	{
2318	const char pszSet; const char pszClear; uint32_t fFlag;
2319	} s_aFlags[] =
2320	{
2321	{ "vip",NULL, X86_EFL_VIP },
2322	{ "vif",NULL, X86_EFL_VIF },
2323	{ "ac", NULL, X86_EFL_AC },
2324	{ "vm", NULL, X86_EFL_VM },
2325	{ "rf", NULL, X86_EFL_RF },
2326	{ "nt", NULL, X86_EFL_NT },
2327	{ "ov", "nv", X86_EFL_OF },
2328	{ "dn", "up", X86_EFL_DF },
2329	{ "ei", "di", X86_EFL_IF },
2330	{ "tf", NULL, X86_EFL_TF },
2331	{ "nt", "pl", X86_EFL_SF },
2332	{ "nz", "zr", X86_EFL_ZF },
2333	{ "ac", "na", X86_EFL_AF },
2334	{ "po", "pe", X86_EFL_PF },
2335	{ "cy", "nc", X86_EFL_CF },
2336	};
2337	char *psz = pszEFlags;
2338	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2339	{
2340	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2341	if (pszAdd)
2342	{
2343	strcpy(psz, pszAdd);
2344	psz += strlen(pszAdd);
2345	*psz++ = ' ';
2346	}
2347	}
2348	psz[-1] = '\0';
2349	}
2350
2351
2352	/**
2353	* Formats a full register dump.
2354	*
2355	* @param pVM VM Handle.
2356	* @param pCtx The context to format.
2357	* @param pCtxCore The context core to format.
2358	* @param pHlp Output functions.
2359	* @param enmType The dump type.
2360	* @param pszPrefix Register name prefix.
2361	*/
2362	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2363	{
2364	/*
2365	* Format the EFLAGS.
2366	*/
2367	uint32_t efl = pCtxCore->eflags.u32;
2368	char szEFlags[80];
2369	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2370
2371	/*
2372	* Format the registers.
2373	*/
2374	switch (enmType)
2375	{
2376	case CPUMDUMPTYPE_TERSE:
2377	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2378	pHlp->pfnPrintf(pHlp,
2379	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2380	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2381	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2382	"%sr14=%016RX64 %sr15=%016RX64\n"
2383	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2384	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2385	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2386	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2387	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2388	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2389	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2390	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2391	else
2392	pHlp->pfnPrintf(pHlp,
2393	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2394	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2395	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2396	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2397	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2398	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2399	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2400	break;
2401
2402	case CPUMDUMPTYPE_DEFAULT:
2403	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2404	pHlp->pfnPrintf(pHlp,
2405	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2406	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2407	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2408	"%sr14=%016RX64 %sr15=%016RX64\n"
2409	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2410	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2411	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2412	,
2413	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2414	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2415	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2416	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2417	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2418	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2419	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2420	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2421	else
2422	pHlp->pfnPrintf(pHlp,
2423	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2424	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2425	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2426	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2427	,
2428	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2429	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2430	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2431	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2432	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2433	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2434	break;
2435
2436	case CPUMDUMPTYPE_VERBOSE:
2437	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2438	pHlp->pfnPrintf(pHlp,
2439	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2440	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2441	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2442	"%sr14=%016RX64 %sr15=%016RX64\n"
2443	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2444	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2445	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2446	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2447	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2448	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2449	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2450	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2451	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2452	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2453	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2454	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2455	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2456	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2457	,
2458	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2459	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2460	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2461	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2462	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2463	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2464	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2465	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2466	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2467	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2468	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2469	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2470	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2471	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2472	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2473	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2474	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2475	else
2476	pHlp->pfnPrintf(pHlp,
2477	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2478	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2479	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2480	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2481	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2482	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2483	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2484	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2485	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2486	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2487	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2488	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2489	,
2490	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2491	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2492	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2493	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2494	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2495	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2496	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2497	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2498	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2499	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2500	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2501	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2502
2503	pHlp->pfnPrintf(pHlp,
2504	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2505	"%sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2506	,
2507	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2508	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2509	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2510	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2511	);
2512	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2513	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2514	{
2515	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2516	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2517	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2518	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2519	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2520	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2521	/** @todo This isn't entirenly correct and needs more work! */
2522	pHlp->pfnPrintf(pHlp,
2523	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2524	pszPrefix, iST, pszPrefix, iFPR,
2525	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2526	uTag, chSign, iInteger, u64Fraction, uExponent);
2527	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2528	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2529	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2530	else
2531	pHlp->pfnPrintf(pHlp, "\n");
2532	}
2533	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2534	pHlp->pfnPrintf(pHlp,
2535	iXMM & 1
2536	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2537	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2538	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2539	pCtx->fpu.aXMM[iXMM].au32[3],
2540	pCtx->fpu.aXMM[iXMM].au32[2],
2541	pCtx->fpu.aXMM[iXMM].au32[1],
2542	pCtx->fpu.aXMM[iXMM].au32[0]);
2543	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2544	if (pCtx->fpu.au32RsrvdRest[i])
2545	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2546	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2547
2548	pHlp->pfnPrintf(pHlp,
2549	"%sEFER =%016RX64\n"
2550	"%sPAT =%016RX64\n"
2551	"%sSTAR =%016RX64\n"
2552	"%sCSTAR =%016RX64\n"
2553	"%sLSTAR =%016RX64\n"
2554	"%sSFMASK =%016RX64\n"
2555	"%sKERNELGSBASE =%016RX64\n",
2556	pszPrefix, pCtx->msrEFER,
2557	pszPrefix, pCtx->msrPAT,
2558	pszPrefix, pCtx->msrSTAR,
2559	pszPrefix, pCtx->msrCSTAR,
2560	pszPrefix, pCtx->msrLSTAR,
2561	pszPrefix, pCtx->msrSFMASK,
2562	pszPrefix, pCtx->msrKERNELGSBASE);
2563	break;
2564	}
2565	}
2566
2567
2568	/**
2569	* Display all cpu states and any other cpum info.
2570	*
2571	* @param pVM VM Handle.
2572	* @param pHlp The info helper functions.
2573	* @param pszArgs Arguments, ignored.
2574	*/
2575	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2576	{
2577	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2578	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2579	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2580	cpumR3InfoHost(pVM, pHlp, pszArgs);
2581	}
2582
2583
2584	/**
2585	* Parses the info argument.
2586	*
2587	* The argument starts with 'verbose', 'terse' or 'default' and then
2588	* continues with the comment string.
2589	*
2590	* @param pszArgs The pointer to the argument string.
2591	* @param penmType Where to store the dump type request.
2592	* @param ppszComment Where to store the pointer to the comment string.
2593	*/
2594	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2595	{
2596	if (!pszArgs)
2597	{
2598	*penmType = CPUMDUMPTYPE_DEFAULT;
2599	*ppszComment = "";
2600	}
2601	else
2602	{
2603	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2604	{
2605	pszArgs += 5;
2606	*penmType = CPUMDUMPTYPE_VERBOSE;
2607	}
2608	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2609	{
2610	pszArgs += 5;
2611	*penmType = CPUMDUMPTYPE_TERSE;
2612	}
2613	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2614	{
2615	pszArgs += 7;
2616	*penmType = CPUMDUMPTYPE_DEFAULT;
2617	}
2618	else
2619	*penmType = CPUMDUMPTYPE_DEFAULT;
2620	*ppszComment = RTStrStripL(pszArgs);
2621	}
2622	}
2623
2624
2625	/**
2626	* Display the guest cpu state.
2627	*
2628	* @param pVM VM Handle.
2629	* @param pHlp The info helper functions.
2630	* @param pszArgs Arguments, ignored.
2631	*/
2632	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2633	{
2634	CPUMDUMPTYPE enmType;
2635	const char *pszComment;
2636	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2637
2638	/* @todo SMP support! */
2639	PVMCPU pVCpu = VMMGetCpu(pVM);
2640	if (!pVCpu)
2641	pVCpu = &pVM->aCpus[0];
2642
2643	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2644
2645	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2646	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2647	}
2648
2649
2650	/**
2651	* Display the current guest instruction
2652	*
2653	* @param pVM VM Handle.
2654	* @param pHlp The info helper functions.
2655	* @param pszArgs Arguments, ignored.
2656	*/
2657	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2658	{
2659	char szInstruction[256];
2660	/* @todo SMP support! */
2661	PVMCPU pVCpu = VMMGetCpu(pVM);
2662	if (!pVCpu)
2663	pVCpu = &pVM->aCpus[0];
2664
2665	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2666	if (RT_SUCCESS(rc))
2667	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2668	}
2669
2670
2671	/**
2672	* Display the hypervisor cpu state.
2673	*
2674	* @param pVM VM Handle.
2675	* @param pHlp The info helper functions.
2676	* @param pszArgs Arguments, ignored.
2677	*/
2678	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2679	{
2680	CPUMDUMPTYPE enmType;
2681	const char *pszComment;
2682	/* @todo SMP */
2683	PVMCPU pVCpu = &pVM->aCpus[0];
2684
2685	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2686	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2687	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2688	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2689	}
2690
2691
2692	/**
2693	* Display the host cpu state.
2694	*
2695	* @param pVM VM Handle.
2696	* @param pHlp The info helper functions.
2697	* @param pszArgs Arguments, ignored.
2698	*/
2699	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2700	{
2701	CPUMDUMPTYPE enmType;
2702	const char *pszComment;
2703	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2704	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2705
2706	/*
2707	* Format the EFLAGS.
2708	*/
2709	/* @todo SMP */
2710	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2711	#if HC_ARCH_BITS == 32
2712	uint32_t efl = pCtx->eflags.u32;
2713	#else
2714	uint64_t efl = pCtx->rflags;
2715	#endif
2716	char szEFlags[80];
2717	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2718
2719	/*
2720	* Format the registers.
2721	*/
2722	#if HC_ARCH_BITS == 32
2723	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2724	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2725	# endif
2726	{
2727	pHlp->pfnPrintf(pHlp,
2728	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2729	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2730	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2731	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2732	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2733	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2734	,
2735	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2736	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2737	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2738	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2739	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2740	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2741	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2742	}
2743	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2744	else
2745	# endif
2746	#endif
2747	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2748	{
2749	pHlp->pfnPrintf(pHlp,
2750	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2751	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2752	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2753	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2754	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2755	"r14=%016RX64 r15=%016RX64\n"
2756	"iopl=%d %31s\n"
2757	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2758	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2759	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2760	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2761	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2762	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2763	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2764	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2765	,
2766	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2767	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2768	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2769	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2770	pCtx->r11, pCtx->r12, pCtx->r13,
2771	pCtx->r14, pCtx->r15,
2772	X86_EFL_GET_IOPL(efl), szEFlags,
2773	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2774	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2775	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2776	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2777	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2778	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2779	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2780	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2781	}
2782	#endif
2783	}
2784
2785
2786	/**
2787	* Get L1 cache / TLS associativity.
2788	*/
2789	static const char getCacheAss(unsigned u, char pszBuf)
2790	{
2791	if (u == 0)
2792	return "res0 ";
2793	if (u == 1)
2794	return "direct";
2795	if (u == 255)
2796	return "fully";
2797	if (u >= 256)
2798	return "???";
2799
2800	RTStrPrintf(pszBuf, 16, "%d way", u);
2801	return pszBuf;
2802	}
2803
2804
2805	/**
2806	* Get L2 cache soociativity.
2807	*/
2808	const char *getL2CacheAss(unsigned u)
2809	{
2810	switch (u)
2811	{
2812	case 0: return "off ";
2813	case 1: return "direct";
2814	case 2: return "2 way ";
2815	case 3: return "res3 ";
2816	case 4: return "4 way ";
2817	case 5: return "res5 ";
2818	case 6: return "8 way ";
2819	case 7: return "res7 ";
2820	case 8: return "16 way";
2821	case 9: return "res9 ";
2822	case 10: return "res10 ";
2823	case 11: return "res11 ";
2824	case 12: return "res12 ";
2825	case 13: return "res13 ";
2826	case 14: return "res14 ";
2827	case 15: return "fully ";
2828	default: return "????";
2829	}
2830	}
2831
2832
2833	/**
2834	* Display the guest CpuId leaves.
2835	*
2836	* @param pVM VM Handle.
2837	* @param pHlp The info helper functions.
2838	* @param pszArgs "terse", "default" or "verbose".
2839	*/
2840	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2841	{
2842	/*
2843	* Parse the argument.
2844	*/
2845	unsigned iVerbosity = 1;
2846	if (pszArgs)
2847	{
2848	pszArgs = RTStrStripL(pszArgs);
2849	if (!strcmp(pszArgs, "terse"))
2850	iVerbosity--;
2851	else if (!strcmp(pszArgs, "verbose"))
2852	iVerbosity++;
2853	}
2854
2855	/*
2856	* Start cracking.
2857	*/
2858	CPUMCPUID Host;
2859	CPUMCPUID Guest;
2860	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2861
2862	pHlp->pfnPrintf(pHlp,
2863	" RAW Standard CPUIDs\n"
2864	" Function eax ebx ecx edx\n");
2865	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2866	{
2867	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2868	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2869
2870	pHlp->pfnPrintf(pHlp,
2871	"Gst: %08x %08x %08x %08x %08x%s\n"
2872	"Hst: %08x %08x %08x %08x\n",
2873	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2874	i <= cStdMax ? "" : "*",
2875	Host.eax, Host.ebx, Host.ecx, Host.edx);
2876	}
2877
2878	/*
2879	* If verbose, decode it.
2880	*/
2881	if (iVerbosity)
2882	{
2883	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2884	pHlp->pfnPrintf(pHlp,
2885	"Name: %.04s%.04s%.04s\n"
2886	"Supports: 0-%x\n",
2887	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2888	}
2889
2890	/*
2891	* Get Features.
2892	*/
2893	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2894	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2895	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2896	if (cStdMax >= 1 && iVerbosity)
2897	{
2898	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
2899
2900	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2901	uint32_t uEAX = Guest.eax;
2902
2903	pHlp->pfnPrintf(pHlp,
2904	"Family: %d \tExtended: %d \tEffective: %d\n"
2905	"Model: %d \tExtended: %d \tEffective: %d\n"
2906	"Stepping: %d\n"
2907	"Type: %d (%s)\n"
2908	"APIC ID: %#04x\n"
2909	"Logical CPUs: %d\n"
2910	"CLFLUSH Size: %d\n"
2911	"Brand ID: %#04x\n",
2912	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2913	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2914	ASMGetCpuStepping(uEAX),
2915	(uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
2916	(Guest.ebx >> 24) & 0xff,
2917	(Guest.ebx >> 16) & 0xff,
2918	(Guest.ebx >> 8) & 0xff,
2919	(Guest.ebx >> 0) & 0xff);
2920	if (iVerbosity == 1)
2921	{
2922	uint32_t uEDX = Guest.edx;
2923	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2924	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2925	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2926	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2927	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2928	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2929	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2930	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2931	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2932	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2933	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2934	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2935	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2936	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2937	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2938	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2939	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2940	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2941	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2942	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2943	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2944	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2945	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2946	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2947	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2948	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2949	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2950	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2951	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2952	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2953	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2954	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2955	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2956	pHlp->pfnPrintf(pHlp, "\n");
2957
2958	uint32_t uECX = Guest.ecx;
2959	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2960	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2961	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2962	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2963	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2964	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2965	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2966	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2967	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2968	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2969	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2970	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2971	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2972	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2973	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2974	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2975	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2976	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2977	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " 17");
2978	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2979	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4_1");
2980	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4_2");
2981	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2982	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2983	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2984	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " 24");
2985	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2986	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2987	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2988	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2989	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2990	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2991	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2992	pHlp->pfnPrintf(pHlp, "\n");
2993	}
2994	else
2995	{
2996	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2997
2998	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2999	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3000	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3001	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3002
3003	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3004	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3005	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3006	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3007	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3008	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3009	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3010	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3011	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3012	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3013	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3014	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3015	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3016	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3017	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3018	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3019	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3020	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3021	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3022	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3023	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3024	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3025	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3026	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3027	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3028	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3029	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3030	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3031	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3032	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3033	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3034	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3035	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3036
3037	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3038	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3039	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3040	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3041	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3042	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3043	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3044	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3045	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3046	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3047	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3048	pHlp->pfnPrintf(pHlp, "FMA = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3049	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3050	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3051	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3052	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3053	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3054	pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3055	pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3056	pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3057	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3058	pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3059	pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3060	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
3061	pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3062	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3063	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
3064	}
3065	}
3066	if (cStdMax >= 2 && iVerbosity)
3067	{
3068	/** @todo */
3069	}
3070
3071	/*
3072	* Extended.
3073	* Implemented after AMD specs.
3074	*/
3075	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3076
3077	pHlp->pfnPrintf(pHlp,
3078	"\n"
3079	" RAW Extended CPUIDs\n"
3080	" Function eax ebx ecx edx\n");
3081	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3082	{
3083	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3084	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3085
3086	pHlp->pfnPrintf(pHlp,
3087	"Gst: %08x %08x %08x %08x %08x%s\n"
3088	"Hst: %08x %08x %08x %08x\n",
3089	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3090	i <= cExtMax ? "" : "*",
3091	Host.eax, Host.ebx, Host.ecx, Host.edx);
3092	}
3093
3094	/*
3095	* Understandable output
3096	*/
3097	if (iVerbosity)
3098	{
3099	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3100	pHlp->pfnPrintf(pHlp,
3101	"Ext Name: %.4s%.4s%.4s\n"
3102	"Ext Supports: 0x80000000-%#010x\n",
3103	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3104	}
3105
3106	if (iVerbosity && cExtMax >= 1)
3107	{
3108	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3109	uint32_t uEAX = Guest.eax;
3110	pHlp->pfnPrintf(pHlp,
3111	"Family: %d \tExtended: %d \tEffective: %d\n"
3112	"Model: %d \tExtended: %d \tEffective: %d\n"
3113	"Stepping: %d\n"
3114	"Brand ID: %#05x\n",
3115	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3116	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3117	ASMGetCpuStepping(uEAX),
3118	Guest.ebx & 0xfff);
3119
3120	if (iVerbosity == 1)
3121	{
3122	uint32_t uEDX = Guest.edx;
3123	pHlp->pfnPrintf(pHlp, "Features EDX: ");
3124	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3125	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3126	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3127	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3128	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3129	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3130	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3131	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3132	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3133	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3134	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3135	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3136	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3137	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3138	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3139	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3140	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3141	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3142	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3143	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3144	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3145	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3146	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3147	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3148	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3149	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3150	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3151	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3152	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3153	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3154	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3155	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3156	pHlp->pfnPrintf(pHlp, "\n");
3157
3158	uint32_t uECX = Guest.ecx;
3159	pHlp->pfnPrintf(pHlp, "Features ECX: ");
3160	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3161	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3162	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3163	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3164	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3165	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3166	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3167	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3168	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3169	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3170	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3171	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3172	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3173	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3174	for (unsigned iBit = 5; iBit < 32; iBit++)
3175	if (uECX & RT_BIT(iBit))
3176	pHlp->pfnPrintf(pHlp, " %d", iBit);
3177	pHlp->pfnPrintf(pHlp, "\n");
3178	}
3179	else
3180	{
3181	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3182
3183	uint32_t uEdxGst = Guest.edx;
3184	uint32_t uEdxHst = Host.edx;
3185	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3186	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3187	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3188	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3189	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3190	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3191	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3192	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3193	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3194	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3195	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3196	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3197	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3198	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3199	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3200	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3201	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3202	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3203	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3204	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3205	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3206	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3207	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3208	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3209	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3210	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3211	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3212	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3213	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3214	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3215	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3216	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3217	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3218
3219	uint32_t uEcxGst = Guest.ecx;
3220	uint32_t uEcxHst = Host.ecx;
3221	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3222	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3223	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3224	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3225	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3226	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3227	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3228	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3229	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3230	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3231	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3232	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3233	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3234	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3235	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3236	}
3237	}
3238
3239	if (iVerbosity && cExtMax >= 2)
3240	{
3241	char szString[443+1] = {0};
3242	uint32_t pu32 = (uint32_t )szString;
3243	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3244	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3245	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3246	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3247	if (cExtMax >= 3)
3248	{
3249	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3250	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3251	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3252	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3253	}
3254	if (cExtMax >= 4)
3255	{
3256	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3257	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3258	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3259	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3260	}
3261	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3262	}
3263
3264	if (iVerbosity && cExtMax >= 5)
3265	{
3266	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3267	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3268	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3269	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3270	char sz1[32];
3271	char sz2[32];
3272
3273	pHlp->pfnPrintf(pHlp,
3274	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3275	"TLB 2/4M Data: %s %3d entries\n",
3276	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3277	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3278	pHlp->pfnPrintf(pHlp,
3279	"TLB 4K Instr/Uni: %s %3d entries\n"
3280	"TLB 4K Data: %s %3d entries\n",
3281	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3282	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3283	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3284	"L1 Instr Cache Lines Per Tag: %d\n"
3285	"L1 Instr Cache Associativity: %s\n"
3286	"L1 Instr Cache Size: %d KB\n",
3287	(uEDX >> 0) & 0xff,
3288	(uEDX >> 8) & 0xff,
3289	getCacheAss((uEDX >> 16) & 0xff, sz1),
3290	(uEDX >> 24) & 0xff);
3291	pHlp->pfnPrintf(pHlp,
3292	"L1 Data Cache Line Size: %d bytes\n"
3293	"L1 Data Cache Lines Per Tag: %d\n"
3294	"L1 Data Cache Associativity: %s\n"
3295	"L1 Data Cache Size: %d KB\n",
3296	(uECX >> 0) & 0xff,
3297	(uECX >> 8) & 0xff,
3298	getCacheAss((uECX >> 16) & 0xff, sz1),
3299	(uECX >> 24) & 0xff);
3300	}
3301
3302	if (iVerbosity && cExtMax >= 6)
3303	{
3304	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3305	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3306	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3307
3308	pHlp->pfnPrintf(pHlp,
3309	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3310	"L2 TLB 2/4M Data: %s %4d entries\n",
3311	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3312	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3313	pHlp->pfnPrintf(pHlp,
3314	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3315	"L2 TLB 4K Data: %s %4d entries\n",
3316	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3317	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3318	pHlp->pfnPrintf(pHlp,
3319	"L2 Cache Line Size: %d bytes\n"
3320	"L2 Cache Lines Per Tag: %d\n"
3321	"L2 Cache Associativity: %s\n"
3322	"L2 Cache Size: %d KB\n",
3323	(uEDX >> 0) & 0xff,
3324	(uEDX >> 8) & 0xf,
3325	getL2CacheAss((uEDX >> 12) & 0xf),
3326	(uEDX >> 16) & 0xffff);
3327	}
3328
3329	if (iVerbosity && cExtMax >= 7)
3330	{
3331	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3332
3333	pHlp->pfnPrintf(pHlp, "APM Features: ");
3334	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3335	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3336	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3337	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3338	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3339	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3340	for (unsigned iBit = 6; iBit < 32; iBit++)
3341	if (uEDX & RT_BIT(iBit))
3342	pHlp->pfnPrintf(pHlp, " %d", iBit);
3343	pHlp->pfnPrintf(pHlp, "\n");
3344	}
3345
3346	if (iVerbosity && cExtMax >= 8)
3347	{
3348	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3349	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3350
3351	pHlp->pfnPrintf(pHlp,
3352	"Physical Address Width: %d bits\n"
3353	"Virtual Address Width: %d bits\n"
3354	"Guest Physical Address Width: %d bits\n",
3355	(uEAX >> 0) & 0xff,
3356	(uEAX >> 8) & 0xff,
3357	(uEAX >> 16) & 0xff);
3358	pHlp->pfnPrintf(pHlp,
3359	"Physical Core Count: %d\n",
3360	(uECX >> 0) & 0xff);
3361	}
3362
3363
3364	/*
3365	* Centaur.
3366	*/
3367	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3368
3369	pHlp->pfnPrintf(pHlp,
3370	"\n"
3371	" RAW Centaur CPUIDs\n"
3372	" Function eax ebx ecx edx\n");
3373	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3374	{
3375	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3376	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3377
3378	pHlp->pfnPrintf(pHlp,
3379	"Gst: %08x %08x %08x %08x %08x%s\n"
3380	"Hst: %08x %08x %08x %08x\n",
3381	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3382	i <= cCentaurMax ? "" : "*",
3383	Host.eax, Host.ebx, Host.ecx, Host.edx);
3384	}
3385
3386	/*
3387	* Understandable output
3388	*/
3389	if (iVerbosity)
3390	{
3391	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3392	pHlp->pfnPrintf(pHlp,
3393	"Centaur Supports: 0xc0000000-%#010x\n",
3394	Guest.eax);
3395	}
3396
3397	if (iVerbosity && cCentaurMax >= 1)
3398	{
3399	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3400	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3401	uint32_t uEdxHst = Host.edx;
3402
3403	if (iVerbosity == 1)
3404	{
3405	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3406	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3407	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3408	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3409	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3410	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3411	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3412	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3413	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3414	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3415	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3416	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3417	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3418	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3419	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3420	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3421	for (unsigned iBit = 14; iBit < 32; iBit++)
3422	if (uEdxGst & RT_BIT(iBit))
3423	pHlp->pfnPrintf(pHlp, " %d", iBit);
3424	pHlp->pfnPrintf(pHlp, "\n");
3425	}
3426	else
3427	{
3428	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3429	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3430	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3431	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3432	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3433	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3434	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3435	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3436	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3437	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3438	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3439	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3440	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3441	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3442	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3443	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3444	for (unsigned iBit = 14; iBit < 32; iBit++)
3445	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3446	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3447	pHlp->pfnPrintf(pHlp, "\n");
3448	}
3449	}
3450	}
3451
3452
3453	/**
3454	* Structure used when disassembling and instructions in DBGF.
3455	* This is used so the reader function can get the stuff it needs.
3456	*/
3457	typedef struct CPUMDISASSTATE
3458	{
3459	/** Pointer to the CPU structure. */
3460	PDISCPUSTATE pCpu;
3461	/** The VM handle. */
3462	PVM pVM;
3463	/** The VMCPU handle. */
3464	PVMCPU pVCpu;
3465	/** Pointer to the first byte in the segemnt. */
3466	RTGCUINTPTR GCPtrSegBase;
3467	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3468	RTGCUINTPTR GCPtrSegEnd;
3469	/** The size of the segment minus 1. */
3470	RTGCUINTPTR cbSegLimit;
3471	/** Pointer to the current page - R3 Ptr. */
3472	void const *pvPageR3;
3473	/** Pointer to the current page - GC Ptr. */
3474	RTGCPTR pvPageGC;
3475	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3476	PGMPAGEMAPLOCK PageMapLock;
3477	/** Whether the PageMapLock is valid or not. */
3478	bool fLocked;
3479	/** 64 bits mode or not. */
3480	bool f64Bits;
3481	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3482
3483
3484	/**
3485	* Instruction reader.
3486	*
3487	* @returns VBox status code.
3488	* @param PtrSrc Address to read from.
3489	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3490	* @param pu8Dst Where to store the bytes.
3491	* @param cbRead Number of bytes to read.
3492	* @param uDisCpu Pointer to the disassembler cpu state.
3493	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3494	*/
3495	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3496	{
3497	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3498	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3499	Assert(cbRead > 0);
3500	for (;;)
3501	{
3502	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3503
3504	/* Need to update the page translation? */
3505	if ( !pState->pvPageR3
3506	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3507	{
3508	int rc = VINF_SUCCESS;
3509
3510	/* translate the address */
3511	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3512	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3513	&& !HWACCMIsEnabled(pState->pVM))
3514	{
3515	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3516	if (!pState->pvPageR3)
3517	rc = VERR_INVALID_POINTER;
3518	}
3519	else
3520	{
3521	/* Release mapping lock previously acquired. */
3522	if (pState->fLocked)
3523	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3524	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3525	pState->fLocked = RT_SUCCESS_NP(rc);
3526	}
3527	if (RT_FAILURE(rc))
3528	{
3529	pState->pvPageR3 = NULL;
3530	return rc;
3531	}
3532	}
3533
3534	/* check the segemnt limit */
3535	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3536	return VERR_OUT_OF_SELECTOR_BOUNDS;
3537
3538	/* calc how much we can read */
3539	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3540	if (!pState->f64Bits)
3541	{
3542	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3543	if (cb > cbSeg && cbSeg)
3544	cb = cbSeg;
3545	}
3546	if (cb > cbRead)
3547	cb = cbRead;
3548
3549	/* read and advance */
3550	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3551	cbRead -= cb;
3552	if (!cbRead)
3553	return VINF_SUCCESS;
3554	pu8Dst += cb;
3555	PtrSrc += cb;
3556	}
3557	}
3558
3559
3560	/**
3561	* Disassemble an instruction and return the information in the provided structure.
3562	*
3563	* @returns VBox status code.
3564	* @param pVM VM Handle
3565	* @param pVCpu VMCPU Handle
3566	* @param pCtx CPU context
3567	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3568	* @param pCpu Disassembly state
3569	* @param pszPrefix String prefix for logging (debug only)
3570	*
3571	*/
3572	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3573	{
3574	CPUMDISASSTATE State;
3575	int rc;
3576
3577	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3578	State.pCpu = pCpu;
3579	State.pvPageGC = 0;
3580	State.pvPageR3 = NULL;
3581	State.pVM = pVM;
3582	State.pVCpu = pVCpu;
3583	State.fLocked = false;
3584	State.f64Bits = false;
3585
3586	/*
3587	* Get selector information.
3588	*/
3589	if ( (pCtx->cr0 & X86_CR0_PE)
3590	&& pCtx->eflags.Bits.u1VM == 0)
3591	{
3592	if (CPUMAreHiddenSelRegsValid(pVCpu))
3593	{
3594	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3595	State.GCPtrSegBase = pCtx->csHid.u64Base;
3596	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3597	State.cbSegLimit = pCtx->csHid.u32Limit;
3598	pCpu->mode = (State.f64Bits)
3599	? CPUMODE_64BIT
3600	: pCtx->csHid.Attr.n.u1DefBig
3601	? CPUMODE_32BIT
3602	: CPUMODE_16BIT;
3603	}
3604	else
3605	{
3606	DBGFSELINFO SelInfo;
3607
3608	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3609	if (RT_FAILURE(rc))
3610	{
3611	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3612	return rc;
3613	}
3614
3615	/*
3616	* Validate the selector.
3617	*/
3618	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3619	if (RT_FAILURE(rc))
3620	{
3621	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3622	return rc;
3623	}
3624	State.GCPtrSegBase = SelInfo.GCPtrBase;
3625	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3626	State.cbSegLimit = SelInfo.cbLimit;
3627	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3628	}
3629	}
3630	else
3631	{
3632	/* real or V86 mode */
3633	pCpu->mode = CPUMODE_16BIT;
3634	State.GCPtrSegBase = pCtx->cs * 16;
3635	State.GCPtrSegEnd = 0xFFFFFFFF;
3636	State.cbSegLimit = 0xFFFFFFFF;
3637	}
3638
3639	/*
3640	* Disassemble the instruction.
3641	*/
3642	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3643	pCpu->apvUserData[0] = &State;
3644
3645	uint32_t cbInstr;
3646	#ifndef LOG_ENABLED
3647	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3648	if (RT_SUCCESS(rc))
3649	{
3650	#else
3651	char szOutput[160];
3652	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3653	if (RT_SUCCESS(rc))
3654	{
3655	/* log it */
3656	if (pszPrefix)
3657	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3658	else
3659	Log(("%s", szOutput));
3660	#endif
3661	rc = VINF_SUCCESS;
3662	}
3663	else
3664	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3665
3666	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3667	if (State.fLocked)
3668	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3669
3670	return rc;
3671	}
3672
3673	#ifdef DEBUG
3674
3675	/**
3676	* Disassemble an instruction and dump it to the log
3677	*
3678	* @returns VBox status code.
3679	* @param pVM VM Handle
3680	* @param pVCpu VMCPU Handle
3681	* @param pCtx CPU context
3682	* @param pc GC instruction pointer
3683	* @param pszPrefix String prefix for logging
3684	*
3685	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3686	*/
3687	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3688	{
3689	DISCPUSTATE Cpu;
3690	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3691	}
3692
3693
3694	/**
3695	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3696	*
3697	* @internal
3698	*/
3699	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3700	{
3701	/** @todo SMP support!! */
3702	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3703	}
3704
3705	#endif /* DEBUG */
3706
3707	/**
3708	* API for controlling a few of the CPU features found in CR4.
3709	*
3710	* Currently only X86_CR4_TSD is accepted as input.
3711	*
3712	* @returns VBox status code.
3713	*
3714	* @param pVM The VM handle.
3715	* @param fOr The CR4 OR mask.
3716	* @param fAnd The CR4 AND mask.
3717	*/
3718	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3719	{
3720	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3721	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3722
3723	pVM->cpum.s.CR4.OrMask &= fAnd;
3724	pVM->cpum.s.CR4.OrMask \|= fOr;
3725
3726	return VINF_SUCCESS;
3727	}
3728
3729
3730	/**
3731	* Gets a pointer to the array of standard CPUID leaves.
3732	*
3733	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3734	*
3735	* @returns Pointer to the standard CPUID leaves (read-only).
3736	* @param pVM The VM handle.
3737	* @remark Intended for PATM.
3738	*/
3739	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3740	{
3741	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3742	}
3743
3744
3745	/**
3746	* Gets a pointer to the array of extended CPUID leaves.
3747	*
3748	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3749	*
3750	* @returns Pointer to the extended CPUID leaves (read-only).
3751	* @param pVM The VM handle.
3752	* @remark Intended for PATM.
3753	*/
3754	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3755	{
3756	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3757	}
3758
3759
3760	/**
3761	* Gets a pointer to the array of centaur CPUID leaves.
3762	*
3763	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3764	*
3765	* @returns Pointer to the centaur CPUID leaves (read-only).
3766	* @param pVM The VM handle.
3767	* @remark Intended for PATM.
3768	*/
3769	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3770	{
3771	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3772	}
3773
3774
3775	/**
3776	* Gets a pointer to the default CPUID leaf.
3777	*
3778	* @returns Pointer to the default CPUID leaf (read-only).
3779	* @param pVM The VM handle.
3780	* @remark Intended for PATM.
3781	*/
3782	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3783	{
3784	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3785	}
3786
3787
3788	/**
3789	* Transforms the guest CPU state to raw-ring mode.
3790	*
3791	* This function will change the any of the cs and ss register with DPL=0 to DPL=1.
3792	*
3793	* @returns VBox status. (recompiler failure)
3794	* @param pVCpu The VMCPU handle.
3795	* @param pCtxCore The context core (for trap usage).
3796	* @see @ref pg_raw
3797	*/
3798	VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
3799	{
3800	PVM pVM = pVCpu->CTX_SUFF(pVM);
3801
3802	Assert(!pVCpu->cpum.s.fRawEntered);
3803	Assert(!pVCpu->cpum.s.fRemEntered);
3804	if (!pCtxCore)
3805	pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
3806
3807	/*
3808	* Are we in Ring-0?
3809	*/
3810	if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
3811	&& !pCtxCore->eflags.Bits.u1VM)
3812	{
3813	/*
3814	* Enter execution mode.
3815	*/
3816	PATMRawEnter(pVM, pCtxCore);
3817
3818	/*
3819	* Set CPL to Ring-1.
3820	*/
3821	pCtxCore->ss \|= 1;
3822	if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
3823	pCtxCore->cs \|= 1;
3824	}
3825	else
3826	{
3827	AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 \|\| pCtxCore->eflags.Bits.u1VM,
3828	("ring-1 code not supported\n"));
3829	/*
3830	* PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
3831	*/
3832	PATMRawEnter(pVM, pCtxCore);
3833	}
3834
3835	/*
3836	* Invalidate the hidden registers.
3837	*/
3838	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3839
3840	/*
3841	* Assert sanity.
3842	*/
3843	AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
3844	AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
3845	\|\| pCtxCore->eflags.Bits.u1VM,
3846	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3847	Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)) == (X86_CR0_PG \| X86_CR0_PE \| X86_CR0_WP));
3848
3849	pCtxCore->eflags.u32 \|= X86_EFL_IF; /* paranoia */
3850
3851	pVCpu->cpum.s.fRawEntered = true;
3852	return VINF_SUCCESS;
3853	}
3854
3855
3856	/**
3857	* Transforms the guest CPU state from raw-ring mode to correct values.
3858	*
3859	* This function will change any selector registers with DPL=1 to DPL=0.
3860	*
3861	* @returns Adjusted rc.
3862	* @param pVCpu The VMCPU handle.
3863	* @param rc Raw mode return code
3864	* @param pCtxCore The context core (for trap usage).
3865	* @see @ref pg_raw
3866	*/
3867	VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
3868	{
3869	PVM pVM = pVCpu->CTX_SUFF(pVM);
3870
3871	/*
3872	* Don't leave if we've already left (in GC).
3873	*/
3874	Assert(pVCpu->cpum.s.fRawEntered);
3875	Assert(!pVCpu->cpum.s.fRemEntered);
3876	if (!pVCpu->cpum.s.fRawEntered)
3877	return rc;
3878	pVCpu->cpum.s.fRawEntered = false;
3879
3880	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3881	if (!pCtxCore)
3882	pCtxCore = CPUMCTX2CORE(pCtx);
3883	Assert(pCtxCore->eflags.Bits.u1VM \|\| (pCtxCore->ss & X86_SEL_RPL));
3884	AssertMsg(pCtxCore->eflags.Bits.u1VM \|\| pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
3885	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3886
3887	/*
3888	* Are we executing in raw ring-1?
3889	*/
3890	if ( (pCtxCore->ss & X86_SEL_RPL) == 1
3891	&& !pCtxCore->eflags.Bits.u1VM)
3892	{
3893	/*
3894	* Leave execution mode.
3895	*/
3896	PATMRawLeave(pVM, pCtxCore, rc);
3897	/* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
3898	/** @todo See what happens if we remove this. */
3899	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3900	pCtxCore->ds &= ~X86_SEL_RPL;
3901	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3902	pCtxCore->es &= ~X86_SEL_RPL;
3903	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3904	pCtxCore->fs &= ~X86_SEL_RPL;
3905	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3906	pCtxCore->gs &= ~X86_SEL_RPL;
3907
3908	/*
3909	* Ring-1 selector => Ring-0.
3910	*/
3911	pCtxCore->ss &= ~X86_SEL_RPL;
3912	if ((pCtxCore->cs & X86_SEL_RPL) == 1)
3913	pCtxCore->cs &= ~X86_SEL_RPL;
3914	}
3915	else
3916	{
3917	/*
3918	* PATM is taking care of the IOPL and IF flags for us.
3919	*/
3920	PATMRawLeave(pVM, pCtxCore, rc);
3921	if (!pCtxCore->eflags.Bits.u1VM)
3922	{
3923	/** @todo See what happens if we remove this. */
3924	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3925	pCtxCore->ds &= ~X86_SEL_RPL;
3926	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3927	pCtxCore->es &= ~X86_SEL_RPL;
3928	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3929	pCtxCore->fs &= ~X86_SEL_RPL;
3930	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3931	pCtxCore->gs &= ~X86_SEL_RPL;
3932	}
3933	}
3934
3935	return rc;
3936	}
3937
3938
3939	/**
3940	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3941	*
3942	* Only REM should ever call this function!
3943	*
3944	* @returns The changed flags.
3945	* @param pVCpu The VMCPU handle.
3946	* @param puCpl Where to return the current privilege level (CPL).
3947	*/
3948	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3949	{
3950	Assert(!pVCpu->cpum.s.fRawEntered);
3951	Assert(!pVCpu->cpum.s.fRemEntered);
3952
3953	/*
3954	* Get the CPL first.
3955	*/
3956	*puCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
3957
3958	/*
3959	* Get and reset the flags, leaving CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID set.
3960	*/
3961	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3962	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* leave it set */
3963
3964	/** @todo change the switcher to use the fChanged flags. */
3965	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3966	{
3967	fFlags \|= CPUM_CHANGED_FPU_REM;
3968	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3969	}
3970
3971	pVCpu->cpum.s.fRemEntered = true;
3972	return fFlags;
3973	}
3974
3975
3976	/**
3977	* Leaves REM and works the CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID flag.
3978	*
3979	* @param pVCpu The virtual CPU handle.
3980	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3981	* registers.
3982	*/
3983	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3984	{
3985	Assert(!pVCpu->cpum.s.fRawEntered);
3986	Assert(pVCpu->cpum.s.fRemEntered);
3987
3988	if (fNoOutOfSyncSels)
3989	pVCpu->cpum.s.fChanged &= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3990	else
3991	pVCpu->cpum.s.fChanged \|= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3992
3993	pVCpu->cpum.s.fRemEntered = false;
3994	}
3995

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 30978

Download in other formats: