CPUM.cpp@ 31879

Last change on this file since 31879 was 31395, checked in by vboxsync, 14 years ago
CPUM.cpp: Added /CPUM/EnableNX config option, defaults to false. Useful for raw-mode where we don't normally enable NXE.
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File size: 187.9 KB

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1	/* $Id: CPUM.cpp 31395 2010-08-05 12:15:00Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers accross world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*/
33
34	/*******************************************************************************
35	* Header Files *
36	*******************************************************************************/
37	#define LOG_GROUP LOG_GROUP_CPUM
38	#include <VBox/cpum.h>
39	#include <VBox/cpumdis.h>
40	#include <VBox/pgm.h>
41	#include <VBox/mm.h>
42	#include <VBox/selm.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/patm.h>
45	#include <VBox/hwaccm.h>
46	#include <VBox/ssm.h>
47	#include "CPUMInternal.h"
48	#include <VBox/vm.h>
49
50	#include <VBox/param.h>
51	#include <VBox/dis.h>
52	#include <VBox/err.h>
53	#include <VBox/log.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm-amd64-x86.h>
56	#include <iprt/string.h>
57	#include <iprt/mp.h>
58	#include <iprt/cpuset.h>
59	#include <include/internal/pgm.h>
60
61	/*******************************************************************************
62	* Defined Constants And Macros *
63	*******************************************************************************/
64	/** The current saved state version. */
65	#define CPUM_SAVED_STATE_VERSION 12
66	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
67	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
68	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
69	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
70	* changes. */
71	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
72	/** The saved state version for the 2.1 trunk before the MSR changes. */
73	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
74	/** The saved state version of 2.0, used for backwards compatibility. */
75	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
76	/** The saved state version of 1.6, used for backwards compatability. */
77	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
78
79
80	/*******************************************************************************
81	* Structures and Typedefs *
82	*******************************************************************************/
83
84	/**
85	* What kind of cpu info dump to perform.
86	*/
87	typedef enum CPUMDUMPTYPE
88	{
89	CPUMDUMPTYPE_TERSE,
90	CPUMDUMPTYPE_DEFAULT,
91	CPUMDUMPTYPE_VERBOSE
92	} CPUMDUMPTYPE;
93	/** Pointer to a cpu info dump type. */
94	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97	/*******************************************************************************
98	* Internal Functions *
99	*******************************************************************************/
100	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
101	static int cpumR3CpuIdInit(PVM pVM);
102	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
103	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
104	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
106	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
107	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113
114
115	/**
116	* Initializes the CPUM.
117	*
118	* @returns VBox status code.
119	* @param pVM The VM to operate on.
120	*/
121	VMMR3DECL(int) CPUMR3Init(PVM pVM)
122	{
123	LogFlow(("CPUMR3Init\n"));
124
125	/*
126	* Assert alignment and sizes.
127	*/
128	AssertCompileMemberAlignment(VM, cpum.s, 32);
129	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
130	AssertCompileSizeAlignment(CPUMCTX, 64);
131	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
132	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
133	AssertCompileMemberAlignment(VM, cpum, 64);
134	AssertCompileMemberAlignment(VM, aCpus, 64);
135	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
136	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
137
138	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
139	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
140	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
141
142	/* Calculate the offset from CPUMCPU to CPUM. */
143	for (VMCPUID i = 0; i < pVM->cCpus; i++)
144	{
145	PVMCPU pVCpu = &pVM->aCpus[i];
146
147	/*
148	* Setup any fixed pointers and offsets.
149	*/
150	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
151	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
152
153	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
154	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
155	}
156
157	/*
158	* Check that the CPU supports the minimum features we require.
159	*/
160	if (!ASMHasCpuId())
161	{
162	Log(("The CPU doesn't support CPUID!\n"));
163	return VERR_UNSUPPORTED_CPU;
164	}
165	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
166	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
167
168	/* Setup the CR4 AND and OR masks used in the switcher */
169	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
170	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
171	{
172	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
173	/* No FXSAVE implies no SSE */
174	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
175	pVM->cpum.s.CR4.OrMask = 0;
176	}
177	else
178	{
179	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
180	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
181	}
182
183	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
184	{
185	Log(("The CPU doesn't support MMX!\n"));
186	return VERR_UNSUPPORTED_CPU;
187	}
188	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
189	{
190	Log(("The CPU doesn't support TSC!\n"));
191	return VERR_UNSUPPORTED_CPU;
192	}
193	/* Bogus on AMD? */
194	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
195	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
196
197	/*
198	* Detech the host CPU vendor.
199	* (The guest CPU vendor is re-detected later on.)
200	*/
201	uint32_t uEAX, uEBX, uECX, uEDX;
202	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
203	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
204	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
205
206	/*
207	* Setup hypervisor startup values.
208	*/
209
210	/*
211	* Register saved state data item.
212	*/
213	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
214	NULL, cpumR3LiveExec, NULL,
215	NULL, cpumR3SaveExec, NULL,
216	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
217	if (RT_FAILURE(rc))
218	return rc;
219
220	/*
221	* Register info handlers.
222	*/
223	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
224	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
225	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
227	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
228	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
229
230	/*
231	* Initialize the Guest CPUID state.
232	*/
233	rc = cpumR3CpuIdInit(pVM);
234	if (RT_FAILURE(rc))
235	return rc;
236	CPUMR3Reset(pVM);
237	return VINF_SUCCESS;
238	}
239
240
241	/**
242	* Initializes the per-VCPU CPUM.
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
248	{
249	LogFlow(("CPUMR3InitCPU\n"));
250	return VINF_SUCCESS;
251	}
252
253
254	/**
255	* Detect the CPU vendor give n the
256	*
257	* @returns The vendor.
258	* @param uEAX EAX from CPUID(0).
259	* @param uEBX EBX from CPUID(0).
260	* @param uECX ECX from CPUID(0).
261	* @param uEDX EDX from CPUID(0).
262	*/
263	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
264	{
265	if ( uEAX >= 1
266	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
267	&& uECX == X86_CPUID_VENDOR_AMD_ECX
268	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
269	return CPUMCPUVENDOR_AMD;
270
271	if ( uEAX >= 1
272	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
273	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
274	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
275	return CPUMCPUVENDOR_INTEL;
276
277	/** @todo detect the other buggers... */
278	return CPUMCPUVENDOR_UNKNOWN;
279	}
280
281
282	/**
283	* Fetches overrides for a CPUID leaf.
284	*
285	* @returns VBox status code.
286	* @param pLeaf The leaf to load the overrides into.
287	* @param pCfgNode The CFGM node containing the overrides
288	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
289	* @param iLeaf The CPUID leaf number.
290	*/
291	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
292	{
293	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
294	if (pLeafNode)
295	{
296	uint32_t u32;
297	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
298	if (RT_SUCCESS(rc))
299	pLeaf->eax = u32;
300	else
301	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
302
303	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
304	if (RT_SUCCESS(rc))
305	pLeaf->ebx = u32;
306	else
307	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
308
309	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
310	if (RT_SUCCESS(rc))
311	pLeaf->ecx = u32;
312	else
313	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
314
315	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
316	if (RT_SUCCESS(rc))
317	pLeaf->edx = u32;
318	else
319	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
320
321	}
322	return VINF_SUCCESS;
323	}
324
325
326	/**
327	* Load the overrides for a set of CPUID leaves.
328	*
329	* @returns VBox status code.
330	* @param paLeaves The leaf array.
331	* @param cLeaves The number of leaves.
332	* @param uStart The start leaf number.
333	* @param pCfgNode The CFGM node containing the overrides
334	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
335	*/
336	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
337	{
338	for (uint32_t i = 0; i < cLeaves; i++)
339	{
340	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
341	if (RT_FAILURE(rc))
342	return rc;
343	}
344
345	return VINF_SUCCESS;
346	}
347
348	/**
349	* Init a set of host CPUID leaves.
350	*
351	* @returns VBox status code.
352	* @param paLeaves The leaf array.
353	* @param cLeaves The number of leaves.
354	* @param uStart The start leaf number.
355	* @param pCfgNode The /CPUM/HostCPUID/ node.
356	*/
357	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
358	{
359	/* Using the ECX variant for all of them can't hurt... */
360	for (uint32_t i = 0; i < cLeaves; i++)
361	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
362
363	/* Load CPUID leaf override; we currently don't care if the user
364	specifies features the host CPU doesn't support. */
365	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
366	}
367
368
369	/**
370	* Initializes the emulated CPU's cpuid information.
371	*
372	* @returns VBox status code.
373	* @param pVM The VM to operate on.
374	*/
375	static int cpumR3CpuIdInit(PVM pVM)
376	{
377	PCPUM pCPUM = &pVM->cpum.s;
378	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
379	uint32_t i;
380	int rc;
381
382	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
383	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
384	{ \
385	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
386	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
387	}
388	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
389	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
390	{ \
391	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
392	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
393	}
394
395	/*
396	* Read the configuration.
397	*/
398	/** @cfgm{CPUM/SyntheticCpu, boolean, false}
399	* Enables the Synthetic CPU. The Vendor ID and Processor Name are
400	* completely overridden by VirtualBox custom strings. Some
401	* CPUID information is withheld, like the cache info. */
402	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
403	AssertRCReturn(rc, rc);
404
405	/** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
406	* When non-zero CPUID features that could cause portability issues will be
407	* stripped. The higher the value the more features gets stripped. Higher
408	* values should only be used when older CPUs are involved since it may
409	* harm performance and maybe also cause problems with specific guests. */
410	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
411	AssertRCReturn(rc, rc);
412
413	AssertLogRelReturn(!pCPUM->fSyntheticCpu \|\| !pCPUM->u8PortableCpuIdLevel, VERR_INTERNAL_ERROR_2);
414
415	/*
416	* Get the host CPUID leaves and redetect the guest CPU vendor (could've
417	* been overridden).
418	*/
419	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
420	* Overrides the host CPUID leaf values used for calculating the guest CPUID
421	* leaves. This can be used to preserve the CPUID values when moving a VM
422	* to a different machine. Another use is restricting (or extending) the
423	* feature set exposed to the guest. */
424	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
425	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
426	AssertRCReturn(rc, rc);
427	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
428	AssertRCReturn(rc, rc);
429	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
430	AssertRCReturn(rc, rc);
431
432	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
433	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
434
435	/*
436	* Determine the default leaf.
437	*
438	* Intel returns values of the highest standard function, while AMD
439	* returns zeros. VIA on the other hand seems to returning nothing or
440	* perhaps some random garbage, we don't try to duplicate this behavior.
441	*/
442	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
443	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
444	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
445
446
447	/* Cpuid 1 & 0x80000001:
448	* Only report features we can support.
449	*
450	* Note! When enabling new features the Synthetic CPU and Portable CPUID
451	* options may require adjusting (i.e. stripping what was enabled).
452	*/
453	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
454	\| X86_CPUID_FEATURE_EDX_VME
455	\| X86_CPUID_FEATURE_EDX_DE
456	\| X86_CPUID_FEATURE_EDX_PSE
457	\| X86_CPUID_FEATURE_EDX_TSC
458	\| X86_CPUID_FEATURE_EDX_MSR
459	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
460	\| X86_CPUID_FEATURE_EDX_MCE
461	\| X86_CPUID_FEATURE_EDX_CX8
462	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
463	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
464	//\| X86_CPUID_FEATURE_EDX_SEP
465	\| X86_CPUID_FEATURE_EDX_MTRR
466	\| X86_CPUID_FEATURE_EDX_PGE
467	\| X86_CPUID_FEATURE_EDX_MCA
468	\| X86_CPUID_FEATURE_EDX_CMOV
469	\| X86_CPUID_FEATURE_EDX_PAT
470	\| X86_CPUID_FEATURE_EDX_PSE36
471	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
472	\| X86_CPUID_FEATURE_EDX_CLFSH
473	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
474	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
475	\| X86_CPUID_FEATURE_EDX_MMX
476	\| X86_CPUID_FEATURE_EDX_FXSR
477	\| X86_CPUID_FEATURE_EDX_SSE
478	\| X86_CPUID_FEATURE_EDX_SSE2
479	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
480	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
481	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
482	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
483	\| 0;
484	pCPUM->aGuestCpuIdStd[1].ecx &= 0
485	\| X86_CPUID_FEATURE_ECX_SSE3
486	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
487	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
488	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
489	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
490	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
491	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
492	\| X86_CPUID_FEATURE_ECX_SSSE3
493	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
494	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
495	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
496	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
497	/* ECX Bit 21 - x2APIC support - not yet. */
498	// \| X86_CPUID_FEATURE_ECX_X2APIC
499	/* ECX Bit 23 - POPCNT instruction. */
500	//\| X86_CPUID_FEATURE_ECX_POPCNT
501	\| 0;
502	if (pCPUM->u8PortableCpuIdLevel > 0)
503	{
504	PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
505	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
506	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
507	PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
508	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
509	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
510	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
511
512	Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
513	\| X86_CPUID_FEATURE_EDX_PSN
514	\| X86_CPUID_FEATURE_EDX_DS
515	\| X86_CPUID_FEATURE_EDX_ACPI
516	\| X86_CPUID_FEATURE_EDX_SS
517	\| X86_CPUID_FEATURE_EDX_TM
518	\| X86_CPUID_FEATURE_EDX_PBE
519	)));
520	Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
521	\| X86_CPUID_FEATURE_ECX_DTES64
522	\| X86_CPUID_FEATURE_ECX_CPLDS
523	\| X86_CPUID_FEATURE_ECX_VMX
524	\| X86_CPUID_FEATURE_ECX_SMX
525	\| X86_CPUID_FEATURE_ECX_EST
526	\| X86_CPUID_FEATURE_ECX_TM2
527	\| X86_CPUID_FEATURE_ECX_CNTXID
528	\| X86_CPUID_FEATURE_ECX_FMA
529	\| X86_CPUID_FEATURE_ECX_CX16
530	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
531	\| X86_CPUID_FEATURE_ECX_PDCM
532	\| X86_CPUID_FEATURE_ECX_DCA
533	\| X86_CPUID_FEATURE_ECX_MOVBE
534	\| X86_CPUID_FEATURE_ECX_AES
535	\| X86_CPUID_FEATURE_ECX_POPCNT
536	\| X86_CPUID_FEATURE_ECX_XSAVE
537	\| X86_CPUID_FEATURE_ECX_OSXSAVE
538	\| X86_CPUID_FEATURE_ECX_AVX
539	)));
540	}
541
542	/* Cpuid 0x80000001:
543	* Only report features we can support.
544	*
545	* Note! When enabling new features the Synthetic CPU and Portable CPUID
546	* options may require adjusting (i.e. stripping what was enabled).
547	*
548	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
549	*/
550	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
551	\| X86_CPUID_AMD_FEATURE_EDX_VME
552	\| X86_CPUID_AMD_FEATURE_EDX_DE
553	\| X86_CPUID_AMD_FEATURE_EDX_PSE
554	\| X86_CPUID_AMD_FEATURE_EDX_TSC
555	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
556	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
557	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
558	\| X86_CPUID_AMD_FEATURE_EDX_CX8
559	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
560	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
561	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
562	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
563	\| X86_CPUID_AMD_FEATURE_EDX_PGE
564	\| X86_CPUID_AMD_FEATURE_EDX_MCA
565	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
566	\| X86_CPUID_AMD_FEATURE_EDX_PAT
567	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
568	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
569	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
570	\| X86_CPUID_AMD_FEATURE_EDX_MMX
571	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
572	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
573	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
574	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
575	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
576	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
577	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
578	\| 0;
579	pCPUM->aGuestCpuIdExt[1].ecx &= 0
580	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
581	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
582	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
583	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
584	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
585	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
586	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
587	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
588	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
589	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
590	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
591	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
592	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
593	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
594	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
595	\| 0;
596	if (pCPUM->u8PortableCpuIdLevel > 0)
597	{
598	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
599	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
600	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
601	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
602	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
603	PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
604	PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
605
606	Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
607	\| X86_CPUID_AMD_FEATURE_ECX_SVM
608	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
609	\| X86_CPUID_AMD_FEATURE_ECX_CR8L
610	\| X86_CPUID_AMD_FEATURE_ECX_ABM
611	\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
612	\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
613	\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
614	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
615	\| X86_CPUID_AMD_FEATURE_ECX_IBS
616	\| X86_CPUID_AMD_FEATURE_ECX_SSE5
617	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
618	\| X86_CPUID_AMD_FEATURE_ECX_WDT
619	\| UINT32_C(0xffffc000)
620	)));
621	Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
622	\| X86_CPUID_AMD_FEATURE_EDX_SEP
623	\| RT_BIT(18)
624	\| RT_BIT(19)
625	\| RT_BIT(21)
626	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
627	\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
628	\| RT_BIT(28)
629	)));
630	}
631
632	/*
633	* Apply the Synthetic CPU modifications. (TODO: move this up)
634	*/
635	if (pCPUM->fSyntheticCpu)
636	{
637	static const char s_szVendor[13] = "VirtualBox ";
638	static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
639
640	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
641
642	/* Limit the nr of standard leaves; 5 for monitor/mwait */
643	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
644
645	/* 0: Vendor */
646	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
647	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
648	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
649
650	/* 1.eax: Version information. family : model : stepping */
651	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
652
653	/* Leaves 2 - 4 are Intel only - zero them out */
654	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
655	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
656	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
657
658	/* Leaf 5 = monitor/mwait */
659
660	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
661	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
662	/* AMD only - set to zero. */
663	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
664
665	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
666	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
667
668	/* 0x800000002-4: Processor Name String Identifier. */
669	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
670	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
671	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
672	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
673	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
674	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
675	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
676	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
677	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
678	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
679	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
680	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
681
682	/* 0x800000005-7 - reserved -> zero */
683	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
684	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
685	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
686
687	/* 0x800000008: only the max virtual and physical address size. */
688	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
689	}
690
691	/*
692	* Hide HTT, multicode, SMP, whatever.
693	* (APIC-ID := 0 and #LogCpus := 0)
694	*/
695	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
696	#ifdef VBOX_WITH_MULTI_CORE
697	if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
698	&& pVM->cCpus > 1)
699	{
700	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
701	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
702	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
703	}
704	#endif
705
706	/* Cpuid 2:
707	* Intel: Cache and TLB information
708	* AMD: Reserved
709	* Safe to expose; restrict the number of calls to 1 for the portable case.
710	*/
711	if ( pCPUM->u8PortableCpuIdLevel > 0
712	&& pCPUM->aGuestCpuIdStd[0].eax >= 2
713	&& (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
714	{
715	LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
716	pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
717	}
718
719	/* Cpuid 3:
720	* Intel: EAX, EBX - reserved (transmeta uses these)
721	* ECX, EDX - Processor Serial Number if available, otherwise reserved
722	* AMD: Reserved
723	* Safe to expose
724	*/
725	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
726	{
727	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
728	if (pCPUM->u8PortableCpuIdLevel > 0)
729	pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
730	}
731
732	/* Cpuid 4:
733	* Intel: Deterministic Cache Parameters Leaf
734	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
735	* AMD: Reserved
736	* Safe to expose, except for EAX:
737	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
738	* Bits 31-26: Maximum number of processor cores in this physical package**
739	* Note: These SMP values are constant regardless of ECX
740	*/
741	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
742	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
743	#ifdef VBOX_WITH_MULTI_CORE
744	if ( pVM->cCpus > 1
745	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
746	{
747	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
748	/* One logical processor with possibly multiple cores. */
749	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
750	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
751	}
752	#endif
753
754	/* Cpuid 5: Monitor/mwait Leaf
755	* Intel: ECX, EDX - reserved
756	* EAX, EBX - Smallest and largest monitor line size
757	* AMD: EDX - reserved
758	* EAX, EBX - Smallest and largest monitor line size
759	* ECX - extensions (ignored for now)
760	* Safe to expose
761	*/
762	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
763	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
764
765	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
766	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
767	* Expose MWAIT extended features to the guest. For now we expose
768	* just MWAIT break on interrupt feature (bit 1).
769	*/
770	bool fMWaitExtensions;
771	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
772	if (fMWaitExtensions)
773	{
774	pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
775	/* @todo: for now we just expose host's MWAIT C-states, although conceptually
776	it shall be part of our power management virtualization model */
777	#if 0
778	/* MWAIT sub C-states */
779	pCPUM->aGuestCpuIdStd[5].edx =
780	(0 << 0) /* 0 in C0 */ \|
781	(2 << 4) /* 2 in C1 */ \|
782	(2 << 8) /* 2 in C2 */ \|
783	(2 << 12) /* 2 in C3 */ \|
784	(0 << 16) /* 0 in C4 */
785	;
786	#endif
787	}
788	else
789	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
790
791	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
792	* Safe to pass on to the guest.
793	*
794	* Intel: 0x800000005 reserved
795	* 0x800000006 L2 cache information
796	* AMD: 0x800000005 L1 cache information
797	* 0x800000006 L2/L3 cache information
798	*/
799
800	/* Cpuid 0x800000007:
801	* AMD: EAX, EBX, ECX - reserved
802	* EDX: Advanced Power Management Information
803	* Intel: Reserved
804	*/
805	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
806	{
807	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
808
809	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
810
811	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
812	{
813	/* Only expose the TSC invariant capability bit to the guest. */
814	pCPUM->aGuestCpuIdExt[7].edx &= 0
815	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
816	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
817	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
818	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
819	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
820	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
821	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
822	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
823	#if 0 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
824	* Linux kernels blindly assume that the AMD performance counters work
825	* if this is set for 64 bits guests. (Can't really find a CPUID feature
826	* bit for them though.) */
827	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
828	#endif
829	\| 0;
830	}
831	else
832	pCPUM->aGuestCpuIdExt[7].edx = 0;
833	}
834
835	/* Cpuid 0x800000008:
836	* AMD: EBX, EDX - reserved
837	* EAX: Virtual/Physical/Guest address Size
838	* ECX: Number of cores + APICIdCoreIdSize
839	* Intel: EAX: Virtual/Physical address Size
840	* EBX, ECX, EDX - reserved
841	*/
842	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
843	{
844	/* Only expose the virtual and physical address sizes to the guest. */
845	pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
846	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
847	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
848	* NC (0-7) Number of cores; 0 equals 1 core */
849	pCPUM->aGuestCpuIdExt[8].ecx = 0;
850	#ifdef VBOX_WITH_MULTI_CORE
851	if ( pVM->cCpus > 1
852	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
853	{
854	/* Legacy method to determine the number of cores. */
855	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
856	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
857	}
858	#endif
859	}
860
861	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
862	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
863	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
864	* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
865	*/
866	bool fNt4LeafLimit;
867	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
868	if (fNt4LeafLimit)
869	pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
870
871	/*
872	* Limit it the number of entries and fill the remaining with the defaults.
873	*
874	* The limits are masking off stuff about power saving and similar, this
875	* is perhaps a bit crudely done as there is probably some relatively harmless
876	* info too in these leaves (like words about having a constant TSC).
877	*/
878	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
879	pCPUM->aGuestCpuIdStd[0].eax = 5;
880	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
881	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
882
883	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
884	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
885	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
886	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
887	: 0;
888	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
889	i++)
890	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
891
892	/*
893	* Centaur stuff (VIA).
894	*
895	* The important part here (we think) is to make sure the 0xc0000000
896	* function returns 0xc0000001. As for the features, we don't currently
897	* let on about any of those... 0xc0000002 seems to be some
898	* temperature/hz/++ stuff, include it as well (static).
899	*/
900	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
901	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
902	{
903	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
904	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
905	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
906	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
907	i++)
908	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
909	}
910	else
911	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
912	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
913
914
915	/*
916	* Load CPUID overrides from configuration.
917	* Note: Kind of redundant now, but allows unchanged overrides
918	*/
919	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
920	* Overrides the CPUID leaf values. */
921	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
922	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
923	AssertRCReturn(rc, rc);
924	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
925	AssertRCReturn(rc, rc);
926	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
927	AssertRCReturn(rc, rc);
928
929	/*
930	* Check if PAE was explicitely enabled by the user.
931	*/
932	bool fEnable;
933	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
934	if (fEnable)
935	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
936
937	/*
938	* We don't normally enable NX for raw-mode, so give the user a chance to
939	* force it on.
940	*/
941	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
942	if (fEnable)
943	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
944
945	/*
946	* Log the cpuid and we're good.
947	*/
948	RTCPUSET OnlineSet;
949	LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
950	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
951	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
952	LogRel(("*********************** CPUID dump **********************\n"));
953	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
954	LogRel(("\n"));
955	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
956	LogRel(("****************** End of CPUID dump ********************\n"));
957
958	#undef PORTABLE_DISABLE_FEATURE_BIT
959	#undef PORTABLE_CLEAR_BITS_WHEN
960
961	return VINF_SUCCESS;
962	}
963
964
965	/**
966	* Applies relocations to data and code managed by this
967	* component. This function will be called at init and
968	* whenever the VMM need to relocate it self inside the GC.
969	*
970	* The CPUM will update the addresses used by the switcher.
971	*
972	* @param pVM The VM.
973	*/
974	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
975	{
976	LogFlow(("CPUMR3Relocate\n"));
977	for (VMCPUID i = 0; i < pVM->cCpus; i++)
978	{
979	/*
980	* Switcher pointers.
981	*/
982	PVMCPU pVCpu = &pVM->aCpus[i];
983	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
984	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
985
986	}
987	}
988
989
990	/**
991	* Apply late CPUM property changes based on the fHWVirtEx setting
992	*
993	* @param pVM The VM to operate on.
994	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
995	*/
996	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
997	{
998	/*
999	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1000	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1001	* of processors from (cpuid(4).eax >> 26) + 1.
1002	*
1003	* Note: this code is obsolete, but let's keep it here for reference.
1004	* Purpose is valid when we artifically cap the max std id to less than 4.
1005	*/
1006	if (!fHWVirtExEnabled)
1007	{
1008	Assert(pVM->cpum.s.aGuestCpuIdStd[4].eax == 0);
1009	pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1010	}
1011	}
1012
1013	/**
1014	* Terminates the CPUM.
1015	*
1016	* Termination means cleaning up and freeing all resources,
1017	* the VM it self is at this point powered off or suspended.
1018	*
1019	* @returns VBox status code.
1020	* @param pVM The VM to operate on.
1021	*/
1022	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1023	{
1024	CPUMR3TermCPU(pVM);
1025	return 0;
1026	}
1027
1028
1029	/**
1030	* Terminates the per-VCPU CPUM.
1031	*
1032	* Termination means cleaning up and freeing all resources,
1033	* the VM it self is at this point powered off or suspended.
1034	*
1035	* @returns VBox status code.
1036	* @param pVM The VM to operate on.
1037	*/
1038	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
1039	{
1040	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1041	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1042	{
1043	PVMCPU pVCpu = &pVM->aCpus[i];
1044	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1045
1046	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1047	pVCpu->cpum.s.uMagic = 0;
1048	pCtx->dr[5] = 0;
1049	}
1050	#endif
1051	return 0;
1052	}
1053
1054
1055	/**
1056	* Resets a virtual CPU.
1057	*
1058	* Used by CPUMR3Reset and CPU hot plugging.
1059	*
1060	* @param pVCpu The virtual CPU handle.
1061	*/
1062	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1063	{
1064	/** @todo anything different for VCPU > 0? */
1065	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1066
1067	/*
1068	* Initialize everything to ZERO first.
1069	*/
1070	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1071	memset(pCtx, 0, sizeof(*pCtx));
1072	pVCpu->cpum.s.fUseFlags = fUseFlags;
1073
1074	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1075	pCtx->eip = 0x0000fff0;
1076	pCtx->edx = 0x00000600; /* P6 processor */
1077	pCtx->eflags.Bits.u1Reserved0 = 1;
1078
1079	pCtx->cs = 0xf000;
1080	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
1081	pCtx->csHid.u32Limit = 0x0000ffff;
1082	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
1083	pCtx->csHid.Attr.n.u1Present = 1;
1084	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
1085
1086	pCtx->dsHid.u32Limit = 0x0000ffff;
1087	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
1088	pCtx->dsHid.Attr.n.u1Present = 1;
1089	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1090
1091	pCtx->esHid.u32Limit = 0x0000ffff;
1092	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
1093	pCtx->esHid.Attr.n.u1Present = 1;
1094	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1095
1096	pCtx->fsHid.u32Limit = 0x0000ffff;
1097	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
1098	pCtx->fsHid.Attr.n.u1Present = 1;
1099	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1100
1101	pCtx->gsHid.u32Limit = 0x0000ffff;
1102	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
1103	pCtx->gsHid.Attr.n.u1Present = 1;
1104	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1105
1106	pCtx->ssHid.u32Limit = 0x0000ffff;
1107	pCtx->ssHid.Attr.n.u1Present = 1;
1108	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
1109	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1110
1111	pCtx->idtr.cbIdt = 0xffff;
1112	pCtx->gdtr.cbGdt = 0xffff;
1113
1114	pCtx->ldtrHid.u32Limit = 0xffff;
1115	pCtx->ldtrHid.Attr.n.u1Present = 1;
1116	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1117
1118	pCtx->trHid.u32Limit = 0xffff;
1119	pCtx->trHid.Attr.n.u1Present = 1;
1120	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
1121
1122	pCtx->dr[6] = X86_DR6_INIT_VAL;
1123	pCtx->dr[7] = X86_DR7_INIT_VAL;
1124
1125	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
1126	pCtx->fpu.FCW = 0x37f;
1127
1128	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
1129	pCtx->fpu.MXCSR = 0x1F80;
1130
1131	/* Init PAT MSR */
1132	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1133
1134	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1135	* The Intel docs don't mention it.
1136	*/
1137	pCtx->msrEFER = 0;
1138	}
1139
1140
1141	/**
1142	* Resets the CPU.
1143	*
1144	* @returns VINF_SUCCESS.
1145	* @param pVM The VM handle.
1146	*/
1147	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1148	{
1149	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1150	{
1151	CPUMR3ResetCpu(&pVM->aCpus[i]);
1152
1153	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1154	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1155
1156	/* Magic marker for searching in crash dumps. */
1157	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1158	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1159	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1160	#endif
1161	}
1162	}
1163
1164
1165	/**
1166	* Called both in pass 0 and the final pass.
1167	*
1168	* @param pVM The VM handle.
1169	* @param pSSM The saved state handle.
1170	*/
1171	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1172	{
1173	/*
1174	* Save all the CPU ID leaves here so we can check them for compatability
1175	* upon loading.
1176	*/
1177	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1178	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1179
1180	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1181	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1182
1183	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1184	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1185
1186	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1187
1188	/*
1189	* Save a good portion of the raw CPU IDs as well as they may come in
1190	* handy when validating features for raw mode.
1191	*/
1192	CPUMCPUID aRawStd[16];
1193	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1194	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1195	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1196	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1197
1198	CPUMCPUID aRawExt[32];
1199	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1200	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1201	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1202	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1203	}
1204
1205
1206	/**
1207	* Loads the CPU ID leaves saved by pass 0.
1208	*
1209	* @returns VBox status code.
1210	* @param pVM The VM handle.
1211	* @param pSSM The saved state handle.
1212	* @param uVersion The format version.
1213	*/
1214	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1215	{
1216	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1217
1218	/*
1219	* Define a bunch of macros for simplifying the code.
1220	*/
1221	/* Generic expression + failure message. */
1222	#define CPUID_CHECK_RET(expr, fmt) \
1223	do { \
1224	if (!(expr)) \
1225	{ \
1226	char pszMsg = RTStrAPrintf2 fmt; / lack of variadict macros sucks */ \
1227	if (fStrictCpuIdChecks) \
1228	{ \
1229	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1230	RTStrFree(pszMsg); \
1231	return rcCpuid; \
1232	} \
1233	LogRel(("CPUM: %s\n", pszMsg)); \
1234	RTStrFree(pszMsg); \
1235	} \
1236	} while (0)
1237	#define CPUID_CHECK_WRN(expr, fmt) \
1238	do { \
1239	if (!(expr)) \
1240	LogRel(fmt); \
1241	} while (0)
1242
1243	/* For comparing two values and bitch if they differs. */
1244	#define CPUID_CHECK2_RET(what, host, saved) \
1245	do { \
1246	if ((host) != (saved)) \
1247	{ \
1248	if (fStrictCpuIdChecks) \
1249	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1250	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1251	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1252	} \
1253	} while (0)
1254	#define CPUID_CHECK2_WRN(what, host, saved) \
1255	do { \
1256	if ((host) != (saved)) \
1257	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1258	} while (0)
1259
1260	/* For checking raw cpu features (raw mode). */
1261	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1262	do { \
1263	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1264	{ \
1265	if (fStrictCpuIdChecks) \
1266	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1267	N_(#bit " mismatch: host=%d saved=%d"), \
1268	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1269	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1270	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1271	} \
1272	} while (0)
1273	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1274	do { \
1275	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1276	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1277	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1278	} while (0)
1279	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1280
1281	/* For checking guest features. */
1282	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1283	do { \
1284	if ( (aGuestCpuId##set [1].reg & bit) \
1285	&& !(aHostRaw##set [1].reg & bit) \
1286	&& !(aHostOverride##set [1].reg & bit) \
1287	&& !(aGuestOverride##set [1].reg & bit) \
1288	) \
1289	{ \
1290	if (fStrictCpuIdChecks) \
1291	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1292	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1293	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1294	} \
1295	} while (0)
1296	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1297	do { \
1298	if ( (aGuestCpuId##set [1].reg & bit) \
1299	&& !(aHostRaw##set [1].reg & bit) \
1300	&& !(aHostOverride##set [1].reg & bit) \
1301	&& !(aGuestOverride##set [1].reg & bit) \
1302	) \
1303	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1304	} while (0)
1305	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1306	do { \
1307	if ( (aGuestCpuId##set [1].reg & bit) \
1308	&& !(aHostRaw##set [1].reg & bit) \
1309	&& !(aHostOverride##set [1].reg & bit) \
1310	&& !(aGuestOverride##set [1].reg & bit) \
1311	) \
1312	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1313	} while (0)
1314	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1315
1316	/* For checking guest features if AMD guest CPU. */
1317	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1318	do { \
1319	if ( (aGuestCpuId##set [1].reg & bit) \
1320	&& fGuestAmd \
1321	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1322	&& !(aHostOverride##set [1].reg & bit) \
1323	&& !(aGuestOverride##set [1].reg & bit) \
1324	) \
1325	{ \
1326	if (fStrictCpuIdChecks) \
1327	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1328	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1329	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1330	} \
1331	} while (0)
1332	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1333	do { \
1334	if ( (aGuestCpuId##set [1].reg & bit) \
1335	&& fGuestAmd \
1336	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1337	&& !(aHostOverride##set [1].reg & bit) \
1338	&& !(aGuestOverride##set [1].reg & bit) \
1339	) \
1340	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1341	} while (0)
1342	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1343	do { \
1344	if ( (aGuestCpuId##set [1].reg & bit) \
1345	&& fGuestAmd \
1346	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1347	&& !(aHostOverride##set [1].reg & bit) \
1348	&& !(aGuestOverride##set [1].reg & bit) \
1349	) \
1350	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1351	} while (0)
1352	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1353
1354	/* For checking AMD features which have a corresponding bit in the standard
1355	range. (Intel defines very few bits in the extended feature sets.) */
1356	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1357	do { \
1358	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1359	&& !(fHostAmd \
1360	? aHostRawExt[1].reg & (ExtBit) \
1361	: aHostRawStd[1].reg & (StdBit)) \
1362	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1363	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1364	) \
1365	{ \
1366	if (fStrictCpuIdChecks) \
1367	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1368	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1369	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1370	} \
1371	} while (0)
1372	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1373	do { \
1374	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1375	&& !(fHostAmd \
1376	? aHostRawExt[1].reg & (ExtBit) \
1377	: aHostRawStd[1].reg & (StdBit)) \
1378	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1379	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1380	) \
1381	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1382	} while (0)
1383	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1384	do { \
1385	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1386	&& !(fHostAmd \
1387	? aHostRawExt[1].reg & (ExtBit) \
1388	: aHostRawStd[1].reg & (StdBit)) \
1389	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1390	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1391	) \
1392	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1393	} while (0)
1394	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1395
1396	/*
1397	* Load them into stack buffers first.
1398	*/
1399	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1400	uint32_t cGuestCpuIdStd;
1401	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1402	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1403	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1404	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1405
1406	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1407	uint32_t cGuestCpuIdExt;
1408	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1409	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1410	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1411	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1412
1413	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1414	uint32_t cGuestCpuIdCentaur;
1415	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1416	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1417	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1418	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1419
1420	CPUMCPUID GuestCpuIdDef;
1421	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1422	AssertRCReturn(rc, rc);
1423
1424	CPUMCPUID aRawStd[16];
1425	uint32_t cRawStd;
1426	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1427	if (cRawStd > RT_ELEMENTS(aRawStd))
1428	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1429	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1430
1431	CPUMCPUID aRawExt[32];
1432	uint32_t cRawExt;
1433	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1434	if (cRawExt > RT_ELEMENTS(aRawExt))
1435	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1436	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1437	AssertRCReturn(rc, rc);
1438
1439	/*
1440	* Note that we support restoring less than the current amount of standard
1441	* leaves because we've been allowed more is newer version of VBox.
1442	*
1443	* So, pad new entries with the default.
1444	*/
1445	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1446	aGuestCpuIdStd[i] = GuestCpuIdDef;
1447
1448	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1449	aGuestCpuIdExt[i] = GuestCpuIdDef;
1450
1451	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1452	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1453
1454	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1455	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1456
1457	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1458	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1459
1460	/*
1461	* Get the raw CPU IDs for the current host.
1462	*/
1463	CPUMCPUID aHostRawStd[16];
1464	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1465	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1466
1467	CPUMCPUID aHostRawExt[32];
1468	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1469	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1470
1471	/*
1472	* Get the host and guest overrides so we don't reject the state because
1473	* some feature was enabled thru these interfaces.
1474	* Note! We currently only need the feature leaves, so skip rest.
1475	*/
1476	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1477	CPUMCPUID aGuestOverrideStd[2];
1478	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1479	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1480
1481	CPUMCPUID aGuestOverrideExt[2];
1482	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1483	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1484
1485	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1486	CPUMCPUID aHostOverrideStd[2];
1487	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1488	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1489
1490	CPUMCPUID aHostOverrideExt[2];
1491	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1492	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1493
1494	/*
1495	* This can be skipped.
1496	*/
1497	bool fStrictCpuIdChecks;
1498	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1499
1500
1501
1502	/*
1503	* For raw-mode we'll require that the CPUs are very similar since we don't
1504	* intercept CPUID instructions for user mode applications.
1505	*/
1506	if (!HWACCMIsEnabled(pVM))
1507	{
1508	/* CPUID(0) */
1509	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1510	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1511	&& aHostRawStd[0].edx == aRawStd[0].edx,
1512	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1513	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1514	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1515	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1516	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1517	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1518
1519	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1520
1521	/* CPUID(1).eax */
1522	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1523	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1524	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1525
1526	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1527	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1528	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1529
1530	/* CPUID(1).ecx */
1531	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1532	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1533	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1534	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1535	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1536	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1537	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1538	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1539	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1540	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1541	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1542	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1543	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1544	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1545	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1546	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1547	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1548	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1549	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1550	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1551	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1552	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1553	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1554	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1555	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1556	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1557	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1558	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1559	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1560	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1561	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1562	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1563
1564	/* CPUID(1).edx */
1565	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1566	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1567	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1568	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1569	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1570	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1571	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1572	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1573	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1574	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1575	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1576	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1577	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1578	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1579	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1580	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1581	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1582	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1583	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1584	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1585	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1586	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1587	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1588	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1589	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1590	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1591	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1592	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1593	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1594	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1595	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1596	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1597
1598	/* CPUID(2) - config, mostly about caches. ignore. */
1599	/* CPUID(3) - processor serial number. ignore. */
1600	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1601	/* CPUID(5) - mwait/monitor config. ignore. */
1602	/* CPUID(6) - power management. ignore. */
1603	/* CPUID(7) - ???. ignore. */
1604	/* CPUID(8) - ???. ignore. */
1605	/* CPUID(9) - DCA. ignore for now. */
1606	/* CPUID(a) - PeMo info. ignore for now. */
1607	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1608
1609	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1610	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1611	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1612	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1613	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1614	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1615	{
1616	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1617	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1618	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1619	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1620	}
1621
1622	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1623	Note! Intel have/is marking many of the fields here as reserved. We
1624	will verify them as if it's an AMD CPU. */
1625	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1626	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1627	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
1628	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1629	{
1630	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1631	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1632	&& aHostRawExt[0].edx == aRawExt[0].edx,
1633	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1634	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1635	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1636	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1637
1638	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1639	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1640	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1641	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1642	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1643	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1644
1645	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1646	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1647	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1648	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1649
1650	/* CPUID(0x80000001).ecx */
1651	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1652	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1653	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1654	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1655	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1656	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1657	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1658	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1659	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1660	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1661	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1662	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1663	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1664	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1665	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1666	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1667	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1668	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1669	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1670	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1671	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1672	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1673	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1674	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1675	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1676	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1677	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1678	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1679	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1680	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1681	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1682	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1683
1684	/* CPUID(0x80000001).edx */
1685	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1686	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1687	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1688	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1689	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1690	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1691	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1692	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1693	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1694	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1695	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1696	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1697	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1698	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1699	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1700	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1701	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1702	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1703	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1704	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1705	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1706	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1707	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1708	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1709	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1710	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1711	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1712	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1713	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1714	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1715	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1716	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1717
1718	/** @todo verify the rest as well. */
1719	}
1720	}
1721
1722
1723
1724	/*
1725	* Verify that we can support the features already exposed to the guest on
1726	* this host.
1727	*
1728	* Most of the features we're emulating requires intercepting instruction
1729	* and doing it the slow way, so there is no need to warn when they aren't
1730	* present in the host CPU. Thus we use IGN instead of EMU on these.
1731	*
1732	* Trailing comments:
1733	* "EMU" - Possible to emulate, could be lots of work and very slow.
1734	* "EMU?" - Can this be emulated?
1735	*/
1736	/* CPUID(1).ecx */
1737	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1738	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1739	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1740	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1741	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1742	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1743	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1744	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1745	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1746	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1747	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1748	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1749	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1750	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1751	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1752	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1753	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1754	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1755	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1756	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1757	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1758	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1759	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1760	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1761	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1762	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1763	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1764	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1765	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1766	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1767	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1768	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1769
1770	/* CPUID(1).edx */
1771	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1772	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1773	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1774	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1775	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1776	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1777	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1778	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1779	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1780	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1781	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1782	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1783	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1784	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1785	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1786	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1787	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1788	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1789	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1790	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1791	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1792	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1793	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1794	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1795	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1796	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1797	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1798	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1799	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1800	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1801	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1802	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1803
1804	/* CPUID(0x80000000). */
1805	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1806	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1807	{
1808	/** @todo deal with no 0x80000001 on the host. */
1809	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1810	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1811
1812	/* CPUID(0x80000001).ecx */
1813	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1814	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1815	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1816	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1817	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1818	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1819	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1820	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1821	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1822	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1823	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1824	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1825	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1826	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1827	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1828	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1829	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1830	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1831	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1832	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1833	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1834	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1835	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1836	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1837	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1838	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1839	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1840	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1841	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1842	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1843	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1844	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1845
1846	/* CPUID(0x80000001).edx */
1847	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1848	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1849	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1850	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1851	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1852	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1853	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1854	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1855	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1856	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1857	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1858	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1859	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1860	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1861	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1862	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1863	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1864	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1865	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1866	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1867	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1868	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1869	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1870	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1871	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1872	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1873	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1874	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1875	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1876	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1877	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1878	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1879	}
1880
1881	/*
1882	* We're good, commit the CPU ID leaves.
1883	*/
1884	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1885	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1886	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1887	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1888
1889	#undef CPUID_CHECK_RET
1890	#undef CPUID_CHECK_WRN
1891	#undef CPUID_CHECK2_RET
1892	#undef CPUID_CHECK2_WRN
1893	#undef CPUID_RAW_FEATURE_RET
1894	#undef CPUID_RAW_FEATURE_WRN
1895	#undef CPUID_RAW_FEATURE_IGN
1896	#undef CPUID_GST_FEATURE_RET
1897	#undef CPUID_GST_FEATURE_WRN
1898	#undef CPUID_GST_FEATURE_EMU
1899	#undef CPUID_GST_FEATURE_IGN
1900	#undef CPUID_GST_FEATURE2_RET
1901	#undef CPUID_GST_FEATURE2_WRN
1902	#undef CPUID_GST_FEATURE2_EMU
1903	#undef CPUID_GST_FEATURE2_IGN
1904	#undef CPUID_GST_AMD_FEATURE_RET
1905	#undef CPUID_GST_AMD_FEATURE_WRN
1906	#undef CPUID_GST_AMD_FEATURE_EMU
1907	#undef CPUID_GST_AMD_FEATURE_IGN
1908
1909	return VINF_SUCCESS;
1910	}
1911
1912
1913	/**
1914	* Pass 0 live exec callback.
1915	*
1916	* @returns VINF_SSM_DONT_CALL_AGAIN.
1917	* @param pVM The VM handle.
1918	* @param pSSM The saved state handle.
1919	* @param uPass The pass (0).
1920	*/
1921	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1922	{
1923	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1924	cpumR3SaveCpuId(pVM, pSSM);
1925	return VINF_SSM_DONT_CALL_AGAIN;
1926	}
1927
1928
1929	/**
1930	* Execute state save operation.
1931	*
1932	* @returns VBox status code.
1933	* @param pVM VM Handle.
1934	* @param pSSM SSM operation handle.
1935	*/
1936	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1937	{
1938	/*
1939	* Save.
1940	*/
1941	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1942	{
1943	PVMCPU pVCpu = &pVM->aCpus[i];
1944
1945	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1946	}
1947
1948	SSMR3PutU32(pSSM, pVM->cCpus);
1949	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1950	{
1951	PVMCPU pVCpu = &pVM->aCpus[i];
1952
1953	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1954	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1955	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1956	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1957	}
1958
1959	cpumR3SaveCpuId(pVM, pSSM);
1960	return VINF_SUCCESS;
1961	}
1962
1963
1964	/**
1965	* Load a version 1.6 CPUMCTX structure.
1966	*
1967	* @returns VBox status code.
1968	* @param pVM VM Handle.
1969	* @param pCpumctx16 Version 1.6 CPUMCTX
1970	*/
1971	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1972	{
1973	#define CPUMCTX16_LOADREG(RegName) \
1974	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1975
1976	#define CPUMCTX16_LOADDRXREG(RegName) \
1977	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1978
1979	#define CPUMCTX16_LOADHIDREG(RegName) \
1980	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1981	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1982	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1983
1984	#define CPUMCTX16_LOADSEGREG(RegName) \
1985	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1986	CPUMCTX16_LOADHIDREG(RegName);
1987
1988	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1989
1990	CPUMCTX16_LOADREG(rax);
1991	CPUMCTX16_LOADREG(rbx);
1992	CPUMCTX16_LOADREG(rcx);
1993	CPUMCTX16_LOADREG(rdx);
1994	CPUMCTX16_LOADREG(rdi);
1995	CPUMCTX16_LOADREG(rsi);
1996	CPUMCTX16_LOADREG(rbp);
1997	CPUMCTX16_LOADREG(esp);
1998	CPUMCTX16_LOADREG(rip);
1999	CPUMCTX16_LOADREG(rflags);
2000
2001	CPUMCTX16_LOADSEGREG(cs);
2002	CPUMCTX16_LOADSEGREG(ds);
2003	CPUMCTX16_LOADSEGREG(es);
2004	CPUMCTX16_LOADSEGREG(fs);
2005	CPUMCTX16_LOADSEGREG(gs);
2006	CPUMCTX16_LOADSEGREG(ss);
2007
2008	CPUMCTX16_LOADREG(r8);
2009	CPUMCTX16_LOADREG(r9);
2010	CPUMCTX16_LOADREG(r10);
2011	CPUMCTX16_LOADREG(r11);
2012	CPUMCTX16_LOADREG(r12);
2013	CPUMCTX16_LOADREG(r13);
2014	CPUMCTX16_LOADREG(r14);
2015	CPUMCTX16_LOADREG(r15);
2016
2017	CPUMCTX16_LOADREG(cr0);
2018	CPUMCTX16_LOADREG(cr2);
2019	CPUMCTX16_LOADREG(cr3);
2020	CPUMCTX16_LOADREG(cr4);
2021
2022	CPUMCTX16_LOADDRXREG(0);
2023	CPUMCTX16_LOADDRXREG(1);
2024	CPUMCTX16_LOADDRXREG(2);
2025	CPUMCTX16_LOADDRXREG(3);
2026	CPUMCTX16_LOADDRXREG(4);
2027	CPUMCTX16_LOADDRXREG(5);
2028	CPUMCTX16_LOADDRXREG(6);
2029	CPUMCTX16_LOADDRXREG(7);
2030
2031	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
2032	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
2033	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
2034	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
2035
2036	CPUMCTX16_LOADREG(ldtr);
2037	CPUMCTX16_LOADREG(tr);
2038
2039	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
2040
2041	CPUMCTX16_LOADREG(msrEFER);
2042	CPUMCTX16_LOADREG(msrSTAR);
2043	CPUMCTX16_LOADREG(msrPAT);
2044	CPUMCTX16_LOADREG(msrLSTAR);
2045	CPUMCTX16_LOADREG(msrCSTAR);
2046	CPUMCTX16_LOADREG(msrSFMASK);
2047	CPUMCTX16_LOADREG(msrKERNELGSBASE);
2048
2049	CPUMCTX16_LOADHIDREG(ldtr);
2050	CPUMCTX16_LOADHIDREG(tr);
2051
2052	#undef CPUMCTX16_LOADSEGREG
2053	#undef CPUMCTX16_LOADHIDREG
2054	#undef CPUMCTX16_LOADDRXREG
2055	#undef CPUMCTX16_LOADREG
2056	}
2057
2058
2059	/**
2060	* @copydoc FNSSMINTLOADPREP
2061	*/
2062	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2063	{
2064	pVM->cpum.s.fPendingRestore = true;
2065	return VINF_SUCCESS;
2066	}
2067
2068
2069	/**
2070	* @copydoc FNSSMINTLOADEXEC
2071	*/
2072	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2073	{
2074	/*
2075	* Validate version.
2076	*/
2077	if ( uVersion != CPUM_SAVED_STATE_VERSION
2078	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2079	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2080	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2081	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2082	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2083	{
2084	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2085	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2086	}
2087
2088	if (uPass == SSM_PASS_FINAL)
2089	{
2090	/*
2091	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2092	* really old SSM file versions.)
2093	*/
2094	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2095	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2096	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2097	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2098
2099	/*
2100	* Restore.
2101	*/
2102	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2103	{
2104	PVMCPU pVCpu = &pVM->aCpus[i];
2105	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2106	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
2107
2108	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
2109	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2110	pVCpu->cpum.s.Hyper.esp = uESP;
2111	}
2112
2113	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2114	{
2115	CPUMCTX_VER1_6 cpumctx16;
2116	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
2117	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
2118
2119	/* Save the old cpumctx state into the new one. */
2120	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
2121
2122	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
2123	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
2124	}
2125	else
2126	{
2127	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2128	{
2129	uint32_t cCpus;
2130	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2131	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2132	VERR_SSM_UNEXPECTED_DATA);
2133	}
2134	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2135	\|\| pVM->cCpus == 1,
2136	("cCpus=%u\n", pVM->cCpus),
2137	VERR_SSM_UNEXPECTED_DATA);
2138
2139	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2140	{
2141	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
2142	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
2143	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
2144	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2145	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
2146	}
2147	}
2148
2149	/* Older states does not set CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID for
2150	raw-mode guest, so we have to do it ourselves. */
2151	if ( uVersion <= CPUM_SAVED_STATE_VERSION_VER3_2
2152	&& !HWACCMIsEnabled(pVM))
2153	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2154	pVM->aCpus[iCpu].cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2155	}
2156
2157	pVM->cpum.s.fPendingRestore = false;
2158
2159	/*
2160	* Guest CPUIDs.
2161	*/
2162	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2163	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2164
2165	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2166	* actually required. */
2167
2168	/*
2169	* Restore the CPUID leaves.
2170	*
2171	* Note that we support restoring less than the current amount of standard
2172	* leaves because we've been allowed more is newer version of VBox.
2173	*/
2174	uint32_t cElements;
2175	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2176	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2177	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2178	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2179
2180	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2181	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2182	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2183	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2184
2185	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2186	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2187	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2188	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2189
2190	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2191
2192	/*
2193	* Check that the basic cpuid id information is unchanged.
2194	*/
2195	/** @todo we should check the 64 bits capabilities too! */
2196	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2197	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2198	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2199	uint32_t au32CpuIdSaved[8];
2200	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2201	if (RT_SUCCESS(rc))
2202	{
2203	/* Ignore CPU stepping. */
2204	au32CpuId[4] &= 0xfffffff0;
2205	au32CpuIdSaved[4] &= 0xfffffff0;
2206
2207	/* Ignore APIC ID (AMD specs). */
2208	au32CpuId[5] &= ~0xff000000;
2209	au32CpuIdSaved[5] &= ~0xff000000;
2210
2211	/* Ignore the number of Logical CPUs (AMD specs). */
2212	au32CpuId[5] &= ~0x00ff0000;
2213	au32CpuIdSaved[5] &= ~0x00ff0000;
2214
2215	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2216	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2217	\| X86_CPUID_FEATURE_ECX_VMX
2218	\| X86_CPUID_FEATURE_ECX_SMX
2219	\| X86_CPUID_FEATURE_ECX_EST
2220	\| X86_CPUID_FEATURE_ECX_TM2
2221	\| X86_CPUID_FEATURE_ECX_CNTXID
2222	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2223	\| X86_CPUID_FEATURE_ECX_PDCM
2224	\| X86_CPUID_FEATURE_ECX_DCA
2225	\| X86_CPUID_FEATURE_ECX_X2APIC
2226	);
2227	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2228	\| X86_CPUID_FEATURE_ECX_VMX
2229	\| X86_CPUID_FEATURE_ECX_SMX
2230	\| X86_CPUID_FEATURE_ECX_EST
2231	\| X86_CPUID_FEATURE_ECX_TM2
2232	\| X86_CPUID_FEATURE_ECX_CNTXID
2233	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2234	\| X86_CPUID_FEATURE_ECX_PDCM
2235	\| X86_CPUID_FEATURE_ECX_DCA
2236	\| X86_CPUID_FEATURE_ECX_X2APIC
2237	);
2238
2239	/* Make sure we don't forget to update the masks when enabling
2240	* features in the future.
2241	*/
2242	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2243	( X86_CPUID_FEATURE_ECX_DTES64
2244	\| X86_CPUID_FEATURE_ECX_VMX
2245	\| X86_CPUID_FEATURE_ECX_SMX
2246	\| X86_CPUID_FEATURE_ECX_EST
2247	\| X86_CPUID_FEATURE_ECX_TM2
2248	\| X86_CPUID_FEATURE_ECX_CNTXID
2249	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2250	\| X86_CPUID_FEATURE_ECX_PDCM
2251	\| X86_CPUID_FEATURE_ECX_DCA
2252	\| X86_CPUID_FEATURE_ECX_X2APIC
2253	)));
2254	/* do the compare */
2255	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2256	{
2257	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2258	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2259	"Saved=%.*Rhxs\n"
2260	"Real =%.*Rhxs\n",
2261	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2262	sizeof(au32CpuId), au32CpuId));
2263	else
2264	{
2265	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2266	"Saved=%.*Rhxs\n"
2267	"Real =%.*Rhxs\n",
2268	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2269	sizeof(au32CpuId), au32CpuId));
2270	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2271	}
2272	}
2273	}
2274
2275	return rc;
2276	}
2277
2278
2279	/**
2280	* @copydoc FNSSMINTLOADPREP
2281	*/
2282	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2283	{
2284	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2285	return VINF_SUCCESS;
2286
2287	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2288	if (pVM->cpum.s.fPendingRestore)
2289	{
2290	LogRel(("CPUM: Missing state!\n"));
2291	return VERR_INTERNAL_ERROR_2;
2292	}
2293
2294	/* Notify PGM of the NXE states in case they've changed. */
2295	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2296	PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2297	return VINF_SUCCESS;
2298	}
2299
2300
2301	/**
2302	* Checks if the CPUM state restore is still pending.
2303	*
2304	* @returns true / false.
2305	* @param pVM The VM handle.
2306	*/
2307	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2308	{
2309	return pVM->cpum.s.fPendingRestore;
2310	}
2311
2312
2313	/**
2314	* Formats the EFLAGS value into mnemonics.
2315	*
2316	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2317	* @param efl The EFLAGS value.
2318	*/
2319	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2320	{
2321	/*
2322	* Format the flags.
2323	*/
2324	static const struct
2325	{
2326	const char pszSet; const char pszClear; uint32_t fFlag;
2327	} s_aFlags[] =
2328	{
2329	{ "vip",NULL, X86_EFL_VIP },
2330	{ "vif",NULL, X86_EFL_VIF },
2331	{ "ac", NULL, X86_EFL_AC },
2332	{ "vm", NULL, X86_EFL_VM },
2333	{ "rf", NULL, X86_EFL_RF },
2334	{ "nt", NULL, X86_EFL_NT },
2335	{ "ov", "nv", X86_EFL_OF },
2336	{ "dn", "up", X86_EFL_DF },
2337	{ "ei", "di", X86_EFL_IF },
2338	{ "tf", NULL, X86_EFL_TF },
2339	{ "nt", "pl", X86_EFL_SF },
2340	{ "nz", "zr", X86_EFL_ZF },
2341	{ "ac", "na", X86_EFL_AF },
2342	{ "po", "pe", X86_EFL_PF },
2343	{ "cy", "nc", X86_EFL_CF },
2344	};
2345	char *psz = pszEFlags;
2346	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2347	{
2348	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2349	if (pszAdd)
2350	{
2351	strcpy(psz, pszAdd);
2352	psz += strlen(pszAdd);
2353	*psz++ = ' ';
2354	}
2355	}
2356	psz[-1] = '\0';
2357	}
2358
2359
2360	/**
2361	* Formats a full register dump.
2362	*
2363	* @param pVM VM Handle.
2364	* @param pCtx The context to format.
2365	* @param pCtxCore The context core to format.
2366	* @param pHlp Output functions.
2367	* @param enmType The dump type.
2368	* @param pszPrefix Register name prefix.
2369	*/
2370	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2371	{
2372	/*
2373	* Format the EFLAGS.
2374	*/
2375	uint32_t efl = pCtxCore->eflags.u32;
2376	char szEFlags[80];
2377	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2378
2379	/*
2380	* Format the registers.
2381	*/
2382	switch (enmType)
2383	{
2384	case CPUMDUMPTYPE_TERSE:
2385	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2386	pHlp->pfnPrintf(pHlp,
2387	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2388	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2389	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2390	"%sr14=%016RX64 %sr15=%016RX64\n"
2391	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2392	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2393	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2394	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2395	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2396	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2397	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2398	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2399	else
2400	pHlp->pfnPrintf(pHlp,
2401	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2402	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2403	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2404	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2405	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2406	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2407	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2408	break;
2409
2410	case CPUMDUMPTYPE_DEFAULT:
2411	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2412	pHlp->pfnPrintf(pHlp,
2413	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2414	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2415	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2416	"%sr14=%016RX64 %sr15=%016RX64\n"
2417	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2418	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2419	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2420	,
2421	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2422	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2423	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2424	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2425	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2426	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2427	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2428	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2429	else
2430	pHlp->pfnPrintf(pHlp,
2431	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2432	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2433	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2434	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2435	,
2436	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2437	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2438	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2439	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2440	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2441	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2442	break;
2443
2444	case CPUMDUMPTYPE_VERBOSE:
2445	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2446	pHlp->pfnPrintf(pHlp,
2447	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2448	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2449	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2450	"%sr14=%016RX64 %sr15=%016RX64\n"
2451	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2452	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2453	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2454	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2455	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2456	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2457	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2458	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2459	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2460	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2461	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2462	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2463	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2464	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2465	,
2466	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2467	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2468	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2469	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2470	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2471	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2472	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2473	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2474	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2475	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2476	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2477	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2478	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2479	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2480	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2481	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2482	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2483	else
2484	pHlp->pfnPrintf(pHlp,
2485	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2486	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2487	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2488	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2489	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2490	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2491	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2492	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2493	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2494	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2495	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2496	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2497	,
2498	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2499	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2500	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2501	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2502	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2503	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2504	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2505	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2506	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2507	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2508	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2509	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2510
2511	pHlp->pfnPrintf(pHlp,
2512	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2513	"%sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2514	,
2515	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2516	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2517	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2518	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2519	);
2520	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2521	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2522	{
2523	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2524	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2525	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2526	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2527	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2528	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2529	/** @todo This isn't entirenly correct and needs more work! */
2530	pHlp->pfnPrintf(pHlp,
2531	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2532	pszPrefix, iST, pszPrefix, iFPR,
2533	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2534	uTag, chSign, iInteger, u64Fraction, uExponent);
2535	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2536	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2537	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2538	else
2539	pHlp->pfnPrintf(pHlp, "\n");
2540	}
2541	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2542	pHlp->pfnPrintf(pHlp,
2543	iXMM & 1
2544	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2545	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2546	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2547	pCtx->fpu.aXMM[iXMM].au32[3],
2548	pCtx->fpu.aXMM[iXMM].au32[2],
2549	pCtx->fpu.aXMM[iXMM].au32[1],
2550	pCtx->fpu.aXMM[iXMM].au32[0]);
2551	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2552	if (pCtx->fpu.au32RsrvdRest[i])
2553	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2554	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2555
2556	pHlp->pfnPrintf(pHlp,
2557	"%sEFER =%016RX64\n"
2558	"%sPAT =%016RX64\n"
2559	"%sSTAR =%016RX64\n"
2560	"%sCSTAR =%016RX64\n"
2561	"%sLSTAR =%016RX64\n"
2562	"%sSFMASK =%016RX64\n"
2563	"%sKERNELGSBASE =%016RX64\n",
2564	pszPrefix, pCtx->msrEFER,
2565	pszPrefix, pCtx->msrPAT,
2566	pszPrefix, pCtx->msrSTAR,
2567	pszPrefix, pCtx->msrCSTAR,
2568	pszPrefix, pCtx->msrLSTAR,
2569	pszPrefix, pCtx->msrSFMASK,
2570	pszPrefix, pCtx->msrKERNELGSBASE);
2571	break;
2572	}
2573	}
2574
2575
2576	/**
2577	* Display all cpu states and any other cpum info.
2578	*
2579	* @param pVM VM Handle.
2580	* @param pHlp The info helper functions.
2581	* @param pszArgs Arguments, ignored.
2582	*/
2583	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2584	{
2585	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2586	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2587	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2588	cpumR3InfoHost(pVM, pHlp, pszArgs);
2589	}
2590
2591
2592	/**
2593	* Parses the info argument.
2594	*
2595	* The argument starts with 'verbose', 'terse' or 'default' and then
2596	* continues with the comment string.
2597	*
2598	* @param pszArgs The pointer to the argument string.
2599	* @param penmType Where to store the dump type request.
2600	* @param ppszComment Where to store the pointer to the comment string.
2601	*/
2602	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2603	{
2604	if (!pszArgs)
2605	{
2606	*penmType = CPUMDUMPTYPE_DEFAULT;
2607	*ppszComment = "";
2608	}
2609	else
2610	{
2611	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2612	{
2613	pszArgs += 5;
2614	*penmType = CPUMDUMPTYPE_VERBOSE;
2615	}
2616	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2617	{
2618	pszArgs += 5;
2619	*penmType = CPUMDUMPTYPE_TERSE;
2620	}
2621	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2622	{
2623	pszArgs += 7;
2624	*penmType = CPUMDUMPTYPE_DEFAULT;
2625	}
2626	else
2627	*penmType = CPUMDUMPTYPE_DEFAULT;
2628	*ppszComment = RTStrStripL(pszArgs);
2629	}
2630	}
2631
2632
2633	/**
2634	* Display the guest cpu state.
2635	*
2636	* @param pVM VM Handle.
2637	* @param pHlp The info helper functions.
2638	* @param pszArgs Arguments, ignored.
2639	*/
2640	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2641	{
2642	CPUMDUMPTYPE enmType;
2643	const char *pszComment;
2644	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2645
2646	/* @todo SMP support! */
2647	PVMCPU pVCpu = VMMGetCpu(pVM);
2648	if (!pVCpu)
2649	pVCpu = &pVM->aCpus[0];
2650
2651	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2652
2653	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2654	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2655	}
2656
2657
2658	/**
2659	* Display the current guest instruction
2660	*
2661	* @param pVM VM Handle.
2662	* @param pHlp The info helper functions.
2663	* @param pszArgs Arguments, ignored.
2664	*/
2665	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2666	{
2667	char szInstruction[256];
2668	/* @todo SMP support! */
2669	PVMCPU pVCpu = VMMGetCpu(pVM);
2670	if (!pVCpu)
2671	pVCpu = &pVM->aCpus[0];
2672
2673	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2674	if (RT_SUCCESS(rc))
2675	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2676	}
2677
2678
2679	/**
2680	* Display the hypervisor cpu state.
2681	*
2682	* @param pVM VM Handle.
2683	* @param pHlp The info helper functions.
2684	* @param pszArgs Arguments, ignored.
2685	*/
2686	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2687	{
2688	CPUMDUMPTYPE enmType;
2689	const char *pszComment;
2690	/* @todo SMP */
2691	PVMCPU pVCpu = &pVM->aCpus[0];
2692
2693	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2694	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2695	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2696	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2697	}
2698
2699
2700	/**
2701	* Display the host cpu state.
2702	*
2703	* @param pVM VM Handle.
2704	* @param pHlp The info helper functions.
2705	* @param pszArgs Arguments, ignored.
2706	*/
2707	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2708	{
2709	CPUMDUMPTYPE enmType;
2710	const char *pszComment;
2711	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2712	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2713
2714	/*
2715	* Format the EFLAGS.
2716	*/
2717	/* @todo SMP */
2718	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2719	#if HC_ARCH_BITS == 32
2720	uint32_t efl = pCtx->eflags.u32;
2721	#else
2722	uint64_t efl = pCtx->rflags;
2723	#endif
2724	char szEFlags[80];
2725	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2726
2727	/*
2728	* Format the registers.
2729	*/
2730	#if HC_ARCH_BITS == 32
2731	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2732	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2733	# endif
2734	{
2735	pHlp->pfnPrintf(pHlp,
2736	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2737	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2738	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2739	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2740	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2741	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2742	,
2743	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2744	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2745	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2746	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2747	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2748	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2749	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2750	}
2751	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2752	else
2753	# endif
2754	#endif
2755	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2756	{
2757	pHlp->pfnPrintf(pHlp,
2758	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2759	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2760	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2761	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2762	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2763	"r14=%016RX64 r15=%016RX64\n"
2764	"iopl=%d %31s\n"
2765	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2766	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2767	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2768	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2769	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2770	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2771	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2772	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2773	,
2774	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2775	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2776	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2777	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2778	pCtx->r11, pCtx->r12, pCtx->r13,
2779	pCtx->r14, pCtx->r15,
2780	X86_EFL_GET_IOPL(efl), szEFlags,
2781	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2782	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2783	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2784	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2785	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2786	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2787	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2788	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2789	}
2790	#endif
2791	}
2792
2793
2794	/**
2795	* Get L1 cache / TLS associativity.
2796	*/
2797	static const char getCacheAss(unsigned u, char pszBuf)
2798	{
2799	if (u == 0)
2800	return "res0 ";
2801	if (u == 1)
2802	return "direct";
2803	if (u == 255)
2804	return "fully";
2805	if (u >= 256)
2806	return "???";
2807
2808	RTStrPrintf(pszBuf, 16, "%d way", u);
2809	return pszBuf;
2810	}
2811
2812
2813	/**
2814	* Get L2 cache soociativity.
2815	*/
2816	const char *getL2CacheAss(unsigned u)
2817	{
2818	switch (u)
2819	{
2820	case 0: return "off ";
2821	case 1: return "direct";
2822	case 2: return "2 way ";
2823	case 3: return "res3 ";
2824	case 4: return "4 way ";
2825	case 5: return "res5 ";
2826	case 6: return "8 way ";
2827	case 7: return "res7 ";
2828	case 8: return "16 way";
2829	case 9: return "res9 ";
2830	case 10: return "res10 ";
2831	case 11: return "res11 ";
2832	case 12: return "res12 ";
2833	case 13: return "res13 ";
2834	case 14: return "res14 ";
2835	case 15: return "fully ";
2836	default: return "????";
2837	}
2838	}
2839
2840
2841	/**
2842	* Display the guest CpuId leaves.
2843	*
2844	* @param pVM VM Handle.
2845	* @param pHlp The info helper functions.
2846	* @param pszArgs "terse", "default" or "verbose".
2847	*/
2848	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2849	{
2850	/*
2851	* Parse the argument.
2852	*/
2853	unsigned iVerbosity = 1;
2854	if (pszArgs)
2855	{
2856	pszArgs = RTStrStripL(pszArgs);
2857	if (!strcmp(pszArgs, "terse"))
2858	iVerbosity--;
2859	else if (!strcmp(pszArgs, "verbose"))
2860	iVerbosity++;
2861	}
2862
2863	/*
2864	* Start cracking.
2865	*/
2866	CPUMCPUID Host;
2867	CPUMCPUID Guest;
2868	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2869
2870	pHlp->pfnPrintf(pHlp,
2871	" RAW Standard CPUIDs\n"
2872	" Function eax ebx ecx edx\n");
2873	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2874	{
2875	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2876	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2877
2878	pHlp->pfnPrintf(pHlp,
2879	"Gst: %08x %08x %08x %08x %08x%s\n"
2880	"Hst: %08x %08x %08x %08x\n",
2881	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2882	i <= cStdMax ? "" : "*",
2883	Host.eax, Host.ebx, Host.ecx, Host.edx);
2884	}
2885
2886	/*
2887	* If verbose, decode it.
2888	*/
2889	if (iVerbosity)
2890	{
2891	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2892	pHlp->pfnPrintf(pHlp,
2893	"Name: %.04s%.04s%.04s\n"
2894	"Supports: 0-%x\n",
2895	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2896	}
2897
2898	/*
2899	* Get Features.
2900	*/
2901	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2902	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2903	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2904	if (cStdMax >= 1 && iVerbosity)
2905	{
2906	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
2907
2908	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2909	uint32_t uEAX = Guest.eax;
2910
2911	pHlp->pfnPrintf(pHlp,
2912	"Family: %d \tExtended: %d \tEffective: %d\n"
2913	"Model: %d \tExtended: %d \tEffective: %d\n"
2914	"Stepping: %d\n"
2915	"Type: %d (%s)\n"
2916	"APIC ID: %#04x\n"
2917	"Logical CPUs: %d\n"
2918	"CLFLUSH Size: %d\n"
2919	"Brand ID: %#04x\n",
2920	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2921	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2922	ASMGetCpuStepping(uEAX),
2923	(uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
2924	(Guest.ebx >> 24) & 0xff,
2925	(Guest.ebx >> 16) & 0xff,
2926	(Guest.ebx >> 8) & 0xff,
2927	(Guest.ebx >> 0) & 0xff);
2928	if (iVerbosity == 1)
2929	{
2930	uint32_t uEDX = Guest.edx;
2931	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2932	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2933	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2934	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2935	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2936	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2937	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2938	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2939	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2940	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2941	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2942	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2943	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2944	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2945	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2946	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2947	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2948	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2949	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2950	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2951	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2952	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2953	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2954	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2955	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2956	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2957	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2958	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2959	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2960	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2961	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2962	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2963	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2964	pHlp->pfnPrintf(pHlp, "\n");
2965
2966	uint32_t uECX = Guest.ecx;
2967	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2968	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2969	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2970	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2971	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2972	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2973	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2974	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2975	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2976	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2977	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2978	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2979	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2980	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2981	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2982	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2983	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2984	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2985	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " 17");
2986	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2987	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4_1");
2988	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4_2");
2989	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2990	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2991	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2992	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " 24");
2993	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2994	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2995	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2996	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2997	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2998	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2999	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
3000	pHlp->pfnPrintf(pHlp, "\n");
3001	}
3002	else
3003	{
3004	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3005
3006	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3007	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3008	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3009	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3010
3011	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3012	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3013	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3014	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3015	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3016	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3017	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3018	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3019	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3020	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3021	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3022	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3023	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3024	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3025	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3026	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3027	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3028	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3029	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3030	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3031	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3032	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3033	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3034	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3035	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3036	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3037	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3038	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3039	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3040	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3041	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3042	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3043	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3044
3045	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3046	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3047	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3048	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3049	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3050	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3051	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3052	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3053	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3054	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3055	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3056	pHlp->pfnPrintf(pHlp, "FMA = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3057	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3058	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3059	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3060	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3061	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3062	pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3063	pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3064	pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3065	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3066	pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3067	pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3068	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
3069	pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3070	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3071	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
3072	}
3073	}
3074	if (cStdMax >= 2 && iVerbosity)
3075	{
3076	/** @todo */
3077	}
3078
3079	/*
3080	* Extended.
3081	* Implemented after AMD specs.
3082	*/
3083	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3084
3085	pHlp->pfnPrintf(pHlp,
3086	"\n"
3087	" RAW Extended CPUIDs\n"
3088	" Function eax ebx ecx edx\n");
3089	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3090	{
3091	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3092	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3093
3094	pHlp->pfnPrintf(pHlp,
3095	"Gst: %08x %08x %08x %08x %08x%s\n"
3096	"Hst: %08x %08x %08x %08x\n",
3097	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3098	i <= cExtMax ? "" : "*",
3099	Host.eax, Host.ebx, Host.ecx, Host.edx);
3100	}
3101
3102	/*
3103	* Understandable output
3104	*/
3105	if (iVerbosity)
3106	{
3107	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3108	pHlp->pfnPrintf(pHlp,
3109	"Ext Name: %.4s%.4s%.4s\n"
3110	"Ext Supports: 0x80000000-%#010x\n",
3111	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3112	}
3113
3114	if (iVerbosity && cExtMax >= 1)
3115	{
3116	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3117	uint32_t uEAX = Guest.eax;
3118	pHlp->pfnPrintf(pHlp,
3119	"Family: %d \tExtended: %d \tEffective: %d\n"
3120	"Model: %d \tExtended: %d \tEffective: %d\n"
3121	"Stepping: %d\n"
3122	"Brand ID: %#05x\n",
3123	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3124	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3125	ASMGetCpuStepping(uEAX),
3126	Guest.ebx & 0xfff);
3127
3128	if (iVerbosity == 1)
3129	{
3130	uint32_t uEDX = Guest.edx;
3131	pHlp->pfnPrintf(pHlp, "Features EDX: ");
3132	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3133	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3134	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3135	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3136	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3137	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3138	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3139	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3140	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3141	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3142	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3143	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3144	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3145	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3146	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3147	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3148	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3149	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3150	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3151	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3152	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3153	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3154	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3155	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3156	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3157	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3158	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3159	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3160	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3161	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3162	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3163	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3164	pHlp->pfnPrintf(pHlp, "\n");
3165
3166	uint32_t uECX = Guest.ecx;
3167	pHlp->pfnPrintf(pHlp, "Features ECX: ");
3168	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3169	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3170	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3171	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3172	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3173	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3174	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3175	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3176	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3177	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3178	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3179	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3180	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3181	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3182	for (unsigned iBit = 5; iBit < 32; iBit++)
3183	if (uECX & RT_BIT(iBit))
3184	pHlp->pfnPrintf(pHlp, " %d", iBit);
3185	pHlp->pfnPrintf(pHlp, "\n");
3186	}
3187	else
3188	{
3189	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3190
3191	uint32_t uEdxGst = Guest.edx;
3192	uint32_t uEdxHst = Host.edx;
3193	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3194	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3195	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3196	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3197	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3198	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3199	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3200	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3201	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3202	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3203	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3204	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3205	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3206	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3207	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3208	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3209	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3210	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3211	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3212	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3213	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3214	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3215	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3216	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3217	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3218	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3219	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3220	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3221	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3222	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3223	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3224	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3225	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3226
3227	uint32_t uEcxGst = Guest.ecx;
3228	uint32_t uEcxHst = Host.ecx;
3229	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3230	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3231	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3232	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3233	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3234	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3235	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3236	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3237	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3238	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3239	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3240	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3241	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3242	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3243	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3244	}
3245	}
3246
3247	if (iVerbosity && cExtMax >= 2)
3248	{
3249	char szString[443+1] = {0};
3250	uint32_t pu32 = (uint32_t )szString;
3251	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3252	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3253	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3254	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3255	if (cExtMax >= 3)
3256	{
3257	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3258	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3259	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3260	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3261	}
3262	if (cExtMax >= 4)
3263	{
3264	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3265	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3266	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3267	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3268	}
3269	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3270	}
3271
3272	if (iVerbosity && cExtMax >= 5)
3273	{
3274	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3275	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3276	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3277	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3278	char sz1[32];
3279	char sz2[32];
3280
3281	pHlp->pfnPrintf(pHlp,
3282	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3283	"TLB 2/4M Data: %s %3d entries\n",
3284	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3285	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3286	pHlp->pfnPrintf(pHlp,
3287	"TLB 4K Instr/Uni: %s %3d entries\n"
3288	"TLB 4K Data: %s %3d entries\n",
3289	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3290	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3291	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3292	"L1 Instr Cache Lines Per Tag: %d\n"
3293	"L1 Instr Cache Associativity: %s\n"
3294	"L1 Instr Cache Size: %d KB\n",
3295	(uEDX >> 0) & 0xff,
3296	(uEDX >> 8) & 0xff,
3297	getCacheAss((uEDX >> 16) & 0xff, sz1),
3298	(uEDX >> 24) & 0xff);
3299	pHlp->pfnPrintf(pHlp,
3300	"L1 Data Cache Line Size: %d bytes\n"
3301	"L1 Data Cache Lines Per Tag: %d\n"
3302	"L1 Data Cache Associativity: %s\n"
3303	"L1 Data Cache Size: %d KB\n",
3304	(uECX >> 0) & 0xff,
3305	(uECX >> 8) & 0xff,
3306	getCacheAss((uECX >> 16) & 0xff, sz1),
3307	(uECX >> 24) & 0xff);
3308	}
3309
3310	if (iVerbosity && cExtMax >= 6)
3311	{
3312	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3313	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3314	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3315
3316	pHlp->pfnPrintf(pHlp,
3317	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3318	"L2 TLB 2/4M Data: %s %4d entries\n",
3319	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3320	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3321	pHlp->pfnPrintf(pHlp,
3322	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3323	"L2 TLB 4K Data: %s %4d entries\n",
3324	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3325	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3326	pHlp->pfnPrintf(pHlp,
3327	"L2 Cache Line Size: %d bytes\n"
3328	"L2 Cache Lines Per Tag: %d\n"
3329	"L2 Cache Associativity: %s\n"
3330	"L2 Cache Size: %d KB\n",
3331	(uEDX >> 0) & 0xff,
3332	(uEDX >> 8) & 0xf,
3333	getL2CacheAss((uEDX >> 12) & 0xf),
3334	(uEDX >> 16) & 0xffff);
3335	}
3336
3337	if (iVerbosity && cExtMax >= 7)
3338	{
3339	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3340
3341	pHlp->pfnPrintf(pHlp, "APM Features: ");
3342	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3343	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3344	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3345	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3346	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3347	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3348	for (unsigned iBit = 6; iBit < 32; iBit++)
3349	if (uEDX & RT_BIT(iBit))
3350	pHlp->pfnPrintf(pHlp, " %d", iBit);
3351	pHlp->pfnPrintf(pHlp, "\n");
3352	}
3353
3354	if (iVerbosity && cExtMax >= 8)
3355	{
3356	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3357	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3358
3359	pHlp->pfnPrintf(pHlp,
3360	"Physical Address Width: %d bits\n"
3361	"Virtual Address Width: %d bits\n"
3362	"Guest Physical Address Width: %d bits\n",
3363	(uEAX >> 0) & 0xff,
3364	(uEAX >> 8) & 0xff,
3365	(uEAX >> 16) & 0xff);
3366	pHlp->pfnPrintf(pHlp,
3367	"Physical Core Count: %d\n",
3368	(uECX >> 0) & 0xff);
3369	}
3370
3371
3372	/*
3373	* Centaur.
3374	*/
3375	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3376
3377	pHlp->pfnPrintf(pHlp,
3378	"\n"
3379	" RAW Centaur CPUIDs\n"
3380	" Function eax ebx ecx edx\n");
3381	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3382	{
3383	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3384	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3385
3386	pHlp->pfnPrintf(pHlp,
3387	"Gst: %08x %08x %08x %08x %08x%s\n"
3388	"Hst: %08x %08x %08x %08x\n",
3389	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3390	i <= cCentaurMax ? "" : "*",
3391	Host.eax, Host.ebx, Host.ecx, Host.edx);
3392	}
3393
3394	/*
3395	* Understandable output
3396	*/
3397	if (iVerbosity)
3398	{
3399	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3400	pHlp->pfnPrintf(pHlp,
3401	"Centaur Supports: 0xc0000000-%#010x\n",
3402	Guest.eax);
3403	}
3404
3405	if (iVerbosity && cCentaurMax >= 1)
3406	{
3407	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3408	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3409	uint32_t uEdxHst = Host.edx;
3410
3411	if (iVerbosity == 1)
3412	{
3413	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3414	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3415	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3416	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3417	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3418	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3419	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3420	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3421	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3422	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3423	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3424	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3425	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3426	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3427	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3428	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3429	for (unsigned iBit = 14; iBit < 32; iBit++)
3430	if (uEdxGst & RT_BIT(iBit))
3431	pHlp->pfnPrintf(pHlp, " %d", iBit);
3432	pHlp->pfnPrintf(pHlp, "\n");
3433	}
3434	else
3435	{
3436	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3437	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3438	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3439	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3440	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3441	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3442	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3443	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3444	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3445	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3446	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3447	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3448	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3449	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3450	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3451	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3452	for (unsigned iBit = 14; iBit < 32; iBit++)
3453	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3454	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3455	pHlp->pfnPrintf(pHlp, "\n");
3456	}
3457	}
3458	}
3459
3460
3461	/**
3462	* Structure used when disassembling and instructions in DBGF.
3463	* This is used so the reader function can get the stuff it needs.
3464	*/
3465	typedef struct CPUMDISASSTATE
3466	{
3467	/** Pointer to the CPU structure. */
3468	PDISCPUSTATE pCpu;
3469	/** The VM handle. */
3470	PVM pVM;
3471	/** The VMCPU handle. */
3472	PVMCPU pVCpu;
3473	/** Pointer to the first byte in the segemnt. */
3474	RTGCUINTPTR GCPtrSegBase;
3475	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3476	RTGCUINTPTR GCPtrSegEnd;
3477	/** The size of the segment minus 1. */
3478	RTGCUINTPTR cbSegLimit;
3479	/** Pointer to the current page - R3 Ptr. */
3480	void const *pvPageR3;
3481	/** Pointer to the current page - GC Ptr. */
3482	RTGCPTR pvPageGC;
3483	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3484	PGMPAGEMAPLOCK PageMapLock;
3485	/** Whether the PageMapLock is valid or not. */
3486	bool fLocked;
3487	/** 64 bits mode or not. */
3488	bool f64Bits;
3489	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3490
3491
3492	/**
3493	* Instruction reader.
3494	*
3495	* @returns VBox status code.
3496	* @param PtrSrc Address to read from.
3497	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3498	* @param pu8Dst Where to store the bytes.
3499	* @param cbRead Number of bytes to read.
3500	* @param uDisCpu Pointer to the disassembler cpu state.
3501	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3502	*/
3503	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3504	{
3505	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3506	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3507	Assert(cbRead > 0);
3508	for (;;)
3509	{
3510	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3511
3512	/* Need to update the page translation? */
3513	if ( !pState->pvPageR3
3514	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3515	{
3516	int rc = VINF_SUCCESS;
3517
3518	/* translate the address */
3519	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3520	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3521	&& !HWACCMIsEnabled(pState->pVM))
3522	{
3523	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3524	if (!pState->pvPageR3)
3525	rc = VERR_INVALID_POINTER;
3526	}
3527	else
3528	{
3529	/* Release mapping lock previously acquired. */
3530	if (pState->fLocked)
3531	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3532	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3533	pState->fLocked = RT_SUCCESS_NP(rc);
3534	}
3535	if (RT_FAILURE(rc))
3536	{
3537	pState->pvPageR3 = NULL;
3538	return rc;
3539	}
3540	}
3541
3542	/* check the segemnt limit */
3543	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3544	return VERR_OUT_OF_SELECTOR_BOUNDS;
3545
3546	/* calc how much we can read */
3547	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3548	if (!pState->f64Bits)
3549	{
3550	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3551	if (cb > cbSeg && cbSeg)
3552	cb = cbSeg;
3553	}
3554	if (cb > cbRead)
3555	cb = cbRead;
3556
3557	/* read and advance */
3558	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3559	cbRead -= cb;
3560	if (!cbRead)
3561	return VINF_SUCCESS;
3562	pu8Dst += cb;
3563	PtrSrc += cb;
3564	}
3565	}
3566
3567
3568	/**
3569	* Disassemble an instruction and return the information in the provided structure.
3570	*
3571	* @returns VBox status code.
3572	* @param pVM VM Handle
3573	* @param pVCpu VMCPU Handle
3574	* @param pCtx CPU context
3575	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3576	* @param pCpu Disassembly state
3577	* @param pszPrefix String prefix for logging (debug only)
3578	*
3579	*/
3580	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3581	{
3582	CPUMDISASSTATE State;
3583	int rc;
3584
3585	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3586	State.pCpu = pCpu;
3587	State.pvPageGC = 0;
3588	State.pvPageR3 = NULL;
3589	State.pVM = pVM;
3590	State.pVCpu = pVCpu;
3591	State.fLocked = false;
3592	State.f64Bits = false;
3593
3594	/*
3595	* Get selector information.
3596	*/
3597	if ( (pCtx->cr0 & X86_CR0_PE)
3598	&& pCtx->eflags.Bits.u1VM == 0)
3599	{
3600	if (CPUMAreHiddenSelRegsValid(pVCpu))
3601	{
3602	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3603	State.GCPtrSegBase = pCtx->csHid.u64Base;
3604	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3605	State.cbSegLimit = pCtx->csHid.u32Limit;
3606	pCpu->mode = (State.f64Bits)
3607	? CPUMODE_64BIT
3608	: pCtx->csHid.Attr.n.u1DefBig
3609	? CPUMODE_32BIT
3610	: CPUMODE_16BIT;
3611	}
3612	else
3613	{
3614	DBGFSELINFO SelInfo;
3615
3616	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3617	if (RT_FAILURE(rc))
3618	{
3619	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3620	return rc;
3621	}
3622
3623	/*
3624	* Validate the selector.
3625	*/
3626	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3627	if (RT_FAILURE(rc))
3628	{
3629	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3630	return rc;
3631	}
3632	State.GCPtrSegBase = SelInfo.GCPtrBase;
3633	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3634	State.cbSegLimit = SelInfo.cbLimit;
3635	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3636	}
3637	}
3638	else
3639	{
3640	/* real or V86 mode */
3641	pCpu->mode = CPUMODE_16BIT;
3642	State.GCPtrSegBase = pCtx->cs * 16;
3643	State.GCPtrSegEnd = 0xFFFFFFFF;
3644	State.cbSegLimit = 0xFFFFFFFF;
3645	}
3646
3647	/*
3648	* Disassemble the instruction.
3649	*/
3650	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3651	pCpu->apvUserData[0] = &State;
3652
3653	uint32_t cbInstr;
3654	#ifndef LOG_ENABLED
3655	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3656	if (RT_SUCCESS(rc))
3657	{
3658	#else
3659	char szOutput[160];
3660	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3661	if (RT_SUCCESS(rc))
3662	{
3663	/* log it */
3664	if (pszPrefix)
3665	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3666	else
3667	Log(("%s", szOutput));
3668	#endif
3669	rc = VINF_SUCCESS;
3670	}
3671	else
3672	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3673
3674	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3675	if (State.fLocked)
3676	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3677
3678	return rc;
3679	}
3680
3681	#ifdef DEBUG
3682
3683	/**
3684	* Disassemble an instruction and dump it to the log
3685	*
3686	* @returns VBox status code.
3687	* @param pVM VM Handle
3688	* @param pVCpu VMCPU Handle
3689	* @param pCtx CPU context
3690	* @param pc GC instruction pointer
3691	* @param pszPrefix String prefix for logging
3692	*
3693	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3694	*/
3695	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3696	{
3697	DISCPUSTATE Cpu;
3698	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3699	}
3700
3701
3702	/**
3703	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3704	*
3705	* @internal
3706	*/
3707	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3708	{
3709	/** @todo SMP support!! */
3710	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3711	}
3712
3713	#endif /* DEBUG */
3714
3715	/**
3716	* API for controlling a few of the CPU features found in CR4.
3717	*
3718	* Currently only X86_CR4_TSD is accepted as input.
3719	*
3720	* @returns VBox status code.
3721	*
3722	* @param pVM The VM handle.
3723	* @param fOr The CR4 OR mask.
3724	* @param fAnd The CR4 AND mask.
3725	*/
3726	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3727	{
3728	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3729	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3730
3731	pVM->cpum.s.CR4.OrMask &= fAnd;
3732	pVM->cpum.s.CR4.OrMask \|= fOr;
3733
3734	return VINF_SUCCESS;
3735	}
3736
3737
3738	/**
3739	* Gets a pointer to the array of standard CPUID leaves.
3740	*
3741	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3742	*
3743	* @returns Pointer to the standard CPUID leaves (read-only).
3744	* @param pVM The VM handle.
3745	* @remark Intended for PATM.
3746	*/
3747	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3748	{
3749	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3750	}
3751
3752
3753	/**
3754	* Gets a pointer to the array of extended CPUID leaves.
3755	*
3756	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3757	*
3758	* @returns Pointer to the extended CPUID leaves (read-only).
3759	* @param pVM The VM handle.
3760	* @remark Intended for PATM.
3761	*/
3762	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3763	{
3764	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3765	}
3766
3767
3768	/**
3769	* Gets a pointer to the array of centaur CPUID leaves.
3770	*
3771	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3772	*
3773	* @returns Pointer to the centaur CPUID leaves (read-only).
3774	* @param pVM The VM handle.
3775	* @remark Intended for PATM.
3776	*/
3777	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3778	{
3779	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3780	}
3781
3782
3783	/**
3784	* Gets a pointer to the default CPUID leaf.
3785	*
3786	* @returns Pointer to the default CPUID leaf (read-only).
3787	* @param pVM The VM handle.
3788	* @remark Intended for PATM.
3789	*/
3790	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3791	{
3792	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3793	}
3794
3795
3796	/**
3797	* Transforms the guest CPU state to raw-ring mode.
3798	*
3799	* This function will change the any of the cs and ss register with DPL=0 to DPL=1.
3800	*
3801	* @returns VBox status. (recompiler failure)
3802	* @param pVCpu The VMCPU handle.
3803	* @param pCtxCore The context core (for trap usage).
3804	* @see @ref pg_raw
3805	*/
3806	VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
3807	{
3808	PVM pVM = pVCpu->CTX_SUFF(pVM);
3809
3810	Assert(!pVCpu->cpum.s.fRawEntered);
3811	Assert(!pVCpu->cpum.s.fRemEntered);
3812	if (!pCtxCore)
3813	pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
3814
3815	/*
3816	* Are we in Ring-0?
3817	*/
3818	if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
3819	&& !pCtxCore->eflags.Bits.u1VM)
3820	{
3821	/*
3822	* Enter execution mode.
3823	*/
3824	PATMRawEnter(pVM, pCtxCore);
3825
3826	/*
3827	* Set CPL to Ring-1.
3828	*/
3829	pCtxCore->ss \|= 1;
3830	if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
3831	pCtxCore->cs \|= 1;
3832	}
3833	else
3834	{
3835	AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 \|\| pCtxCore->eflags.Bits.u1VM,
3836	("ring-1 code not supported\n"));
3837	/*
3838	* PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
3839	*/
3840	PATMRawEnter(pVM, pCtxCore);
3841	}
3842
3843	/*
3844	* Invalidate the hidden registers.
3845	*/
3846	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3847
3848	/*
3849	* Assert sanity.
3850	*/
3851	AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
3852	AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
3853	\|\| pCtxCore->eflags.Bits.u1VM,
3854	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3855	Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)) == (X86_CR0_PG \| X86_CR0_PE \| X86_CR0_WP));
3856
3857	pCtxCore->eflags.u32 \|= X86_EFL_IF; /* paranoia */
3858
3859	pVCpu->cpum.s.fRawEntered = true;
3860	return VINF_SUCCESS;
3861	}
3862
3863
3864	/**
3865	* Transforms the guest CPU state from raw-ring mode to correct values.
3866	*
3867	* This function will change any selector registers with DPL=1 to DPL=0.
3868	*
3869	* @returns Adjusted rc.
3870	* @param pVCpu The VMCPU handle.
3871	* @param rc Raw mode return code
3872	* @param pCtxCore The context core (for trap usage).
3873	* @see @ref pg_raw
3874	*/
3875	VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
3876	{
3877	PVM pVM = pVCpu->CTX_SUFF(pVM);
3878
3879	/*
3880	* Don't leave if we've already left (in GC).
3881	*/
3882	Assert(pVCpu->cpum.s.fRawEntered);
3883	Assert(!pVCpu->cpum.s.fRemEntered);
3884	if (!pVCpu->cpum.s.fRawEntered)
3885	return rc;
3886	pVCpu->cpum.s.fRawEntered = false;
3887
3888	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3889	if (!pCtxCore)
3890	pCtxCore = CPUMCTX2CORE(pCtx);
3891	Assert(pCtxCore->eflags.Bits.u1VM \|\| (pCtxCore->ss & X86_SEL_RPL));
3892	AssertMsg(pCtxCore->eflags.Bits.u1VM \|\| pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
3893	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3894
3895	/*
3896	* Are we executing in raw ring-1?
3897	*/
3898	if ( (pCtxCore->ss & X86_SEL_RPL) == 1
3899	&& !pCtxCore->eflags.Bits.u1VM)
3900	{
3901	/*
3902	* Leave execution mode.
3903	*/
3904	PATMRawLeave(pVM, pCtxCore, rc);
3905	/* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
3906	/** @todo See what happens if we remove this. */
3907	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3908	pCtxCore->ds &= ~X86_SEL_RPL;
3909	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3910	pCtxCore->es &= ~X86_SEL_RPL;
3911	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3912	pCtxCore->fs &= ~X86_SEL_RPL;
3913	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3914	pCtxCore->gs &= ~X86_SEL_RPL;
3915
3916	/*
3917	* Ring-1 selector => Ring-0.
3918	*/
3919	pCtxCore->ss &= ~X86_SEL_RPL;
3920	if ((pCtxCore->cs & X86_SEL_RPL) == 1)
3921	pCtxCore->cs &= ~X86_SEL_RPL;
3922	}
3923	else
3924	{
3925	/*
3926	* PATM is taking care of the IOPL and IF flags for us.
3927	*/
3928	PATMRawLeave(pVM, pCtxCore, rc);
3929	if (!pCtxCore->eflags.Bits.u1VM)
3930	{
3931	/** @todo See what happens if we remove this. */
3932	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3933	pCtxCore->ds &= ~X86_SEL_RPL;
3934	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3935	pCtxCore->es &= ~X86_SEL_RPL;
3936	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3937	pCtxCore->fs &= ~X86_SEL_RPL;
3938	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3939	pCtxCore->gs &= ~X86_SEL_RPL;
3940	}
3941	}
3942
3943	return rc;
3944	}
3945
3946
3947	/**
3948	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3949	*
3950	* Only REM should ever call this function!
3951	*
3952	* @returns The changed flags.
3953	* @param pVCpu The VMCPU handle.
3954	* @param puCpl Where to return the current privilege level (CPL).
3955	*/
3956	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3957	{
3958	Assert(!pVCpu->cpum.s.fRawEntered);
3959	Assert(!pVCpu->cpum.s.fRemEntered);
3960
3961	/*
3962	* Get the CPL first.
3963	*/
3964	*puCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
3965
3966	/*
3967	* Get and reset the flags, leaving CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID set.
3968	*/
3969	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3970	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* leave it set */
3971
3972	/** @todo change the switcher to use the fChanged flags. */
3973	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3974	{
3975	fFlags \|= CPUM_CHANGED_FPU_REM;
3976	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3977	}
3978
3979	pVCpu->cpum.s.fRemEntered = true;
3980	return fFlags;
3981	}
3982
3983
3984	/**
3985	* Leaves REM and works the CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID flag.
3986	*
3987	* @param pVCpu The virtual CPU handle.
3988	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3989	* registers.
3990	*/
3991	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3992	{
3993	Assert(!pVCpu->cpum.s.fRawEntered);
3994	Assert(pVCpu->cpum.s.fRemEntered);
3995
3996	if (fNoOutOfSyncSels)
3997	pVCpu->cpum.s.fChanged &= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3998	else
3999	pVCpu->cpum.s.fChanged \|= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
4000
4001	pVCpu->cpum.s.fRemEntered = false;
4002	}
4003

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 31879

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