VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 577

Last change on this file since 577 was 465, checked in by vboxsync, 18 years ago

Added code to emulate rdtsc in the guest context. (disabled)
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 72.7 KB
Line 
1/* $Id: CPUM.cpp 465 2007-01-31 15:05:57Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager)
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_CPUM
27#include <VBox/cpum.h>
28#include <VBox/cpumdis.h>
29#include <VBox/pgm.h>
30#include <VBox/mm.h>
31#include <VBox/selm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/ssm.h>
35#include "CPUMInternal.h"
36#include <VBox/vm.h>
37
38#include <VBox/param.h>
39#include <VBox/dis.h>
40#include <VBox/err.h>
41#include <VBox/log.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <iprt/system.h>
46#include "x86context.h"
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51/** The saved state version. */
52#define CPUM_SAVED_STATE_VERSION 3
53
54
55/*******************************************************************************
56* Structures and Typedefs *
57*******************************************************************************/
58
59/**
60 * What kind of cpu info dump to performe.
61 */
62typedef enum CPUMDUMPTYPE
63{
64 CPUMDUMPTYPE_TERSE,
65 CPUMDUMPTYPE_DEFAULT,
66 CPUMDUMPTYPE_VERBOSE
67
68} CPUMDUMPTYPE, *PCPUMDUMPTYPE;
69
70
71/*******************************************************************************
72* Internal Functions *
73*******************************************************************************/
74static int cpumR3CpuIdInit(PVM pVM);
75static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
76static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
77static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
78static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
79static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
80static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
81static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
82
83
84/**
85 * Initializes the CPUM.
86 *
87 * @returns VBox status code.
88 * @param pVM The VM to operate on.
89 */
90CPUMR3DECL(int) CPUMR3Init(PVM pVM)
91{
92 LogFlow(("CPUMR3Init\n"));
93
94 /*
95 * Assert alignment and sizes.
96 */
97 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
98 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
99
100 /*
101 * Setup any fixed pointers and offsets.
102 */
103 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
104 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
105 pVM->cpum.s.pHyperCoreHC = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
106
107 /* Hidden selector registers are invalid by default. */
108 pVM->cpum.s.fValidHiddenSelRegs = false;
109
110 /*
111 * Check that the CPU supports the minimum features we require.
112 */
113 /** @todo check the contract! */
114 if (!ASMHasCpuId())
115 {
116 Log(("The CPU doesn't support CPUID!\n"));
117 return VERR_UNSUPPORTED_CPU;
118 }
119 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
120
121 /* Setup the CR4 AND and OR masks used in the switcher */
122 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
123 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
124 {
125 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
126 /* No FXSAVE implies no SSE */
127 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
128 pVM->cpum.s.CR4.OrMask = 0;
129 }
130 else
131 {
132 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
133 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
134 }
135
136#ifdef CPUM_TRAP_RDTSC
137 pVM->cpum.s.CR4.OrMask |= X86_CR4_TSD;
138#endif
139
140 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
141 {
142 Log(("The CPU doesn't support MMX!\n"));
143 return VERR_UNSUPPORTED_CPU;
144 }
145 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
146 {
147 Log(("The CPU doesn't support TSC!\n"));
148 return VERR_UNSUPPORTED_CPU;
149 }
150 /* Bogus on AMD? */
151 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
152 {
153 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
154 }
155
156 /*
157 * Setup hypervisor startup values.
158 */
159
160 /*
161 * Register saved state data item.
162 */
163 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
164 NULL, cpumR3Save, NULL,
165 NULL, cpumR3Load, NULL);
166 if (VBOX_FAILURE(rc))
167 return rc;
168
169 /*
170 * Register info handlers.
171 */
172 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
173 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
174 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
175 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
176 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leafs.", &cpumR3CpuIdInfo);
177
178 /*
179 * Initialize the Guest CPU state.
180 */
181 rc = cpumR3CpuIdInit(pVM);
182 if (VBOX_FAILURE(rc))
183 return rc;
184 CPUMR3Reset(pVM);
185 return VINF_SUCCESS;
186}
187
188
189/**
190 * Initializes the emulated CPU's cpuid information.
191 *
192 * @returns VBox status code.
193 * @param pVM The VM to operate on.
194 */
195static int cpumR3CpuIdInit(PVM pVM)
196{
197 PCPUM pCPUM = &pVM->cpum.s;
198 uint32_t i;
199
200 /*
201 * Get the host CPUIDs.
202 */
203 for (i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
204 ASMCpuId(i,
205 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
206 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
207 for (i = 0; i < ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
208 ASMCpuId(0x80000000 + i,
209 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
210 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
211
212 /*
213 * Only report features we can support.
214 */
215 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
216 //| X86_CPUID_FEATURE_EDX_VME - recompiler doesn't do this.
217 | X86_CPUID_FEATURE_EDX_DE
218 | X86_CPUID_FEATURE_EDX_PSE
219 | X86_CPUID_FEATURE_EDX_TSC
220 | X86_CPUID_FEATURE_EDX_MSR
221 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
222 | X86_CPUID_FEATURE_EDX_MCE
223 | X86_CPUID_FEATURE_EDX_CX8
224 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
225 | X86_CPUID_FEATURE_EDX_SEP
226 //| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
227 | X86_CPUID_FEATURE_EDX_PGE
228 //| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
229 | X86_CPUID_FEATURE_EDX_CMOV
230 //| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
231 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
232 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
233 //| X86_CPUID_FEATURE_EDX_CLFSH - no CLFLUSH instruction.
234 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
235 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
236 | X86_CPUID_FEATURE_EDX_MMX
237 | X86_CPUID_FEATURE_EDX_FXSR
238 | X86_CPUID_FEATURE_EDX_SSE
239 | X86_CPUID_FEATURE_EDX_SSE2
240 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
241 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
242 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
243 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
244 | 0;
245 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
246 | X86_CPUID_FEATURE_ECX_MONITOR
247 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
248 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
249 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
250 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
251 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
252 | 0;
253
254#if 1 /* we didn't used to do this, but I guess we should */
255 /* ASSUMES that this is ALLWAYS the AMD define feature set if present. */
256 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
257 //| X86_CPUID_AMD_FEATURE_EDX_VME - recompiler doesn't do this.
258 | X86_CPUID_AMD_FEATURE_EDX_DE
259 | X86_CPUID_AMD_FEATURE_EDX_PSE
260 | X86_CPUID_AMD_FEATURE_EDX_TSC
261 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
262 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
263 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
264 | X86_CPUID_AMD_FEATURE_EDX_CX8
265 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
266 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
267 //| X86_CPUID_AMD_FEATURE_EDX_SEP
268 //| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
269 | X86_CPUID_AMD_FEATURE_EDX_PGE
270 //| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
271 | X86_CPUID_AMD_FEATURE_EDX_CMOV
272 | X86_CPUID_AMD_FEATURE_EDX_PAT
273 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
274 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
275 | X86_CPUID_AMD_FEATURE_EDX_MMX
276 | X86_CPUID_AMD_FEATURE_EDX_FXSR
277 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
278 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - definintly not.
279 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
280 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
281 | 0;
282 pCPUM->aGuestCpuIdExt[1].ecx &= 0//X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
283 | 0;
284#endif
285
286#if 0 /* this is what we used to do. */
287 /*
288 * Set BrandIndex=0, CLFLUSH-line-size=0, Num-Logical-Cpus=0 and APIC-ID=0.
289 */
290 pCPUM->aGuestCpuIdStd[1].ebx = 0;
291
292 /*
293 * Set the max standard index to 2.
294 */
295 pCPUM->aGuestCpuIdStd[0].eax = 2;
296 pCPUM->GuestCpuIdDef = pCPUM->aGuestCpuIdStd[2]; /** @todo this default is *NOT* right for AMD, only Intel CPUs. (see tstInlineAsm) */
297
298#else /* this is what we probably should do */
299 /*
300 * Hide HTT, multicode, SMP, whatever.
301 * (APIC-ID := 0 and #LogCpus := 0)
302 */
303 pCPUM->aGuestCpuIdStd[1].ebx = 0x0000ffff;
304
305 /*
306 * Determin the default value and limit it the number of entries.
307 * Intel returns values of the highest standard function, while AMD returns zeros.
308 */
309 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
310 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
311 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
312
313 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
314 pCPUM->aGuestCpuIdStd[0].eax = 2;
315
316 if (pCPUM->aGuestCpuIdExt[0].eax > 0x80000004)
317 pCPUM->aGuestCpuIdExt[0].eax = 0x80000004;
318
319#endif
320
321 /*
322 * Assign defaults to the entries we chopped off.
323 */
324 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
325 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
326 for (i = pCPUM->aGuestCpuIdExt[0].eax - 0x80000000 + 1; i < ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
327 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
328
329 /*
330 * Load CPUID overrides from configuration.
331 */
332 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
333 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
334 for (;;)
335 {
336 while (cElements-- < 0)
337 {
338 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
339 if (pNode)
340 {
341 uint32_t u32;
342 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
343 if (VBOX_SUCCESS(rc))
344 pCpuId->eax = u32;
345 else
346 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
347
348 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
349 if (VBOX_SUCCESS(rc))
350 pCpuId->ebx = u32;
351 else
352 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
353
354 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
355 if (VBOX_SUCCESS(rc))
356 pCpuId->ecx = u32;
357 else
358 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
359
360 rc = CFGMR3QueryU32(pNode, "edx", &u32);
361 if (VBOX_SUCCESS(rc))
362 pCpuId->edx = u32;
363 else
364 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
365 }
366 }
367
368 /* next */
369 if (i & 0x80000000)
370 break;
371 pCpuId = &pCPUM->aGuestCpuIdExt[0];
372 cElements = ELEMENTS(pCPUM->aGuestCpuIdExt);
373 i = 0x80000000;
374 }
375
376 /*
377 * Log the cpuid and we're good.
378 */
379 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
380 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
381 LogRel(("************************* CPUID dump ************************\n"));
382 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
383 LogRel(("\n"));
384 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
385 LogRel(("******************** End of CPUID dump **********************\n"));
386 return VINF_SUCCESS;
387}
388
389
390
391
392/**
393 * Applies relocations to data and code managed by this
394 * component. This function will be called at init and
395 * whenever the VMM need to relocate it self inside the GC.
396 *
397 * The CPUM will update the addresses used by the switcher.
398 *
399 * @param pVM The VM.
400 */
401CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
402{
403 LogFlow(("CPUMR3Relocate\n"));
404 /*
405 * Switcher pointers.
406 */
407 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
408 pVM->cpum.s.pHyperCoreGC = MMHyperHC2GC(pVM, pVM->cpum.s.pHyperCoreHC);
409}
410
411
412/**
413 * Queries the pointer to the internal CPUMCTX structure
414 *
415 * @returns VBox status code.
416 * @param pVM Handle to the virtual machine.
417 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
418 */
419CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx)
420{
421 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
422 /*
423 * Store the address. (Later we might check how's calling, thus the RC.)
424 */
425 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
426 return VINF_SUCCESS;
427}
428
429
430/**
431 * Terminates the CPUM.
432 *
433 * Termination means cleaning up and freeing all resources,
434 * the VM it self is at this point powered off or suspended.
435 *
436 * @returns VBox status code.
437 * @param pVM The VM to operate on.
438 */
439CPUMR3DECL(int) CPUMR3Term(PVM pVM)
440{
441 /** @todo */
442 return 0;
443}
444
445
446/**
447 * Resets the CPU.
448 *
449 * @returns VINF_SUCCESS.
450 * @param pVM The VM handle.
451 */
452CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
453{
454 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
455
456 /*
457 * Initialize everything to ZERO first.
458 */
459 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
460 memset(pCtx, 0, sizeof(*pCtx));
461 pVM->cpum.s.fUseFlags = fUseFlags;
462
463 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
464 pCtx->eip = 0x0000fff0;
465 pCtx->edx = 0x00000600; /* P6 processor */
466 pCtx->eflags.Bits.u1Reserved0 = 1;
467
468 pCtx->cs = 0xf000;
469 pCtx->csHid.u32Base = 0xffff0000;
470 pCtx->csHid.u32Limit = 0x0000ffff;
471 pCtx->dsHid.u32Limit = 0x0000ffff;
472 pCtx->esHid.u32Limit = 0x0000ffff;
473 pCtx->fsHid.u32Limit = 0x0000ffff;
474 pCtx->gsHid.u32Limit = 0x0000ffff;
475 pCtx->ssHid.u32Limit = 0x0000ffff;
476 pCtx->idtr.cbIdt = 0xffff;
477 pCtx->gdtr.cbGdt = 0xffff;
478 pCtx->ldtrHid.u32Limit = 0xffff;
479 pCtx->ldtrHid.Attr.u = X86_DESC_P;
480 pCtx->trHid.u32Limit = 0xffff;
481 pCtx->trHid.Attr.u = X86_DESC_P;
482
483 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
484 pCtx->fpu.FCW = 0x37f;
485}
486
487
488
489/**
490 * Execute state save operation.
491 *
492 * @returns VBox status code.
493 * @param pVM VM Handle.
494 * @param pSSM SSM operation handle.
495 */
496static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
497{
498 /*
499 * Save.
500 */
501 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
502 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
503 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
504 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
505
506 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
507 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
508
509 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
510 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
511
512 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
513
514 /* Add the cpuid for checking that the cpu is unchanged. */
515 uint32_t au32CpuId[8] = {0};
516 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
517 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
518 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
519}
520
521
522/**
523 * Execute state load operation.
524 *
525 * @returns VBox status code.
526 * @param pVM VM Handle.
527 * @param pSSM SSM operation handle.
528 * @param u32Version Data layout version.
529 */
530static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
531{
532 /*
533 * Validate version.
534 */
535 if (u32Version != CPUM_SAVED_STATE_VERSION)
536 {
537 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
538 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
539 }
540
541 /*
542 * Restore.
543 */
544 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
545 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
546 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
547 pVM->cpum.s.Hyper.cr3 = uCR3;
548 pVM->cpum.s.Hyper.esp = uESP;
549 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
550 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
551 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
552
553 uint32_t cElements;
554 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
555 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
556 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
557 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
558
559 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
560 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
561 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
562 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
563
564 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
565
566 /*
567 * Check that the basic cpuid id information is unchanged.
568 */
569 uint32_t au32CpuId[8] = {0};
570 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
571 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
572 uint32_t au32CpuIdSaved[8];
573 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
574 if (VBOX_SUCCESS(rc))
575 {
576 /* Ignore APIC ID (AMD specs). */
577 au32CpuId[5] &= ~0xff000000;
578 au32CpuIdSaved[5] &= ~0xff000000;
579 /* Ignore the number of Logical CPUs (AMD specs). */
580 au32CpuId[5] &= ~0x00ff0000;
581 au32CpuIdSaved[5] &= ~0x00ff0000;
582
583 /* do the compare */
584 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
585 {
586 Log(("cpumR3Load: CpuId mismatch!\n"
587 "Saved=%.*Vhxs\n"
588 "Real =%.*Vhxs\n",
589 sizeof(au32CpuIdSaved), au32CpuIdSaved,
590 sizeof(au32CpuId), au32CpuId));
591 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
592 }
593 }
594
595 return rc;
596}
597
598
599/**
600 * Formats the EFLAGS value into mnemonics.
601 *
602 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
603 * @param efl The EFLAGS value.
604 */
605static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
606{
607 /*
608 * Format the flags.
609 */
610 static struct
611 {
612 const char *pszSet; const char *pszClear; uint32_t fFlag;
613 } s_aFlags[] =
614 {
615 { "vip",NULL, X86_EFL_VIP },
616 { "vif",NULL, X86_EFL_VIF },
617 { "ac", NULL, X86_EFL_AC },
618 { "vm", NULL, X86_EFL_VM },
619 { "rf", NULL, X86_EFL_RF },
620 { "nt", NULL, X86_EFL_NT },
621 { "ov", "nv", X86_EFL_OF },
622 { "dn", "up", X86_EFL_DF },
623 { "ei", "di", X86_EFL_IF },
624 { "tf", NULL, X86_EFL_TF },
625 { "nt", "pl", X86_EFL_SF },
626 { "nz", "zr", X86_EFL_ZF },
627 { "ac", "na", X86_EFL_AF },
628 { "po", "pe", X86_EFL_PF },
629 { "cy", "nc", X86_EFL_CF },
630 };
631 char *psz = pszEFlags;
632 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
633 {
634 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
635 if (pszAdd)
636 {
637 strcpy(psz, pszAdd);
638 psz += strlen(pszAdd);
639 *psz++ = ' ';
640 }
641 }
642 psz[-1] = '\0';
643}
644
645
646/**
647 * Formats a full register dump.
648 *
649 * @param pCtx The context to format.
650 * @param pCtxCore The context core to format.
651 * @param pHlp Output functions.
652 * @param enmType The dump type.
653 * @param pszPrefix Register name prefix.
654 */
655static void cpumR3InfoOne(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
656{
657 /*
658 * Format the EFLAGS.
659 */
660 uint32_t efl = pCtxCore->eflags.u32;
661 char szEFlags[80];
662 cpumR3InfoFormatFlags(&szEFlags[0], efl);
663
664 /*
665 * Format the registers.
666 */
667 switch (enmType)
668 {
669 case CPUMDUMPTYPE_TERSE:
670 pHlp->pfnPrintf(pHlp,
671 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
672 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
673 "%scs=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
674 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
675 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
676 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
677 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
678 break;
679
680 case CPUMDUMPTYPE_DEFAULT:
681 pHlp->pfnPrintf(pHlp,
682 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
683 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
684 "%scs=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n"
685 "%scr0=%08x %scr2=%08x %scr3=%08x %scr4=%08x %sgdtr=%08x:%04x %sldtr=%04x\n"
686 ,
687 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
688 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
689 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
690 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl,
691 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
692 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
693 break;
694
695 case CPUMDUMPTYPE_VERBOSE:
696 pHlp->pfnPrintf(pHlp,
697 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
698 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
699 "%scs={%04x base=%08x limit=%08x flags=%08x} %sdr0=%08x %sdr1=%08x\n"
700 "%sds={%04x base=%08x limit=%08x flags=%08x} %sdr2=%08x %sdr3=%08x\n"
701 "%ses={%04x base=%08x limit=%08x flags=%08x} %sdr4=%08x %sdr5=%08x\n"
702 "%sfs={%04x base=%08x limit=%08x flags=%08x} %sdr6=%08x %sdr7=%08x\n"
703 "%sgs={%04x base=%08x limit=%08x flags=%08x} %scr0=%08x %scr2=%08x\n"
704 "%sss={%04x base=%08x limit=%08x flags=%08x} %scr3=%08x %scr4=%08x\n"
705 "%sgdtr=%08x:%04x %sidtr=%08x:%04x %seflags=%08x\n"
706 "%sldtr={%04x base=%08x limit=%08x flags=%08x}\n"
707 "%str ={%04x base=%08x limit=%08x flags=%08x}\n"
708 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
709 "%sFCW=%04x %sFSW=%04x %sFTW=%04x\n"
710 ,
711 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
712 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
713 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
714 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
715 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
716 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
717 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
718 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
719 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
720 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u32Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
721 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u32Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
722 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
723 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW);
724 break;
725 }
726}
727
728
729/**
730 * Display all cpu states and any other cpum info.
731 *
732 * @param pVM VM Handle.
733 * @param pHlp The info helper functions.
734 * @param pszArgs Arguments, ignored.
735 */
736static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
737{
738 cpumR3InfoGuest(pVM, pHlp, pszArgs);
739 cpumR3InfoHyper(pVM, pHlp, pszArgs);
740 cpumR3InfoHost(pVM, pHlp, pszArgs);
741}
742
743
744/**
745 * Parses the info argument.
746 *
747 * The argument starts with 'verbose', 'terse' or 'default' and then
748 * continues with the comment string.
749 *
750 * @param pszArgs The pointer to the argument string.
751 * @param penmType Where to store the dump type request.
752 * @param ppszComment Where to store the pointer to the comment string.
753 */
754static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
755{
756 if (!pszArgs)
757 {
758 *penmType = CPUMDUMPTYPE_DEFAULT;
759 *ppszComment = "";
760 }
761 else
762 {
763 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
764 {
765 pszArgs += 5;
766 *penmType = CPUMDUMPTYPE_VERBOSE;
767 }
768 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
769 {
770 pszArgs += 5;
771 *penmType = CPUMDUMPTYPE_TERSE;
772 }
773 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
774 {
775 pszArgs += 7;
776 *penmType = CPUMDUMPTYPE_DEFAULT;
777 }
778 else
779 *penmType = CPUMDUMPTYPE_DEFAULT;
780 *ppszComment = RTStrStripL(pszArgs);
781 }
782}
783
784
785/**
786 * Display the guest cpu state.
787 *
788 * @param pVM VM Handle.
789 * @param pHlp The info helper functions.
790 * @param pszArgs Arguments, ignored.
791 */
792static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
793{
794 CPUMDUMPTYPE enmType;
795 const char *pszComment;
796 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
797 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
798 cpumR3InfoOne(&pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
799}
800
801
802/**
803 * Display the hypervisor cpu state.
804 *
805 * @param pVM VM Handle.
806 * @param pHlp The info helper functions.
807 * @param pszArgs Arguments, ignored.
808 */
809static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
810{
811 CPUMDUMPTYPE enmType;
812 const char *pszComment;
813 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
814 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
815 cpumR3InfoOne(&pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreHC, pHlp, enmType, ".");
816}
817
818
819/**
820 * Display the host cpu state.
821 *
822 * @param pVM VM Handle.
823 * @param pHlp The info helper functions.
824 * @param pszArgs Arguments, ignored.
825 */
826static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
827{
828 CPUMDUMPTYPE enmType;
829 const char *pszComment;
830 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
831 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
832
833 /*
834 * Format the EFLAGS.
835 */
836 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
837#if HC_ARCH_BITS == 32
838 uint32_t efl = pCtx->eflags.u32;
839#else
840 uint64_t efl = pCtx->rflags;
841#endif
842 char szEFlags[80];
843 cpumR3InfoFormatFlags(&szEFlags[0], efl);
844
845 /*
846 * Format the registers.
847 */
848#if HC_ARCH_BITS == 32
849 pHlp->pfnPrintf(pHlp,
850 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
851 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
852 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
853 "cr0=%08x cr2=xxxxxxxx cr3=%08x cr4=%08x gdtr=%08x:%04x ldtr=%04x\n"
854 "dr0=%08x dr1=%08x dr2=%08x dr3=%08x dr6=%08x dr7=%08x\n"
855 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
856 ,
857 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
858 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
859 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
860 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
861 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
862 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, (RTSEL)pCtx->ldtr,
863 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
864#else /* 64-bit */
865 pHlp->pfnPrintf(pHlp,
866 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
867 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
868 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
869 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
870 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
871 "r14=%016RX64 r15=%016RX64\n"
872 "iopl=%d %31s\n"
873 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
874 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
875 "cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
876 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
877 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
878 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
879 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
880 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
881 ,
882 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
883 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
884 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
885 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
886 pCtx->r11, pCtx->r12, pCtx->r13,
887 pCtx->r14, pCtx->r15,
888 X86_EFL_GET_IOPL(efl), szEFlags,
889 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
890 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
891 pCtx->cr4, pCtx->cr8, pCtx->ldtr, pCtx->tr,
892 pCtx->dr0, pCtx->dr1, pCtx->dr2,
893 pCtx->dr3, pCtx->dr6, pCtx->dr7,
894 *(uint64_t *)&pCtx->gdtr[2], *(uint16_t *)&pCtx->gdtr[0], *(uint64_t *)&pCtx->idtr[2], *(uint16_t *)&pCtx->idtr[0],
895 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
896 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
897#endif
898}
899
900/**
901 * Get L1 cache / TLS associativity.
902 */
903static const char *getCacheAss(unsigned u, char *pszBuf)
904{
905 if (u == 0)
906 return "res0 ";
907 if (u == 1)
908 return "direct";
909 if (u >= 256)
910 return "???";
911
912 RTStrPrintf(pszBuf, 16, "%d way", u);
913 return pszBuf;
914}
915
916
917/**
918 * Get L2 cache soociativity.
919 */
920const char *getL2CacheAss(unsigned u)
921{
922 switch (u)
923 {
924 case 0: return "off ";
925 case 1: return "direct";
926 case 2: return "2 way ";
927 case 3: return "res3 ";
928 case 4: return "4 way ";
929 case 5: return "res5 ";
930 case 6: return "8 way ";
931 case 7: return "res7 ";
932 case 8: return "16 way";
933 case 9: return "res9 ";
934 case 10: return "res10 ";
935 case 11: return "res11 ";
936 case 12: return "res12 ";
937 case 13: return "res13 ";
938 case 14: return "res14 ";
939 case 15: return "fully ";
940 default:
941 return "????";
942 }
943}
944
945
946/**
947 * Display the guest CpuId leafs.
948 *
949 * @param pVM VM Handle.
950 * @param pHlp The info helper functions.
951 * @param pszArgs "terse", "default" or "verbose".
952 */
953static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
954{
955 /*
956 * Parse the argument.
957 */
958 unsigned iVerbosity = 1;
959 if (pszArgs)
960 {
961 pszArgs = RTStrStripL(pszArgs);
962 if (!strcmp(pszArgs, "terse"))
963 iVerbosity--;
964 else if (!strcmp(pszArgs, "verbose"))
965 iVerbosity++;
966 }
967
968 /*
969 * Start cracking.
970 */
971 CPUMCPUID Host;
972 CPUMCPUID Guest;
973 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
974
975 pHlp->pfnPrintf(pHlp,
976 " RAW Standard CPUIDs\n"
977 " Function eax ebx ecx edx\n");
978 for (unsigned i = 0; i <= ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
979 {
980 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
981 ASMCpuId(i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
982
983 pHlp->pfnPrintf(pHlp,
984 "Gst: %08x %08x %08x %08x %08x%s\n"
985 "Hst: %08x %08x %08x %08x\n",
986 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
987 i <= cStdMax ? "" : "*",
988 Host.eax, Host.ebx, Host.ecx, Host.edx);
989 }
990
991 /*
992 * If verbose, decode it.
993 */
994 if (iVerbosity)
995 {
996 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
997 pHlp->pfnPrintf(pHlp,
998 "Name: %.04s%.04s%.04s\n"
999 "Supports: 0-%x\n",
1000 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1001 }
1002
1003 /*
1004 * Get Features.
1005 */
1006 if (cStdMax >= 1 && iVerbosity)
1007 {
1008 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1009 uint32_t uEAX = Guest.eax;
1010
1011 pHlp->pfnPrintf(pHlp,
1012 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1013 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1014 "Stepping: %d\n"
1015 "APIC ID: %#04x\n"
1016 "Logical CPUs: %d\n"
1017 "CLFLUSH Size: %d\n"
1018 "Brand ID: %#04x\n",
1019 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1020 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1021 (uEAX >> 0) & 0xf,
1022 (Guest.ebx >> 24) & 0xff,
1023 (Guest.ebx >> 16) & 0xff,
1024 (Guest.ebx >> 8) & 0xff,
1025 (Guest.ebx >> 0) & 0xff);
1026 if (iVerbosity == 1)
1027 {
1028 uint32_t uEDX = Guest.edx;
1029 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1030 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1031 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1032 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1033 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1034 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1035 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1036 if (uEDX & BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1037 if (uEDX & BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1038 if (uEDX & BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1039 if (uEDX & BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1040 if (uEDX & BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1041 if (uEDX & BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1042 if (uEDX & BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1043 if (uEDX & BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1044 if (uEDX & BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1045 if (uEDX & BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1046 if (uEDX & BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1047 if (uEDX & BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1048 if (uEDX & BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1049 if (uEDX & BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1050 if (uEDX & BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1051 if (uEDX & BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1052 if (uEDX & BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1053 if (uEDX & BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1054 if (uEDX & BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1055 if (uEDX & BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1056 if (uEDX & BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1057 if (uEDX & BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1058 if (uEDX & BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1059 if (uEDX & BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1060 if (uEDX & BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1061 if (uEDX & BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1062 pHlp->pfnPrintf(pHlp, "\n");
1063
1064 uint32_t uECX = Guest.ecx;
1065 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1066 if (uECX & BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1067 if (uECX & BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1068 if (uECX & BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1069 if (uECX & BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1070 if (uECX & BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1071 if (uECX & BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1072 if (uECX & BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1073 if (uECX & BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1074 if (uECX & BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1075 if (uECX & BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1076 if (uECX & BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1077 if (uECX & BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1078 if (uECX & BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1079 if (uECX & BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1080 for (unsigned iBit = 14; iBit < 32; iBit++)
1081 if (uECX & BIT(iBit))
1082 pHlp->pfnPrintf(pHlp, " %d", iBit);
1083 pHlp->pfnPrintf(pHlp, "\n");
1084 }
1085 else
1086 {
1087 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1088
1089 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1090 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1091 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1092 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1093
1094 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1095 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1096 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1097 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1098 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1099 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1100 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1101 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1102 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1103 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1104 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1105 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1106 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1107 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1108 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1109 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1110 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1111 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1112 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1113 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1114 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1115 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1116 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1117 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1118 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1119 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1120 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1121 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1122 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1123 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1124 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1125 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1126 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1127
1128 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1129 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1130 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1131 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1132 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1133 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1134 pHlp->pfnPrintf(pHlp, "Enh. SpeedStep Tech = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1135 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1136 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved3, EcxHost.u1Reserved3);
1137 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1138 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1139 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1140 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u18Reserved5, EcxHost.u18Reserved5);
1141 }
1142 }
1143 if (cStdMax >= 2 && iVerbosity)
1144 {
1145 /** @todo */
1146 }
1147
1148 /*
1149 * Extended.
1150 * Implemented after AMD specs.
1151 */
1152 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1153
1154 pHlp->pfnPrintf(pHlp,
1155 "\n"
1156 " RAW Extended CPUIDs\n"
1157 " Function eax ebx ecx edx\n");
1158 for (unsigned i = 0; i <= ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1159 {
1160 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1161 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1162
1163 pHlp->pfnPrintf(pHlp,
1164 "Gst: %08x %08x %08x %08x %08x%s\n"
1165 "Hst: %08x %08x %08x %08x\n",
1166 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1167 i <= cExtMax ? "" : "*",
1168 Host.eax, Host.ebx, Host.ecx, Host.edx);
1169 }
1170
1171 /*
1172 * Understandable output
1173 */
1174 if (iVerbosity && cExtMax >= 0)
1175 {
1176 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1177 pHlp->pfnPrintf(pHlp,
1178 "Ext Name: %.4s%.4s%.4s\n"
1179 "Ext Supports: 0x80000000-%#010x\n",
1180 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1181 }
1182
1183 if (iVerbosity && cExtMax >= 1)
1184 {
1185 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1186 uint32_t uEAX = Guest.eax;
1187 pHlp->pfnPrintf(pHlp,
1188 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1189 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1190 "Stepping: %d\n"
1191 "Brand ID: %#05x\n",
1192 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1193 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1194 (uEAX >> 0) & 0xf,
1195 Guest.ebx & 0xfff);
1196
1197 if (iVerbosity == 1)
1198 {
1199 uint32_t uEDX = Guest.edx;
1200 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1201 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1202 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1203 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1204 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1205 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1206 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1207 if (uEDX & BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1208 if (uEDX & BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1209 if (uEDX & BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1210 if (uEDX & BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1211 if (uEDX & BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1212 if (uEDX & BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1213 if (uEDX & BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1214 if (uEDX & BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1215 if (uEDX & BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1216 if (uEDX & BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1217 if (uEDX & BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1218 if (uEDX & BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1219 if (uEDX & BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1220 if (uEDX & BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1221 if (uEDX & BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1222 if (uEDX & BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1223 if (uEDX & BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1224 if (uEDX & BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1225 if (uEDX & BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1226 if (uEDX & BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1227 if (uEDX & BIT(26)) pHlp->pfnPrintf(pHlp, " 26");
1228 if (uEDX & BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1229 if (uEDX & BIT(28)) pHlp->pfnPrintf(pHlp, " 29");
1230 if (uEDX & BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1231 if (uEDX & BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1232 if (uEDX & BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1233 pHlp->pfnPrintf(pHlp, "\n");
1234
1235 uint32_t uECX = Guest.ecx;
1236 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1237 if (uECX & BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1238 if (uECX & BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1239 if (uECX & BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1240 if (uECX & BIT(3)) pHlp->pfnPrintf(pHlp, " SVM");
1241 if (uECX & BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1242 for (unsigned iBit = 5; iBit < 32; iBit++)
1243 if (uECX & BIT(iBit))
1244 pHlp->pfnPrintf(pHlp, " %d", iBit);
1245 pHlp->pfnPrintf(pHlp, "\n");
1246 }
1247 else
1248 {
1249 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1250
1251 uint32_t uEdxGst = Guest.edx;
1252 uint32_t uEdxHst = Host.edx;
1253 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1254 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & BIT( 0)), !!(uEdxHst & BIT( 0)));
1255 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & BIT( 1)), !!(uEdxHst & BIT( 1)));
1256 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & BIT( 2)), !!(uEdxHst & BIT( 2)));
1257 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & BIT( 3)), !!(uEdxHst & BIT( 3)));
1258 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & BIT( 4)), !!(uEdxHst & BIT( 4)));
1259 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & BIT( 5)), !!(uEdxHst & BIT( 5)));
1260 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & BIT( 6)), !!(uEdxHst & BIT( 6)));
1261 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & BIT( 7)), !!(uEdxHst & BIT( 7)));
1262 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & BIT( 8)), !!(uEdxHst & BIT( 8)));
1263 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & BIT( 9)), !!(uEdxHst & BIT( 9)));
1264 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(10)), !!(uEdxHst & BIT(10)));
1265 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & BIT(11)), !!(uEdxHst & BIT(11)));
1266 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & BIT(12)), !!(uEdxHst & BIT(12)));
1267 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & BIT(13)), !!(uEdxHst & BIT(13)));
1268 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & BIT(14)), !!(uEdxHst & BIT(14)));
1269 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & BIT(15)), !!(uEdxHst & BIT(15)));
1270 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & BIT(16)), !!(uEdxHst & BIT(16)));
1271 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & BIT(17)), !!(uEdxHst & BIT(17)));
1272 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(18)), !!(uEdxHst & BIT(18)));
1273 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(19)), !!(uEdxHst & BIT(19)));
1274 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & BIT(20)), !!(uEdxHst & BIT(20)));
1275 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & BIT(21)), !!(uEdxHst & BIT(21)));
1276 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & BIT(22)), !!(uEdxHst & BIT(22)));
1277 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & BIT(23)), !!(uEdxHst & BIT(23)));
1278 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & BIT(24)), !!(uEdxHst & BIT(24)));
1279 pHlp->pfnPrintf(pHlp, "?? - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & BIT(25)), !!(uEdxHst & BIT(25)));
1280 pHlp->pfnPrintf(pHlp, "26 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(26)), !!(uEdxHst & BIT(26)));
1281 pHlp->pfnPrintf(pHlp, "27 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(27)), !!(uEdxHst & BIT(27)));
1282 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(28)), !!(uEdxHst & BIT(28)));
1283 pHlp->pfnPrintf(pHlp, "?? - AMD Long Mode = %d (%d)\n", !!(uEdxGst & BIT(29)), !!(uEdxHst & BIT(29)));
1284 pHlp->pfnPrintf(pHlp, "?? - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & BIT(30)), !!(uEdxHst & BIT(30)));
1285 pHlp->pfnPrintf(pHlp, "?? - AMD 3DNow = %d (%d)\n", !!(uEdxGst & BIT(31)), !!(uEdxHst & BIT(31)));
1286
1287 uint32_t uEcxGst = Guest.ecx;
1288 uint32_t uEcxHst = Host.ecx;
1289 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & BIT( 0)), !!(uEcxHst & BIT( 0)));
1290 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & BIT( 1)), !!(uEcxHst & BIT( 1)));
1291 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & BIT( 2)), !!(uEcxHst & BIT( 2)));
1292 pHlp->pfnPrintf(pHlp, "3 - Reserved = %d (%d)\n", !!(uEcxGst & BIT( 3)), !!(uEcxHst & BIT( 3)));
1293 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & BIT( 4)), !!(uEcxHst & BIT( 4)));
1294 pHlp->pfnPrintf(pHlp, "31:5 - Reserved = %#x (%#x)\n", uEcxGst >> 5, uEcxHst >> 5);
1295 }
1296 }
1297
1298 if (iVerbosity && cExtMax >= 2)
1299 {
1300 char szString[4*4*3+1] = {0};
1301 uint32_t *pu32 = (uint32_t *)szString;
1302 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1303 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1304 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1305 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1306 if (cExtMax >= 3)
1307 {
1308 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1309 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1310 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1311 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1312 }
1313 if (cExtMax >= 4)
1314 {
1315 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1316 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1317 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1318 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1319 }
1320 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1321 }
1322
1323 if (iVerbosity && cExtMax >= 5)
1324 {
1325 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1326 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1327 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1328 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1329 char sz1[32];
1330 char sz2[32];
1331
1332 pHlp->pfnPrintf(pHlp,
1333 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1334 "TLB 2/4M Data: %s %3d entries\n",
1335 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1336 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1337 pHlp->pfnPrintf(pHlp,
1338 "TLB 4K Instr/Uni: %s %3d entries\n"
1339 "TLB 4K Data: %s %3d entries\n",
1340 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1341 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1342 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1343 "L1 Instr Cache Lines Per Tag: %d\n"
1344 "L1 Instr Cache Associativity: %s\n"
1345 "L1 Instr Cache Size: %d KB\n",
1346 (uEDX >> 0) & 0xff,
1347 (uEDX >> 8) & 0xff,
1348 getCacheAss((uEDX >> 16) & 0xff, sz1),
1349 (uEDX >> 24) & 0xff);
1350 pHlp->pfnPrintf(pHlp,
1351 "L1 Data Cache Line Size: %d bytes\n"
1352 "L1 Data Cache Lines Per Tag: %d\n"
1353 "L1 Data Cache Associativity: %s\n"
1354 "L1 Data Cache Size: %d KB\n",
1355 (uECX >> 0) & 0xff,
1356 (uECX >> 8) & 0xff,
1357 getCacheAss((uECX >> 16) & 0xff, sz1),
1358 (uECX >> 24) & 0xff);
1359 }
1360
1361 if (iVerbosity && cExtMax >= 6)
1362 {
1363 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1364 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1365 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1366
1367 pHlp->pfnPrintf(pHlp,
1368 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1369 "L2 TLB 2/4M Data: %s %4d entries\n",
1370 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1371 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1372 pHlp->pfnPrintf(pHlp,
1373 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1374 "L2 TLB 4K Data: %s %4d entries\n",
1375 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1376 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1377 pHlp->pfnPrintf(pHlp,
1378 "L2 Cache Line Size: %d bytes\n"
1379 "L2 Cache Lines Per Tag: %d\n"
1380 "L2 Cache Associativity: %s\n"
1381 "L2 Cache Size: %d KB\n",
1382 (uEDX >> 0) & 0xff,
1383 (uEDX >> 8) & 0xf,
1384 getL2CacheAss((uEDX >> 12) & 0xf),
1385 (uEDX >> 16) & 0xffff);
1386 }
1387
1388 if (iVerbosity && cExtMax >= 7)
1389 {
1390 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1391
1392 pHlp->pfnPrintf(pHlp, "APM Features: ");
1393 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1394 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1395 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1396 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1397 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1398 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1399 for (unsigned iBit = 6; iBit < 32; iBit++)
1400 if (uEDX & BIT(iBit))
1401 pHlp->pfnPrintf(pHlp, " %d", iBit);
1402 pHlp->pfnPrintf(pHlp, "\n");
1403 }
1404
1405 if (iVerbosity && cExtMax >= 8)
1406 {
1407 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1408 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1409
1410 pHlp->pfnPrintf(pHlp,
1411 "Physical Address Width: %d bits\n"
1412 "Virtual Address Width: %d bits\n",
1413 (uEAX >> 0) & 0xff,
1414 (uEAX >> 8) & 0xff);
1415 pHlp->pfnPrintf(pHlp,
1416 "Physical Core Count: %d\n",
1417 (uECX >> 0) & 0xff);
1418 }
1419}
1420
1421
1422/**
1423 * Structure used when disassembling and instructions in DBGF.
1424 * This is used so the reader function can get the stuff it needs.
1425 */
1426typedef struct CPUMDISASSTATE
1427{
1428 /** Pointer to the CPU structure. */
1429 PDISCPUSTATE pCpu;
1430 /** The VM handle. */
1431 PVM pVM;
1432 /** Pointer to the first byte in the segemnt. */
1433 RTGCUINTPTR GCPtrSegBase;
1434 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1435 RTGCUINTPTR GCPtrSegEnd;
1436 /** The size of the segment minus 1. */
1437 RTGCUINTPTR cbSegLimit;
1438 /** Pointer to the current page - HC Ptr. */
1439 void *pvPageHC;
1440 /** Pointer to the current page - GC Ptr. */
1441 RTGCPTR pvPageGC;
1442 /** The rc of the operation.
1443 *
1444 * @todo r=bird: it's rather annoying that we have to keep track of the status code of the operation.
1445 * When we've got time we should adjust the disassembler to use VBox status codes and not
1446 * boolean returns.
1447 */
1448 int rc;
1449} CPUMDISASSTATE, *PCPUMDISASSTATE;
1450
1451
1452/**
1453 * Instruction reader.
1454 *
1455 * @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
1456 * @param PtrSrc Address to read from.
1457 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1458 * @param pu8Dst Where to store the bytes.
1459 * @param cbRead Number of bytes to read.
1460 * @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
1461 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1462 * @todo r=bird: The status code should be an int. The PtrSrc should *NOT* be a RTHCUINTPTR. The uDisCpu could just as well be
1463 * declared as what it actually is a PDISCPUSTATE.
1464 */
1465static DECLCALLBACK(int32_t) cpumR3DisasInstrRead(RTHCUINTPTR PtrSrc, uint8_t *pu8Dst, uint32_t cbRead, RTHCUINTPTR uDisCpu)
1466{
1467 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1468 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->dwUserData[0]; /** @todo r=bird: Invalid prefix, dw='double word' which it isn't. Besides it's an array too. And btw. RTHCUINTPTR isn't the right thing either in a 32-bit host 64-bit guest situation */
1469 Assert(cbRead > 0);
1470 for (;;)
1471 {
1472 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1473
1474 /* Need to update the page translation? */
1475 if ( !pState->pvPageHC
1476 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1477 {
1478 /* translate the address */
1479 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1480 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1481 {
1482 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1483 if (!pState->pvPageHC)
1484 pState->rc = VERR_INVALID_POINTER;
1485 }
1486 else
1487 pState->rc = PGMPhysGCPtr2HCPtr(pState->pVM, pState->pvPageGC, &pState->pvPageHC);
1488 if (VBOX_FAILURE(pState->rc))
1489 {
1490 pState->pvPageHC = NULL;
1491 return pState->rc;
1492 }
1493 }
1494
1495 /* check the segemnt limit */
1496 if (PtrSrc > pState->cbSegLimit)
1497 return pState->rc = VERR_OUT_OF_SELECTOR_BOUNDS;
1498
1499 /* calc how much we can read */
1500 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1501 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1502 if (cb > cbSeg && !cbSeg)
1503 cb = cbSeg;
1504 if (cb > cbRead)
1505 cb = cbRead;
1506
1507 /* read and advance */
1508 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1509 cbRead -= cb;
1510 if (!cbRead)
1511 return VINF_SUCCESS;
1512 pu8Dst += cb;
1513 PtrSrc += cb;
1514 }
1515}
1516
1517
1518/**
1519 * Disassemble an instruction and return the information in the provided structure.
1520 *
1521 * @returns VBox status code.
1522 * @param pVM VM Handle
1523 * @param pCtx CPU context
1524 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1525 * @param pCpu Disassembly state
1526 * @param pszPrefix String prefix for logging (debug only)
1527 *
1528 */
1529CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1530{
1531 CPUMDISASSTATE State;
1532 int rc;
1533
1534 State.pCpu = pCpu;
1535 State.pvPageGC = 0;
1536 State.pvPageHC = NULL;
1537 State.rc = VINF_SUCCESS;
1538 State.pVM = pVM;
1539 /*
1540 * Get selector information.
1541 */
1542 if (pCtx->eflags.Bits.u1VM == 0)
1543 {
1544 if (CPUMAreHiddenSelRegsValid(pVM))
1545 {
1546 State.GCPtrSegBase = pCtx->csHid.u32Base;
1547 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u32Base;
1548 State.cbSegLimit = pCtx->csHid.u32Limit;
1549 pCpu->mode = pCtx->csHid.Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1550 }
1551 else
1552 {
1553 SELMSELINFO SelInfo;
1554
1555 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1556 if (!VBOX_SUCCESS(rc))
1557 {
1558 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1559 return rc;
1560 }
1561
1562 /*
1563 * Validate the selector.
1564 */
1565 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1566 if (!VBOX_SUCCESS(rc))
1567 {
1568 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1569 return rc;
1570 }
1571 State.GCPtrSegBase = SelInfo.GCPtrBase;
1572 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1573 State.cbSegLimit = SelInfo.cbLimit;
1574 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1575 }
1576 }
1577 else
1578 {
1579 /* V86 mode */
1580 pCpu->mode = CPUMODE_16BIT; /* @todo */
1581 State.GCPtrSegBase = pCtx->cs * 16;
1582 State.GCPtrSegEnd = 0xFFFFFFFF;
1583 State.cbSegLimit = 0xFFFFFFFF;
1584 }
1585
1586 /*
1587 * Disassemble the instruction.
1588 */
1589 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
1590 pCpu->dwUserData[0] = (uintptr_t)&State;
1591
1592 uint32_t cbInstr;
1593#ifdef LOG_ENABLED
1594 if (DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL))
1595 {
1596#else
1597 char szOutput[160];
1598 if (DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]))
1599 {
1600 /* log it */
1601 if (pszPrefix)
1602 Log(("%s: %s", pszPrefix, szOutput));
1603 else
1604 Log(("%s", szOutput));
1605#endif
1606 return VINF_SUCCESS;
1607 }
1608
1609 /* DISInstr failure */
1610 if (VBOX_FAILURE(State.rc))
1611 {
1612 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, State.rc));
1613 return State.rc;
1614 }
1615 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv\n", pCtx->cs, GCPtrPC));
1616 rc = VERR_GENERAL_FAILURE;
1617 return rc;
1618}
1619
1620
1621#ifdef DEBUG
1622/**
1623 * Disassemble an instruction and dump it to the log
1624 *
1625 * @returns VBox status code.
1626 * @param pVM VM Handle
1627 * @param pCtx CPU context
1628 * @param pc GC instruction pointer
1629 * @param prefix String prefix for logging
1630 * @deprecated Use DBGFR3DisasInstrCurrentLog().
1631 *
1632 */
1633CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
1634{
1635 DISCPUSTATE cpu;
1636
1637 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1638}
1639
1640/**
1641 * Disassemble an instruction and dump it to the log
1642 *
1643 * @returns VBox status code.
1644 * @param pVM VM Handle
1645 * @param pCtx CPU context
1646 * @param pc GC instruction pointer
1647 * @param prefix String prefix for logging
1648 * @param nrInstructions
1649 *
1650 */
1651CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
1652{
1653 for(int i=0;i<nrInstructions;i++)
1654 {
1655 DISCPUSTATE cpu;
1656
1657 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1658 pc += cpu.opsize;
1659 }
1660}
1661
1662#endif
1663
1664#ifdef DEBUG
1665/**
1666 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
1667 *
1668 * @internal
1669 */
1670CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
1671{
1672 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
1673}
1674#endif
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette