CPUM.cpp@ 771

Last change on this file since 771 was 771, checked in by vboxsync, 18 years ago
AMD-V was stil left disabled. Now enabled. Enabled sysenter/sysexit in hwaccm mode.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 72.9 KB

Line
1	/* $Id: CPUM.cpp 771 2007-02-08 10:41:53Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor(/Manager)
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_CPUM
27	#include <VBox/cpum.h>
28	#include <VBox/cpumdis.h>
29	#include <VBox/pgm.h>
30	#include <VBox/mm.h>
31	#include <VBox/selm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/patm.h>
34	#include <VBox/ssm.h>
35	#include "CPUMInternal.h"
36	#include <VBox/vm.h>
37
38	#include <VBox/param.h>
39	#include <VBox/dis.h>
40	#include <VBox/err.h>
41	#include <VBox/log.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/string.h>
45	#include <iprt/system.h>
46	#include "x86context.h"
47
48	/*******************************************************************************
49	* Defined Constants And Macros *
50	*******************************************************************************/
51	/** The saved state version. */
52	#define CPUM_SAVED_STATE_VERSION 3
53
54
55	/*******************************************************************************
56	* Structures and Typedefs *
57	*******************************************************************************/
58
59	/**
60	* What kind of cpu info dump to performe.
61	*/
62	typedef enum CPUMDUMPTYPE
63	{
64	CPUMDUMPTYPE_TERSE,
65	CPUMDUMPTYPE_DEFAULT,
66	CPUMDUMPTYPE_VERBOSE
67
68	} CPUMDUMPTYPE, *PCPUMDUMPTYPE;
69
70
71	/*******************************************************************************
72	* Internal Functions *
73	*******************************************************************************/
74	static int cpumR3CpuIdInit(PVM pVM);
75	static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
76	static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
77	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
78	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
79	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
80	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
81	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
82
83
84	/**
85	* Initializes the CPUM.
86	*
87	* @returns VBox status code.
88	* @param pVM The VM to operate on.
89	*/
90	CPUMR3DECL(int) CPUMR3Init(PVM pVM)
91	{
92	LogFlow(("CPUMR3Init\n"));
93
94	/*
95	* Assert alignment and sizes.
96	*/
97	AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
98	AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
99
100	/*
101	* Setup any fixed pointers and offsets.
102	*/
103	pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
104	pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
105	pVM->cpum.s.pHyperCoreHC = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
106
107	/* Hidden selector registers are invalid by default. */
108	pVM->cpum.s.fValidHiddenSelRegs = false;
109
110	/*
111	* Check that the CPU supports the minimum features we require.
112	*/
113	/** @todo check the contract! */
114	if (!ASMHasCpuId())
115	{
116	Log(("The CPU doesn't support CPUID!\n"));
117	return VERR_UNSUPPORTED_CPU;
118	}
119	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
120
121	/* Setup the CR4 AND and OR masks used in the switcher */
122	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
123	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
124	{
125	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
126	/* No FXSAVE implies no SSE */
127	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
128	pVM->cpum.s.CR4.OrMask = 0;
129	}
130	else
131	{
132	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
133	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
134	}
135
136	#ifdef CPUM_TRAP_RDTSC
137	pVM->cpum.s.CR4.OrMask \|= X86_CR4_TSD;
138	#endif
139
140	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
141	{
142	Log(("The CPU doesn't support MMX!\n"));
143	return VERR_UNSUPPORTED_CPU;
144	}
145	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
146	{
147	Log(("The CPU doesn't support TSC!\n"));
148	return VERR_UNSUPPORTED_CPU;
149	}
150	/* Bogus on AMD? */
151	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
152	{
153	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
154	}
155
156	/*
157	* Setup hypervisor startup values.
158	*/
159
160	/*
161	* Register saved state data item.
162	*/
163	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
164	NULL, cpumR3Save, NULL,
165	NULL, cpumR3Load, NULL);
166	if (VBOX_FAILURE(rc))
167	return rc;
168
169	/*
170	* Register info handlers.
171	*/
172	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
173	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
174	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
175	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
176	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leafs.", &cpumR3CpuIdInfo);
177
178	/*
179	* Initialize the Guest CPU state.
180	*/
181	rc = cpumR3CpuIdInit(pVM);
182	if (VBOX_FAILURE(rc))
183	return rc;
184	CPUMR3Reset(pVM);
185	return VINF_SUCCESS;
186	}
187
188
189	/**
190	* Initializes the emulated CPU's cpuid information.
191	*
192	* @returns VBox status code.
193	* @param pVM The VM to operate on.
194	*/
195	static int cpumR3CpuIdInit(PVM pVM)
196	{
197	PCPUM pCPUM = &pVM->cpum.s;
198	uint32_t i;
199
200	/*
201	* Get the host CPUIDs.
202	*/
203	for (i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
204	ASMCpuId(i,
205	&pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
206	&pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
207	for (i = 0; i < ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
208	ASMCpuId(0x80000000 + i,
209	&pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
210	&pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
211
212	/*
213	* Only report features we can support.
214	*/
215	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
216	//\| X86_CPUID_FEATURE_EDX_VME - recompiler doesn't do this.
217	\| X86_CPUID_FEATURE_EDX_DE
218	\| X86_CPUID_FEATURE_EDX_PSE
219	\| X86_CPUID_FEATURE_EDX_TSC
220	\| X86_CPUID_FEATURE_EDX_MSR
221	//\| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
222	\| X86_CPUID_FEATURE_EDX_MCE
223	\| X86_CPUID_FEATURE_EDX_CX8
224	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
225	/** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
226	//\| X86_CPUID_FEATURE_EDX_SEP
227	//\| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
228	\| X86_CPUID_FEATURE_EDX_PGE
229	//\| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
230	\| X86_CPUID_FEATURE_EDX_CMOV
231	//\| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
232	//\| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
233	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
234	//\| X86_CPUID_FEATURE_EDX_CLFSH - no CLFLUSH instruction.
235	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
236	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
237	\| X86_CPUID_FEATURE_EDX_MMX
238	\| X86_CPUID_FEATURE_EDX_FXSR
239	\| X86_CPUID_FEATURE_EDX_SSE
240	\| X86_CPUID_FEATURE_EDX_SSE2
241	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
242	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
243	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
244	//\| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
245	\| 0;
246	pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
247	\| X86_CPUID_FEATURE_ECX_MONITOR
248	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
249	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
250	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
251	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
252	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
253	\| 0;
254
255	#if 1 /* we didn't used to do this, but I guess we should */
256	/* ASSUMES that this is ALLWAYS the AMD define feature set if present. */
257	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
258	//\| X86_CPUID_AMD_FEATURE_EDX_VME - recompiler doesn't do this.
259	\| X86_CPUID_AMD_FEATURE_EDX_DE
260	\| X86_CPUID_AMD_FEATURE_EDX_PSE
261	\| X86_CPUID_AMD_FEATURE_EDX_TSC
262	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
263	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
264	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
265	\| X86_CPUID_AMD_FEATURE_EDX_CX8
266	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
267	/** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
268	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
269	//\| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
270	\| X86_CPUID_AMD_FEATURE_EDX_PGE
271	//\| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
272	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
273	\| X86_CPUID_AMD_FEATURE_EDX_PAT
274	//\| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
275	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
276	\| X86_CPUID_AMD_FEATURE_EDX_MMX
277	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
278	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
279	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - definintly not.
280	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
281	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
282	\| 0;
283	pCPUM->aGuestCpuIdExt[1].ecx &= 0//X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
284	\| 0;
285	#endif
286
287	#if 0 /* this is what we used to do. */
288	/*
289	* Set BrandIndex=0, CLFLUSH-line-size=0, Num-Logical-Cpus=0 and APIC-ID=0.
290	*/
291	pCPUM->aGuestCpuIdStd[1].ebx = 0;
292
293	/*
294	* Set the max standard index to 2.
295	*/
296	pCPUM->aGuestCpuIdStd[0].eax = 2;
297	pCPUM->GuestCpuIdDef = pCPUM->aGuestCpuIdStd[2]; /** @todo this default is NOT right for AMD, only Intel CPUs. (see tstInlineAsm) */
298
299	#else /* this is what we probably should do */
300	/*
301	* Hide HTT, multicode, SMP, whatever.
302	* (APIC-ID := 0 and #LogCpus := 0)
303	*/
304	pCPUM->aGuestCpuIdStd[1].ebx = 0x0000ffff;
305
306	/*
307	* Determin the default value and limit it the number of entries.
308	* Intel returns values of the highest standard function, while AMD returns zeros.
309	*/
310	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
311	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
312	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
313
314	if (pCPUM->aGuestCpuIdStd[0].eax > 2)
315	pCPUM->aGuestCpuIdStd[0].eax = 2;
316
317	if (pCPUM->aGuestCpuIdExt[0].eax > 0x80000004)
318	pCPUM->aGuestCpuIdExt[0].eax = 0x80000004;
319
320	#endif
321
322	/*
323	* Assign defaults to the entries we chopped off.
324	*/
325	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
326	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
327	for (i = pCPUM->aGuestCpuIdExt[0].eax - 0x80000000 + 1; i < ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
328	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
329
330	/*
331	* Load CPUID overrides from configuration.
332	*/
333	PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
334	uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
335	for (;;)
336	{
337	while (cElements-- < 0)
338	{
339	PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
340	if (pNode)
341	{
342	uint32_t u32;
343	int rc = CFGMR3QueryU32(pNode, "eax", &u32);
344	if (VBOX_SUCCESS(rc))
345	pCpuId->eax = u32;
346	else
347	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
348
349	rc = CFGMR3QueryU32(pNode, "ebx", &u32);
350	if (VBOX_SUCCESS(rc))
351	pCpuId->ebx = u32;
352	else
353	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
354
355	rc = CFGMR3QueryU32(pNode, "ecx", &u32);
356	if (VBOX_SUCCESS(rc))
357	pCpuId->ecx = u32;
358	else
359	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
360
361	rc = CFGMR3QueryU32(pNode, "edx", &u32);
362	if (VBOX_SUCCESS(rc))
363	pCpuId->edx = u32;
364	else
365	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
366	}
367	}
368
369	/* next */
370	if (i & 0x80000000)
371	break;
372	pCpuId = &pCPUM->aGuestCpuIdExt[0];
373	cElements = ELEMENTS(pCPUM->aGuestCpuIdExt);
374	i = 0x80000000;
375	}
376
377	/*
378	* Log the cpuid and we're good.
379	*/
380	LogRel(("Logical host processors: %d, processor active mask: %08x\n",
381	RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
382	LogRel(("*********************** CPUID dump **********************\n"));
383	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
384	LogRel(("\n"));
385	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
386	LogRel(("****************** End of CPUID dump ********************\n"));
387	return VINF_SUCCESS;
388	}
389
390
391
392
393	/**
394	* Applies relocations to data and code managed by this
395	* component. This function will be called at init and
396	* whenever the VMM need to relocate it self inside the GC.
397	*
398	* The CPUM will update the addresses used by the switcher.
399	*
400	* @param pVM The VM.
401	*/
402	CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
403	{
404	LogFlow(("CPUMR3Relocate\n"));
405	/*
406	* Switcher pointers.
407	*/
408	pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
409	pVM->cpum.s.pHyperCoreGC = MMHyperHC2GC(pVM, pVM->cpum.s.pHyperCoreHC);
410	}
411
412
413	/**
414	* Queries the pointer to the internal CPUMCTX structure
415	*
416	* @returns VBox status code.
417	* @param pVM Handle to the virtual machine.
418	* @param ppCtx Receives the CPUMCTX GC pointer when successful.
419	*/
420	CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx)
421	{
422	LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
423	/*
424	* Store the address. (Later we might check how's calling, thus the RC.)
425	*/
426	*ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
427	return VINF_SUCCESS;
428	}
429
430
431	/**
432	* Terminates the CPUM.
433	*
434	* Termination means cleaning up and freeing all resources,
435	* the VM it self is at this point powered off or suspended.
436	*
437	* @returns VBox status code.
438	* @param pVM The VM to operate on.
439	*/
440	CPUMR3DECL(int) CPUMR3Term(PVM pVM)
441	{
442	/** @todo */
443	return 0;
444	}
445
446
447	/**
448	* Resets the CPU.
449	*
450	* @returns VINF_SUCCESS.
451	* @param pVM The VM handle.
452	*/
453	CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
454	{
455	PCPUMCTX pCtx = &pVM->cpum.s.Guest;
456
457	/*
458	* Initialize everything to ZERO first.
459	*/
460	uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
461	memset(pCtx, 0, sizeof(*pCtx));
462	pVM->cpum.s.fUseFlags = fUseFlags;
463
464	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
465	pCtx->eip = 0x0000fff0;
466	pCtx->edx = 0x00000600; /* P6 processor */
467	pCtx->eflags.Bits.u1Reserved0 = 1;
468
469	pCtx->cs = 0xf000;
470	pCtx->csHid.u32Base = 0xffff0000;
471	pCtx->csHid.u32Limit = 0x0000ffff;
472	pCtx->dsHid.u32Limit = 0x0000ffff;
473	pCtx->esHid.u32Limit = 0x0000ffff;
474	pCtx->fsHid.u32Limit = 0x0000ffff;
475	pCtx->gsHid.u32Limit = 0x0000ffff;
476	pCtx->ssHid.u32Limit = 0x0000ffff;
477	pCtx->idtr.cbIdt = 0xffff;
478	pCtx->gdtr.cbGdt = 0xffff;
479	pCtx->ldtrHid.u32Limit = 0xffff;
480	pCtx->ldtrHid.Attr.u = X86_DESC_P;
481	pCtx->trHid.u32Limit = 0xffff;
482	pCtx->trHid.Attr.u = X86_DESC_P;
483
484	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
485	pCtx->fpu.FCW = 0x37f;
486	}
487
488
489
490	/**
491	* Execute state save operation.
492	*
493	* @returns VBox status code.
494	* @param pVM VM Handle.
495	* @param pSSM SSM operation handle.
496	*/
497	static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
498	{
499	/*
500	* Save.
501	*/
502	SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
503	SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
504	SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
505	SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
506
507	SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
508	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
509
510	SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
511	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
512
513	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
514
515	/* Add the cpuid for checking that the cpu is unchanged. */
516	uint32_t au32CpuId[8] = {0};
517	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
518	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
519	return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
520	}
521
522
523	/**
524	* Execute state load operation.
525	*
526	* @returns VBox status code.
527	* @param pVM VM Handle.
528	* @param pSSM SSM operation handle.
529	* @param u32Version Data layout version.
530	*/
531	static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
532	{
533	/*
534	* Validate version.
535	*/
536	if (u32Version != CPUM_SAVED_STATE_VERSION)
537	{
538	Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
539	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
540	}
541
542	/*
543	* Restore.
544	*/
545	uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
546	uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
547	SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
548	pVM->cpum.s.Hyper.cr3 = uCR3;
549	pVM->cpum.s.Hyper.esp = uESP;
550	SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
551	SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
552	SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
553
554	uint32_t cElements;
555	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
556	if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
557	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
558	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
559
560	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
561	if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
562	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
563	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
564
565	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
566
567	/*
568	* Check that the basic cpuid id information is unchanged.
569	*/
570	uint32_t au32CpuId[8] = {0};
571	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
572	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
573	uint32_t au32CpuIdSaved[8];
574	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
575	if (VBOX_SUCCESS(rc))
576	{
577	/* Ignore APIC ID (AMD specs). */
578	au32CpuId[5] &= ~0xff000000;
579	au32CpuIdSaved[5] &= ~0xff000000;
580	/* Ignore the number of Logical CPUs (AMD specs). */
581	au32CpuId[5] &= ~0x00ff0000;
582	au32CpuIdSaved[5] &= ~0x00ff0000;
583
584	/* do the compare */
585	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
586	{
587	Log(("cpumR3Load: CpuId mismatch!\n"
588	"Saved=%.*Vhxs\n"
589	"Real =%.*Vhxs\n",
590	sizeof(au32CpuIdSaved), au32CpuIdSaved,
591	sizeof(au32CpuId), au32CpuId));
592	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
593	}
594	}
595
596	return rc;
597	}
598
599
600	/**
601	* Formats the EFLAGS value into mnemonics.
602	*
603	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
604	* @param efl The EFLAGS value.
605	*/
606	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
607	{
608	/*
609	* Format the flags.
610	*/
611	static struct
612	{
613	const char pszSet; const char pszClear; uint32_t fFlag;
614	} s_aFlags[] =
615	{
616	{ "vip",NULL, X86_EFL_VIP },
617	{ "vif",NULL, X86_EFL_VIF },
618	{ "ac", NULL, X86_EFL_AC },
619	{ "vm", NULL, X86_EFL_VM },
620	{ "rf", NULL, X86_EFL_RF },
621	{ "nt", NULL, X86_EFL_NT },
622	{ "ov", "nv", X86_EFL_OF },
623	{ "dn", "up", X86_EFL_DF },
624	{ "ei", "di", X86_EFL_IF },
625	{ "tf", NULL, X86_EFL_TF },
626	{ "nt", "pl", X86_EFL_SF },
627	{ "nz", "zr", X86_EFL_ZF },
628	{ "ac", "na", X86_EFL_AF },
629	{ "po", "pe", X86_EFL_PF },
630	{ "cy", "nc", X86_EFL_CF },
631	};
632	char *psz = pszEFlags;
633	for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
634	{
635	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
636	if (pszAdd)
637	{
638	strcpy(psz, pszAdd);
639	psz += strlen(pszAdd);
640	*psz++ = ' ';
641	}
642	}
643	psz[-1] = '\0';
644	}
645
646
647	/**
648	* Formats a full register dump.
649	*
650	* @param pCtx The context to format.
651	* @param pCtxCore The context core to format.
652	* @param pHlp Output functions.
653	* @param enmType The dump type.
654	* @param pszPrefix Register name prefix.
655	*/
656	static void cpumR3InfoOne(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
657	{
658	/*
659	* Format the EFLAGS.
660	*/
661	uint32_t efl = pCtxCore->eflags.u32;
662	char szEFlags[80];
663	cpumR3InfoFormatFlags(&szEFlags[0], efl);
664
665	/*
666	* Format the registers.
667	*/
668	switch (enmType)
669	{
670	case CPUMDUMPTYPE_TERSE:
671	pHlp->pfnPrintf(pHlp,
672	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
673	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
674	"%scs=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
675	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
676	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
677	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
678	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
679	break;
680
681	case CPUMDUMPTYPE_DEFAULT:
682	pHlp->pfnPrintf(pHlp,
683	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
684	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
685	"%scs=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n"
686	"%scr0=%08x %scr2=%08x %scr3=%08x %scr4=%08x %sgdtr=%08x:%04x %sldtr=%04x\n"
687	,
688	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
689	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
690	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
691	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl,
692	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
693	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
694	break;
695
696	case CPUMDUMPTYPE_VERBOSE:
697	pHlp->pfnPrintf(pHlp,
698	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
699	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
700	"%scs={%04x base=%08x limit=%08x flags=%08x} %sdr0=%08x %sdr1=%08x\n"
701	"%sds={%04x base=%08x limit=%08x flags=%08x} %sdr2=%08x %sdr3=%08x\n"
702	"%ses={%04x base=%08x limit=%08x flags=%08x} %sdr4=%08x %sdr5=%08x\n"
703	"%sfs={%04x base=%08x limit=%08x flags=%08x} %sdr6=%08x %sdr7=%08x\n"
704	"%sgs={%04x base=%08x limit=%08x flags=%08x} %scr0=%08x %scr2=%08x\n"
705	"%sss={%04x base=%08x limit=%08x flags=%08x} %scr3=%08x %scr4=%08x\n"
706	"%sgdtr=%08x:%04x %sidtr=%08x:%04x %seflags=%08x\n"
707	"%sldtr={%04x base=%08x limit=%08x flags=%08x}\n"
708	"%str ={%04x base=%08x limit=%08x flags=%08x}\n"
709	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
710	"%sFCW=%04x %sFSW=%04x %sFTW=%04x\n"
711	,
712	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
713	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
714	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
715	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
716	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
717	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
718	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
719	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
720	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
721	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u32Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
722	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u32Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
723	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
724	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW);
725	break;
726	}
727	}
728
729
730	/**
731	* Display all cpu states and any other cpum info.
732	*
733	* @param pVM VM Handle.
734	* @param pHlp The info helper functions.
735	* @param pszArgs Arguments, ignored.
736	*/
737	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
738	{
739	cpumR3InfoGuest(pVM, pHlp, pszArgs);
740	cpumR3InfoHyper(pVM, pHlp, pszArgs);
741	cpumR3InfoHost(pVM, pHlp, pszArgs);
742	}
743
744
745	/**
746	* Parses the info argument.
747	*
748	* The argument starts with 'verbose', 'terse' or 'default' and then
749	* continues with the comment string.
750	*
751	* @param pszArgs The pointer to the argument string.
752	* @param penmType Where to store the dump type request.
753	* @param ppszComment Where to store the pointer to the comment string.
754	*/
755	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
756	{
757	if (!pszArgs)
758	{
759	*penmType = CPUMDUMPTYPE_DEFAULT;
760	*ppszComment = "";
761	}
762	else
763	{
764	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
765	{
766	pszArgs += 5;
767	*penmType = CPUMDUMPTYPE_VERBOSE;
768	}
769	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
770	{
771	pszArgs += 5;
772	*penmType = CPUMDUMPTYPE_TERSE;
773	}
774	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
775	{
776	pszArgs += 7;
777	*penmType = CPUMDUMPTYPE_DEFAULT;
778	}
779	else
780	*penmType = CPUMDUMPTYPE_DEFAULT;
781	*ppszComment = RTStrStripL(pszArgs);
782	}
783	}
784
785
786	/**
787	* Display the guest cpu state.
788	*
789	* @param pVM VM Handle.
790	* @param pHlp The info helper functions.
791	* @param pszArgs Arguments, ignored.
792	*/
793	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
794	{
795	CPUMDUMPTYPE enmType;
796	const char *pszComment;
797	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
798	pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
799	cpumR3InfoOne(&pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
800	}
801
802
803	/**
804	* Display the hypervisor cpu state.
805	*
806	* @param pVM VM Handle.
807	* @param pHlp The info helper functions.
808	* @param pszArgs Arguments, ignored.
809	*/
810	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
811	{
812	CPUMDUMPTYPE enmType;
813	const char *pszComment;
814	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
815	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
816	cpumR3InfoOne(&pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreHC, pHlp, enmType, ".");
817	}
818
819
820	/**
821	* Display the host cpu state.
822	*
823	* @param pVM VM Handle.
824	* @param pHlp The info helper functions.
825	* @param pszArgs Arguments, ignored.
826	*/
827	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
828	{
829	CPUMDUMPTYPE enmType;
830	const char *pszComment;
831	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
832	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
833
834	/*
835	* Format the EFLAGS.
836	*/
837	PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
838	#if HC_ARCH_BITS == 32
839	uint32_t efl = pCtx->eflags.u32;
840	#else
841	uint64_t efl = pCtx->rflags;
842	#endif
843	char szEFlags[80];
844	cpumR3InfoFormatFlags(&szEFlags[0], efl);
845
846	/*
847	* Format the registers.
848	*/
849	#if HC_ARCH_BITS == 32
850	pHlp->pfnPrintf(pHlp,
851	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
852	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
853	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
854	"cr0=%08x cr2=xxxxxxxx cr3=%08x cr4=%08x gdtr=%08x:%04x ldtr=%04x\n"
855	"dr0=%08x dr1=%08x dr2=%08x dr3=%08x dr6=%08x dr7=%08x\n"
856	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
857	,
858	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
859	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
860	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
861	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
862	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
863	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, (RTSEL)pCtx->ldtr,
864	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
865	#else /* 64-bit */
866	pHlp->pfnPrintf(pHlp,
867	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
868	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
869	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
870	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
871	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
872	"r14=%016RX64 r15=%016RX64\n"
873	"iopl=%d %31s\n"
874	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
875	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
876	"cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
877	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
878	"dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
879	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
880	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
881	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
882	,
883	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
884	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
885	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
886	/pCtx->r8, pCtx->r9,/ pCtx->r10,
887	pCtx->r11, pCtx->r12, pCtx->r13,
888	pCtx->r14, pCtx->r15,
889	X86_EFL_GET_IOPL(efl), szEFlags,
890	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
891	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
892	pCtx->cr4, pCtx->cr8, pCtx->ldtr, pCtx->tr,
893	pCtx->dr0, pCtx->dr1, pCtx->dr2,
894	pCtx->dr3, pCtx->dr6, pCtx->dr7,
895	(uint64_t )&pCtx->gdtr[2], (uint16_t )&pCtx->gdtr[0], (uint64_t )&pCtx->idtr[2], (uint16_t )&pCtx->idtr[0],
896	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
897	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
898	#endif
899	}
900
901	/**
902	* Get L1 cache / TLS associativity.
903	*/
904	static const char getCacheAss(unsigned u, char pszBuf)
905	{
906	if (u == 0)
907	return "res0 ";
908	if (u == 1)
909	return "direct";
910	if (u >= 256)
911	return "???";
912
913	RTStrPrintf(pszBuf, 16, "%d way", u);
914	return pszBuf;
915	}
916
917
918	/**
919	* Get L2 cache soociativity.
920	*/
921	const char *getL2CacheAss(unsigned u)
922	{
923	switch (u)
924	{
925	case 0: return "off ";
926	case 1: return "direct";
927	case 2: return "2 way ";
928	case 3: return "res3 ";
929	case 4: return "4 way ";
930	case 5: return "res5 ";
931	case 6: return "8 way ";
932	case 7: return "res7 ";
933	case 8: return "16 way";
934	case 9: return "res9 ";
935	case 10: return "res10 ";
936	case 11: return "res11 ";
937	case 12: return "res12 ";
938	case 13: return "res13 ";
939	case 14: return "res14 ";
940	case 15: return "fully ";
941	default:
942	return "????";
943	}
944	}
945
946
947	/**
948	* Display the guest CpuId leafs.
949	*
950	* @param pVM VM Handle.
951	* @param pHlp The info helper functions.
952	* @param pszArgs "terse", "default" or "verbose".
953	*/
954	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
955	{
956	/*
957	* Parse the argument.
958	*/
959	unsigned iVerbosity = 1;
960	if (pszArgs)
961	{
962	pszArgs = RTStrStripL(pszArgs);
963	if (!strcmp(pszArgs, "terse"))
964	iVerbosity--;
965	else if (!strcmp(pszArgs, "verbose"))
966	iVerbosity++;
967	}
968
969	/*
970	* Start cracking.
971	*/
972	CPUMCPUID Host;
973	CPUMCPUID Guest;
974	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
975
976	pHlp->pfnPrintf(pHlp,
977	" RAW Standard CPUIDs\n"
978	" Function eax ebx ecx edx\n");
979	for (unsigned i = 0; i <= ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
980	{
981	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
982	ASMCpuId(i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
983
984	pHlp->pfnPrintf(pHlp,
985	"Gst: %08x %08x %08x %08x %08x%s\n"
986	"Hst: %08x %08x %08x %08x\n",
987	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
988	i <= cStdMax ? "" : "*",
989	Host.eax, Host.ebx, Host.ecx, Host.edx);
990	}
991
992	/*
993	* If verbose, decode it.
994	*/
995	if (iVerbosity)
996	{
997	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
998	pHlp->pfnPrintf(pHlp,
999	"Name: %.04s%.04s%.04s\n"
1000	"Supports: 0-%x\n",
1001	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1002	}
1003
1004	/*
1005	* Get Features.
1006	*/
1007	if (cStdMax >= 1 && iVerbosity)
1008	{
1009	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1010	uint32_t uEAX = Guest.eax;
1011
1012	pHlp->pfnPrintf(pHlp,
1013	"Family: %d \tExtended: %d \tEffectiv: %d\n"
1014	"Model: %d \tExtended: %d \tEffectiv: %d\n"
1015	"Stepping: %d\n"
1016	"APIC ID: %#04x\n"
1017	"Logical CPUs: %d\n"
1018	"CLFLUSH Size: %d\n"
1019	"Brand ID: %#04x\n",
1020	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1021	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) \| (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1022	(uEAX >> 0) & 0xf,
1023	(Guest.ebx >> 24) & 0xff,
1024	(Guest.ebx >> 16) & 0xff,
1025	(Guest.ebx >> 8) & 0xff,
1026	(Guest.ebx >> 0) & 0xff);
1027	if (iVerbosity == 1)
1028	{
1029	uint32_t uEDX = Guest.edx;
1030	pHlp->pfnPrintf(pHlp, "Features EDX: ");
1031	if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1032	if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1033	if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1034	if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1035	if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1036	if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1037	if (uEDX & BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1038	if (uEDX & BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1039	if (uEDX & BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1040	if (uEDX & BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1041	if (uEDX & BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1042	if (uEDX & BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1043	if (uEDX & BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1044	if (uEDX & BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1045	if (uEDX & BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1046	if (uEDX & BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1047	if (uEDX & BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1048	if (uEDX & BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1049	if (uEDX & BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1050	if (uEDX & BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1051	if (uEDX & BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1052	if (uEDX & BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1053	if (uEDX & BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1054	if (uEDX & BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1055	if (uEDX & BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1056	if (uEDX & BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1057	if (uEDX & BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1058	if (uEDX & BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1059	if (uEDX & BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1060	if (uEDX & BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1061	if (uEDX & BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1062	if (uEDX & BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1063	pHlp->pfnPrintf(pHlp, "\n");
1064
1065	uint32_t uECX = Guest.ecx;
1066	pHlp->pfnPrintf(pHlp, "Features ECX: ");
1067	if (uECX & BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1068	if (uECX & BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1069	if (uECX & BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1070	if (uECX & BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1071	if (uECX & BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1072	if (uECX & BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1073	if (uECX & BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1074	if (uECX & BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1075	if (uECX & BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1076	if (uECX & BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1077	if (uECX & BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1078	if (uECX & BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1079	if (uECX & BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1080	if (uECX & BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1081	for (unsigned iBit = 14; iBit < 32; iBit++)
1082	if (uECX & BIT(iBit))
1083	pHlp->pfnPrintf(pHlp, " %d", iBit);
1084	pHlp->pfnPrintf(pHlp, "\n");
1085	}
1086	else
1087	{
1088	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1089
1090	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1091	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1092	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1093	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1094
1095	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1096	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1097	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1098	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1099	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1100	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1101	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1102	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1103	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1104	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1105	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1106	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1107	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1108	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1109	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1110	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1111	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1112	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1113	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1114	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1115	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1116	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1117	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1118	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1119	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1120	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1121	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1122	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1123	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1124	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1125	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1126	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1127	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1128
1129	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1130	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1131	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1132	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1133	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1134	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1135	pHlp->pfnPrintf(pHlp, "Enh. SpeedStep Tech = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1136	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1137	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved3, EcxHost.u1Reserved3);
1138	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1139	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1140	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1141	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u18Reserved5, EcxHost.u18Reserved5);
1142	}
1143	}
1144	if (cStdMax >= 2 && iVerbosity)
1145	{
1146	/** @todo */
1147	}
1148
1149	/*
1150	* Extended.
1151	* Implemented after AMD specs.
1152	*/
1153	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1154
1155	pHlp->pfnPrintf(pHlp,
1156	"\n"
1157	" RAW Extended CPUIDs\n"
1158	" Function eax ebx ecx edx\n");
1159	for (unsigned i = 0; i <= ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1160	{
1161	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1162	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1163
1164	pHlp->pfnPrintf(pHlp,
1165	"Gst: %08x %08x %08x %08x %08x%s\n"
1166	"Hst: %08x %08x %08x %08x\n",
1167	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1168	i <= cExtMax ? "" : "*",
1169	Host.eax, Host.ebx, Host.ecx, Host.edx);
1170	}
1171
1172	/*
1173	* Understandable output
1174	*/
1175	if (iVerbosity && cExtMax >= 0)
1176	{
1177	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1178	pHlp->pfnPrintf(pHlp,
1179	"Ext Name: %.4s%.4s%.4s\n"
1180	"Ext Supports: 0x80000000-%#010x\n",
1181	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1182	}
1183
1184	if (iVerbosity && cExtMax >= 1)
1185	{
1186	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1187	uint32_t uEAX = Guest.eax;
1188	pHlp->pfnPrintf(pHlp,
1189	"Family: %d \tExtended: %d \tEffectiv: %d\n"
1190	"Model: %d \tExtended: %d \tEffectiv: %d\n"
1191	"Stepping: %d\n"
1192	"Brand ID: %#05x\n",
1193	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1194	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) \| (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1195	(uEAX >> 0) & 0xf,
1196	Guest.ebx & 0xfff);
1197
1198	if (iVerbosity == 1)
1199	{
1200	uint32_t uEDX = Guest.edx;
1201	pHlp->pfnPrintf(pHlp, "Features EDX: ");
1202	if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1203	if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1204	if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1205	if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1206	if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1207	if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1208	if (uEDX & BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1209	if (uEDX & BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1210	if (uEDX & BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1211	if (uEDX & BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1212	if (uEDX & BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1213	if (uEDX & BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1214	if (uEDX & BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1215	if (uEDX & BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1216	if (uEDX & BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1217	if (uEDX & BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1218	if (uEDX & BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1219	if (uEDX & BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1220	if (uEDX & BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1221	if (uEDX & BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1222	if (uEDX & BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1223	if (uEDX & BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1224	if (uEDX & BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1225	if (uEDX & BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1226	if (uEDX & BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1227	if (uEDX & BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1228	if (uEDX & BIT(26)) pHlp->pfnPrintf(pHlp, " 26");
1229	if (uEDX & BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1230	if (uEDX & BIT(28)) pHlp->pfnPrintf(pHlp, " 29");
1231	if (uEDX & BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1232	if (uEDX & BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1233	if (uEDX & BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1234	pHlp->pfnPrintf(pHlp, "\n");
1235
1236	uint32_t uECX = Guest.ecx;
1237	pHlp->pfnPrintf(pHlp, "Features ECX: ");
1238	if (uECX & BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1239	if (uECX & BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1240	if (uECX & BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1241	if (uECX & BIT(3)) pHlp->pfnPrintf(pHlp, " SVM");
1242	if (uECX & BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1243	for (unsigned iBit = 5; iBit < 32; iBit++)
1244	if (uECX & BIT(iBit))
1245	pHlp->pfnPrintf(pHlp, " %d", iBit);
1246	pHlp->pfnPrintf(pHlp, "\n");
1247	}
1248	else
1249	{
1250	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1251
1252	uint32_t uEdxGst = Guest.edx;
1253	uint32_t uEdxHst = Host.edx;
1254	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1255	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & BIT( 0)), !!(uEdxHst & BIT( 0)));
1256	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & BIT( 1)), !!(uEdxHst & BIT( 1)));
1257	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & BIT( 2)), !!(uEdxHst & BIT( 2)));
1258	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & BIT( 3)), !!(uEdxHst & BIT( 3)));
1259	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & BIT( 4)), !!(uEdxHst & BIT( 4)));
1260	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & BIT( 5)), !!(uEdxHst & BIT( 5)));
1261	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & BIT( 6)), !!(uEdxHst & BIT( 6)));
1262	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & BIT( 7)), !!(uEdxHst & BIT( 7)));
1263	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & BIT( 8)), !!(uEdxHst & BIT( 8)));
1264	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & BIT( 9)), !!(uEdxHst & BIT( 9)));
1265	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(10)), !!(uEdxHst & BIT(10)));
1266	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & BIT(11)), !!(uEdxHst & BIT(11)));
1267	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & BIT(12)), !!(uEdxHst & BIT(12)));
1268	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & BIT(13)), !!(uEdxHst & BIT(13)));
1269	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & BIT(14)), !!(uEdxHst & BIT(14)));
1270	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & BIT(15)), !!(uEdxHst & BIT(15)));
1271	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & BIT(16)), !!(uEdxHst & BIT(16)));
1272	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & BIT(17)), !!(uEdxHst & BIT(17)));
1273	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(18)), !!(uEdxHst & BIT(18)));
1274	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(19)), !!(uEdxHst & BIT(19)));
1275	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & BIT(20)), !!(uEdxHst & BIT(20)));
1276	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & BIT(21)), !!(uEdxHst & BIT(21)));
1277	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & BIT(22)), !!(uEdxHst & BIT(22)));
1278	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & BIT(23)), !!(uEdxHst & BIT(23)));
1279	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & BIT(24)), !!(uEdxHst & BIT(24)));
1280	pHlp->pfnPrintf(pHlp, "?? - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & BIT(25)), !!(uEdxHst & BIT(25)));
1281	pHlp->pfnPrintf(pHlp, "26 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(26)), !!(uEdxHst & BIT(26)));
1282	pHlp->pfnPrintf(pHlp, "27 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(27)), !!(uEdxHst & BIT(27)));
1283	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(28)), !!(uEdxHst & BIT(28)));
1284	pHlp->pfnPrintf(pHlp, "?? - AMD Long Mode = %d (%d)\n", !!(uEdxGst & BIT(29)), !!(uEdxHst & BIT(29)));
1285	pHlp->pfnPrintf(pHlp, "?? - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & BIT(30)), !!(uEdxHst & BIT(30)));
1286	pHlp->pfnPrintf(pHlp, "?? - AMD 3DNow = %d (%d)\n", !!(uEdxGst & BIT(31)), !!(uEdxHst & BIT(31)));
1287
1288	uint32_t uEcxGst = Guest.ecx;
1289	uint32_t uEcxHst = Host.ecx;
1290	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & BIT( 0)), !!(uEcxHst & BIT( 0)));
1291	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & BIT( 1)), !!(uEcxHst & BIT( 1)));
1292	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & BIT( 2)), !!(uEcxHst & BIT( 2)));
1293	pHlp->pfnPrintf(pHlp, "3 - Reserved = %d (%d)\n", !!(uEcxGst & BIT( 3)), !!(uEcxHst & BIT( 3)));
1294	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & BIT( 4)), !!(uEcxHst & BIT( 4)));
1295	pHlp->pfnPrintf(pHlp, "31:5 - Reserved = %#x (%#x)\n", uEcxGst >> 5, uEcxHst >> 5);
1296	}
1297	}
1298
1299	if (iVerbosity && cExtMax >= 2)
1300	{
1301	char szString[443+1] = {0};
1302	uint32_t pu32 = (uint32_t )szString;
1303	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1304	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1305	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1306	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1307	if (cExtMax >= 3)
1308	{
1309	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1310	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1311	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1312	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1313	}
1314	if (cExtMax >= 4)
1315	{
1316	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1317	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1318	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1319	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1320	}
1321	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1322	}
1323
1324	if (iVerbosity && cExtMax >= 5)
1325	{
1326	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1327	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1328	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1329	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1330	char sz1[32];
1331	char sz2[32];
1332
1333	pHlp->pfnPrintf(pHlp,
1334	"TLB 2/4M Instr/Uni: %s %3d entries\n"
1335	"TLB 2/4M Data: %s %3d entries\n",
1336	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1337	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1338	pHlp->pfnPrintf(pHlp,
1339	"TLB 4K Instr/Uni: %s %3d entries\n"
1340	"TLB 4K Data: %s %3d entries\n",
1341	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1342	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1343	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1344	"L1 Instr Cache Lines Per Tag: %d\n"
1345	"L1 Instr Cache Associativity: %s\n"
1346	"L1 Instr Cache Size: %d KB\n",
1347	(uEDX >> 0) & 0xff,
1348	(uEDX >> 8) & 0xff,
1349	getCacheAss((uEDX >> 16) & 0xff, sz1),
1350	(uEDX >> 24) & 0xff);
1351	pHlp->pfnPrintf(pHlp,
1352	"L1 Data Cache Line Size: %d bytes\n"
1353	"L1 Data Cache Lines Per Tag: %d\n"
1354	"L1 Data Cache Associativity: %s\n"
1355	"L1 Data Cache Size: %d KB\n",
1356	(uECX >> 0) & 0xff,
1357	(uECX >> 8) & 0xff,
1358	getCacheAss((uECX >> 16) & 0xff, sz1),
1359	(uECX >> 24) & 0xff);
1360	}
1361
1362	if (iVerbosity && cExtMax >= 6)
1363	{
1364	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1365	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1366	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1367
1368	pHlp->pfnPrintf(pHlp,
1369	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1370	"L2 TLB 2/4M Data: %s %4d entries\n",
1371	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1372	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1373	pHlp->pfnPrintf(pHlp,
1374	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
1375	"L2 TLB 4K Data: %s %4d entries\n",
1376	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1377	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1378	pHlp->pfnPrintf(pHlp,
1379	"L2 Cache Line Size: %d bytes\n"
1380	"L2 Cache Lines Per Tag: %d\n"
1381	"L2 Cache Associativity: %s\n"
1382	"L2 Cache Size: %d KB\n",
1383	(uEDX >> 0) & 0xff,
1384	(uEDX >> 8) & 0xf,
1385	getL2CacheAss((uEDX >> 12) & 0xf),
1386	(uEDX >> 16) & 0xffff);
1387	}
1388
1389	if (iVerbosity && cExtMax >= 7)
1390	{
1391	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1392
1393	pHlp->pfnPrintf(pHlp, "APM Features: ");
1394	if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1395	if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1396	if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1397	if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1398	if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1399	if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1400	for (unsigned iBit = 6; iBit < 32; iBit++)
1401	if (uEDX & BIT(iBit))
1402	pHlp->pfnPrintf(pHlp, " %d", iBit);
1403	pHlp->pfnPrintf(pHlp, "\n");
1404	}
1405
1406	if (iVerbosity && cExtMax >= 8)
1407	{
1408	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1409	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1410
1411	pHlp->pfnPrintf(pHlp,
1412	"Physical Address Width: %d bits\n"
1413	"Virtual Address Width: %d bits\n",
1414	(uEAX >> 0) & 0xff,
1415	(uEAX >> 8) & 0xff);
1416	pHlp->pfnPrintf(pHlp,
1417	"Physical Core Count: %d\n",
1418	(uECX >> 0) & 0xff);
1419	}
1420	}
1421
1422
1423	/**
1424	* Structure used when disassembling and instructions in DBGF.
1425	* This is used so the reader function can get the stuff it needs.
1426	*/
1427	typedef struct CPUMDISASSTATE
1428	{
1429	/** Pointer to the CPU structure. */
1430	PDISCPUSTATE pCpu;
1431	/** The VM handle. */
1432	PVM pVM;
1433	/** Pointer to the first byte in the segemnt. */
1434	RTGCUINTPTR GCPtrSegBase;
1435	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
1436	RTGCUINTPTR GCPtrSegEnd;
1437	/** The size of the segment minus 1. */
1438	RTGCUINTPTR cbSegLimit;
1439	/** Pointer to the current page - HC Ptr. */
1440	void *pvPageHC;
1441	/** Pointer to the current page - GC Ptr. */
1442	RTGCPTR pvPageGC;
1443	/** The rc of the operation.
1444	*
1445	* @todo r=bird: it's rather annoying that we have to keep track of the status code of the operation.
1446	* When we've got time we should adjust the disassembler to use VBox status codes and not
1447	* boolean returns.
1448	*/
1449	int rc;
1450	} CPUMDISASSTATE, *PCPUMDISASSTATE;
1451
1452
1453	/**
1454	* Instruction reader.
1455	*
1456	* @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
1457	* @param PtrSrc Address to read from.
1458	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1459	* @param pu8Dst Where to store the bytes.
1460	* @param cbRead Number of bytes to read.
1461	* @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
1462	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
1463	* @todo r=bird: The status code should be an int. The PtrSrc should NOT be a RTHCUINTPTR. The uDisCpu could just as well be
1464	* declared as what it actually is a PDISCPUSTATE.
1465	*/
1466	static DECLCALLBACK(int32_t) cpumR3DisasInstrRead(RTHCUINTPTR PtrSrc, uint8_t *pu8Dst, uint32_t cbRead, RTHCUINTPTR uDisCpu)
1467	{
1468	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1469	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->dwUserData[0]; /** @todo r=bird: Invalid prefix, dw='double word' which it isn't. Besides it's an array too. And btw. RTHCUINTPTR isn't the right thing either in a 32-bit host 64-bit guest situation */
1470	Assert(cbRead > 0);
1471	for (;;)
1472	{
1473	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1474
1475	/* Need to update the page translation? */
1476	if ( !pState->pvPageHC
1477	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1478	{
1479	/* translate the address */
1480	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1481	if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1482	{
1483	pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1484	if (!pState->pvPageHC)
1485	pState->rc = VERR_INVALID_POINTER;
1486	}
1487	else
1488	pState->rc = PGMPhysGCPtr2HCPtr(pState->pVM, pState->pvPageGC, &pState->pvPageHC);
1489	if (VBOX_FAILURE(pState->rc))
1490	{
1491	pState->pvPageHC = NULL;
1492	return pState->rc;
1493	}
1494	}
1495
1496	/* check the segemnt limit */
1497	if (PtrSrc > pState->cbSegLimit)
1498	return pState->rc = VERR_OUT_OF_SELECTOR_BOUNDS;
1499
1500	/* calc how much we can read */
1501	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1502	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1503	if (cb > cbSeg && !cbSeg)
1504	cb = cbSeg;
1505	if (cb > cbRead)
1506	cb = cbRead;
1507
1508	/* read and advance */
1509	memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1510	cbRead -= cb;
1511	if (!cbRead)
1512	return VINF_SUCCESS;
1513	pu8Dst += cb;
1514	PtrSrc += cb;
1515	}
1516	}
1517
1518
1519	/**
1520	* Disassemble an instruction and return the information in the provided structure.
1521	*
1522	* @returns VBox status code.
1523	* @param pVM VM Handle
1524	* @param pCtx CPU context
1525	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
1526	* @param pCpu Disassembly state
1527	* @param pszPrefix String prefix for logging (debug only)
1528	*
1529	*/
1530	CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1531	{
1532	CPUMDISASSTATE State;
1533	int rc;
1534
1535	State.pCpu = pCpu;
1536	State.pvPageGC = 0;
1537	State.pvPageHC = NULL;
1538	State.rc = VINF_SUCCESS;
1539	State.pVM = pVM;
1540	/*
1541	* Get selector information.
1542	*/
1543	if (pCtx->eflags.Bits.u1VM == 0)
1544	{
1545	if (CPUMAreHiddenSelRegsValid(pVM))
1546	{
1547	State.GCPtrSegBase = pCtx->csHid.u32Base;
1548	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u32Base;
1549	State.cbSegLimit = pCtx->csHid.u32Limit;
1550	pCpu->mode = pCtx->csHid.Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1551	}
1552	else
1553	{
1554	SELMSELINFO SelInfo;
1555
1556	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1557	if (!VBOX_SUCCESS(rc))
1558	{
1559	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1560	return rc;
1561	}
1562
1563	/*
1564	* Validate the selector.
1565	*/
1566	rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1567	if (!VBOX_SUCCESS(rc))
1568	{
1569	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1570	return rc;
1571	}
1572	State.GCPtrSegBase = SelInfo.GCPtrBase;
1573	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1574	State.cbSegLimit = SelInfo.cbLimit;
1575	pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1576	}
1577	}
1578	else
1579	{
1580	/* V86 mode */
1581	pCpu->mode = CPUMODE_16BIT; /* @todo */
1582	State.GCPtrSegBase = pCtx->cs * 16;
1583	State.GCPtrSegEnd = 0xFFFFFFFF;
1584	State.cbSegLimit = 0xFFFFFFFF;
1585	}
1586
1587	/*
1588	* Disassemble the instruction.
1589	*/
1590	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
1591	pCpu->dwUserData[0] = (uintptr_t)&State;
1592
1593	uint32_t cbInstr;
1594	#ifdef LOG_ENABLED
1595	if (DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL))
1596	{
1597	#else
1598	char szOutput[160];
1599	if (DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]))
1600	{
1601	/* log it */
1602	if (pszPrefix)
1603	Log(("%s: %s", pszPrefix, szOutput));
1604	else
1605	Log(("%s", szOutput));
1606	#endif
1607	return VINF_SUCCESS;
1608	}
1609
1610	/* DISInstr failure */
1611	if (VBOX_FAILURE(State.rc))
1612	{
1613	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, State.rc));
1614	return State.rc;
1615	}
1616	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv\n", pCtx->cs, GCPtrPC));
1617	rc = VERR_GENERAL_FAILURE;
1618	return rc;
1619	}
1620
1621
1622	#ifdef DEBUG
1623	/**
1624	* Disassemble an instruction and dump it to the log
1625	*
1626	* @returns VBox status code.
1627	* @param pVM VM Handle
1628	* @param pCtx CPU context
1629	* @param pc GC instruction pointer
1630	* @param prefix String prefix for logging
1631	* @deprecated Use DBGFR3DisasInstrCurrentLog().
1632	*
1633	*/
1634	CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
1635	{
1636	DISCPUSTATE cpu;
1637
1638	CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1639	}
1640
1641	/**
1642	* Disassemble an instruction and dump it to the log
1643	*
1644	* @returns VBox status code.
1645	* @param pVM VM Handle
1646	* @param pCtx CPU context
1647	* @param pc GC instruction pointer
1648	* @param prefix String prefix for logging
1649	* @param nrInstructions
1650	*
1651	*/
1652	CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
1653	{
1654	for(int i=0;i<nrInstructions;i++)
1655	{
1656	DISCPUSTATE cpu;
1657
1658	CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1659	pc += cpu.opsize;
1660	}
1661	}
1662
1663	#endif
1664
1665	#ifdef DEBUG
1666	/**
1667	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
1668	*
1669	* @internal
1670	*/
1671	CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
1672	{
1673	pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
1674	}
1675	#endif

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 771

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