VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 9216

Last change on this file since 9216 was 9216, checked in by vboxsync, 17 years ago

Compile issues (32 bits host/64 bits guest)
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1/* $Id: CPUM.cpp 9216 2008-05-29 11:29:55Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager)
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_CPUM
27#include <VBox/cpum.h>
28#include <VBox/cpumdis.h>
29#include <VBox/pgm.h>
30#include <VBox/mm.h>
31#include <VBox/selm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/ssm.h>
35#include "CPUMInternal.h"
36#include <VBox/vm.h>
37
38#include <VBox/param.h>
39#include <VBox/dis.h>
40#include <VBox/err.h>
41#include <VBox/log.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <iprt/system.h>
46
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51/** The saved state version. */
52#define CPUM_SAVED_STATE_VERSION 6
53
54
55/*******************************************************************************
56* Structures and Typedefs *
57*******************************************************************************/
58
59/**
60 * What kind of cpu info dump to performe.
61 */
62typedef enum CPUMDUMPTYPE
63{
64 CPUMDUMPTYPE_TERSE,
65 CPUMDUMPTYPE_DEFAULT,
66 CPUMDUMPTYPE_VERBOSE
67
68} CPUMDUMPTYPE, *PCPUMDUMPTYPE;
69
70
71/*******************************************************************************
72* Internal Functions *
73*******************************************************************************/
74static int cpumR3CpuIdInit(PVM pVM);
75static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
76static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
77static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
78static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
79static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
80static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
81static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
82
83
84/**
85 * Initializes the CPUM.
86 *
87 * @returns VBox status code.
88 * @param pVM The VM to operate on.
89 */
90CPUMR3DECL(int) CPUMR3Init(PVM pVM)
91{
92 LogFlow(("CPUMR3Init\n"));
93
94 /*
95 * Assert alignment and sizes.
96 */
97 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
98 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
99
100 /*
101 * Setup any fixed pointers and offsets.
102 */
103 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
104 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
105 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
106 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
107
108 /* Hidden selector registers are invalid by default. */
109 pVM->cpum.s.fValidHiddenSelRegs = false;
110
111 /*
112 * Check that the CPU supports the minimum features we require.
113 */
114 /** @todo check the contract! */
115 if (!ASMHasCpuId())
116 {
117 Log(("The CPU doesn't support CPUID!\n"));
118 return VERR_UNSUPPORTED_CPU;
119 }
120 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
121
122 /* Setup the CR4 AND and OR masks used in the switcher */
123 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
124 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
125 {
126 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
127 /* No FXSAVE implies no SSE */
128 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
129 pVM->cpum.s.CR4.OrMask = 0;
130 }
131 else
132 {
133 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
134 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
135 }
136
137 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
138 {
139 Log(("The CPU doesn't support MMX!\n"));
140 return VERR_UNSUPPORTED_CPU;
141 }
142 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
143 {
144 Log(("The CPU doesn't support TSC!\n"));
145 return VERR_UNSUPPORTED_CPU;
146 }
147 /* Bogus on AMD? */
148 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
149 {
150 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
151 }
152
153 /*
154 * Setup hypervisor startup values.
155 */
156
157 /*
158 * Register saved state data item.
159 */
160 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
161 NULL, cpumR3Save, NULL,
162 NULL, cpumR3Load, NULL);
163 if (VBOX_FAILURE(rc))
164 return rc;
165
166 /*
167 * Register info handlers.
168 */
169 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
170 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
171 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
172 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
173 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
174
175 /*
176 * Initialize the Guest CPU state.
177 */
178 rc = cpumR3CpuIdInit(pVM);
179 if (VBOX_FAILURE(rc))
180 return rc;
181 CPUMR3Reset(pVM);
182 return VINF_SUCCESS;
183}
184
185
186/**
187 * Initializes the emulated CPU's cpuid information.
188 *
189 * @returns VBox status code.
190 * @param pVM The VM to operate on.
191 */
192static int cpumR3CpuIdInit(PVM pVM)
193{
194 PCPUM pCPUM = &pVM->cpum.s;
195 uint32_t i;
196
197 /*
198 * Get the host CPUIDs.
199 */
200 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
201 ASMCpuId_Idx_ECX(i, 0,
202 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
203 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
204 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
205 ASMCpuId(0x80000000 + i,
206 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
207 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
208 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
209 ASMCpuId(0xc0000000 + i,
210 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
211 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
212
213
214 /*
215 * Only report features we can support.
216 */
217 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
218 | X86_CPUID_FEATURE_EDX_VME
219 | X86_CPUID_FEATURE_EDX_DE
220 | X86_CPUID_FEATURE_EDX_PSE
221 | X86_CPUID_FEATURE_EDX_TSC
222 | X86_CPUID_FEATURE_EDX_MSR
223 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
224 | X86_CPUID_FEATURE_EDX_MCE
225 | X86_CPUID_FEATURE_EDX_CX8
226 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
227 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
228 //| X86_CPUID_FEATURE_EDX_SEP
229 //| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
230 | X86_CPUID_FEATURE_EDX_PGE
231 //| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
232 | X86_CPUID_FEATURE_EDX_CMOV
233 //| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
234 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
235 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
236 | X86_CPUID_FEATURE_EDX_CLFSH
237 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
238 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
239 | X86_CPUID_FEATURE_EDX_MMX
240 | X86_CPUID_FEATURE_EDX_FXSR
241 | X86_CPUID_FEATURE_EDX_SSE
242 | X86_CPUID_FEATURE_EDX_SSE2
243 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
244 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
245 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
246 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
247 | 0;
248 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
249 | X86_CPUID_FEATURE_ECX_MONITOR
250 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
251 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
252 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
253 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
254 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
255 | 0;
256
257 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
258 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
259 | X86_CPUID_AMD_FEATURE_EDX_VME
260 | X86_CPUID_AMD_FEATURE_EDX_DE
261 | X86_CPUID_AMD_FEATURE_EDX_PSE
262 | X86_CPUID_AMD_FEATURE_EDX_TSC
263 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
264 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
265 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
266 | X86_CPUID_AMD_FEATURE_EDX_CX8
267 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
268 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
269 //| X86_CPUID_AMD_FEATURE_EDX_SEP
270 //| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
271 | X86_CPUID_AMD_FEATURE_EDX_PGE
272 //| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
273 | X86_CPUID_AMD_FEATURE_EDX_CMOV
274 | X86_CPUID_AMD_FEATURE_EDX_PAT
275 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
276 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
277 | X86_CPUID_AMD_FEATURE_EDX_MMX
278 | X86_CPUID_AMD_FEATURE_EDX_FXSR
279 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
280 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
281 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
282 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
283 | 0;
284 pCPUM->aGuestCpuIdExt[1].ecx &= 0//X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
285 | 0;
286
287 /*
288 * Hide HTT, multicode, SMP, whatever.
289 * (APIC-ID := 0 and #LogCpus := 0)
290 */
291 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
292
293 /*
294 * Determin the default.
295 *
296 * Intel returns values of the highest standard function, while AMD
297 * returns zeros. VIA on the other hand seems to returning nothing or
298 * perhaps some random garbage, we don't try duplicate this behavior.
299 */
300 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
301 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
302 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
303
304 /*
305 * Limit it the number of entries and fill the remaining with the defaults.
306 *
307 * The limits are masking off stuff about power saving and similar, this
308 * is perhaps a bit crudely done as there is probably some relatively harmless
309 * info too in these leaves (like words about having a constant TSC).
310 */
311 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
312 pCPUM->aGuestCpuIdStd[0].eax = 2;
313 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
314 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
315
316 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000004))
317 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000004);
318 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
319 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
320 : 0;
321 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
322 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
323
324 /*
325 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
326 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
327 * We don't support more than 1 processor.
328 */
329 pCPUM->aGuestCpuIdStd[4].eax = 0;
330
331 /*
332 * Centaur stuff (VIA).
333 *
334 * The important part here (we think) is to make sure the 0xc0000000
335 * function returns 0xc0000001. As for the features, we don't currently
336 * let on about any of those... 0xc0000002 seems to be some
337 * temperature/hz/++ stuff, include it as well (static).
338 */
339 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
340 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
341 {
342 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
343 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
344 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
345 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
346 i++)
347 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
348 }
349 else
350 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
351 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
352
353
354 /*
355 * Load CPUID overrides from configuration.
356 */
357 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
358 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
359 for (i=0;; )
360 {
361 while (cElements-- > 0)
362 {
363 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
364 if (pNode)
365 {
366 uint32_t u32;
367 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
368 if (VBOX_SUCCESS(rc))
369 pCpuId->eax = u32;
370 else
371 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
372
373 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
374 if (VBOX_SUCCESS(rc))
375 pCpuId->ebx = u32;
376 else
377 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
378
379 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
380 if (VBOX_SUCCESS(rc))
381 pCpuId->ecx = u32;
382 else
383 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
384
385 rc = CFGMR3QueryU32(pNode, "edx", &u32);
386 if (VBOX_SUCCESS(rc))
387 pCpuId->edx = u32;
388 else
389 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
390 }
391 pCpuId++;
392 i++;
393 }
394
395 /* next */
396 if ((i & UINT32_C(0xc0000000)) == 0)
397 {
398 pCpuId = &pCPUM->aGuestCpuIdExt[0];
399 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
400 i = UINT32_C(0x80000000);
401 }
402 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
403 {
404 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
405 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
406 i = UINT32_C(0xc0000000);
407 }
408 else
409 break;
410 }
411
412 /* Check if PAE was explicitely enabled by the user. */
413 bool fEnable = false;
414 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
415 if (VBOX_SUCCESS(rc) && fEnable)
416 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
417
418 /*
419 * Log the cpuid and we're good.
420 */
421 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
422 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
423 LogRel(("************************* CPUID dump ************************\n"));
424 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
425 LogRel(("\n"));
426 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
427 LogRel(("******************** End of CPUID dump **********************\n"));
428 return VINF_SUCCESS;
429}
430
431
432
433
434/**
435 * Applies relocations to data and code managed by this
436 * component. This function will be called at init and
437 * whenever the VMM need to relocate it self inside the GC.
438 *
439 * The CPUM will update the addresses used by the switcher.
440 *
441 * @param pVM The VM.
442 */
443CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
444{
445 LogFlow(("CPUMR3Relocate\n"));
446 /*
447 * Switcher pointers.
448 */
449 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
450 pVM->cpum.s.pHyperCoreGC = MMHyperCCToGC(pVM, pVM->cpum.s.pHyperCoreR3);
451 Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
452}
453
454
455/**
456 * Queries the pointer to the internal CPUMCTX structure
457 *
458 * @returns VBox status code.
459 * @param pVM Handle to the virtual machine.
460 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
461 */
462CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
463{
464 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
465 /*
466 * Store the address. (Later we might check how's calling, thus the RC.)
467 */
468 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
469 return VINF_SUCCESS;
470}
471
472
473/**
474 * Terminates the CPUM.
475 *
476 * Termination means cleaning up and freeing all resources,
477 * the VM it self is at this point powered off or suspended.
478 *
479 * @returns VBox status code.
480 * @param pVM The VM to operate on.
481 */
482CPUMR3DECL(int) CPUMR3Term(PVM pVM)
483{
484 /** @todo */
485 return 0;
486}
487
488
489/**
490 * Resets the CPU.
491 *
492 * @returns VINF_SUCCESS.
493 * @param pVM The VM handle.
494 */
495CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
496{
497 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
498
499 /*
500 * Initialize everything to ZERO first.
501 */
502 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
503 memset(pCtx, 0, sizeof(*pCtx));
504 pVM->cpum.s.fUseFlags = fUseFlags;
505
506 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
507 pCtx->eip = 0x0000fff0;
508 pCtx->edx = 0x00000600; /* P6 processor */
509 pCtx->eflags.Bits.u1Reserved0 = 1;
510
511 pCtx->cs = 0xf000;
512 pCtx->csHid.u32Base = 0xffff0000;
513 pCtx->csHid.u32Limit = 0x0000ffff;
514 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
515 pCtx->csHid.Attr.n.u1Present = 1;
516 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
517
518 pCtx->dsHid.u32Limit = 0x0000ffff;
519 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
520 pCtx->dsHid.Attr.n.u1Present = 1;
521 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
522
523 pCtx->esHid.u32Limit = 0x0000ffff;
524 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
525 pCtx->esHid.Attr.n.u1Present = 1;
526 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
527
528 pCtx->fsHid.u32Limit = 0x0000ffff;
529 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
530 pCtx->fsHid.Attr.n.u1Present = 1;
531 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
532
533 pCtx->gsHid.u32Limit = 0x0000ffff;
534 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
535 pCtx->gsHid.Attr.n.u1Present = 1;
536 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
537
538 pCtx->ssHid.u32Limit = 0x0000ffff;
539 pCtx->ssHid.Attr.n.u1Present = 1;
540 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
541 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
542
543 pCtx->idtr.cbIdt = 0xffff;
544 pCtx->gdtr.cbGdt = 0xffff;
545
546 pCtx->ldtrHid.u32Limit = 0xffff;
547 pCtx->ldtrHid.Attr.n.u1Present = 1;
548 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
549
550 pCtx->trHid.u32Limit = 0xffff;
551 pCtx->trHid.Attr.n.u1Present = 1;
552 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
553
554 pCtx->dr6 = 0xFFFF0FF0;
555 pCtx->dr7 = 0x400;
556
557 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
558 pCtx->fpu.FCW = 0x37f;
559
560 /* Init PAT MSR */
561 pCtx->msrPAT = 0x0007040600070406ULL; /* @todo correct? */
562}
563
564
565
566/**
567 * Execute state save operation.
568 *
569 * @returns VBox status code.
570 * @param pVM VM Handle.
571 * @param pSSM SSM operation handle.
572 */
573static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
574{
575 /*
576 * Save.
577 */
578 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
579 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
580 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
581 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
582
583 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
584 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
585
586 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
587 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
588
589 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
590 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
591
592 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
593
594 /* Add the cpuid for checking that the cpu is unchanged. */
595 uint32_t au32CpuId[8] = {0};
596 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
597 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
598 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
599}
600
601
602/**
603 * Execute state load operation.
604 *
605 * @returns VBox status code.
606 * @param pVM VM Handle.
607 * @param pSSM SSM operation handle.
608 * @param u32Version Data layout version.
609 */
610static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
611{
612 /*
613 * Validate version.
614 */
615 if (u32Version != CPUM_SAVED_STATE_VERSION)
616 {
617 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
618 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
619 }
620
621 /*
622 * Restore.
623 */
624 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
625 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
626 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
627 pVM->cpum.s.Hyper.cr3 = uCR3;
628 pVM->cpum.s.Hyper.esp = uESP;
629 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
630 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
631 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
632
633 uint32_t cElements;
634 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
635 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
636 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
637 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
638
639 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
640 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
641 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
642 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
643
644 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
645 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
646 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
647 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
648
649 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
650
651 /*
652 * Check that the basic cpuid id information is unchanged.
653 */
654 uint32_t au32CpuId[8] = {0};
655 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
656 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
657 uint32_t au32CpuIdSaved[8];
658 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
659 if (VBOX_SUCCESS(rc))
660 {
661 /* Ignore APIC ID (AMD specs). */
662 au32CpuId[5] &= ~0xff000000;
663 au32CpuIdSaved[5] &= ~0xff000000;
664 /* Ignore the number of Logical CPUs (AMD specs). */
665 au32CpuId[5] &= ~0x00ff0000;
666 au32CpuIdSaved[5] &= ~0x00ff0000;
667
668 /* do the compare */
669 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
670 {
671 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
672 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
673 "Saved=%.*Vhxs\n"
674 "Real =%.*Vhxs\n",
675 sizeof(au32CpuIdSaved), au32CpuIdSaved,
676 sizeof(au32CpuId), au32CpuId));
677 else
678 {
679 LogRel(("cpumR3Load: CpuId mismatch!\n"
680 "Saved=%.*Vhxs\n"
681 "Real =%.*Vhxs\n",
682 sizeof(au32CpuIdSaved), au32CpuIdSaved,
683 sizeof(au32CpuId), au32CpuId));
684 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
685 }
686 }
687 }
688
689 return rc;
690}
691
692
693/**
694 * Formats the EFLAGS value into mnemonics.
695 *
696 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
697 * @param efl The EFLAGS value.
698 */
699static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
700{
701 /*
702 * Format the flags.
703 */
704 static struct
705 {
706 const char *pszSet; const char *pszClear; uint32_t fFlag;
707 } s_aFlags[] =
708 {
709 { "vip",NULL, X86_EFL_VIP },
710 { "vif",NULL, X86_EFL_VIF },
711 { "ac", NULL, X86_EFL_AC },
712 { "vm", NULL, X86_EFL_VM },
713 { "rf", NULL, X86_EFL_RF },
714 { "nt", NULL, X86_EFL_NT },
715 { "ov", "nv", X86_EFL_OF },
716 { "dn", "up", X86_EFL_DF },
717 { "ei", "di", X86_EFL_IF },
718 { "tf", NULL, X86_EFL_TF },
719 { "nt", "pl", X86_EFL_SF },
720 { "nz", "zr", X86_EFL_ZF },
721 { "ac", "na", X86_EFL_AF },
722 { "po", "pe", X86_EFL_PF },
723 { "cy", "nc", X86_EFL_CF },
724 };
725 char *psz = pszEFlags;
726 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
727 {
728 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
729 if (pszAdd)
730 {
731 strcpy(psz, pszAdd);
732 psz += strlen(pszAdd);
733 *psz++ = ' ';
734 }
735 }
736 psz[-1] = '\0';
737}
738
739
740/**
741 * Formats a full register dump.
742 *
743 * @param pCtx The context to format.
744 * @param pCtxCore The context core to format.
745 * @param pHlp Output functions.
746 * @param enmType The dump type.
747 * @param pszPrefix Register name prefix.
748 */
749static void cpumR3InfoOne(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
750{
751 /*
752 * Format the EFLAGS.
753 */
754 uint32_t efl = pCtxCore->eflags.u32;
755 char szEFlags[80];
756 cpumR3InfoFormatFlags(&szEFlags[0], efl);
757
758 /*
759 * Format the registers.
760 */
761 switch (enmType)
762 {
763 case CPUMDUMPTYPE_TERSE:
764 pHlp->pfnPrintf(pHlp,
765 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
766 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
767 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
768 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
769 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
770 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
771 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
772 break;
773
774 case CPUMDUMPTYPE_DEFAULT:
775 pHlp->pfnPrintf(pHlp,
776 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
777 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
778 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
779 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08x:%04x %sldtr=%04x\n"
780 ,
781 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
782 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
783 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
784 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
785 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
786 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
787 break;
788
789 case CPUMDUMPTYPE_VERBOSE:
790 pHlp->pfnPrintf(pHlp,
791 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
792 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
793 "%scs={%04x base=%08x limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
794 "%sds={%04x base=%08x limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
795 "%ses={%04x base=%08x limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
796 "%sfs={%04x base=%08x limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
797 "%sgs={%04x base=%08x limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
798 "%sss={%04x base=%08x limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
799 "%sgdtr=%08x:%04x %sidtr=%08x:%04x %seflags=%08x\n"
800 "%sldtr={%04x base=%08x limit=%08x flags=%08x}\n"
801 "%str ={%04x base=%08x limit=%08x flags=%08x}\n"
802 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
803 ,
804 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
805 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
806 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
807 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
808 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
809 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
810 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
811 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
812 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
813 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u32Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
814 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u32Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
815 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
816
817 pHlp->pfnPrintf(pHlp,
818 "FPU:\n"
819 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
820 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
821 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
822 ,
823 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
824 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
825 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
826 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
827
828
829 break;
830 }
831}
832
833
834/**
835 * Display all cpu states and any other cpum info.
836 *
837 * @param pVM VM Handle.
838 * @param pHlp The info helper functions.
839 * @param pszArgs Arguments, ignored.
840 */
841static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
842{
843 cpumR3InfoGuest(pVM, pHlp, pszArgs);
844 cpumR3InfoHyper(pVM, pHlp, pszArgs);
845 cpumR3InfoHost(pVM, pHlp, pszArgs);
846}
847
848
849/**
850 * Parses the info argument.
851 *
852 * The argument starts with 'verbose', 'terse' or 'default' and then
853 * continues with the comment string.
854 *
855 * @param pszArgs The pointer to the argument string.
856 * @param penmType Where to store the dump type request.
857 * @param ppszComment Where to store the pointer to the comment string.
858 */
859static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
860{
861 if (!pszArgs)
862 {
863 *penmType = CPUMDUMPTYPE_DEFAULT;
864 *ppszComment = "";
865 }
866 else
867 {
868 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
869 {
870 pszArgs += 5;
871 *penmType = CPUMDUMPTYPE_VERBOSE;
872 }
873 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
874 {
875 pszArgs += 5;
876 *penmType = CPUMDUMPTYPE_TERSE;
877 }
878 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
879 {
880 pszArgs += 7;
881 *penmType = CPUMDUMPTYPE_DEFAULT;
882 }
883 else
884 *penmType = CPUMDUMPTYPE_DEFAULT;
885 *ppszComment = RTStrStripL(pszArgs);
886 }
887}
888
889
890/**
891 * Display the guest cpu state.
892 *
893 * @param pVM VM Handle.
894 * @param pHlp The info helper functions.
895 * @param pszArgs Arguments, ignored.
896 */
897static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
898{
899 CPUMDUMPTYPE enmType;
900 const char *pszComment;
901 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
902 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
903 cpumR3InfoOne(&pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
904}
905
906
907/**
908 * Display the hypervisor cpu state.
909 *
910 * @param pVM VM Handle.
911 * @param pHlp The info helper functions.
912 * @param pszArgs Arguments, ignored.
913 */
914static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
915{
916 CPUMDUMPTYPE enmType;
917 const char *pszComment;
918 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
919 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
920 cpumR3InfoOne(&pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
921 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
922}
923
924
925/**
926 * Display the host cpu state.
927 *
928 * @param pVM VM Handle.
929 * @param pHlp The info helper functions.
930 * @param pszArgs Arguments, ignored.
931 */
932static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
933{
934 CPUMDUMPTYPE enmType;
935 const char *pszComment;
936 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
937 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
938
939 /*
940 * Format the EFLAGS.
941 */
942 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
943#if HC_ARCH_BITS == 32
944 uint32_t efl = pCtx->eflags.u32;
945#else
946 uint64_t efl = pCtx->rflags;
947#endif
948 char szEFlags[80];
949 cpumR3InfoFormatFlags(&szEFlags[0], efl);
950
951 /*
952 * Format the registers.
953 */
954#if HC_ARCH_BITS == 32
955# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
956 if (!(pCtx->efer & MSR_K6_EFER_LMA))
957# endif
958 {
959 pHlp->pfnPrintf(pHlp,
960 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
961 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
962 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
963 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
964 "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
965 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
966 ,
967 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
968 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
969 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
970 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
971 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
972 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
973 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
974 }
975# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
976 else
977# endif
978#endif
979#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
980 {
981 pHlp->pfnPrintf(pHlp,
982 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
983 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
984 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
985 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
986 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
987 "r14=%016RX64 r15=%016RX64\n"
988 "iopl=%d %31s\n"
989 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
990 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
991 "cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
992 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
993 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
994 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
995 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
996 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
997 ,
998 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
999 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1000 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1001 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1002 pCtx->r11, pCtx->r12, pCtx->r13,
1003 pCtx->r14, pCtx->r15,
1004 X86_EFL_GET_IOPL(efl), szEFlags,
1005 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1006 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1007 pCtx->cr4, pCtx->cr8, pCtx->ldtr, pCtx->tr,
1008 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1009 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1010 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1011 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1012 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1013 }
1014#endif
1015}
1016
1017/**
1018 * Get L1 cache / TLS associativity.
1019 */
1020static const char *getCacheAss(unsigned u, char *pszBuf)
1021{
1022 if (u == 0)
1023 return "res0 ";
1024 if (u == 1)
1025 return "direct";
1026 if (u >= 256)
1027 return "???";
1028
1029 RTStrPrintf(pszBuf, 16, "%d way", u);
1030 return pszBuf;
1031}
1032
1033
1034/**
1035 * Get L2 cache soociativity.
1036 */
1037const char *getL2CacheAss(unsigned u)
1038{
1039 switch (u)
1040 {
1041 case 0: return "off ";
1042 case 1: return "direct";
1043 case 2: return "2 way ";
1044 case 3: return "res3 ";
1045 case 4: return "4 way ";
1046 case 5: return "res5 ";
1047 case 6: return "8 way "; case 7: return "res7 ";
1048 case 8: return "16 way";
1049 case 9: return "res9 ";
1050 case 10: return "res10 ";
1051 case 11: return "res11 ";
1052 case 12: return "res12 ";
1053 case 13: return "res13 ";
1054 case 14: return "res14 ";
1055 case 15: return "fully ";
1056 default:
1057 return "????";
1058 }
1059}
1060
1061
1062/**
1063 * Display the guest CpuId leaves.
1064 *
1065 * @param pVM VM Handle.
1066 * @param pHlp The info helper functions.
1067 * @param pszArgs "terse", "default" or "verbose".
1068 */
1069static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1070{
1071 /*
1072 * Parse the argument.
1073 */
1074 unsigned iVerbosity = 1;
1075 if (pszArgs)
1076 {
1077 pszArgs = RTStrStripL(pszArgs);
1078 if (!strcmp(pszArgs, "terse"))
1079 iVerbosity--;
1080 else if (!strcmp(pszArgs, "verbose"))
1081 iVerbosity++;
1082 }
1083
1084 /*
1085 * Start cracking.
1086 */
1087 CPUMCPUID Host;
1088 CPUMCPUID Guest;
1089 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1090
1091 pHlp->pfnPrintf(pHlp,
1092 " RAW Standard CPUIDs\n"
1093 " Function eax ebx ecx edx\n");
1094 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1095 {
1096 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1097 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1098
1099 pHlp->pfnPrintf(pHlp,
1100 "Gst: %08x %08x %08x %08x %08x%s\n"
1101 "Hst: %08x %08x %08x %08x\n",
1102 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1103 i <= cStdMax ? "" : "*",
1104 Host.eax, Host.ebx, Host.ecx, Host.edx);
1105 }
1106
1107 /*
1108 * If verbose, decode it.
1109 */
1110 if (iVerbosity)
1111 {
1112 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1113 pHlp->pfnPrintf(pHlp,
1114 "Name: %.04s%.04s%.04s\n"
1115 "Supports: 0-%x\n",
1116 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1117 }
1118
1119 /*
1120 * Get Features.
1121 */
1122 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1123 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1124 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1125 if (cStdMax >= 1 && iVerbosity)
1126 {
1127 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1128 uint32_t uEAX = Guest.eax;
1129
1130 pHlp->pfnPrintf(pHlp,
1131 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1132 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1133 "Stepping: %d\n"
1134 "APIC ID: %#04x\n"
1135 "Logical CPUs: %d\n"
1136 "CLFLUSH Size: %d\n"
1137 "Brand ID: %#04x\n",
1138 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1139 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1140 ASMGetCpuStepping(uEAX),
1141 (Guest.ebx >> 24) & 0xff,
1142 (Guest.ebx >> 16) & 0xff,
1143 (Guest.ebx >> 8) & 0xff,
1144 (Guest.ebx >> 0) & 0xff);
1145 if (iVerbosity == 1)
1146 {
1147 uint32_t uEDX = Guest.edx;
1148 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1149 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1150 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1151 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1152 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1153 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1154 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1155 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1156 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1157 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1158 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1159 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1160 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1161 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1162 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1163 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1164 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1165 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1166 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1167 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1168 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1169 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1170 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1171 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1172 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1173 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1174 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1175 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1176 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1177 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1178 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1179 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1180 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1181 pHlp->pfnPrintf(pHlp, "\n");
1182
1183 uint32_t uECX = Guest.ecx;
1184 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1185 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1186 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1187 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1188 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1189 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1190 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1191 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1192 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1193 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1194 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1195 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1196 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1197 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1198 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1199 for (unsigned iBit = 14; iBit < 32; iBit++)
1200 if (uECX & RT_BIT(iBit))
1201 pHlp->pfnPrintf(pHlp, " %d", iBit);
1202 pHlp->pfnPrintf(pHlp, "\n");
1203 }
1204 else
1205 {
1206 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1207
1208 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1209 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1210 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1211 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1212
1213 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1214 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1215 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1216 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1217 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1218 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1219 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1220 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1221 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1222 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1223 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1224 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1225 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1226 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1227 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1228 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1229 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1230 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1231 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1232 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1233 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1234 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1235 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1236 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1237 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1238 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1239 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1240 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1241 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1242 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1243 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1244 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1245 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1246
1247 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1248 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1249 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1250 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1251 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1252 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1253 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1254 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1255 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1256 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1257 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1258 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1259 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1260 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1261 }
1262 }
1263 if (cStdMax >= 2 && iVerbosity)
1264 {
1265 /** @todo */
1266 }
1267
1268 /*
1269 * Extended.
1270 * Implemented after AMD specs.
1271 */
1272 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1273
1274 pHlp->pfnPrintf(pHlp,
1275 "\n"
1276 " RAW Extended CPUIDs\n"
1277 " Function eax ebx ecx edx\n");
1278 for (unsigned i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1279 {
1280 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1281 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1282
1283 pHlp->pfnPrintf(pHlp,
1284 "Gst: %08x %08x %08x %08x %08x%s\n"
1285 "Hst: %08x %08x %08x %08x\n",
1286 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1287 i <= cExtMax ? "" : "*",
1288 Host.eax, Host.ebx, Host.ecx, Host.edx);
1289 }
1290
1291 /*
1292 * Understandable output
1293 */
1294 if (iVerbosity && cExtMax >= 0)
1295 {
1296 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1297 pHlp->pfnPrintf(pHlp,
1298 "Ext Name: %.4s%.4s%.4s\n"
1299 "Ext Supports: 0x80000000-%#010x\n",
1300 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1301 }
1302
1303 if (iVerbosity && cExtMax >= 1)
1304 {
1305 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1306 uint32_t uEAX = Guest.eax;
1307 pHlp->pfnPrintf(pHlp,
1308 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1309 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1310 "Stepping: %d\n"
1311 "Brand ID: %#05x\n",
1312 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1313 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1314 ASMGetCpuStepping(uEAX),
1315 Guest.ebx & 0xfff);
1316
1317 if (iVerbosity == 1)
1318 {
1319 uint32_t uEDX = Guest.edx;
1320 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1321 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1322 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1323 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1324 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1325 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1326 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1327 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1328 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1329 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1330 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1331 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1332 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1333 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1334 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1335 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1336 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1337 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1338 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1339 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1340 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1341 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1342 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1343 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1344 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1345 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1346 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1347 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1348 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1349 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1350 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1351 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1352 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1353 pHlp->pfnPrintf(pHlp, "\n");
1354
1355 uint32_t uECX = Guest.ecx;
1356 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1357 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1358 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1359 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1360 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1361 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1362 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1363 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1364 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1365 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1366 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1367 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1368 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1369 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1370 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1371 for (unsigned iBit = 5; iBit < 32; iBit++)
1372 if (uECX & RT_BIT(iBit))
1373 pHlp->pfnPrintf(pHlp, " %d", iBit);
1374 pHlp->pfnPrintf(pHlp, "\n");
1375 }
1376 else
1377 {
1378 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1379
1380 uint32_t uEdxGst = Guest.edx;
1381 uint32_t uEdxHst = Host.edx;
1382 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1383 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1384 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1385 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1386 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1387 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1388 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1389 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1390 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1391 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1392 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1393 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1394 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1395 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1396 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1397 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1398 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1399 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1400 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1401 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1402 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1403 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1404 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1405 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1406 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1407 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1408 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1409 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1410 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1411 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1412 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1413 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1414 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1415
1416 uint32_t uEcxGst = Guest.ecx;
1417 uint32_t uEcxHst = Host.ecx;
1418 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1419 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1420 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1421 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1422 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1423 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1424 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1425 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1426 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1427 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1428 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1429 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1430 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1431 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1432 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1433 }
1434 }
1435
1436 if (iVerbosity && cExtMax >= 2)
1437 {
1438 char szString[4*4*3+1] = {0};
1439 uint32_t *pu32 = (uint32_t *)szString;
1440 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1441 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1442 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1443 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1444 if (cExtMax >= 3)
1445 {
1446 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1447 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1448 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1449 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1450 }
1451 if (cExtMax >= 4)
1452 {
1453 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1454 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1455 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1456 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1457 }
1458 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1459 }
1460
1461 if (iVerbosity && cExtMax >= 5)
1462 {
1463 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1464 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1465 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1466 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1467 char sz1[32];
1468 char sz2[32];
1469
1470 pHlp->pfnPrintf(pHlp,
1471 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1472 "TLB 2/4M Data: %s %3d entries\n",
1473 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1474 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1475 pHlp->pfnPrintf(pHlp,
1476 "TLB 4K Instr/Uni: %s %3d entries\n"
1477 "TLB 4K Data: %s %3d entries\n",
1478 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1479 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1480 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1481 "L1 Instr Cache Lines Per Tag: %d\n"
1482 "L1 Instr Cache Associativity: %s\n"
1483 "L1 Instr Cache Size: %d KB\n",
1484 (uEDX >> 0) & 0xff,
1485 (uEDX >> 8) & 0xff,
1486 getCacheAss((uEDX >> 16) & 0xff, sz1),
1487 (uEDX >> 24) & 0xff);
1488 pHlp->pfnPrintf(pHlp,
1489 "L1 Data Cache Line Size: %d bytes\n"
1490 "L1 Data Cache Lines Per Tag: %d\n"
1491 "L1 Data Cache Associativity: %s\n"
1492 "L1 Data Cache Size: %d KB\n",
1493 (uECX >> 0) & 0xff,
1494 (uECX >> 8) & 0xff,
1495 getCacheAss((uECX >> 16) & 0xff, sz1),
1496 (uECX >> 24) & 0xff);
1497 }
1498
1499 if (iVerbosity && cExtMax >= 6)
1500 {
1501 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1502 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1503 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1504
1505 pHlp->pfnPrintf(pHlp,
1506 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1507 "L2 TLB 2/4M Data: %s %4d entries\n",
1508 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1509 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1510 pHlp->pfnPrintf(pHlp,
1511 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1512 "L2 TLB 4K Data: %s %4d entries\n",
1513 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1514 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1515 pHlp->pfnPrintf(pHlp,
1516 "L2 Cache Line Size: %d bytes\n"
1517 "L2 Cache Lines Per Tag: %d\n"
1518 "L2 Cache Associativity: %s\n"
1519 "L2 Cache Size: %d KB\n",
1520 (uEDX >> 0) & 0xff,
1521 (uEDX >> 8) & 0xf,
1522 getL2CacheAss((uEDX >> 12) & 0xf),
1523 (uEDX >> 16) & 0xffff);
1524 }
1525
1526 if (iVerbosity && cExtMax >= 7)
1527 {
1528 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1529
1530 pHlp->pfnPrintf(pHlp, "APM Features: ");
1531 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1532 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1533 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1534 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1535 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1536 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1537 for (unsigned iBit = 6; iBit < 32; iBit++)
1538 if (uEDX & RT_BIT(iBit))
1539 pHlp->pfnPrintf(pHlp, " %d", iBit);
1540 pHlp->pfnPrintf(pHlp, "\n");
1541 }
1542
1543 if (iVerbosity && cExtMax >= 8)
1544 {
1545 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1546 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1547
1548 pHlp->pfnPrintf(pHlp,
1549 "Physical Address Width: %d bits\n"
1550 "Virtual Address Width: %d bits\n",
1551 (uEAX >> 0) & 0xff,
1552 (uEAX >> 8) & 0xff);
1553 pHlp->pfnPrintf(pHlp,
1554 "Physical Core Count: %d\n",
1555 (uECX >> 0) & 0xff);
1556 }
1557
1558
1559 /*
1560 * Centaur.
1561 */
1562 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1563
1564 pHlp->pfnPrintf(pHlp,
1565 "\n"
1566 " RAW Centaur CPUIDs\n"
1567 " Function eax ebx ecx edx\n");
1568 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1569 {
1570 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1571 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1572
1573 pHlp->pfnPrintf(pHlp,
1574 "Gst: %08x %08x %08x %08x %08x%s\n"
1575 "Hst: %08x %08x %08x %08x\n",
1576 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1577 i <= cCentaurMax ? "" : "*",
1578 Host.eax, Host.ebx, Host.ecx, Host.edx);
1579 }
1580
1581 /*
1582 * Understandable output
1583 */
1584 if (iVerbosity && cCentaurMax >= 0)
1585 {
1586 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1587 pHlp->pfnPrintf(pHlp,
1588 "Centaur Supports: 0xc0000000-%#010x\n",
1589 Guest.eax);
1590 }
1591
1592 if (iVerbosity && cCentaurMax >= 1)
1593 {
1594 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1595 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1596 uint32_t uEdxHst = Host.edx;
1597
1598 if (iVerbosity == 1)
1599 {
1600 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1601 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1602 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1603 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1604 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1605 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1606 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1607 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1608 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1609 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1610 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
1611 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
1612 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
1613 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
1614 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
1615 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
1616 for (unsigned iBit = 14; iBit < 32; iBit++)
1617 if (uEdxGst & RT_BIT(iBit))
1618 pHlp->pfnPrintf(pHlp, " %d", iBit);
1619 pHlp->pfnPrintf(pHlp, "\n");
1620 }
1621 else
1622 {
1623 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1624 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1625 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1626 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1627 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1628 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1629 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1630 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1631 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1632 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1633 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1634 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1635 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1636 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1637 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1638 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1639 for (unsigned iBit = 14; iBit < 32; iBit++)
1640 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
1641 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
1642 pHlp->pfnPrintf(pHlp, "\n");
1643 }
1644 }
1645}
1646
1647
1648/**
1649 * Structure used when disassembling and instructions in DBGF.
1650 * This is used so the reader function can get the stuff it needs.
1651 */
1652typedef struct CPUMDISASSTATE
1653{
1654 /** Pointer to the CPU structure. */
1655 PDISCPUSTATE pCpu;
1656 /** The VM handle. */
1657 PVM pVM;
1658 /** Pointer to the first byte in the segemnt. */
1659 RTGCUINTPTR GCPtrSegBase;
1660 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1661 RTGCUINTPTR GCPtrSegEnd;
1662 /** The size of the segment minus 1. */
1663 RTGCUINTPTR cbSegLimit;
1664 /** Pointer to the current page - HC Ptr. */
1665 void const *pvPageHC;
1666 /** Pointer to the current page - GC Ptr. */
1667 RTGCPTR pvPageGC;
1668 /** The lock information that PGMPhysReleasePageMappingLock needs. */
1669 PGMPAGEMAPLOCK PageMapLock;
1670 /** Whether the PageMapLock is valid or not. */
1671 bool fLocked;
1672} CPUMDISASSTATE, *PCPUMDISASSTATE;
1673
1674
1675/**
1676 * Instruction reader.
1677 *
1678 * @returns VBox status code.
1679 * @param PtrSrc Address to read from.
1680 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1681 * @param pu8Dst Where to store the bytes.
1682 * @param cbRead Number of bytes to read.
1683 * @param uDisCpu Pointer to the disassembler cpu state.
1684 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1685 */
1686static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
1687{
1688 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1689 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
1690 Assert(cbRead > 0);
1691 for (;;)
1692 {
1693 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1694
1695 /* Need to update the page translation? */
1696 if ( !pState->pvPageHC
1697 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1698 {
1699 int rc = VINF_SUCCESS;
1700
1701 /* translate the address */
1702 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1703 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1704 {
1705 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1706 if (!pState->pvPageHC)
1707 rc = VERR_INVALID_POINTER;
1708 }
1709 else
1710 {
1711 /* Release mapping lock previously acquired. */
1712 if (pState->fLocked)
1713 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
1714 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
1715 pState->fLocked = RT_SUCCESS_NP(rc);
1716 }
1717 if (VBOX_FAILURE(rc))
1718 {
1719 pState->pvPageHC = NULL;
1720 return rc;
1721 }
1722 }
1723
1724 /* check the segemnt limit */
1725 if (PtrSrc > pState->cbSegLimit)
1726 return VERR_OUT_OF_SELECTOR_BOUNDS;
1727
1728 /* calc how much we can read */
1729 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1730 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1731 if (cb > cbSeg && !cbSeg)
1732 cb = cbSeg;
1733 if (cb > cbRead)
1734 cb = cbRead;
1735
1736 /* read and advance */
1737 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1738 cbRead -= cb;
1739 if (!cbRead)
1740 return VINF_SUCCESS;
1741 pu8Dst += cb;
1742 PtrSrc += cb;
1743 }
1744}
1745
1746
1747/**
1748 * Disassemble an instruction and return the information in the provided structure.
1749 *
1750 * @returns VBox status code.
1751 * @param pVM VM Handle
1752 * @param pCtx CPU context
1753 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1754 * @param pCpu Disassembly state
1755 * @param pszPrefix String prefix for logging (debug only)
1756 *
1757 */
1758CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1759{
1760 CPUMDISASSTATE State;
1761 int rc;
1762
1763 State.pCpu = pCpu;
1764 State.pvPageGC = 0;
1765 State.pvPageHC = NULL;
1766 State.pVM = pVM;
1767 State.fLocked = false;
1768
1769 /*
1770 * Get selector information.
1771 */
1772 if ( (pCtx->cr0 & X86_CR0_PE)
1773 && pCtx->eflags.Bits.u1VM == 0)
1774 {
1775 if (CPUMAreHiddenSelRegsValid(pVM))
1776 {
1777 State.GCPtrSegBase = pCtx->csHid.u32Base;
1778 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u32Base;
1779 State.cbSegLimit = pCtx->csHid.u32Limit;
1780 pCpu->mode = pCtx->csHid.Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1781 }
1782 else
1783 {
1784 SELMSELINFO SelInfo;
1785
1786 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1787 if (!VBOX_SUCCESS(rc))
1788 {
1789 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1790 return rc;
1791 }
1792
1793 /*
1794 * Validate the selector.
1795 */
1796 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1797 if (!VBOX_SUCCESS(rc))
1798 {
1799 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1800 return rc;
1801 }
1802 State.GCPtrSegBase = SelInfo.GCPtrBase;
1803 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1804 State.cbSegLimit = SelInfo.cbLimit;
1805 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1806 }
1807 }
1808 else
1809 {
1810 /* real or V86 mode */
1811 pCpu->mode = CPUMODE_16BIT;
1812 State.GCPtrSegBase = pCtx->cs * 16;
1813 State.GCPtrSegEnd = 0xFFFFFFFF;
1814 State.cbSegLimit = 0xFFFFFFFF;
1815 }
1816
1817 /*
1818 * Disassemble the instruction.
1819 */
1820 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
1821 pCpu->apvUserData[0] = &State;
1822
1823 uint32_t cbInstr;
1824#ifndef LOG_ENABLED
1825 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
1826 if (VBOX_SUCCESS(rc))
1827 {
1828#else
1829 char szOutput[160];
1830 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
1831 if (VBOX_SUCCESS(rc))
1832 {
1833 /* log it */
1834 if (pszPrefix)
1835 Log(("%s: %s", pszPrefix, szOutput));
1836 else
1837 Log(("%s", szOutput));
1838#endif
1839 rc = VINF_SUCCESS;
1840 }
1841 else
1842 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
1843
1844 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
1845 if (State.fLocked)
1846 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
1847
1848 return rc;
1849}
1850
1851
1852#ifdef DEBUG
1853/**
1854 * Disassemble an instruction and dump it to the log
1855 *
1856 * @returns VBox status code.
1857 * @param pVM VM Handle
1858 * @param pCtx CPU context
1859 * @param pc GC instruction pointer
1860 * @param prefix String prefix for logging
1861 * @deprecated Use DBGFR3DisasInstrCurrentLog().
1862 *
1863 */
1864CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
1865{
1866 DISCPUSTATE cpu;
1867
1868 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1869}
1870
1871/**
1872 * Disassemble an instruction and dump it to the log
1873 *
1874 * @returns VBox status code.
1875 * @param pVM VM Handle
1876 * @param pCtx CPU context
1877 * @param pc GC instruction pointer
1878 * @param prefix String prefix for logging
1879 * @param nrInstructions
1880 *
1881 */
1882CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
1883{
1884 for(int i=0;i<nrInstructions;i++)
1885 {
1886 DISCPUSTATE cpu;
1887
1888 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1889 pc += cpu.opsize;
1890 }
1891}
1892
1893#endif
1894
1895#ifdef DEBUG
1896/**
1897 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
1898 *
1899 * @internal
1900 */
1901CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
1902{
1903 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
1904}
1905#endif
1906
1907
1908/**
1909 * API for controlling a few of the CPU features found in CR4.
1910 *
1911 * Currently only X86_CR4_TSD is accepted as input.
1912 *
1913 * @returns VBox status code.
1914 *
1915 * @param pVM The VM handle.
1916 * @param fOr The CR4 OR mask.
1917 * @param fAnd The CR4 AND mask.
1918 */
1919CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
1920{
1921 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
1922 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
1923
1924 pVM->cpum.s.CR4.OrMask &= fAnd;
1925 pVM->cpum.s.CR4.OrMask |= fOr;
1926
1927 return VINF_SUCCESS;
1928}
1929
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