VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 9507

Last change on this file since 9507 was 9465, checked in by vboxsync, 17 years ago

Same for idtr & gdtr
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1/* $Id: CPUM.cpp 9465 2008-06-06 11:38:59Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum
23 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
24 * also responsible for lazy FPU handling and some of the context loading
25 * in raw mode.
26 *
27 * There are three CPU contexts, the most important one is the guest one (GC).
28 * When running in raw-mode (RC) there is a special hyper context for the VMM
29 * that floats around inside the guest address space. When running in raw-mode
30 * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host
31 * context for saving and restoring registers accross world switches. This latter
32 * is done in cooperation with the world switcher (@see pg_vmm).
33 */
34
35/*******************************************************************************
36* Header Files *
37*******************************************************************************/
38#define LOG_GROUP LOG_GROUP_CPUM
39#include <VBox/cpum.h>
40#include <VBox/cpumdis.h>
41#include <VBox/pgm.h>
42#include <VBox/mm.h>
43#include <VBox/selm.h>
44#include <VBox/dbgf.h>
45#include <VBox/patm.h>
46#include <VBox/ssm.h>
47#include "CPUMInternal.h"
48#include <VBox/vm.h>
49
50#include <VBox/param.h>
51#include <VBox/dis.h>
52#include <VBox/err.h>
53#include <VBox/log.h>
54#include <iprt/assert.h>
55#include <iprt/asm.h>
56#include <iprt/string.h>
57#include <iprt/system.h>
58
59
60/*******************************************************************************
61* Defined Constants And Macros *
62*******************************************************************************/
63/** The saved state version. */
64#define CPUM_SAVED_STATE_VERSION 7
65
66
67/*******************************************************************************
68* Structures and Typedefs *
69*******************************************************************************/
70
71/**
72 * What kind of cpu info dump to perform.
73 */
74typedef enum CPUMDUMPTYPE
75{
76 CPUMDUMPTYPE_TERSE,
77 CPUMDUMPTYPE_DEFAULT,
78 CPUMDUMPTYPE_VERBOSE
79
80} CPUMDUMPTYPE;
81/** Pointer to a cpu info dump type. */
82typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
83
84
85/*******************************************************************************
86* Internal Functions *
87*******************************************************************************/
88static int cpumR3CpuIdInit(PVM pVM);
89static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
90static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
91static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
92static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
93static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
94static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
95static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
96
97
98/**
99 * Initializes the CPUM.
100 *
101 * @returns VBox status code.
102 * @param pVM The VM to operate on.
103 */
104CPUMR3DECL(int) CPUMR3Init(PVM pVM)
105{
106 LogFlow(("CPUMR3Init\n"));
107
108 /*
109 * Assert alignment and sizes.
110 */
111 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
112 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
113
114 /*
115 * Setup any fixed pointers and offsets.
116 */
117 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
118 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
119 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
120 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
121
122 /* Hidden selector registers are invalid by default. */
123 pVM->cpum.s.fValidHiddenSelRegs = false;
124
125 /*
126 * Check that the CPU supports the minimum features we require.
127 */
128 /** @todo check the contract! */
129 if (!ASMHasCpuId())
130 {
131 Log(("The CPU doesn't support CPUID!\n"));
132 return VERR_UNSUPPORTED_CPU;
133 }
134 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
135
136 /* Setup the CR4 AND and OR masks used in the switcher */
137 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
138 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
139 {
140 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
141 /* No FXSAVE implies no SSE */
142 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
143 pVM->cpum.s.CR4.OrMask = 0;
144 }
145 else
146 {
147 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
148 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
149 }
150
151 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
152 {
153 Log(("The CPU doesn't support MMX!\n"));
154 return VERR_UNSUPPORTED_CPU;
155 }
156 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
157 {
158 Log(("The CPU doesn't support TSC!\n"));
159 return VERR_UNSUPPORTED_CPU;
160 }
161 /* Bogus on AMD? */
162 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
163 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
164
165 /*
166 * Setup hypervisor startup values.
167 */
168
169 /*
170 * Register saved state data item.
171 */
172 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
173 NULL, cpumR3Save, NULL,
174 NULL, cpumR3Load, NULL);
175 if (VBOX_FAILURE(rc))
176 return rc;
177
178 /* Query the CPU manufacturer. */
179 uint32_t uEAX, uEBX, uECX, uEDX;
180 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
181 if ( uEAX >= 1
182 && uEBX == X86_CPUID_VENDOR_AMD_EBX
183 && uECX == X86_CPUID_VENDOR_AMD_ECX
184 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
185 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
186 else if ( uEAX >= 1
187 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
188 && uECX == X86_CPUID_VENDOR_INTEL_ECX
189 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
190 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
191 else /** @todo Via */
192 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
193
194 /*
195 * Register info handlers.
196 */
197 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
198 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
199 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
200 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
201 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
202
203 /*
204 * Initialize the Guest CPU state.
205 */
206 rc = cpumR3CpuIdInit(pVM);
207 if (VBOX_FAILURE(rc))
208 return rc;
209 CPUMR3Reset(pVM);
210 return VINF_SUCCESS;
211}
212
213
214/**
215 * Initializes the emulated CPU's cpuid information.
216 *
217 * @returns VBox status code.
218 * @param pVM The VM to operate on.
219 */
220static int cpumR3CpuIdInit(PVM pVM)
221{
222 PCPUM pCPUM = &pVM->cpum.s;
223 uint32_t i;
224
225 /*
226 * Get the host CPUIDs.
227 */
228 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
229 ASMCpuId_Idx_ECX(i, 0,
230 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
231 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
232 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
233 ASMCpuId(0x80000000 + i,
234 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
235 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
236 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
237 ASMCpuId(0xc0000000 + i,
238 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
239 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
240
241
242 /*
243 * Only report features we can support.
244 */
245 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
246 | X86_CPUID_FEATURE_EDX_VME
247 | X86_CPUID_FEATURE_EDX_DE
248 | X86_CPUID_FEATURE_EDX_PSE
249 | X86_CPUID_FEATURE_EDX_TSC
250 | X86_CPUID_FEATURE_EDX_MSR
251 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
252 | X86_CPUID_FEATURE_EDX_MCE
253 | X86_CPUID_FEATURE_EDX_CX8
254 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
255 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
256 //| X86_CPUID_FEATURE_EDX_SEP
257 //| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
258 | X86_CPUID_FEATURE_EDX_PGE
259 //| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
260 | X86_CPUID_FEATURE_EDX_CMOV
261 //| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
262 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
263 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
264 | X86_CPUID_FEATURE_EDX_CLFSH
265 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
266 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
267 | X86_CPUID_FEATURE_EDX_MMX
268 | X86_CPUID_FEATURE_EDX_FXSR
269 | X86_CPUID_FEATURE_EDX_SSE
270 | X86_CPUID_FEATURE_EDX_SSE2
271 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
272 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
273 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
274 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
275 | 0;
276 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
277 | X86_CPUID_FEATURE_ECX_MONITOR
278 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
279 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
280 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
281 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
282 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
283 | 0;
284
285 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
286 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
287 | X86_CPUID_AMD_FEATURE_EDX_VME
288 | X86_CPUID_AMD_FEATURE_EDX_DE
289 | X86_CPUID_AMD_FEATURE_EDX_PSE
290 | X86_CPUID_AMD_FEATURE_EDX_TSC
291 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
292 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
293 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
294 | X86_CPUID_AMD_FEATURE_EDX_CX8
295 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
296 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
297 //| X86_CPUID_AMD_FEATURE_EDX_SEP
298 //| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
299 | X86_CPUID_AMD_FEATURE_EDX_PGE
300 //| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
301 | X86_CPUID_AMD_FEATURE_EDX_CMOV
302 | X86_CPUID_AMD_FEATURE_EDX_PAT
303 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
304 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
305 | X86_CPUID_AMD_FEATURE_EDX_MMX
306 | X86_CPUID_AMD_FEATURE_EDX_FXSR
307 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
308 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
309 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
310 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
311 | 0;
312 pCPUM->aGuestCpuIdExt[1].ecx &= 0//X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
313 | 0;
314
315 /*
316 * Hide HTT, multicode, SMP, whatever.
317 * (APIC-ID := 0 and #LogCpus := 0)
318 */
319 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
320
321 /*
322 * Determin the default.
323 *
324 * Intel returns values of the highest standard function, while AMD
325 * returns zeros. VIA on the other hand seems to returning nothing or
326 * perhaps some random garbage, we don't try duplicate this behavior.
327 */
328 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
329 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
330 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
331
332 /*
333 * Limit it the number of entries and fill the remaining with the defaults.
334 *
335 * The limits are masking off stuff about power saving and similar, this
336 * is perhaps a bit crudely done as there is probably some relatively harmless
337 * info too in these leaves (like words about having a constant TSC).
338 */
339 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
340 pCPUM->aGuestCpuIdStd[0].eax = 2;
341 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
342 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
343
344 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000004))
345 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000004);
346 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
347 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
348 : 0;
349 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
350 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
351
352 /*
353 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
354 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
355 * We don't support more than 1 processor.
356 */
357 pCPUM->aGuestCpuIdStd[4].eax = 0;
358
359 /*
360 * Centaur stuff (VIA).
361 *
362 * The important part here (we think) is to make sure the 0xc0000000
363 * function returns 0xc0000001. As for the features, we don't currently
364 * let on about any of those... 0xc0000002 seems to be some
365 * temperature/hz/++ stuff, include it as well (static).
366 */
367 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
368 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
369 {
370 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
371 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
372 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
373 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
374 i++)
375 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
376 }
377 else
378 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
379 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
380
381
382 /*
383 * Load CPUID overrides from configuration.
384 */
385 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
386 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
387 for (i=0;; )
388 {
389 while (cElements-- > 0)
390 {
391 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
392 if (pNode)
393 {
394 uint32_t u32;
395 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
396 if (VBOX_SUCCESS(rc))
397 pCpuId->eax = u32;
398 else
399 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
400
401 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
402 if (VBOX_SUCCESS(rc))
403 pCpuId->ebx = u32;
404 else
405 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
406
407 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
408 if (VBOX_SUCCESS(rc))
409 pCpuId->ecx = u32;
410 else
411 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
412
413 rc = CFGMR3QueryU32(pNode, "edx", &u32);
414 if (VBOX_SUCCESS(rc))
415 pCpuId->edx = u32;
416 else
417 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
418 }
419 pCpuId++;
420 i++;
421 }
422
423 /* next */
424 if ((i & UINT32_C(0xc0000000)) == 0)
425 {
426 pCpuId = &pCPUM->aGuestCpuIdExt[0];
427 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
428 i = UINT32_C(0x80000000);
429 }
430 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
431 {
432 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
433 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
434 i = UINT32_C(0xc0000000);
435 }
436 else
437 break;
438 }
439
440 /* Check if PAE was explicitely enabled by the user. */
441 bool fEnable = false;
442 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
443 if (VBOX_SUCCESS(rc) && fEnable)
444 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
445
446 /*
447 * Log the cpuid and we're good.
448 */
449 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
450 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
451 LogRel(("************************* CPUID dump ************************\n"));
452 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
453 LogRel(("\n"));
454 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
455 LogRel(("******************** End of CPUID dump **********************\n"));
456 return VINF_SUCCESS;
457}
458
459
460
461
462/**
463 * Applies relocations to data and code managed by this
464 * component. This function will be called at init and
465 * whenever the VMM need to relocate it self inside the GC.
466 *
467 * The CPUM will update the addresses used by the switcher.
468 *
469 * @param pVM The VM.
470 */
471CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
472{
473 LogFlow(("CPUMR3Relocate\n"));
474 /*
475 * Switcher pointers.
476 */
477 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
478 pVM->cpum.s.pHyperCoreGC = MMHyperCCToGC(pVM, pVM->cpum.s.pHyperCoreR3);
479 Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
480}
481
482
483/**
484 * Queries the pointer to the internal CPUMCTX structure
485 *
486 * @returns VBox status code.
487 * @param pVM Handle to the virtual machine.
488 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
489 */
490CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
491{
492 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
493 /*
494 * Store the address. (Later we might check how's calling, thus the RC.)
495 */
496 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
497 return VINF_SUCCESS;
498}
499
500
501/**
502 * Terminates the CPUM.
503 *
504 * Termination means cleaning up and freeing all resources,
505 * the VM it self is at this point powered off or suspended.
506 *
507 * @returns VBox status code.
508 * @param pVM The VM to operate on.
509 */
510CPUMR3DECL(int) CPUMR3Term(PVM pVM)
511{
512 /** @todo ? */
513 return 0;
514}
515
516
517/**
518 * Resets the CPU.
519 *
520 * @returns VINF_SUCCESS.
521 * @param pVM The VM handle.
522 */
523CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
524{
525 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
526
527 /*
528 * Initialize everything to ZERO first.
529 */
530 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
531 memset(pCtx, 0, sizeof(*pCtx));
532 pVM->cpum.s.fUseFlags = fUseFlags;
533
534 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
535 pCtx->eip = 0x0000fff0;
536 pCtx->edx = 0x00000600; /* P6 processor */
537 pCtx->eflags.Bits.u1Reserved0 = 1;
538
539 pCtx->cs = 0xf000;
540 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
541 pCtx->csHid.u32Limit = 0x0000ffff;
542 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
543 pCtx->csHid.Attr.n.u1Present = 1;
544 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
545
546 pCtx->dsHid.u32Limit = 0x0000ffff;
547 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
548 pCtx->dsHid.Attr.n.u1Present = 1;
549 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
550
551 pCtx->esHid.u32Limit = 0x0000ffff;
552 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
553 pCtx->esHid.Attr.n.u1Present = 1;
554 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
555
556 pCtx->fsHid.u32Limit = 0x0000ffff;
557 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
558 pCtx->fsHid.Attr.n.u1Present = 1;
559 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
560
561 pCtx->gsHid.u32Limit = 0x0000ffff;
562 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
563 pCtx->gsHid.Attr.n.u1Present = 1;
564 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
565
566 pCtx->ssHid.u32Limit = 0x0000ffff;
567 pCtx->ssHid.Attr.n.u1Present = 1;
568 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
569 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
570
571 pCtx->idtr.cbIdt = 0xffff;
572 pCtx->gdtr.cbGdt = 0xffff;
573
574 pCtx->ldtrHid.u32Limit = 0xffff;
575 pCtx->ldtrHid.Attr.n.u1Present = 1;
576 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
577
578 pCtx->trHid.u32Limit = 0xffff;
579 pCtx->trHid.Attr.n.u1Present = 1;
580 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
581
582 pCtx->dr6 = UINT32_C(0xFFFF0FF0);
583 pCtx->dr7 = 0x400;
584
585 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
586 pCtx->fpu.FCW = 0x37f;
587
588 /* Init PAT MSR */
589 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
590}
591
592
593/**
594 * Execute state save operation.
595 *
596 * @returns VBox status code.
597 * @param pVM VM Handle.
598 * @param pSSM SSM operation handle.
599 */
600static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
601{
602 /*
603 * Save.
604 */
605 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
606 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
607 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
608 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
609
610 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
611 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
612
613 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
614 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
615
616 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
617 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
618
619 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
620
621 /* Add the cpuid for checking that the cpu is unchanged. */
622 uint32_t au32CpuId[8] = {0};
623 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
624 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
625 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
626}
627
628
629/**
630 * Execute state load operation.
631 *
632 * @returns VBox status code.
633 * @param pVM VM Handle.
634 * @param pSSM SSM operation handle.
635 * @param u32Version Data layout version.
636 */
637static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
638{
639 /*
640 * Validate version.
641 */
642 if (u32Version != CPUM_SAVED_STATE_VERSION)
643 {
644 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
645 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
646 }
647
648 /*
649 * Restore.
650 */
651 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
652 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
653 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
654 pVM->cpum.s.Hyper.cr3 = uCR3;
655 pVM->cpum.s.Hyper.esp = uESP;
656 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
657 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
658 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
659
660 uint32_t cElements;
661 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
662 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
663 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
664 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
665
666 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
667 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
668 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
669 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
670
671 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
672 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
673 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
674 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
675
676 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
677
678 /*
679 * Check that the basic cpuid id information is unchanged.
680 */
681 uint32_t au32CpuId[8] = {0};
682 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
683 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
684 uint32_t au32CpuIdSaved[8];
685 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
686 if (VBOX_SUCCESS(rc))
687 {
688 /* Ignore APIC ID (AMD specs). */
689 au32CpuId[5] &= ~0xff000000;
690 au32CpuIdSaved[5] &= ~0xff000000;
691 /* Ignore the number of Logical CPUs (AMD specs). */
692 au32CpuId[5] &= ~0x00ff0000;
693 au32CpuIdSaved[5] &= ~0x00ff0000;
694
695 /* do the compare */
696 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
697 {
698 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
699 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
700 "Saved=%.*Vhxs\n"
701 "Real =%.*Vhxs\n",
702 sizeof(au32CpuIdSaved), au32CpuIdSaved,
703 sizeof(au32CpuId), au32CpuId));
704 else
705 {
706 LogRel(("cpumR3Load: CpuId mismatch!\n"
707 "Saved=%.*Vhxs\n"
708 "Real =%.*Vhxs\n",
709 sizeof(au32CpuIdSaved), au32CpuIdSaved,
710 sizeof(au32CpuId), au32CpuId));
711 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
712 }
713 }
714 }
715
716 return rc;
717}
718
719
720/**
721 * Formats the EFLAGS value into mnemonics.
722 *
723 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
724 * @param efl The EFLAGS value.
725 */
726static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
727{
728 /*
729 * Format the flags.
730 */
731 static struct
732 {
733 const char *pszSet; const char *pszClear; uint32_t fFlag;
734 } s_aFlags[] =
735 {
736 { "vip",NULL, X86_EFL_VIP },
737 { "vif",NULL, X86_EFL_VIF },
738 { "ac", NULL, X86_EFL_AC },
739 { "vm", NULL, X86_EFL_VM },
740 { "rf", NULL, X86_EFL_RF },
741 { "nt", NULL, X86_EFL_NT },
742 { "ov", "nv", X86_EFL_OF },
743 { "dn", "up", X86_EFL_DF },
744 { "ei", "di", X86_EFL_IF },
745 { "tf", NULL, X86_EFL_TF },
746 { "nt", "pl", X86_EFL_SF },
747 { "nz", "zr", X86_EFL_ZF },
748 { "ac", "na", X86_EFL_AF },
749 { "po", "pe", X86_EFL_PF },
750 { "cy", "nc", X86_EFL_CF },
751 };
752 char *psz = pszEFlags;
753 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
754 {
755 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
756 if (pszAdd)
757 {
758 strcpy(psz, pszAdd);
759 psz += strlen(pszAdd);
760 *psz++ = ' ';
761 }
762 }
763 psz[-1] = '\0';
764}
765
766
767/**
768 * Formats a full register dump.
769 *
770 * @param pCtx The context to format.
771 * @param pCtxCore The context core to format.
772 * @param pHlp Output functions.
773 * @param enmType The dump type.
774 * @param pszPrefix Register name prefix.
775 */
776static void cpumR3InfoOne(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
777{
778 /*
779 * Format the EFLAGS.
780 */
781 uint32_t efl = pCtxCore->eflags.u32;
782 char szEFlags[80];
783 cpumR3InfoFormatFlags(&szEFlags[0], efl);
784
785 /*
786 * Format the registers.
787 */
788 switch (enmType)
789 {
790 case CPUMDUMPTYPE_TERSE:
791 pHlp->pfnPrintf(pHlp,
792 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
793 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
794 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
795 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
796 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
797 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
798 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
799 break;
800
801 case CPUMDUMPTYPE_DEFAULT:
802 pHlp->pfnPrintf(pHlp,
803 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
804 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
805 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
806 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
807 ,
808 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
809 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
810 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
811 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
812 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
813 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
814 break;
815
816 case CPUMDUMPTYPE_VERBOSE:
817 pHlp->pfnPrintf(pHlp,
818 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
819 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
820 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
821 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
822 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
823 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
824 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
825 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
826 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
827 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
828 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
829 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
830 ,
831 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
832 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
833 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
834 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
835 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
836 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
837 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
838 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
839 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
840 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
841 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
842 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
843
844 pHlp->pfnPrintf(pHlp,
845 "FPU:\n"
846 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
847 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
848 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
849 ,
850 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
851 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
852 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
853 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
854
855
856 break;
857 }
858}
859
860
861/**
862 * Display all cpu states and any other cpum info.
863 *
864 * @param pVM VM Handle.
865 * @param pHlp The info helper functions.
866 * @param pszArgs Arguments, ignored.
867 */
868static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
869{
870 cpumR3InfoGuest(pVM, pHlp, pszArgs);
871 cpumR3InfoHyper(pVM, pHlp, pszArgs);
872 cpumR3InfoHost(pVM, pHlp, pszArgs);
873}
874
875
876/**
877 * Parses the info argument.
878 *
879 * The argument starts with 'verbose', 'terse' or 'default' and then
880 * continues with the comment string.
881 *
882 * @param pszArgs The pointer to the argument string.
883 * @param penmType Where to store the dump type request.
884 * @param ppszComment Where to store the pointer to the comment string.
885 */
886static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
887{
888 if (!pszArgs)
889 {
890 *penmType = CPUMDUMPTYPE_DEFAULT;
891 *ppszComment = "";
892 }
893 else
894 {
895 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
896 {
897 pszArgs += 5;
898 *penmType = CPUMDUMPTYPE_VERBOSE;
899 }
900 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
901 {
902 pszArgs += 5;
903 *penmType = CPUMDUMPTYPE_TERSE;
904 }
905 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
906 {
907 pszArgs += 7;
908 *penmType = CPUMDUMPTYPE_DEFAULT;
909 }
910 else
911 *penmType = CPUMDUMPTYPE_DEFAULT;
912 *ppszComment = RTStrStripL(pszArgs);
913 }
914}
915
916
917/**
918 * Display the guest cpu state.
919 *
920 * @param pVM VM Handle.
921 * @param pHlp The info helper functions.
922 * @param pszArgs Arguments, ignored.
923 */
924static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
925{
926 CPUMDUMPTYPE enmType;
927 const char *pszComment;
928 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
929 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
930 cpumR3InfoOne(&pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
931}
932
933
934/**
935 * Display the hypervisor cpu state.
936 *
937 * @param pVM VM Handle.
938 * @param pHlp The info helper functions.
939 * @param pszArgs Arguments, ignored.
940 */
941static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
942{
943 CPUMDUMPTYPE enmType;
944 const char *pszComment;
945 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
946 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
947 cpumR3InfoOne(&pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
948 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
949}
950
951
952/**
953 * Display the host cpu state.
954 *
955 * @param pVM VM Handle.
956 * @param pHlp The info helper functions.
957 * @param pszArgs Arguments, ignored.
958 */
959static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
960{
961 CPUMDUMPTYPE enmType;
962 const char *pszComment;
963 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
964 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
965
966 /*
967 * Format the EFLAGS.
968 */
969 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
970#if HC_ARCH_BITS == 32
971 uint32_t efl = pCtx->eflags.u32;
972#else
973 uint64_t efl = pCtx->rflags;
974#endif
975 char szEFlags[80];
976 cpumR3InfoFormatFlags(&szEFlags[0], efl);
977
978 /*
979 * Format the registers.
980 */
981#if HC_ARCH_BITS == 32
982# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
983 if (!(pCtx->efer & MSR_K6_EFER_LMA))
984# endif
985 {
986 pHlp->pfnPrintf(pHlp,
987 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
988 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
989 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
990 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
991 "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
992 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
993 ,
994 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
995 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
996 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
997 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
998 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
999 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1000 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1001 }
1002# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1003 else
1004# endif
1005#endif
1006#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1007 {
1008 pHlp->pfnPrintf(pHlp,
1009 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1010 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1011 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1012 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1013 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1014 "r14=%016RX64 r15=%016RX64\n"
1015 "iopl=%d %31s\n"
1016 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1017 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1018 "cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
1019 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
1020 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1021 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1022 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1023 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1024 ,
1025 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1026 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1027 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1028 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1029 pCtx->r11, pCtx->r12, pCtx->r13,
1030 pCtx->r14, pCtx->r15,
1031 X86_EFL_GET_IOPL(efl), szEFlags,
1032 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1033 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1034 pCtx->cr4, pCtx->cr8, pCtx->ldtr, pCtx->tr,
1035 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1036 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1037 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1038 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1039 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1040 }
1041#endif
1042}
1043
1044
1045/**
1046 * Get L1 cache / TLS associativity.
1047 */
1048static const char *getCacheAss(unsigned u, char *pszBuf)
1049{
1050 if (u == 0)
1051 return "res0 ";
1052 if (u == 1)
1053 return "direct";
1054 if (u >= 256)
1055 return "???";
1056
1057 RTStrPrintf(pszBuf, 16, "%d way", u);
1058 return pszBuf;
1059}
1060
1061
1062/**
1063 * Get L2 cache soociativity.
1064 */
1065const char *getL2CacheAss(unsigned u)
1066{
1067 switch (u)
1068 {
1069 case 0: return "off ";
1070 case 1: return "direct";
1071 case 2: return "2 way ";
1072 case 3: return "res3 ";
1073 case 4: return "4 way ";
1074 case 5: return "res5 ";
1075 case 6: return "8 way "; case 7: return "res7 ";
1076 case 8: return "16 way";
1077 case 9: return "res9 ";
1078 case 10: return "res10 ";
1079 case 11: return "res11 ";
1080 case 12: return "res12 ";
1081 case 13: return "res13 ";
1082 case 14: return "res14 ";
1083 case 15: return "fully ";
1084 default:
1085 return "????";
1086 }
1087}
1088
1089
1090/**
1091 * Display the guest CpuId leaves.
1092 *
1093 * @param pVM VM Handle.
1094 * @param pHlp The info helper functions.
1095 * @param pszArgs "terse", "default" or "verbose".
1096 */
1097static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1098{
1099 /*
1100 * Parse the argument.
1101 */
1102 unsigned iVerbosity = 1;
1103 if (pszArgs)
1104 {
1105 pszArgs = RTStrStripL(pszArgs);
1106 if (!strcmp(pszArgs, "terse"))
1107 iVerbosity--;
1108 else if (!strcmp(pszArgs, "verbose"))
1109 iVerbosity++;
1110 }
1111
1112 /*
1113 * Start cracking.
1114 */
1115 CPUMCPUID Host;
1116 CPUMCPUID Guest;
1117 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1118
1119 pHlp->pfnPrintf(pHlp,
1120 " RAW Standard CPUIDs\n"
1121 " Function eax ebx ecx edx\n");
1122 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1123 {
1124 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1125 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1126
1127 pHlp->pfnPrintf(pHlp,
1128 "Gst: %08x %08x %08x %08x %08x%s\n"
1129 "Hst: %08x %08x %08x %08x\n",
1130 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1131 i <= cStdMax ? "" : "*",
1132 Host.eax, Host.ebx, Host.ecx, Host.edx);
1133 }
1134
1135 /*
1136 * If verbose, decode it.
1137 */
1138 if (iVerbosity)
1139 {
1140 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1141 pHlp->pfnPrintf(pHlp,
1142 "Name: %.04s%.04s%.04s\n"
1143 "Supports: 0-%x\n",
1144 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1145 }
1146
1147 /*
1148 * Get Features.
1149 */
1150 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1151 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1152 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1153 if (cStdMax >= 1 && iVerbosity)
1154 {
1155 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1156 uint32_t uEAX = Guest.eax;
1157
1158 pHlp->pfnPrintf(pHlp,
1159 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1160 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1161 "Stepping: %d\n"
1162 "APIC ID: %#04x\n"
1163 "Logical CPUs: %d\n"
1164 "CLFLUSH Size: %d\n"
1165 "Brand ID: %#04x\n",
1166 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1167 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1168 ASMGetCpuStepping(uEAX),
1169 (Guest.ebx >> 24) & 0xff,
1170 (Guest.ebx >> 16) & 0xff,
1171 (Guest.ebx >> 8) & 0xff,
1172 (Guest.ebx >> 0) & 0xff);
1173 if (iVerbosity == 1)
1174 {
1175 uint32_t uEDX = Guest.edx;
1176 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1177 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1178 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1179 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1180 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1181 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1182 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1183 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1184 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1185 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1186 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1187 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1188 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1189 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1190 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1191 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1192 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1193 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1194 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1195 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1196 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1197 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1198 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1199 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1200 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1201 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1202 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1203 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1204 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1205 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1206 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1207 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1208 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1209 pHlp->pfnPrintf(pHlp, "\n");
1210
1211 uint32_t uECX = Guest.ecx;
1212 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1213 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1214 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1215 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1216 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1217 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1218 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1219 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1220 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1221 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1222 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1223 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1224 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1225 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1226 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1227 for (unsigned iBit = 14; iBit < 32; iBit++)
1228 if (uECX & RT_BIT(iBit))
1229 pHlp->pfnPrintf(pHlp, " %d", iBit);
1230 pHlp->pfnPrintf(pHlp, "\n");
1231 }
1232 else
1233 {
1234 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1235
1236 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1237 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1238 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1239 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1240
1241 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1242 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1243 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1244 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1245 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1246 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1247 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1248 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1249 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1250 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1251 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1252 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1253 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1254 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1255 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1256 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1257 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1258 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1259 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1260 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1261 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1262 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1263 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1264 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1265 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1266 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1267 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1268 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1269 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1270 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1271 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1272 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1273 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1274
1275 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1276 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1277 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1278 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1279 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1280 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1281 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1282 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1283 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1284 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1285 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1286 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1287 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1288 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1289 }
1290 }
1291 if (cStdMax >= 2 && iVerbosity)
1292 {
1293 /** @todo */
1294 }
1295
1296 /*
1297 * Extended.
1298 * Implemented after AMD specs.
1299 */
1300 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1301
1302 pHlp->pfnPrintf(pHlp,
1303 "\n"
1304 " RAW Extended CPUIDs\n"
1305 " Function eax ebx ecx edx\n");
1306 for (unsigned i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1307 {
1308 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1309 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1310
1311 pHlp->pfnPrintf(pHlp,
1312 "Gst: %08x %08x %08x %08x %08x%s\n"
1313 "Hst: %08x %08x %08x %08x\n",
1314 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1315 i <= cExtMax ? "" : "*",
1316 Host.eax, Host.ebx, Host.ecx, Host.edx);
1317 }
1318
1319 /*
1320 * Understandable output
1321 */
1322 if (iVerbosity && cExtMax >= 0)
1323 {
1324 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1325 pHlp->pfnPrintf(pHlp,
1326 "Ext Name: %.4s%.4s%.4s\n"
1327 "Ext Supports: 0x80000000-%#010x\n",
1328 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1329 }
1330
1331 if (iVerbosity && cExtMax >= 1)
1332 {
1333 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1334 uint32_t uEAX = Guest.eax;
1335 pHlp->pfnPrintf(pHlp,
1336 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1337 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1338 "Stepping: %d\n"
1339 "Brand ID: %#05x\n",
1340 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1341 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1342 ASMGetCpuStepping(uEAX),
1343 Guest.ebx & 0xfff);
1344
1345 if (iVerbosity == 1)
1346 {
1347 uint32_t uEDX = Guest.edx;
1348 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1349 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1350 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1351 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1352 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1353 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1354 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1355 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1356 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1357 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1358 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1359 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1360 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1361 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1362 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1363 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1364 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1365 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1366 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1367 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1368 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1369 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1370 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1371 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1372 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1373 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1374 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1375 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1376 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1377 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1378 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1379 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1380 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1381 pHlp->pfnPrintf(pHlp, "\n");
1382
1383 uint32_t uECX = Guest.ecx;
1384 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1385 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1386 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1387 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1388 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1389 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1390 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1391 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1392 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1393 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1394 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1395 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1396 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1397 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1398 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1399 for (unsigned iBit = 5; iBit < 32; iBit++)
1400 if (uECX & RT_BIT(iBit))
1401 pHlp->pfnPrintf(pHlp, " %d", iBit);
1402 pHlp->pfnPrintf(pHlp, "\n");
1403 }
1404 else
1405 {
1406 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1407
1408 uint32_t uEdxGst = Guest.edx;
1409 uint32_t uEdxHst = Host.edx;
1410 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1411 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1412 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1413 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1414 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1415 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1416 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1417 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1418 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1419 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1420 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1421 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1422 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1423 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1424 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1425 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1426 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1427 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1428 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1429 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1430 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1431 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1432 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1433 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1434 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1435 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1436 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1437 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1438 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1439 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1440 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1441 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1442 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1443
1444 uint32_t uEcxGst = Guest.ecx;
1445 uint32_t uEcxHst = Host.ecx;
1446 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1447 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1448 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1449 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1450 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1451 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1452 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1453 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1454 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1455 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1456 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1457 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1458 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1459 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1460 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1461 }
1462 }
1463
1464 if (iVerbosity && cExtMax >= 2)
1465 {
1466 char szString[4*4*3+1] = {0};
1467 uint32_t *pu32 = (uint32_t *)szString;
1468 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1469 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1470 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1471 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1472 if (cExtMax >= 3)
1473 {
1474 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1475 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1476 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1477 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1478 }
1479 if (cExtMax >= 4)
1480 {
1481 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1482 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1483 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1484 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1485 }
1486 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1487 }
1488
1489 if (iVerbosity && cExtMax >= 5)
1490 {
1491 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1492 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1493 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1494 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1495 char sz1[32];
1496 char sz2[32];
1497
1498 pHlp->pfnPrintf(pHlp,
1499 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1500 "TLB 2/4M Data: %s %3d entries\n",
1501 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1502 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1503 pHlp->pfnPrintf(pHlp,
1504 "TLB 4K Instr/Uni: %s %3d entries\n"
1505 "TLB 4K Data: %s %3d entries\n",
1506 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1507 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1508 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1509 "L1 Instr Cache Lines Per Tag: %d\n"
1510 "L1 Instr Cache Associativity: %s\n"
1511 "L1 Instr Cache Size: %d KB\n",
1512 (uEDX >> 0) & 0xff,
1513 (uEDX >> 8) & 0xff,
1514 getCacheAss((uEDX >> 16) & 0xff, sz1),
1515 (uEDX >> 24) & 0xff);
1516 pHlp->pfnPrintf(pHlp,
1517 "L1 Data Cache Line Size: %d bytes\n"
1518 "L1 Data Cache Lines Per Tag: %d\n"
1519 "L1 Data Cache Associativity: %s\n"
1520 "L1 Data Cache Size: %d KB\n",
1521 (uECX >> 0) & 0xff,
1522 (uECX >> 8) & 0xff,
1523 getCacheAss((uECX >> 16) & 0xff, sz1),
1524 (uECX >> 24) & 0xff);
1525 }
1526
1527 if (iVerbosity && cExtMax >= 6)
1528 {
1529 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1530 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1531 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1532
1533 pHlp->pfnPrintf(pHlp,
1534 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1535 "L2 TLB 2/4M Data: %s %4d entries\n",
1536 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1537 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1538 pHlp->pfnPrintf(pHlp,
1539 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1540 "L2 TLB 4K Data: %s %4d entries\n",
1541 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1542 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1543 pHlp->pfnPrintf(pHlp,
1544 "L2 Cache Line Size: %d bytes\n"
1545 "L2 Cache Lines Per Tag: %d\n"
1546 "L2 Cache Associativity: %s\n"
1547 "L2 Cache Size: %d KB\n",
1548 (uEDX >> 0) & 0xff,
1549 (uEDX >> 8) & 0xf,
1550 getL2CacheAss((uEDX >> 12) & 0xf),
1551 (uEDX >> 16) & 0xffff);
1552 }
1553
1554 if (iVerbosity && cExtMax >= 7)
1555 {
1556 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1557
1558 pHlp->pfnPrintf(pHlp, "APM Features: ");
1559 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1560 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1561 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1562 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1563 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1564 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1565 for (unsigned iBit = 6; iBit < 32; iBit++)
1566 if (uEDX & RT_BIT(iBit))
1567 pHlp->pfnPrintf(pHlp, " %d", iBit);
1568 pHlp->pfnPrintf(pHlp, "\n");
1569 }
1570
1571 if (iVerbosity && cExtMax >= 8)
1572 {
1573 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1574 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1575
1576 pHlp->pfnPrintf(pHlp,
1577 "Physical Address Width: %d bits\n"
1578 "Virtual Address Width: %d bits\n",
1579 (uEAX >> 0) & 0xff,
1580 (uEAX >> 8) & 0xff);
1581 pHlp->pfnPrintf(pHlp,
1582 "Physical Core Count: %d\n",
1583 (uECX >> 0) & 0xff);
1584 }
1585
1586
1587 /*
1588 * Centaur.
1589 */
1590 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1591
1592 pHlp->pfnPrintf(pHlp,
1593 "\n"
1594 " RAW Centaur CPUIDs\n"
1595 " Function eax ebx ecx edx\n");
1596 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1597 {
1598 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1599 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1600
1601 pHlp->pfnPrintf(pHlp,
1602 "Gst: %08x %08x %08x %08x %08x%s\n"
1603 "Hst: %08x %08x %08x %08x\n",
1604 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1605 i <= cCentaurMax ? "" : "*",
1606 Host.eax, Host.ebx, Host.ecx, Host.edx);
1607 }
1608
1609 /*
1610 * Understandable output
1611 */
1612 if (iVerbosity && cCentaurMax >= 0)
1613 {
1614 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1615 pHlp->pfnPrintf(pHlp,
1616 "Centaur Supports: 0xc0000000-%#010x\n",
1617 Guest.eax);
1618 }
1619
1620 if (iVerbosity && cCentaurMax >= 1)
1621 {
1622 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1623 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1624 uint32_t uEdxHst = Host.edx;
1625
1626 if (iVerbosity == 1)
1627 {
1628 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1629 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1630 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1631 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1632 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1633 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1634 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1635 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1636 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1637 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1638 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
1639 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
1640 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
1641 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
1642 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
1643 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
1644 for (unsigned iBit = 14; iBit < 32; iBit++)
1645 if (uEdxGst & RT_BIT(iBit))
1646 pHlp->pfnPrintf(pHlp, " %d", iBit);
1647 pHlp->pfnPrintf(pHlp, "\n");
1648 }
1649 else
1650 {
1651 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1652 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1653 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1654 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1655 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1656 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1657 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1658 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1659 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1660 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1661 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1662 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1663 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1664 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1665 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1666 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1667 for (unsigned iBit = 14; iBit < 32; iBit++)
1668 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
1669 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
1670 pHlp->pfnPrintf(pHlp, "\n");
1671 }
1672 }
1673}
1674
1675
1676/**
1677 * Structure used when disassembling and instructions in DBGF.
1678 * This is used so the reader function can get the stuff it needs.
1679 */
1680typedef struct CPUMDISASSTATE
1681{
1682 /** Pointer to the CPU structure. */
1683 PDISCPUSTATE pCpu;
1684 /** The VM handle. */
1685 PVM pVM;
1686 /** Pointer to the first byte in the segemnt. */
1687 RTGCUINTPTR GCPtrSegBase;
1688 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1689 RTGCUINTPTR GCPtrSegEnd;
1690 /** The size of the segment minus 1. */
1691 RTGCUINTPTR cbSegLimit;
1692 /** Pointer to the current page - HC Ptr. */
1693 void const *pvPageHC;
1694 /** Pointer to the current page - GC Ptr. */
1695 RTGCPTR pvPageGC;
1696 /** The lock information that PGMPhysReleasePageMappingLock needs. */
1697 PGMPAGEMAPLOCK PageMapLock;
1698 /** Whether the PageMapLock is valid or not. */
1699 bool fLocked;
1700} CPUMDISASSTATE, *PCPUMDISASSTATE;
1701
1702
1703/**
1704 * Instruction reader.
1705 *
1706 * @returns VBox status code.
1707 * @param PtrSrc Address to read from.
1708 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1709 * @param pu8Dst Where to store the bytes.
1710 * @param cbRead Number of bytes to read.
1711 * @param uDisCpu Pointer to the disassembler cpu state.
1712 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1713 */
1714static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
1715{
1716 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1717 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
1718 Assert(cbRead > 0);
1719 for (;;)
1720 {
1721 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1722
1723 /* Need to update the page translation? */
1724 if ( !pState->pvPageHC
1725 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1726 {
1727 int rc = VINF_SUCCESS;
1728
1729 /* translate the address */
1730 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1731 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1732 {
1733 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1734 if (!pState->pvPageHC)
1735 rc = VERR_INVALID_POINTER;
1736 }
1737 else
1738 {
1739 /* Release mapping lock previously acquired. */
1740 if (pState->fLocked)
1741 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
1742 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
1743 pState->fLocked = RT_SUCCESS_NP(rc);
1744 }
1745 if (VBOX_FAILURE(rc))
1746 {
1747 pState->pvPageHC = NULL;
1748 return rc;
1749 }
1750 }
1751
1752 /* check the segemnt limit */
1753 if (PtrSrc > pState->cbSegLimit)
1754 return VERR_OUT_OF_SELECTOR_BOUNDS;
1755
1756 /* calc how much we can read */
1757 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1758 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1759 if (cb > cbSeg && !cbSeg)
1760 cb = cbSeg;
1761 if (cb > cbRead)
1762 cb = cbRead;
1763
1764 /* read and advance */
1765 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1766 cbRead -= cb;
1767 if (!cbRead)
1768 return VINF_SUCCESS;
1769 pu8Dst += cb;
1770 PtrSrc += cb;
1771 }
1772}
1773
1774
1775/**
1776 * Disassemble an instruction and return the information in the provided structure.
1777 *
1778 * @returns VBox status code.
1779 * @param pVM VM Handle
1780 * @param pCtx CPU context
1781 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1782 * @param pCpu Disassembly state
1783 * @param pszPrefix String prefix for logging (debug only)
1784 *
1785 */
1786CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1787{
1788 CPUMDISASSTATE State;
1789 int rc;
1790
1791 State.pCpu = pCpu;
1792 State.pvPageGC = 0;
1793 State.pvPageHC = NULL;
1794 State.pVM = pVM;
1795 State.fLocked = false;
1796
1797 /*
1798 * Get selector information.
1799 */
1800 if ( (pCtx->cr0 & X86_CR0_PE)
1801 && pCtx->eflags.Bits.u1VM == 0)
1802 {
1803 if (CPUMAreHiddenSelRegsValid(pVM))
1804 {
1805 State.GCPtrSegBase = pCtx->csHid.u64Base;
1806 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
1807 State.cbSegLimit = pCtx->csHid.u32Limit;
1808 pCpu->mode = pCtx->csHid.Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1809 }
1810 else
1811 {
1812 SELMSELINFO SelInfo;
1813
1814 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1815 if (!VBOX_SUCCESS(rc))
1816 {
1817 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1818 return rc;
1819 }
1820
1821 /*
1822 * Validate the selector.
1823 */
1824 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1825 if (!VBOX_SUCCESS(rc))
1826 {
1827 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1828 return rc;
1829 }
1830 State.GCPtrSegBase = SelInfo.GCPtrBase;
1831 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1832 State.cbSegLimit = SelInfo.cbLimit;
1833 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1834 }
1835 }
1836 else
1837 {
1838 /* real or V86 mode */
1839 pCpu->mode = CPUMODE_16BIT;
1840 State.GCPtrSegBase = pCtx->cs * 16;
1841 State.GCPtrSegEnd = 0xFFFFFFFF;
1842 State.cbSegLimit = 0xFFFFFFFF;
1843 }
1844
1845 /*
1846 * Disassemble the instruction.
1847 */
1848 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
1849 pCpu->apvUserData[0] = &State;
1850
1851 uint32_t cbInstr;
1852#ifndef LOG_ENABLED
1853 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
1854 if (VBOX_SUCCESS(rc))
1855 {
1856#else
1857 char szOutput[160];
1858 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
1859 if (VBOX_SUCCESS(rc))
1860 {
1861 /* log it */
1862 if (pszPrefix)
1863 Log(("%s: %s", pszPrefix, szOutput));
1864 else
1865 Log(("%s", szOutput));
1866#endif
1867 rc = VINF_SUCCESS;
1868 }
1869 else
1870 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
1871
1872 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
1873 if (State.fLocked)
1874 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
1875
1876 return rc;
1877}
1878
1879#ifdef DEBUG
1880
1881/**
1882 * Disassemble an instruction and dump it to the log
1883 *
1884 * @returns VBox status code.
1885 * @param pVM VM Handle
1886 * @param pCtx CPU context
1887 * @param pc GC instruction pointer
1888 * @param prefix String prefix for logging
1889 * @deprecated Use DBGFR3DisasInstrCurrentLog().
1890 *
1891 */
1892CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
1893{
1894 DISCPUSTATE cpu;
1895
1896 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1897}
1898
1899/**
1900 * Disassemble an instruction and dump it to the log
1901 *
1902 * @returns VBox status code.
1903 * @param pVM VM Handle
1904 * @param pCtx CPU context
1905 * @param pc GC instruction pointer
1906 * @param prefix String prefix for logging
1907 * @param nrInstructions
1908 *
1909 */
1910CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
1911{
1912 for(int i=0;i<nrInstructions;i++)
1913 {
1914 DISCPUSTATE cpu;
1915
1916 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1917 pc += cpu.opsize;
1918 }
1919}
1920
1921#endif /* DEBUG */
1922
1923#ifdef DEBUG
1924/**
1925 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
1926 *
1927 * @internal
1928 */
1929CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
1930{
1931 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
1932}
1933#endif /* DEBUG */
1934
1935
1936/**
1937 * API for controlling a few of the CPU features found in CR4.
1938 *
1939 * Currently only X86_CR4_TSD is accepted as input.
1940 *
1941 * @returns VBox status code.
1942 *
1943 * @param pVM The VM handle.
1944 * @param fOr The CR4 OR mask.
1945 * @param fAnd The CR4 AND mask.
1946 */
1947CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
1948{
1949 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
1950 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
1951
1952 pVM->cpum.s.CR4.OrMask &= fAnd;
1953 pVM->cpum.s.CR4.OrMask |= fOr;
1954
1955 return VINF_SUCCESS;
1956}
1957
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