VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 9543

Last change on this file since 9543 was 9543, checked in by vboxsync, 16 years ago

Long mode CPU state dumping.
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File size: 94.7 KB
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1/* $Id: CPUM.cpp 9543 2008-06-09 12:53:11Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum
23 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
24 * also responsible for lazy FPU handling and some of the context loading
25 * in raw mode.
26 *
27 * There are three CPU contexts, the most important one is the guest one (GC).
28 * When running in raw-mode (RC) there is a special hyper context for the VMM
29 * that floats around inside the guest address space. When running in raw-mode
30 * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host
31 * context for saving and restoring registers accross world switches. This latter
32 * is done in cooperation with the world switcher (@see pg_vmm).
33 */
34
35/*******************************************************************************
36* Header Files *
37*******************************************************************************/
38#define LOG_GROUP LOG_GROUP_CPUM
39#include <VBox/cpum.h>
40#include <VBox/cpumdis.h>
41#include <VBox/pgm.h>
42#include <VBox/mm.h>
43#include <VBox/selm.h>
44#include <VBox/dbgf.h>
45#include <VBox/patm.h>
46#include <VBox/ssm.h>
47#include "CPUMInternal.h"
48#include <VBox/vm.h>
49
50#include <VBox/param.h>
51#include <VBox/dis.h>
52#include <VBox/err.h>
53#include <VBox/log.h>
54#include <iprt/assert.h>
55#include <iprt/asm.h>
56#include <iprt/string.h>
57#include <iprt/system.h>
58
59
60/*******************************************************************************
61* Defined Constants And Macros *
62*******************************************************************************/
63/** The saved state version. */
64#define CPUM_SAVED_STATE_VERSION 7
65
66
67/*******************************************************************************
68* Structures and Typedefs *
69*******************************************************************************/
70
71/**
72 * What kind of cpu info dump to perform.
73 */
74typedef enum CPUMDUMPTYPE
75{
76 CPUMDUMPTYPE_TERSE,
77 CPUMDUMPTYPE_DEFAULT,
78 CPUMDUMPTYPE_VERBOSE
79
80} CPUMDUMPTYPE;
81/** Pointer to a cpu info dump type. */
82typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
83
84
85/*******************************************************************************
86* Internal Functions *
87*******************************************************************************/
88static int cpumR3CpuIdInit(PVM pVM);
89static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
90static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
91static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
92static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
93static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
94static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
95static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
96
97
98/**
99 * Initializes the CPUM.
100 *
101 * @returns VBox status code.
102 * @param pVM The VM to operate on.
103 */
104CPUMR3DECL(int) CPUMR3Init(PVM pVM)
105{
106 LogFlow(("CPUMR3Init\n"));
107
108 /*
109 * Assert alignment and sizes.
110 */
111 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
112 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
113
114 /*
115 * Setup any fixed pointers and offsets.
116 */
117 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
118 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
119 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
120 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
121
122 /* Hidden selector registers are invalid by default. */
123 pVM->cpum.s.fValidHiddenSelRegs = false;
124
125 /*
126 * Check that the CPU supports the minimum features we require.
127 */
128 /** @todo check the contract! */
129 if (!ASMHasCpuId())
130 {
131 Log(("The CPU doesn't support CPUID!\n"));
132 return VERR_UNSUPPORTED_CPU;
133 }
134 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
135
136 /* Setup the CR4 AND and OR masks used in the switcher */
137 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
138 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
139 {
140 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
141 /* No FXSAVE implies no SSE */
142 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
143 pVM->cpum.s.CR4.OrMask = 0;
144 }
145 else
146 {
147 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
148 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
149 }
150
151 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
152 {
153 Log(("The CPU doesn't support MMX!\n"));
154 return VERR_UNSUPPORTED_CPU;
155 }
156 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
157 {
158 Log(("The CPU doesn't support TSC!\n"));
159 return VERR_UNSUPPORTED_CPU;
160 }
161 /* Bogus on AMD? */
162 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
163 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
164
165 /*
166 * Setup hypervisor startup values.
167 */
168
169 /*
170 * Register saved state data item.
171 */
172 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
173 NULL, cpumR3Save, NULL,
174 NULL, cpumR3Load, NULL);
175 if (VBOX_FAILURE(rc))
176 return rc;
177
178 /* Query the CPU manufacturer. */
179 uint32_t uEAX, uEBX, uECX, uEDX;
180 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
181 if ( uEAX >= 1
182 && uEBX == X86_CPUID_VENDOR_AMD_EBX
183 && uECX == X86_CPUID_VENDOR_AMD_ECX
184 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
185 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
186 else if ( uEAX >= 1
187 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
188 && uECX == X86_CPUID_VENDOR_INTEL_ECX
189 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
190 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
191 else /** @todo Via */
192 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
193
194 /*
195 * Register info handlers.
196 */
197 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
198 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
199 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
200 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
201 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
202
203 /*
204 * Initialize the Guest CPU state.
205 */
206 rc = cpumR3CpuIdInit(pVM);
207 if (VBOX_FAILURE(rc))
208 return rc;
209 CPUMR3Reset(pVM);
210 return VINF_SUCCESS;
211}
212
213
214/**
215 * Initializes the emulated CPU's cpuid information.
216 *
217 * @returns VBox status code.
218 * @param pVM The VM to operate on.
219 */
220static int cpumR3CpuIdInit(PVM pVM)
221{
222 PCPUM pCPUM = &pVM->cpum.s;
223 uint32_t i;
224
225 /*
226 * Get the host CPUIDs.
227 */
228 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
229 ASMCpuId_Idx_ECX(i, 0,
230 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
231 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
232 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
233 ASMCpuId(0x80000000 + i,
234 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
235 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
236 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
237 ASMCpuId(0xc0000000 + i,
238 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
239 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
240
241
242 /*
243 * Only report features we can support.
244 */
245 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
246 | X86_CPUID_FEATURE_EDX_VME
247 | X86_CPUID_FEATURE_EDX_DE
248 | X86_CPUID_FEATURE_EDX_PSE
249 | X86_CPUID_FEATURE_EDX_TSC
250 | X86_CPUID_FEATURE_EDX_MSR
251 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
252 | X86_CPUID_FEATURE_EDX_MCE
253 | X86_CPUID_FEATURE_EDX_CX8
254 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
255 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
256 //| X86_CPUID_FEATURE_EDX_SEP
257 //| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
258 | X86_CPUID_FEATURE_EDX_PGE
259 //| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
260 | X86_CPUID_FEATURE_EDX_CMOV
261 //| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
262 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
263 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
264 | X86_CPUID_FEATURE_EDX_CLFSH
265 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
266 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
267 | X86_CPUID_FEATURE_EDX_MMX
268 | X86_CPUID_FEATURE_EDX_FXSR
269 | X86_CPUID_FEATURE_EDX_SSE
270 | X86_CPUID_FEATURE_EDX_SSE2
271 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
272 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
273 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
274 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
275 | 0;
276 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
277 | X86_CPUID_FEATURE_ECX_MONITOR
278 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
279 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
280 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
281 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
282 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
283 | 0;
284
285 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
286 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
287 | X86_CPUID_AMD_FEATURE_EDX_VME
288 | X86_CPUID_AMD_FEATURE_EDX_DE
289 | X86_CPUID_AMD_FEATURE_EDX_PSE
290 | X86_CPUID_AMD_FEATURE_EDX_TSC
291 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
292 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
293 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
294 | X86_CPUID_AMD_FEATURE_EDX_CX8
295 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
296 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
297 //| X86_CPUID_AMD_FEATURE_EDX_SEP
298 //| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
299 | X86_CPUID_AMD_FEATURE_EDX_PGE
300 //| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
301 | X86_CPUID_AMD_FEATURE_EDX_CMOV
302 | X86_CPUID_AMD_FEATURE_EDX_PAT
303 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
304 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
305 | X86_CPUID_AMD_FEATURE_EDX_MMX
306 | X86_CPUID_AMD_FEATURE_EDX_FXSR
307 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
308 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
309 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
310 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
311 | 0;
312 pCPUM->aGuestCpuIdExt[1].ecx &= 0//X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
313 | 0;
314
315 /*
316 * Hide HTT, multicode, SMP, whatever.
317 * (APIC-ID := 0 and #LogCpus := 0)
318 */
319 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
320
321 /*
322 * Determin the default.
323 *
324 * Intel returns values of the highest standard function, while AMD
325 * returns zeros. VIA on the other hand seems to returning nothing or
326 * perhaps some random garbage, we don't try duplicate this behavior.
327 */
328 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
329 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
330 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
331
332 /*
333 * Limit it the number of entries and fill the remaining with the defaults.
334 *
335 * The limits are masking off stuff about power saving and similar, this
336 * is perhaps a bit crudely done as there is probably some relatively harmless
337 * info too in these leaves (like words about having a constant TSC).
338 */
339 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
340 pCPUM->aGuestCpuIdStd[0].eax = 2;
341 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
342 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
343
344 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000004))
345 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000004);
346 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
347 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
348 : 0;
349 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
350 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
351
352 /*
353 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
354 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
355 * We don't support more than 1 processor.
356 */
357 pCPUM->aGuestCpuIdStd[4].eax = 0;
358
359 /*
360 * Centaur stuff (VIA).
361 *
362 * The important part here (we think) is to make sure the 0xc0000000
363 * function returns 0xc0000001. As for the features, we don't currently
364 * let on about any of those... 0xc0000002 seems to be some
365 * temperature/hz/++ stuff, include it as well (static).
366 */
367 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
368 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
369 {
370 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
371 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
372 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
373 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
374 i++)
375 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
376 }
377 else
378 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
379 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
380
381
382 /*
383 * Load CPUID overrides from configuration.
384 */
385 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
386 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
387 for (i=0;; )
388 {
389 while (cElements-- > 0)
390 {
391 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
392 if (pNode)
393 {
394 uint32_t u32;
395 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
396 if (VBOX_SUCCESS(rc))
397 pCpuId->eax = u32;
398 else
399 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
400
401 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
402 if (VBOX_SUCCESS(rc))
403 pCpuId->ebx = u32;
404 else
405 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
406
407 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
408 if (VBOX_SUCCESS(rc))
409 pCpuId->ecx = u32;
410 else
411 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
412
413 rc = CFGMR3QueryU32(pNode, "edx", &u32);
414 if (VBOX_SUCCESS(rc))
415 pCpuId->edx = u32;
416 else
417 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
418 }
419 pCpuId++;
420 i++;
421 }
422
423 /* next */
424 if ((i & UINT32_C(0xc0000000)) == 0)
425 {
426 pCpuId = &pCPUM->aGuestCpuIdExt[0];
427 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
428 i = UINT32_C(0x80000000);
429 }
430 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
431 {
432 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
433 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
434 i = UINT32_C(0xc0000000);
435 }
436 else
437 break;
438 }
439
440 /* Check if PAE was explicitely enabled by the user. */
441 bool fEnable = false;
442 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
443 if (VBOX_SUCCESS(rc) && fEnable)
444 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
445
446 /*
447 * Log the cpuid and we're good.
448 */
449 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
450 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
451 LogRel(("************************* CPUID dump ************************\n"));
452 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
453 LogRel(("\n"));
454 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
455 LogRel(("******************** End of CPUID dump **********************\n"));
456 return VINF_SUCCESS;
457}
458
459
460
461
462/**
463 * Applies relocations to data and code managed by this
464 * component. This function will be called at init and
465 * whenever the VMM need to relocate it self inside the GC.
466 *
467 * The CPUM will update the addresses used by the switcher.
468 *
469 * @param pVM The VM.
470 */
471CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
472{
473 LogFlow(("CPUMR3Relocate\n"));
474 /*
475 * Switcher pointers.
476 */
477 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
478 pVM->cpum.s.pHyperCoreGC = MMHyperCCToGC(pVM, pVM->cpum.s.pHyperCoreR3);
479 Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
480}
481
482
483/**
484 * Queries the pointer to the internal CPUMCTX structure
485 *
486 * @returns VBox status code.
487 * @param pVM Handle to the virtual machine.
488 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
489 */
490CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
491{
492 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
493 /*
494 * Store the address. (Later we might check how's calling, thus the RC.)
495 */
496 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
497 return VINF_SUCCESS;
498}
499
500
501/**
502 * Terminates the CPUM.
503 *
504 * Termination means cleaning up and freeing all resources,
505 * the VM it self is at this point powered off or suspended.
506 *
507 * @returns VBox status code.
508 * @param pVM The VM to operate on.
509 */
510CPUMR3DECL(int) CPUMR3Term(PVM pVM)
511{
512 /** @todo ? */
513 return 0;
514}
515
516
517/**
518 * Resets the CPU.
519 *
520 * @returns VINF_SUCCESS.
521 * @param pVM The VM handle.
522 */
523CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
524{
525 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
526
527 /*
528 * Initialize everything to ZERO first.
529 */
530 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
531 memset(pCtx, 0, sizeof(*pCtx));
532 pVM->cpum.s.fUseFlags = fUseFlags;
533
534 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
535 pCtx->eip = 0x0000fff0;
536 pCtx->edx = 0x00000600; /* P6 processor */
537 pCtx->eflags.Bits.u1Reserved0 = 1;
538
539 pCtx->cs = 0xf000;
540 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
541 pCtx->csHid.u32Limit = 0x0000ffff;
542 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
543 pCtx->csHid.Attr.n.u1Present = 1;
544 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
545
546 pCtx->dsHid.u32Limit = 0x0000ffff;
547 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
548 pCtx->dsHid.Attr.n.u1Present = 1;
549 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
550
551 pCtx->esHid.u32Limit = 0x0000ffff;
552 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
553 pCtx->esHid.Attr.n.u1Present = 1;
554 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
555
556 pCtx->fsHid.u32Limit = 0x0000ffff;
557 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
558 pCtx->fsHid.Attr.n.u1Present = 1;
559 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
560
561 pCtx->gsHid.u32Limit = 0x0000ffff;
562 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
563 pCtx->gsHid.Attr.n.u1Present = 1;
564 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
565
566 pCtx->ssHid.u32Limit = 0x0000ffff;
567 pCtx->ssHid.Attr.n.u1Present = 1;
568 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
569 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
570
571 pCtx->idtr.cbIdt = 0xffff;
572 pCtx->gdtr.cbGdt = 0xffff;
573
574 pCtx->ldtrHid.u32Limit = 0xffff;
575 pCtx->ldtrHid.Attr.n.u1Present = 1;
576 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
577
578 pCtx->trHid.u32Limit = 0xffff;
579 pCtx->trHid.Attr.n.u1Present = 1;
580 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
581
582 pCtx->dr6 = UINT32_C(0xFFFF0FF0);
583 pCtx->dr7 = 0x400;
584
585 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
586 pCtx->fpu.FCW = 0x37f;
587
588 /* Init PAT MSR */
589 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
590}
591
592
593/**
594 * Execute state save operation.
595 *
596 * @returns VBox status code.
597 * @param pVM VM Handle.
598 * @param pSSM SSM operation handle.
599 */
600static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
601{
602 /*
603 * Save.
604 */
605 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
606 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
607 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
608 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
609
610 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
611 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
612
613 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
614 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
615
616 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
617 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
618
619 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
620
621 /* Add the cpuid for checking that the cpu is unchanged. */
622 uint32_t au32CpuId[8] = {0};
623 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
624 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
625 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
626}
627
628
629/**
630 * Execute state load operation.
631 *
632 * @returns VBox status code.
633 * @param pVM VM Handle.
634 * @param pSSM SSM operation handle.
635 * @param u32Version Data layout version.
636 */
637static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
638{
639 /*
640 * Validate version.
641 */
642 if (u32Version != CPUM_SAVED_STATE_VERSION)
643 {
644 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
645 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
646 }
647
648 /*
649 * Restore.
650 */
651 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
652 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
653 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
654 pVM->cpum.s.Hyper.cr3 = uCR3;
655 pVM->cpum.s.Hyper.esp = uESP;
656 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
657 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
658 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
659
660 uint32_t cElements;
661 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
662 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
663 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
664 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
665
666 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
667 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
668 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
669 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
670
671 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
672 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
673 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
674 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
675
676 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
677
678 /*
679 * Check that the basic cpuid id information is unchanged.
680 */
681 uint32_t au32CpuId[8] = {0};
682 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
683 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
684 uint32_t au32CpuIdSaved[8];
685 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
686 if (VBOX_SUCCESS(rc))
687 {
688 /* Ignore APIC ID (AMD specs). */
689 au32CpuId[5] &= ~0xff000000;
690 au32CpuIdSaved[5] &= ~0xff000000;
691 /* Ignore the number of Logical CPUs (AMD specs). */
692 au32CpuId[5] &= ~0x00ff0000;
693 au32CpuIdSaved[5] &= ~0x00ff0000;
694
695 /* do the compare */
696 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
697 {
698 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
699 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
700 "Saved=%.*Vhxs\n"
701 "Real =%.*Vhxs\n",
702 sizeof(au32CpuIdSaved), au32CpuIdSaved,
703 sizeof(au32CpuId), au32CpuId));
704 else
705 {
706 LogRel(("cpumR3Load: CpuId mismatch!\n"
707 "Saved=%.*Vhxs\n"
708 "Real =%.*Vhxs\n",
709 sizeof(au32CpuIdSaved), au32CpuIdSaved,
710 sizeof(au32CpuId), au32CpuId));
711 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
712 }
713 }
714 }
715
716 return rc;
717}
718
719
720/**
721 * Formats the EFLAGS value into mnemonics.
722 *
723 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
724 * @param efl The EFLAGS value.
725 */
726static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
727{
728 /*
729 * Format the flags.
730 */
731 static struct
732 {
733 const char *pszSet; const char *pszClear; uint32_t fFlag;
734 } s_aFlags[] =
735 {
736 { "vip",NULL, X86_EFL_VIP },
737 { "vif",NULL, X86_EFL_VIF },
738 { "ac", NULL, X86_EFL_AC },
739 { "vm", NULL, X86_EFL_VM },
740 { "rf", NULL, X86_EFL_RF },
741 { "nt", NULL, X86_EFL_NT },
742 { "ov", "nv", X86_EFL_OF },
743 { "dn", "up", X86_EFL_DF },
744 { "ei", "di", X86_EFL_IF },
745 { "tf", NULL, X86_EFL_TF },
746 { "nt", "pl", X86_EFL_SF },
747 { "nz", "zr", X86_EFL_ZF },
748 { "ac", "na", X86_EFL_AF },
749 { "po", "pe", X86_EFL_PF },
750 { "cy", "nc", X86_EFL_CF },
751 };
752 char *psz = pszEFlags;
753 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
754 {
755 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
756 if (pszAdd)
757 {
758 strcpy(psz, pszAdd);
759 psz += strlen(pszAdd);
760 *psz++ = ' ';
761 }
762 }
763 psz[-1] = '\0';
764}
765
766
767/**
768 * Formats a full register dump.
769 *
770 * @param pVM VM Handle.
771 * @param pCtx The context to format.
772 * @param pCtxCore The context core to format.
773 * @param pHlp Output functions.
774 * @param enmType The dump type.
775 * @param pszPrefix Register name prefix.
776 */
777static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
778{
779 /*
780 * Format the EFLAGS.
781 */
782 uint32_t efl = pCtxCore->eflags.u32;
783 char szEFlags[80];
784 cpumR3InfoFormatFlags(&szEFlags[0], efl);
785
786 /*
787 * Format the registers.
788 */
789 switch (enmType)
790 {
791 case CPUMDUMPTYPE_TERSE:
792 if (CPUMGetGuestMode(pVM) == CPUMMODE_LONG)
793 {
794 pHlp->pfnPrintf(pHlp,
795 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64 %srsi=%016RX64 %srdi=%016RX64\n"
796 "%sr8 =%016RX64 %sr9 =%016RX64 %sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
797 "%sr14=%016RX64 %sr15 =%016RX64\n"
798 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
799 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
800 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
801 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
802 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
803 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
804 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
805 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
806 }
807 else
808 pHlp->pfnPrintf(pHlp,
809 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
810 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
811 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
812 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
813 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
814 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
815 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
816 break;
817
818 case CPUMDUMPTYPE_DEFAULT:
819 if (CPUMGetGuestMode(pVM) == CPUMMODE_LONG)
820 {
821 pHlp->pfnPrintf(pHlp,
822 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64 %srsi=%016RX64 %srdi=%016RX64\n"
823 "%sr8 =%016RX64 %sr9 =%016RX64 %sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
824 "%sr14=%016RX64 %sr15 =%016RX64\n"
825 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
826 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
827 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
828 ,
829 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
830 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
831 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
832 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
833 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
834 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
835 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
836 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
837 }
838 else
839 pHlp->pfnPrintf(pHlp,
840 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
841 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
842 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
843 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
844 ,
845 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
846 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
847 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
848 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
849 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
850 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
851 break;
852
853 case CPUMDUMPTYPE_VERBOSE:
854 if (CPUMGetGuestMode(pVM) == CPUMMODE_LONG)
855 {
856 pHlp->pfnPrintf(pHlp,
857 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64 %srsi=%016RX64 %srdi=%016RX64\n"
858 "%sr8 =%016RX64 %sr9 =%016RX64 %sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
859 "%sr14=%016RX64 %sr15 =%016RX64\n"
860 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
861 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
862 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
863 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
864 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
865 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
866 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
867 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
868 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
869 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
870 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
871 ,
872 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
873 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
874 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
875 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
876 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
877 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
878 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
879 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
880 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
881 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
882 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
883 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
884 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
885 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
886 }
887 else
888 pHlp->pfnPrintf(pHlp,
889 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
890 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
891 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
892 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
893 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
894 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
895 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
896 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
897 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
898 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
899 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
900 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
901 ,
902 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
903 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
904 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
905 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
906 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
907 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
908 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
909 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
910 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
911 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
912 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
913 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
914
915 pHlp->pfnPrintf(pHlp,
916 "FPU:\n"
917 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
918 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
919 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
920 ,
921 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
922 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
923 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
924 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
925
926
927 break;
928 }
929}
930
931
932/**
933 * Display all cpu states and any other cpum info.
934 *
935 * @param pVM VM Handle.
936 * @param pHlp The info helper functions.
937 * @param pszArgs Arguments, ignored.
938 */
939static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
940{
941 cpumR3InfoGuest(pVM, pHlp, pszArgs);
942 cpumR3InfoHyper(pVM, pHlp, pszArgs);
943 cpumR3InfoHost(pVM, pHlp, pszArgs);
944}
945
946
947/**
948 * Parses the info argument.
949 *
950 * The argument starts with 'verbose', 'terse' or 'default' and then
951 * continues with the comment string.
952 *
953 * @param pszArgs The pointer to the argument string.
954 * @param penmType Where to store the dump type request.
955 * @param ppszComment Where to store the pointer to the comment string.
956 */
957static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
958{
959 if (!pszArgs)
960 {
961 *penmType = CPUMDUMPTYPE_DEFAULT;
962 *ppszComment = "";
963 }
964 else
965 {
966 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
967 {
968 pszArgs += 5;
969 *penmType = CPUMDUMPTYPE_VERBOSE;
970 }
971 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
972 {
973 pszArgs += 5;
974 *penmType = CPUMDUMPTYPE_TERSE;
975 }
976 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
977 {
978 pszArgs += 7;
979 *penmType = CPUMDUMPTYPE_DEFAULT;
980 }
981 else
982 *penmType = CPUMDUMPTYPE_DEFAULT;
983 *ppszComment = RTStrStripL(pszArgs);
984 }
985}
986
987
988/**
989 * Display the guest cpu state.
990 *
991 * @param pVM VM Handle.
992 * @param pHlp The info helper functions.
993 * @param pszArgs Arguments, ignored.
994 */
995static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
996{
997 CPUMDUMPTYPE enmType;
998 const char *pszComment;
999 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1000 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1001 cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
1002}
1003
1004
1005/**
1006 * Display the hypervisor cpu state.
1007 *
1008 * @param pVM VM Handle.
1009 * @param pHlp The info helper functions.
1010 * @param pszArgs Arguments, ignored.
1011 */
1012static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1013{
1014 CPUMDUMPTYPE enmType;
1015 const char *pszComment;
1016 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1017 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1018 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1019 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1020}
1021
1022
1023/**
1024 * Display the host cpu state.
1025 *
1026 * @param pVM VM Handle.
1027 * @param pHlp The info helper functions.
1028 * @param pszArgs Arguments, ignored.
1029 */
1030static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1031{
1032 CPUMDUMPTYPE enmType;
1033 const char *pszComment;
1034 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1035 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1036
1037 /*
1038 * Format the EFLAGS.
1039 */
1040 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
1041#if HC_ARCH_BITS == 32
1042 uint32_t efl = pCtx->eflags.u32;
1043#else
1044 uint64_t efl = pCtx->rflags;
1045#endif
1046 char szEFlags[80];
1047 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1048
1049 /*
1050 * Format the registers.
1051 */
1052#if HC_ARCH_BITS == 32
1053# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1054 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1055# endif
1056 {
1057 pHlp->pfnPrintf(pHlp,
1058 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1059 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1060 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1061 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1062 "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
1063 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1064 ,
1065 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1066 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1067 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1068 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1069 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1070 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1071 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1072 }
1073# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1074 else
1075# endif
1076#endif
1077#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1078 {
1079 pHlp->pfnPrintf(pHlp,
1080 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1081 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1082 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1083 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1084 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1085 "r14=%016RX64 r15=%016RX64\n"
1086 "iopl=%d %31s\n"
1087 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1088 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1089 "cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
1090 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
1091 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1092 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1093 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1094 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1095 ,
1096 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1097 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1098 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1099 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1100 pCtx->r11, pCtx->r12, pCtx->r13,
1101 pCtx->r14, pCtx->r15,
1102 X86_EFL_GET_IOPL(efl), szEFlags,
1103 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1104 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1105 pCtx->cr4, pCtx->cr8, pCtx->ldtr, pCtx->tr,
1106 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1107 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1108 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1109 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1110 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1111 }
1112#endif
1113}
1114
1115
1116/**
1117 * Get L1 cache / TLS associativity.
1118 */
1119static const char *getCacheAss(unsigned u, char *pszBuf)
1120{
1121 if (u == 0)
1122 return "res0 ";
1123 if (u == 1)
1124 return "direct";
1125 if (u >= 256)
1126 return "???";
1127
1128 RTStrPrintf(pszBuf, 16, "%d way", u);
1129 return pszBuf;
1130}
1131
1132
1133/**
1134 * Get L2 cache soociativity.
1135 */
1136const char *getL2CacheAss(unsigned u)
1137{
1138 switch (u)
1139 {
1140 case 0: return "off ";
1141 case 1: return "direct";
1142 case 2: return "2 way ";
1143 case 3: return "res3 ";
1144 case 4: return "4 way ";
1145 case 5: return "res5 ";
1146 case 6: return "8 way "; case 7: return "res7 ";
1147 case 8: return "16 way";
1148 case 9: return "res9 ";
1149 case 10: return "res10 ";
1150 case 11: return "res11 ";
1151 case 12: return "res12 ";
1152 case 13: return "res13 ";
1153 case 14: return "res14 ";
1154 case 15: return "fully ";
1155 default:
1156 return "????";
1157 }
1158}
1159
1160
1161/**
1162 * Display the guest CpuId leaves.
1163 *
1164 * @param pVM VM Handle.
1165 * @param pHlp The info helper functions.
1166 * @param pszArgs "terse", "default" or "verbose".
1167 */
1168static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1169{
1170 /*
1171 * Parse the argument.
1172 */
1173 unsigned iVerbosity = 1;
1174 if (pszArgs)
1175 {
1176 pszArgs = RTStrStripL(pszArgs);
1177 if (!strcmp(pszArgs, "terse"))
1178 iVerbosity--;
1179 else if (!strcmp(pszArgs, "verbose"))
1180 iVerbosity++;
1181 }
1182
1183 /*
1184 * Start cracking.
1185 */
1186 CPUMCPUID Host;
1187 CPUMCPUID Guest;
1188 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1189
1190 pHlp->pfnPrintf(pHlp,
1191 " RAW Standard CPUIDs\n"
1192 " Function eax ebx ecx edx\n");
1193 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1194 {
1195 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1196 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1197
1198 pHlp->pfnPrintf(pHlp,
1199 "Gst: %08x %08x %08x %08x %08x%s\n"
1200 "Hst: %08x %08x %08x %08x\n",
1201 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1202 i <= cStdMax ? "" : "*",
1203 Host.eax, Host.ebx, Host.ecx, Host.edx);
1204 }
1205
1206 /*
1207 * If verbose, decode it.
1208 */
1209 if (iVerbosity)
1210 {
1211 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1212 pHlp->pfnPrintf(pHlp,
1213 "Name: %.04s%.04s%.04s\n"
1214 "Supports: 0-%x\n",
1215 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1216 }
1217
1218 /*
1219 * Get Features.
1220 */
1221 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1222 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1223 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1224 if (cStdMax >= 1 && iVerbosity)
1225 {
1226 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1227 uint32_t uEAX = Guest.eax;
1228
1229 pHlp->pfnPrintf(pHlp,
1230 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1231 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1232 "Stepping: %d\n"
1233 "APIC ID: %#04x\n"
1234 "Logical CPUs: %d\n"
1235 "CLFLUSH Size: %d\n"
1236 "Brand ID: %#04x\n",
1237 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1238 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1239 ASMGetCpuStepping(uEAX),
1240 (Guest.ebx >> 24) & 0xff,
1241 (Guest.ebx >> 16) & 0xff,
1242 (Guest.ebx >> 8) & 0xff,
1243 (Guest.ebx >> 0) & 0xff);
1244 if (iVerbosity == 1)
1245 {
1246 uint32_t uEDX = Guest.edx;
1247 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1248 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1249 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1250 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1251 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1252 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1253 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1254 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1255 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1256 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1257 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1258 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1259 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1260 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1261 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1262 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1263 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1264 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1265 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1266 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1267 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1268 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1269 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1270 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1271 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1272 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1273 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1274 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1275 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1276 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1277 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1278 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1279 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1280 pHlp->pfnPrintf(pHlp, "\n");
1281
1282 uint32_t uECX = Guest.ecx;
1283 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1284 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1285 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1286 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1287 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1288 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1289 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1290 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1291 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1292 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1293 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1294 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1295 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1296 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1297 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1298 for (unsigned iBit = 14; iBit < 32; iBit++)
1299 if (uECX & RT_BIT(iBit))
1300 pHlp->pfnPrintf(pHlp, " %d", iBit);
1301 pHlp->pfnPrintf(pHlp, "\n");
1302 }
1303 else
1304 {
1305 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1306
1307 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1308 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1309 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1310 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1311
1312 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1313 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1314 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1315 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1316 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1317 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1318 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1319 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1320 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1321 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1322 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1323 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1324 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1325 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1326 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1327 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1328 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1329 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1330 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1331 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1332 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1333 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1334 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1335 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1336 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1337 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1338 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1339 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1340 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1341 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1342 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1343 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1344 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1345
1346 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1347 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1348 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1349 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1350 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1351 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1352 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1353 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1354 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1355 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1356 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1357 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1358 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1359 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1360 }
1361 }
1362 if (cStdMax >= 2 && iVerbosity)
1363 {
1364 /** @todo */
1365 }
1366
1367 /*
1368 * Extended.
1369 * Implemented after AMD specs.
1370 */
1371 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1372
1373 pHlp->pfnPrintf(pHlp,
1374 "\n"
1375 " RAW Extended CPUIDs\n"
1376 " Function eax ebx ecx edx\n");
1377 for (unsigned i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1378 {
1379 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1380 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1381
1382 pHlp->pfnPrintf(pHlp,
1383 "Gst: %08x %08x %08x %08x %08x%s\n"
1384 "Hst: %08x %08x %08x %08x\n",
1385 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1386 i <= cExtMax ? "" : "*",
1387 Host.eax, Host.ebx, Host.ecx, Host.edx);
1388 }
1389
1390 /*
1391 * Understandable output
1392 */
1393 if (iVerbosity && cExtMax >= 0)
1394 {
1395 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1396 pHlp->pfnPrintf(pHlp,
1397 "Ext Name: %.4s%.4s%.4s\n"
1398 "Ext Supports: 0x80000000-%#010x\n",
1399 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1400 }
1401
1402 if (iVerbosity && cExtMax >= 1)
1403 {
1404 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1405 uint32_t uEAX = Guest.eax;
1406 pHlp->pfnPrintf(pHlp,
1407 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1408 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1409 "Stepping: %d\n"
1410 "Brand ID: %#05x\n",
1411 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1412 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1413 ASMGetCpuStepping(uEAX),
1414 Guest.ebx & 0xfff);
1415
1416 if (iVerbosity == 1)
1417 {
1418 uint32_t uEDX = Guest.edx;
1419 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1420 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1421 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1422 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1423 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1424 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1425 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1426 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1427 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1428 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1429 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1430 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1431 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1432 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1433 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1434 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1435 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1436 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1437 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1438 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1439 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1440 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1441 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1442 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1443 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1444 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1445 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1446 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1447 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1448 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1449 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1450 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1451 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1452 pHlp->pfnPrintf(pHlp, "\n");
1453
1454 uint32_t uECX = Guest.ecx;
1455 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1456 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1457 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1458 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1459 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1460 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1461 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1462 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1463 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1464 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1465 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1466 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1467 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1468 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1469 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1470 for (unsigned iBit = 5; iBit < 32; iBit++)
1471 if (uECX & RT_BIT(iBit))
1472 pHlp->pfnPrintf(pHlp, " %d", iBit);
1473 pHlp->pfnPrintf(pHlp, "\n");
1474 }
1475 else
1476 {
1477 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1478
1479 uint32_t uEdxGst = Guest.edx;
1480 uint32_t uEdxHst = Host.edx;
1481 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1482 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1483 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1484 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1485 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1486 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1487 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1488 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1489 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1490 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1491 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1492 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1493 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1494 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1495 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1496 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1497 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1498 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1499 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1500 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1501 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1502 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1503 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1504 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1505 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1506 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1507 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1508 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1509 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1510 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1511 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1512 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1513 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1514
1515 uint32_t uEcxGst = Guest.ecx;
1516 uint32_t uEcxHst = Host.ecx;
1517 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1518 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1519 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1520 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1521 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1522 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1523 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1524 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1525 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1526 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1527 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1528 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1529 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1530 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1531 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1532 }
1533 }
1534
1535 if (iVerbosity && cExtMax >= 2)
1536 {
1537 char szString[4*4*3+1] = {0};
1538 uint32_t *pu32 = (uint32_t *)szString;
1539 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1540 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1541 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1542 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1543 if (cExtMax >= 3)
1544 {
1545 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1546 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1547 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1548 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1549 }
1550 if (cExtMax >= 4)
1551 {
1552 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1553 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1554 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1555 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1556 }
1557 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1558 }
1559
1560 if (iVerbosity && cExtMax >= 5)
1561 {
1562 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1563 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1564 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1565 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1566 char sz1[32];
1567 char sz2[32];
1568
1569 pHlp->pfnPrintf(pHlp,
1570 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1571 "TLB 2/4M Data: %s %3d entries\n",
1572 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1573 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1574 pHlp->pfnPrintf(pHlp,
1575 "TLB 4K Instr/Uni: %s %3d entries\n"
1576 "TLB 4K Data: %s %3d entries\n",
1577 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1578 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1579 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1580 "L1 Instr Cache Lines Per Tag: %d\n"
1581 "L1 Instr Cache Associativity: %s\n"
1582 "L1 Instr Cache Size: %d KB\n",
1583 (uEDX >> 0) & 0xff,
1584 (uEDX >> 8) & 0xff,
1585 getCacheAss((uEDX >> 16) & 0xff, sz1),
1586 (uEDX >> 24) & 0xff);
1587 pHlp->pfnPrintf(pHlp,
1588 "L1 Data Cache Line Size: %d bytes\n"
1589 "L1 Data Cache Lines Per Tag: %d\n"
1590 "L1 Data Cache Associativity: %s\n"
1591 "L1 Data Cache Size: %d KB\n",
1592 (uECX >> 0) & 0xff,
1593 (uECX >> 8) & 0xff,
1594 getCacheAss((uECX >> 16) & 0xff, sz1),
1595 (uECX >> 24) & 0xff);
1596 }
1597
1598 if (iVerbosity && cExtMax >= 6)
1599 {
1600 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1601 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1602 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1603
1604 pHlp->pfnPrintf(pHlp,
1605 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1606 "L2 TLB 2/4M Data: %s %4d entries\n",
1607 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1608 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1609 pHlp->pfnPrintf(pHlp,
1610 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1611 "L2 TLB 4K Data: %s %4d entries\n",
1612 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1613 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1614 pHlp->pfnPrintf(pHlp,
1615 "L2 Cache Line Size: %d bytes\n"
1616 "L2 Cache Lines Per Tag: %d\n"
1617 "L2 Cache Associativity: %s\n"
1618 "L2 Cache Size: %d KB\n",
1619 (uEDX >> 0) & 0xff,
1620 (uEDX >> 8) & 0xf,
1621 getL2CacheAss((uEDX >> 12) & 0xf),
1622 (uEDX >> 16) & 0xffff);
1623 }
1624
1625 if (iVerbosity && cExtMax >= 7)
1626 {
1627 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1628
1629 pHlp->pfnPrintf(pHlp, "APM Features: ");
1630 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1631 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1632 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1633 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1634 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1635 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1636 for (unsigned iBit = 6; iBit < 32; iBit++)
1637 if (uEDX & RT_BIT(iBit))
1638 pHlp->pfnPrintf(pHlp, " %d", iBit);
1639 pHlp->pfnPrintf(pHlp, "\n");
1640 }
1641
1642 if (iVerbosity && cExtMax >= 8)
1643 {
1644 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1645 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1646
1647 pHlp->pfnPrintf(pHlp,
1648 "Physical Address Width: %d bits\n"
1649 "Virtual Address Width: %d bits\n",
1650 (uEAX >> 0) & 0xff,
1651 (uEAX >> 8) & 0xff);
1652 pHlp->pfnPrintf(pHlp,
1653 "Physical Core Count: %d\n",
1654 (uECX >> 0) & 0xff);
1655 }
1656
1657
1658 /*
1659 * Centaur.
1660 */
1661 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1662
1663 pHlp->pfnPrintf(pHlp,
1664 "\n"
1665 " RAW Centaur CPUIDs\n"
1666 " Function eax ebx ecx edx\n");
1667 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1668 {
1669 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1670 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1671
1672 pHlp->pfnPrintf(pHlp,
1673 "Gst: %08x %08x %08x %08x %08x%s\n"
1674 "Hst: %08x %08x %08x %08x\n",
1675 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1676 i <= cCentaurMax ? "" : "*",
1677 Host.eax, Host.ebx, Host.ecx, Host.edx);
1678 }
1679
1680 /*
1681 * Understandable output
1682 */
1683 if (iVerbosity && cCentaurMax >= 0)
1684 {
1685 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1686 pHlp->pfnPrintf(pHlp,
1687 "Centaur Supports: 0xc0000000-%#010x\n",
1688 Guest.eax);
1689 }
1690
1691 if (iVerbosity && cCentaurMax >= 1)
1692 {
1693 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1694 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1695 uint32_t uEdxHst = Host.edx;
1696
1697 if (iVerbosity == 1)
1698 {
1699 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1700 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1701 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1702 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1703 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1704 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1705 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1706 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1707 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1708 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1709 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
1710 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
1711 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
1712 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
1713 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
1714 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
1715 for (unsigned iBit = 14; iBit < 32; iBit++)
1716 if (uEdxGst & RT_BIT(iBit))
1717 pHlp->pfnPrintf(pHlp, " %d", iBit);
1718 pHlp->pfnPrintf(pHlp, "\n");
1719 }
1720 else
1721 {
1722 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1723 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1724 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1725 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1726 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1727 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1728 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1729 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1730 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1731 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1732 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1733 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1734 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1735 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1736 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1737 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1738 for (unsigned iBit = 14; iBit < 32; iBit++)
1739 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
1740 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
1741 pHlp->pfnPrintf(pHlp, "\n");
1742 }
1743 }
1744}
1745
1746
1747/**
1748 * Structure used when disassembling and instructions in DBGF.
1749 * This is used so the reader function can get the stuff it needs.
1750 */
1751typedef struct CPUMDISASSTATE
1752{
1753 /** Pointer to the CPU structure. */
1754 PDISCPUSTATE pCpu;
1755 /** The VM handle. */
1756 PVM pVM;
1757 /** Pointer to the first byte in the segemnt. */
1758 RTGCUINTPTR GCPtrSegBase;
1759 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1760 RTGCUINTPTR GCPtrSegEnd;
1761 /** The size of the segment minus 1. */
1762 RTGCUINTPTR cbSegLimit;
1763 /** Pointer to the current page - HC Ptr. */
1764 void const *pvPageHC;
1765 /** Pointer to the current page - GC Ptr. */
1766 RTGCPTR pvPageGC;
1767 /** The lock information that PGMPhysReleasePageMappingLock needs. */
1768 PGMPAGEMAPLOCK PageMapLock;
1769 /** Whether the PageMapLock is valid or not. */
1770 bool fLocked;
1771} CPUMDISASSTATE, *PCPUMDISASSTATE;
1772
1773
1774/**
1775 * Instruction reader.
1776 *
1777 * @returns VBox status code.
1778 * @param PtrSrc Address to read from.
1779 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1780 * @param pu8Dst Where to store the bytes.
1781 * @param cbRead Number of bytes to read.
1782 * @param uDisCpu Pointer to the disassembler cpu state.
1783 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1784 */
1785static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
1786{
1787 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1788 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
1789 Assert(cbRead > 0);
1790 for (;;)
1791 {
1792 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1793
1794 /* Need to update the page translation? */
1795 if ( !pState->pvPageHC
1796 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1797 {
1798 int rc = VINF_SUCCESS;
1799
1800 /* translate the address */
1801 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1802 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1803 {
1804 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1805 if (!pState->pvPageHC)
1806 rc = VERR_INVALID_POINTER;
1807 }
1808 else
1809 {
1810 /* Release mapping lock previously acquired. */
1811 if (pState->fLocked)
1812 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
1813 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
1814 pState->fLocked = RT_SUCCESS_NP(rc);
1815 }
1816 if (VBOX_FAILURE(rc))
1817 {
1818 pState->pvPageHC = NULL;
1819 return rc;
1820 }
1821 }
1822
1823 /* check the segemnt limit */
1824 if (PtrSrc > pState->cbSegLimit)
1825 return VERR_OUT_OF_SELECTOR_BOUNDS;
1826
1827 /* calc how much we can read */
1828 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1829 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1830 if (cb > cbSeg && !cbSeg)
1831 cb = cbSeg;
1832 if (cb > cbRead)
1833 cb = cbRead;
1834
1835 /* read and advance */
1836 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1837 cbRead -= cb;
1838 if (!cbRead)
1839 return VINF_SUCCESS;
1840 pu8Dst += cb;
1841 PtrSrc += cb;
1842 }
1843}
1844
1845
1846/**
1847 * Disassemble an instruction and return the information in the provided structure.
1848 *
1849 * @returns VBox status code.
1850 * @param pVM VM Handle
1851 * @param pCtx CPU context
1852 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1853 * @param pCpu Disassembly state
1854 * @param pszPrefix String prefix for logging (debug only)
1855 *
1856 */
1857CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1858{
1859 CPUMDISASSTATE State;
1860 int rc;
1861
1862 State.pCpu = pCpu;
1863 State.pvPageGC = 0;
1864 State.pvPageHC = NULL;
1865 State.pVM = pVM;
1866 State.fLocked = false;
1867
1868 /*
1869 * Get selector information.
1870 */
1871 if ( (pCtx->cr0 & X86_CR0_PE)
1872 && pCtx->eflags.Bits.u1VM == 0)
1873 {
1874 if (CPUMAreHiddenSelRegsValid(pVM))
1875 {
1876 State.GCPtrSegBase = pCtx->csHid.u64Base;
1877 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
1878 State.cbSegLimit = pCtx->csHid.u32Limit;
1879 pCpu->mode = pCtx->csHid.Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1880 }
1881 else
1882 {
1883 SELMSELINFO SelInfo;
1884
1885 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1886 if (!VBOX_SUCCESS(rc))
1887 {
1888 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1889 return rc;
1890 }
1891
1892 /*
1893 * Validate the selector.
1894 */
1895 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1896 if (!VBOX_SUCCESS(rc))
1897 {
1898 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1899 return rc;
1900 }
1901 State.GCPtrSegBase = SelInfo.GCPtrBase;
1902 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1903 State.cbSegLimit = SelInfo.cbLimit;
1904 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1905 }
1906 }
1907 else
1908 {
1909 /* real or V86 mode */
1910 pCpu->mode = CPUMODE_16BIT;
1911 State.GCPtrSegBase = pCtx->cs * 16;
1912 State.GCPtrSegEnd = 0xFFFFFFFF;
1913 State.cbSegLimit = 0xFFFFFFFF;
1914 }
1915
1916 /*
1917 * Disassemble the instruction.
1918 */
1919 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
1920 pCpu->apvUserData[0] = &State;
1921
1922 uint32_t cbInstr;
1923#ifndef LOG_ENABLED
1924 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
1925 if (VBOX_SUCCESS(rc))
1926 {
1927#else
1928 char szOutput[160];
1929 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
1930 if (VBOX_SUCCESS(rc))
1931 {
1932 /* log it */
1933 if (pszPrefix)
1934 Log(("%s: %s", pszPrefix, szOutput));
1935 else
1936 Log(("%s", szOutput));
1937#endif
1938 rc = VINF_SUCCESS;
1939 }
1940 else
1941 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
1942
1943 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
1944 if (State.fLocked)
1945 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
1946
1947 return rc;
1948}
1949
1950#ifdef DEBUG
1951
1952/**
1953 * Disassemble an instruction and dump it to the log
1954 *
1955 * @returns VBox status code.
1956 * @param pVM VM Handle
1957 * @param pCtx CPU context
1958 * @param pc GC instruction pointer
1959 * @param prefix String prefix for logging
1960 * @deprecated Use DBGFR3DisasInstrCurrentLog().
1961 *
1962 */
1963CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
1964{
1965 DISCPUSTATE cpu;
1966
1967 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1968}
1969
1970/**
1971 * Disassemble an instruction and dump it to the log
1972 *
1973 * @returns VBox status code.
1974 * @param pVM VM Handle
1975 * @param pCtx CPU context
1976 * @param pc GC instruction pointer
1977 * @param prefix String prefix for logging
1978 * @param nrInstructions
1979 *
1980 */
1981CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
1982{
1983 for(int i=0;i<nrInstructions;i++)
1984 {
1985 DISCPUSTATE cpu;
1986
1987 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1988 pc += cpu.opsize;
1989 }
1990}
1991
1992#endif /* DEBUG */
1993
1994#ifdef DEBUG
1995/**
1996 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
1997 *
1998 * @internal
1999 */
2000CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2001{
2002 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
2003}
2004#endif /* DEBUG */
2005
2006
2007/**
2008 * API for controlling a few of the CPU features found in CR4.
2009 *
2010 * Currently only X86_CR4_TSD is accepted as input.
2011 *
2012 * @returns VBox status code.
2013 *
2014 * @param pVM The VM handle.
2015 * @param fOr The CR4 OR mask.
2016 * @param fAnd The CR4 AND mask.
2017 */
2018CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2019{
2020 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2021 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2022
2023 pVM->cpum.s.CR4.OrMask &= fAnd;
2024 pVM->cpum.s.CR4.OrMask |= fOr;
2025
2026 return VINF_SUCCESS;
2027}
2028
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