CPUMInternal.h@ 12935

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1	/* $Id: CPUMInternal.h 12659 2008-09-22 23:18:19Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___CPUMInternal_h
23	#define ___CPUMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/x86.h>
28
29
30	#if !defined(IN_CPUM_R3) && !defined(IN_CPUM_R0) && !defined(IN_CPUM_GC)
31	# error "Not in CPUM! This is an internal header!"
32	#endif
33
34
35	/** @defgroup grp_cpum_int Internals
36	* @ingroup grp_cpum
37	* @internal
38	* @{
39	*/
40
41	/** Flags and types for CPUM fault handlers
42	* @{ */
43	/** Type: Load DS */
44	#define CPUM_HANDLER_DS 1
45	/** Type: Load ES */
46	#define CPUM_HANDLER_ES 2
47	/** Type: Load FS */
48	#define CPUM_HANDLER_FS 3
49	/** Type: Load GS */
50	#define CPUM_HANDLER_GS 4
51	/** Type: IRET */
52	#define CPUM_HANDLER_IRET 5
53	/** Type mask. */
54	#define CPUM_HANDLER_TYPEMASK 0xff
55	/** If set EBP points to the CPUMCTXCORE that's being used. */
56	#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
57	/** @} */
58
59
60	/** Use flags (CPUM::fUseFlags).
61	* (Don't forget to sync this with CPUMInternal.mac!)
62	* @{ */
63	/** Used the FPU, SSE or such stuff. */
64	#define CPUM_USED_FPU RT_BIT(0)
65	/** Used the FPU, SSE or such stuff since last we were in REM.
66	* REM syncing is clearing this, lazy FPU is setting it. */
67	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
68	/** Host OS is using SYSENTER and we must NULL the CS. */
69	#define CPUM_USE_SYSENTER RT_BIT(2)
70	/** Host OS is using SYSENTER and we must NULL the CS. */
71	#define CPUM_USE_SYSCALL RT_BIT(3)
72	/** Debug registers are used by host and must be disabled. */
73	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(4)
74	/** Enabled use of debug registers in guest context. */
75	#define CPUM_USE_DEBUG_REGS RT_BIT(5)
76	/** The XMM state was manually restored. (AMD only) */
77	#define CPUM_MANUAL_XMM_RESTORE RT_BIT(6)
78	/** @} */
79
80	/* Sanity check. */
81	#if defined(VBOX_WITH_HYBIRD_32BIT_KERNEL) && (HC_ARCH_BITS != 32 \|\| R0_ARCH_BITS != 32)
82	# error "VBOX_WITH_HYBIRD_32BIT_KERNEL is only for 32 bit builds."
83	#endif
84
85
86	/**
87	* The saved host CPU state.
88	*
89	* @remark The special VBOX_WITH_HYBIRD_32BIT_KERNEL checks here are for the 10.4.x series
90	* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
91	*/
92	typedef struct CPUMHOSTCTX
93	{
94	/** FPU state. (16-byte alignment)
95	* @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
96	X86FXSTATE fpu;
97
98	/** General purpose register, selectors, flags and more
99	* @{ */
100	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
101	/** General purpose register ++
102	* { */
103	//uint64_t rax; - scratch
104	uint64_t rbx;
105	//uint64_t rcx; - scratch
106	//uint64_t rdx; - scratch
107	uint64_t rdi;
108	uint64_t rsi;
109	uint64_t rbp;
110	uint64_t rsp;
111	//uint64_t r8; - scratch
112	//uint64_t r9; - scratch
113	uint64_t r10;
114	uint64_t r11;
115	uint64_t r12;
116	uint64_t r13;
117	uint64_t r14;
118	uint64_t r15;
119	//uint64_t rip; - scratch
120	uint64_t rflags;
121	#endif
122
123	#if HC_ARCH_BITS == 32
124	//uint32_t eax; - scratch
125	uint32_t ebx;
126	//uint32_t ecx; - scratch
127	//uint32_t edx; - scratch
128	uint32_t edi;
129	uint32_t esi;
130	uint32_t ebp;
131	X86EFLAGS eflags;
132	//uint32_t eip; - scratch
133	/* lss pair! */
134	uint32_t esp;
135	#endif
136	/** @} */
137
138	/** Selector registers
139	* @{ */
140	RTSEL ss;
141	RTSEL ssPadding;
142	RTSEL gs;
143	RTSEL gsPadding;
144	RTSEL fs;
145	RTSEL fsPadding;
146	RTSEL es;
147	RTSEL esPadding;
148	RTSEL ds;
149	RTSEL dsPadding;
150	RTSEL cs;
151	RTSEL csPadding;
152	/** @} */
153
154	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
155	/** Control registers.
156	* @{ */
157	uint32_t cr0;
158	//uint32_t cr2; - scratch
159	uint32_t cr3;
160	uint32_t cr4;
161	/** @} */
162
163	/** Debug registers.
164	* @{ */
165	uint32_t dr0;
166	uint32_t dr1;
167	uint32_t dr2;
168	uint32_t dr3;
169	uint32_t dr6;
170	uint32_t dr7;
171	/** @} */
172
173	/** Global Descriptor Table register. */
174	X86XDTR32 gdtr;
175	uint16_t gdtrPadding;
176	/** Interrupt Descriptor Table register. */
177	X86XDTR32 idtr;
178	uint16_t idtrPadding;
179	/** The task register. */
180	RTSEL ldtr;
181	RTSEL ldtrPadding;
182	/** The task register. */
183	RTSEL tr;
184	RTSEL trPadding;
185	uint32_t SysEnterPadding;
186
187	/** The sysenter msr registers.
188	* This member is not used by the hypervisor context. */
189	CPUMSYSENTER SysEnter;
190
191	/* padding to get 64byte aligned size */
192	uint8_t auPadding[24+32];
193
194	#elif HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
195
196	/** Control registers.
197	* @{ */
198	uint64_t cr0;
199	//uint64_t cr2; - scratch
200	uint64_t cr3;
201	uint64_t cr4;
202	uint64_t cr8;
203	/** @} */
204
205	/** Debug registers.
206	* @{ */
207	uint64_t dr0;
208	uint64_t dr1;
209	uint64_t dr2;
210	uint64_t dr3;
211	uint64_t dr6;
212	uint64_t dr7;
213	/** @} */
214
215	/** Global Descriptor Table register. */
216	X86XDTR64 gdtr;
217	uint16_t gdtrPadding;
218	/** Interrupt Descriptor Table register. */
219	X86XDTR64 idtr;
220	uint16_t idtrPadding;
221	/** The task register. */
222	RTSEL ldtr;
223	RTSEL ldtrPadding;
224	/** The task register. */
225	RTSEL tr;
226	RTSEL trPadding;
227
228	/** MSRs
229	* @{ */
230	CPUMSYSENTER SysEnter;
231	uint64_t FSbase;
232	uint64_t GSbase;
233	uint64_t efer;
234	/** @} */
235
236	/* padding to get 32byte aligned size */
237	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
238	uint8_t auPadding[16];
239	# else
240	uint8_t auPadding[8+32];
241	# endif
242
243	#else
244	# error HC_ARCH_BITS not defined
245	#endif
246	} CPUMHOSTCTX;
247	/** Pointer to the saved host CPU state. */
248	typedef CPUMHOSTCTX *PCPUMHOSTCTX;
249
250
251	/**
252	* CPUM Data (part of VM)
253	*/
254	typedef struct CPUM
255	{
256	/**
257	* Saved host context. Only valid while inside GC.
258	* Aligned on a 64-byte boundrary.
259	*/
260	CPUMHOSTCTX Host;
261
262	/**
263	* Hypervisor context.
264	* Aligned on a 64-byte boundrary.
265	*/
266	CPUMCTX Hyper;
267
268	/**
269	* Guest context.
270	* Aligned on a 64-byte boundrary.
271	*/
272	CPUMCTX Guest;
273
274
275	/** Pointer to the current hypervisor core context - R3Ptr. */
276	R3PTRTYPE(PCPUMCTXCORE) pHyperCoreR3;
277	/** Pointer to the current hypervisor core context - R3Ptr. */
278	R0PTRTYPE(PCPUMCTXCORE) pHyperCoreR0;
279	/** Pointer to the current hypervisor core context - RCPtr. */
280	RCPTRTYPE(PCPUMCTXCORE) pHyperCoreRC;
281
282	/** Use flags.
283	* These flags indicates both what is to be used and what have been used.
284	*/
285	uint32_t fUseFlags;
286
287	/** Changed flags.
288	* These flags indicates to REM (and others) which important guest
289	* registers which has been changed since last time the flags were cleared.
290	* See the CPUM_CHANGED_* defines for what we keep track of.
291	*/
292	uint32_t fChanged;
293
294	/** Hidden selector registers state.
295	* Valid (hw accelerated raw mode) or not (normal raw mode)
296	*/
297	uint32_t fValidHiddenSelRegs;
298
299	/** Host CPU Features - ECX */
300	struct
301	{
302	/** edx part */
303	X86CPUIDFEATEDX edx;
304	/** ecx part */
305	X86CPUIDFEATECX ecx;
306	} CPUFeatures;
307	/** Host extended CPU features. */
308	struct
309	{
310	/** edx part */
311	uint32_t edx;
312	/** ecx part */
313	uint32_t ecx;
314	} CPUFeaturesExt;
315
316	/* CPU manufacturer. */
317	CPUMCPUVENDOR enmCPUVendor;
318
319	/** CR4 mask */
320	struct
321	{
322	uint32_t AndMask;
323	uint32_t OrMask;
324	} CR4;
325
326	/** Have we entered rawmode? */
327	bool fRawEntered;
328	uint8_t abPadding[3 + (HC_ARCH_BITS == 64) * 4];
329
330	/** The standard set of CpuId leafs. */
331	CPUMCPUID aGuestCpuIdStd[6];
332	/** The extended set of CpuId leafs. */
333	CPUMCPUID aGuestCpuIdExt[10];
334	/** The centaur set of CpuId leafs. */
335	CPUMCPUID aGuestCpuIdCentaur[4];
336	/** The default set of CpuId leafs. */
337	CPUMCPUID GuestCpuIdDef;
338
339	/** Align the next member, and thereby the structure, on a 64-byte boundrary. */
340	uint8_t abPadding2[HC_ARCH_BITS == 32 ? 56 : 44];
341
342	/**
343	* Guest context on raw mode entry.
344	* This a debug feature, see CPUMR3SaveEntryCtx.
345	*/
346	CPUMCTX GuestEntry;
347	} CPUM;
348	/** Pointer to the CPUM instance data residing in the shared VM structure. */
349	typedef CPUM *PCPUM;
350
351	__BEGIN_DECLS
352
353	DECLASM(int) CPUMHandleLazyFPUAsm(PCPUM pCPUM);
354	DECLASM(int) CPUMRestoreHostFPUStateAsm(PCPUM pCPUM);
355	DECLASM(void) CPUMLoadFPUAsm(PCPUMCTX pCtx);
356	DECLASM(void) CPUMSaveFPUAsm(PCPUMCTX pCtx);
357	DECLASM(void) CPUMLoadXMMAsm(PCPUMCTX pCtx);
358	DECLASM(void) CPUMSaveXMMAsm(PCPUMCTX pCtx);
359	DECLASM(void) CPUMSetFCW(uint16_t u16FCW);
360	DECLASM(uint16_t) CPUMGetFCW();
361	DECLASM(void) CPUMSetMXCSR(uint32_t u32MXCSR);
362	DECLASM(uint32_t) CPUMGetMXCSR();
363
364	__END_DECLS
365
366	/** @} */
367
368	#endif
369

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source: vbox/trunk/src/VBox/VMM/CPUMInternal.h@ 12935

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