VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUMInternal.h@ 6457

Last change on this file since 6457 was 5999, checked in by vboxsync, 17 years ago

The Giant CDDL Dual-License Header Change.

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1/* $Id: CPUMInternal.h 5999 2007-12-07 15:05:06Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___CPUMInternal_h
19#define ___CPUMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/x86.h>
24
25
26#if !defined(IN_CPUM_R3) && !defined(IN_CPUM_R0) && !defined(IN_CPUM_GC)
27# error "Not in CPUM! This is an internal header!"
28#endif
29
30
31/** @defgroup grp_cpum_int Internals
32 * @ingroup grp_cpum
33 * @internal
34 * @{
35 */
36
37/** Flags and types for CPUM fault handlers
38 * @{ */
39/** Type: Load DS */
40#define CPUM_HANDLER_DS 1
41/** Type: Load ES */
42#define CPUM_HANDLER_ES 2
43/** Type: Load FS */
44#define CPUM_HANDLER_FS 3
45/** Type: Load GS */
46#define CPUM_HANDLER_GS 4
47/** Type: IRET */
48#define CPUM_HANDLER_IRET 5
49/** Type mask. */
50#define CPUM_HANDLER_TYPEMASK 0xff
51/** If set EBP points to the CPUMCTXCORE that's being used. */
52#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
53/** @} */
54
55
56/** Use flags (CPUM::fUseFlags).
57 * (Don't forget to sync this with CPUMInternal.mac!)
58 * @{ */
59/** Used the FPU, SSE or such stuff. */
60#define CPUM_USED_FPU RT_BIT(0)
61/** Used the FPU, SSE or such stuff since last we were in REM.
62 * REM syncing is clearing this, lazy FPU is setting it. */
63#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
64/** Host OS is using SYSENTER and we must NULL the CS. */
65#define CPUM_USE_SYSENTER RT_BIT(2)
66/** Host OS is using SYSENTER and we must NULL the CS. */
67#define CPUM_USE_SYSCALL RT_BIT(3)
68/** Debug registers are used by host and must be disabled. */
69#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(4)
70/** Enabled use of debug registers in guest context. */
71#define CPUM_USE_DEBUG_REGS RT_BIT(5)
72/** @} */
73
74/* Sanity check. */
75#if defined(VBOX_WITH_HYBIRD_32BIT_KERNEL) && (HC_ARCH_BITS != 32 || R0_ARCH_BITS != 32)
76# error "VBOX_WITH_HYBIRD_32BIT_KERNEL is only for 32 bit builds."
77#endif
78
79
80/**
81 * The save host CPU state.
82 *
83 * @remark The special VBOX_WITH_HYBIRD_32BIT_KERNEL checks here are for the 10.4.x series
84 * of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
85 */
86typedef struct CPUMHOSTCTX
87{
88 /** FPU state. (16-byte alignment)
89 * @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
90 X86FXSTATE fpu;
91
92 /** General purpose register, selectors, flags and more
93 * @{ */
94#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
95 /** General purpose register ++
96 * { */
97 //uint64_t rax; - scratch
98 uint64_t rbx;
99 //uint64_t rcx; - scratch
100 //uint64_t rdx; - scratch
101 uint64_t rdi;
102 uint64_t rsi;
103 uint64_t rbp;
104 uint64_t rsp;
105 //uint64_t r8; - scratch
106 //uint64_t r9; - scratch
107 uint64_t r10;
108 uint64_t r11;
109 uint64_t r12;
110 uint64_t r13;
111 uint64_t r14;
112 uint64_t r15;
113 //uint64_t rip; - scratch
114 uint64_t rflags;
115#endif
116
117#if HC_ARCH_BITS == 32
118 //uint32_t eax; - scratch
119 uint32_t ebx;
120 //uint32_t ecx; - scratch
121 //uint32_t edx; - scratch
122 uint32_t edi;
123 uint32_t esi;
124 uint32_t ebp;
125 X86EFLAGS eflags;
126 //uint32_t eip; - scratch
127 /* lss pair! */
128 uint32_t esp;
129#endif
130 /** @} */
131
132 /** Selector registers
133 * @{ */
134 RTSEL ss;
135 RTSEL ssPadding;
136 RTSEL gs;
137 RTSEL gsPadding;
138 RTSEL fs;
139 RTSEL fsPadding;
140 RTSEL es;
141 RTSEL esPadding;
142 RTSEL ds;
143 RTSEL dsPadding;
144 RTSEL cs;
145 RTSEL csPadding;
146 /** @} */
147
148#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
149 /** Control registers.
150 * @{ */
151 uint32_t cr0;
152 //uint32_t cr2; - scratch
153 uint32_t cr3;
154 uint32_t cr4;
155 /** @} */
156
157 /** Debug registers.
158 * @{ */
159 uint32_t dr0;
160 uint32_t dr1;
161 uint32_t dr2;
162 uint32_t dr3;
163 uint32_t dr6;
164 uint32_t dr7;
165 /** @} */
166
167 /** Global Descriptor Table register. */
168 X86XDTR32 gdtr;
169 uint16_t gdtrPadding;
170 /** Interrupt Descriptor Table register. */
171 X86XDTR32 idtr;
172 uint16_t idtrPadding;
173 /** The task register. */
174 RTSEL ldtr;
175 RTSEL ldtrPadding;
176 /** The task register. */
177 RTSEL tr;
178 RTSEL trPadding;
179 uint32_t SysEnterPadding;
180
181 /** The sysenter msr registers.
182 * This member is not used by the hypervisor context. */
183 CPUMSYSENTER SysEnter;
184
185 /* padding to get 32byte aligned size */
186 uint8_t auPadding[24];
187
188#elif HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
189
190 /** Control registers.
191 * @{ */
192 uint64_t cr0;
193 //uint64_t cr2; - scratch
194 uint64_t cr3;
195 uint64_t cr4;
196 uint64_t cr8;
197 /** @} */
198
199 /** Debug registers.
200 * @{ */
201 uint64_t dr0;
202 uint64_t dr1;
203 uint64_t dr2;
204 uint64_t dr3;
205 uint64_t dr6;
206 uint64_t dr7;
207 /** @} */
208
209 /** Global Descriptor Table register. */
210 X86XDTR64 gdtr;
211 uint16_t gdtrPadding;
212 /** Interrupt Descriptor Table register. */
213 X86XDTR64 idtr;
214 uint16_t idtrPadding;
215 /** The task register. */
216 RTSEL ldtr;
217 RTSEL ldtrPadding;
218 /** The task register. */
219 RTSEL tr;
220 RTSEL trPadding;
221
222 /** MSRs
223 * @{ */
224 CPUMSYSENTER SysEnter;
225 uint64_t FSbase;
226 uint64_t GSbase;
227 uint64_t efer;
228 /** @} */
229
230 /* padding to get 32byte aligned size */
231# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
232 uint8_t auPadding[16];
233# else
234 uint8_t auPadding[8];
235# endif
236
237#else
238# error HC_ARCH_BITS not defined
239#endif
240} CPUMHOSTCTX, *PCPUMHOSTCTX;
241
242
243/**
244 * Converts a CPUM pointer into a VM pointer.
245 * @returns Pointer to the VM structure the CPUM is part of.
246 * @param pCPUM Pointer to CPUM instance data.
247 */
248#define CPUM2VM(pCPUM) ( (PVM)((char*)pCPUM - pCPUM->offVM) )
249
250
251/**
252 * CPUM Data (part of VM)
253 */
254#pragma pack(1)
255typedef struct CPUM
256{
257 /** Offset to the VM structure. */
258 RTUINT offVM;
259 /** Pointer to CPU structure in GC. */
260 GCPTRTYPE(struct CPUM *) pCPUMGC;
261 /** Pointer to CPU structure in HC. */
262 R3R0PTRTYPE(struct CPUM *) pCPUMHC;
263
264 /** Force 32byte alignment of the next member. */
265 uint32_t padding[4 + (HC_ARCH_BITS == 32)];
266
267 /**
268 * Saved host context. Only valid while inside GC.
269 * Must be aligned on 16 byte boundrary.
270 */
271 CPUMHOSTCTX Host;
272
273 /**
274 * Hypervisor context.
275 * Must be aligned on 16 byte boundrary.
276 */
277 CPUMCTX Hyper;
278
279 /**
280 * Guest context.
281 * Must be aligned on 16 byte boundrary.
282 */
283 CPUMCTX Guest;
284
285
286 /** Pointer to the current hypervisor core context - R3Ptr. */
287 R3PTRTYPE(PCPUMCTXCORE) pHyperCoreR3;
288 /** Pointer to the current hypervisor core context - R3Ptr. */
289 R0PTRTYPE(PCPUMCTXCORE) pHyperCoreR0;
290 /** Pointer to the current hypervisor core context - GCPtr. */
291 GCPTRTYPE(PCPUMCTXCORE) pHyperCoreGC;
292
293 /** Use flags.
294 * These flags indicates both what is to be used and what have been used.
295 */
296 uint32_t fUseFlags;
297
298 /** Changed flags.
299 * These flags indicates to REM (and others) which important guest
300 * registers which has been changed since last time the flags were cleared.
301 * See the CPUM_CHANGED_* defines for what we keep track of.
302 */
303 uint32_t fChanged;
304
305 /** Hidden selector registers state.
306 * Valid (hw accelerated raw mode) or not (normal raw mode)
307 */
308 uint32_t fValidHiddenSelRegs;
309
310 /** Host CPU Features - ECX */
311 struct
312 {
313 /** edx part */
314 X86CPUIDFEATEDX edx;
315 /** ecx part */
316 X86CPUIDFEATECX ecx;
317 } CPUFeatures;
318
319 /** CR4 mask */
320 struct
321 {
322 uint32_t AndMask;
323 uint32_t OrMask;
324 } CR4;
325
326 /** Have we entered rawmode? */
327 bool fRawEntered;
328 uint8_t abPadding[3 + (HC_ARCH_BITS == 64) * 4];
329
330 /** The standard set of CpuId leafs. */
331 CPUMCPUID aGuestCpuIdStd[5];
332 /** The extended set of CpuId leafs. */
333 CPUMCPUID aGuestCpuIdExt[10];
334 /** The centaur set of CpuId leafs. */
335 CPUMCPUID aGuestCpuIdCentaur[4];
336 /** The default set of CpuId leafs. */
337 CPUMCPUID GuestCpuIdDef;
338
339 /**
340 * Guest context on raw mode entry.
341 * This a debug feature.
342 */
343 CPUMCTX GuestEntry;
344} CPUM, *PCPUM;
345#pragma pack()
346
347#ifdef IN_RING3
348
349#endif
350
351__BEGIN_DECLS
352
353DECLASM(int) CPUMHandleLazyFPUAsm(PCPUM pCPUM);
354DECLASM(int) CPUMRestoreHostFPUStateAsm(PCPUM pCPUM);
355
356__END_DECLS
357
358/** @} */
359
360#endif
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