| 1 | ; $Id: CPUMInternal.mac 9817 2008-06-19 11:47:38Z vboxsync $
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| 2 | ;; @file
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| 3 | ; CPUM - Internal header file.
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.virtualbox.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 | ; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 18 | ; Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 19 | ; additional information or have any questions.
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| 20 | ;
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| 21 |
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| 22 | %include "VBox/asmdefs.mac"
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| 23 |
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| 24 | %define CPUM_USED_FPU RT_BIT(0)
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| 25 | %define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
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| 26 | %define CPUM_USE_SYSENTER RT_BIT(2)
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| 27 | %define CPUM_USE_SYSCALL RT_BIT(3)
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| 28 | %define CPUM_USE_DEBUG_REGS_HOST RT_BIT(4)
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| 29 | %define CPUM_USE_DEBUG_REGS RT_BIT(5)
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| 30 |
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| 31 | %define CPUM_HANDLER_DS 1
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| 32 | %define CPUM_HANDLER_ES 2
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| 33 | %define CPUM_HANDLER_FS 3
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| 34 | %define CPUM_HANDLER_GS 4
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| 35 | %define CPUM_HANDLER_IRET 5
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| 36 | %define CPUM_HANDLER_TYPEMASK 0ffh
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| 37 | %define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
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| 38 |
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| 39 | %define VMMGCRET_USED_FPU 040000000h
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| 40 |
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| 41 | %define FPUSTATE_SIZE 512
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| 42 |
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| 43 | ;; if anyone figures how to do %if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL) in
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| 44 | ; nasm please tell / fix this hack.
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| 45 | %ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
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| 46 | %define fVBOX_WITH_HYBIRD_32BIT_KERNEL 1
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| 47 | %else
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| 48 | %define fVBOX_WITH_HYBIRD_32BIT_KERNEL 0
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| 49 | %endif
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| 50 |
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| 51 | struc CPUM
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| 52 | .offVM resd 1
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| 53 | .pCPUMGC RTGCPTR32_RES 1 ; Guest Context pointer
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| 54 | .pCPUMHC RTHCPTR_RES 1 ; Host Context pointer
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| 55 |
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| 56 |
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| 57 | ;
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| 58 | ; Host context state
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| 59 | ;
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| 60 | alignb 32
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| 61 | .Host.fpu resb FPUSTATE_SIZE
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| 62 |
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| 63 | %if HC_ARCH_BITS == 64 || fVBOX_WITH_HYBIRD_32BIT_KERNEL
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| 64 | ;.Host.rax resq 1 - scratch
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| 65 | .Host.rbx resq 1
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| 66 | ;.Host.rcx resq 1 - scratch
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| 67 | ;.Host.rdx resq 1 - scratch
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| 68 | .Host.rdi resq 1
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| 69 | .Host.rsi resq 1
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| 70 | .Host.rbp resq 1
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| 71 | .Host.rsp resq 1
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| 72 | ;.Host.r8 resq 1 - scratch
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| 73 | ;.Host.r9 resq 1 - scratch
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| 74 | .Host.r10 resq 1
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| 75 | .Host.r11 resq 1
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| 76 | .Host.r12 resq 1
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| 77 | .Host.r13 resq 1
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| 78 | .Host.r14 resq 1
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| 79 | .Host.r15 resq 1
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| 80 | ;.Host.rip resd 1 - scratch
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| 81 | .Host.rflags resq 1
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| 82 | %endif
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| 83 | %if HC_ARCH_BITS == 32
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| 84 | ;.Host.eax resd 1 - scratch
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| 85 | .Host.ebx resd 1
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| 86 | ;.Host.edx resd 1 - scratch
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| 87 | ;.Host.ecx resd 1 - scratch
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| 88 | .Host.edi resd 1
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| 89 | .Host.esi resd 1
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| 90 | .Host.ebp resd 1
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| 91 | .Host.eflags resd 1
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| 92 | ;.Host.eip resd 1 - scratch
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| 93 | ; lss pair!
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| 94 | .Host.esp resd 1
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| 95 | %endif
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| 96 | .Host.ss resw 1
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| 97 | .Host.ssPadding resw 1
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| 98 | .Host.gs resw 1
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| 99 | .Host.gsPadding resw 1
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| 100 | .Host.fs resw 1
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| 101 | .Host.fsPadding resw 1
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| 102 | .Host.es resw 1
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| 103 | .Host.esPadding resw 1
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| 104 | .Host.ds resw 1
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| 105 | .Host.dsPadding resw 1
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| 106 | .Host.cs resw 1
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| 107 | .Host.csPadding resw 1
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| 108 |
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| 109 | %if HC_ARCH_BITS == 32 && fVBOX_WITH_HYBIRD_32BIT_KERNEL == 0
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| 110 | .Host.cr0 resd 1
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| 111 | ;.Host.cr2 resd 1 - scratch
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| 112 | .Host.cr3 resd 1
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| 113 | .Host.cr4 resd 1
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| 114 |
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| 115 | .Host.dr0 resd 1
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| 116 | .Host.dr1 resd 1
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| 117 | .Host.dr2 resd 1
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| 118 | .Host.dr3 resd 1
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| 119 | .Host.dr6 resd 1
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| 120 | .Host.dr7 resd 1
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| 121 |
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| 122 | .Host.gdtr resb 6 ; GDT limit + linear address
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| 123 | .Host.gdtrPadding resw 1
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| 124 | .Host.idtr resb 6 ; IDT limit + linear address
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| 125 | .Host.idtrPadding resw 1
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| 126 | .Host.ldtr resw 1
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| 127 | .Host.ldtrPadding resw 1
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| 128 | .Host.tr resw 1
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| 129 | .Host.trPadding resw 1
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| 130 |
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| 131 | .Host.SysEnterPadding resd 1
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| 132 | .Host.SysEnter.cs resq 1
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| 133 | .Host.SysEnter.eip resq 1
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| 134 | .Host.SysEnter.esp resq 1
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| 135 |
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| 136 | %else ; 64-bit
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| 137 |
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| 138 | .Host.cr0 resq 1
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| 139 | ;.Host.cr2 resq 1 - scratch
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| 140 | .Host.cr3 resq 1
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| 141 | .Host.cr4 resq 1
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| 142 | .Host.cr8 resq 1
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| 143 |
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| 144 | .Host.dr0 resq 1
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| 145 | .Host.dr1 resq 1
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| 146 | .Host.dr2 resq 1
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| 147 | .Host.dr3 resq 1
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| 148 | .Host.dr6 resq 1
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| 149 | .Host.dr7 resq 1
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| 150 |
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| 151 | .Host.gdtr resb 10 ; GDT limit + linear address
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| 152 | .Host.gdtrPadding resw 1
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| 153 | .Host.idtr resb 10 ; IDT limit + linear address
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| 154 | .Host.idtrPadding resw 1
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| 155 | .Host.ldtr resw 1
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| 156 | .Host.ldtrPadding resw 1
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| 157 | .Host.tr resw 1
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| 158 | .Host.trPadding resw 1
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| 159 |
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| 160 | .Host.SysEnter.cs resq 1
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| 161 | .Host.SysEnter.eip resq 1
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| 162 | .Host.SysEnter.esp resq 1
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| 163 | .Host.FSbase resq 1
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| 164 | .Host.GSbase resq 1
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| 165 | .Host.efer resq 1
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| 166 | %endif ; 64-bit
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| 167 |
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| 168 |
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| 169 | ;
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| 170 | ; Hypervisor Context.
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| 171 | ; (Identical to .Host.*)
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| 172 | ;
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| 173 | alignb 32 ; the padding
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| 174 | .Hyper.fpu resb FPUSTATE_SIZE
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| 175 |
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| 176 | .Hyper.edi resq 1
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| 177 | .Hyper.esi resq 1
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| 178 | .Hyper.ebp resq 1
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| 179 | .Hyper.eax resq 1
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| 180 | .Hyper.ebx resq 1
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| 181 | .Hyper.edx resq 1
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| 182 | .Hyper.ecx resq 1
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| 183 | .Hyper.esp resq 1
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| 184 | .Hyper.lss_esp resd 1
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| 185 | .Hyper.ss resw 1
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| 186 | .Hyper.ssPadding resw 1
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| 187 | .Hyper.gs resw 1
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| 188 | .Hyper.gsPadding resw 1
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| 189 | .Hyper.fs resw 1
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| 190 | .Hyper.fsPadding resw 1
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| 191 | .Hyper.es resw 1
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| 192 | .Hyper.esPadding resw 1
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| 193 | .Hyper.ds resw 1
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| 194 | .Hyper.dsPadding resw 1
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| 195 | .Hyper.cs resw 1
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| 196 | .Hyper.csPadding resw 3
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| 197 | .Hyper.eflags resq 1
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| 198 | .Hyper.eip resq 1
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| 199 | .Hyper.r8 resq 1
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| 200 | .Hyper.r9 resq 1
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| 201 | .Hyper.r10 resq 1
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| 202 | .Hyper.r11 resq 1
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| 203 | .Hyper.r12 resq 1
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| 204 | .Hyper.r13 resq 1
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| 205 | .Hyper.r14 resq 1
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| 206 | .Hyper.r15 resq 1
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| 207 |
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| 208 | .Hyper.esHid.u64Base resq 1
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| 209 | .Hyper.esHid.u32Limit resd 1
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| 210 | .Hyper.esHid.Attr resd 1
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| 211 |
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| 212 | .Hyper.csHid.u64Base resq 1
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| 213 | .Hyper.csHid.u32Limit resd 1
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| 214 | .Hyper.csHid.Attr resd 1
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| 215 |
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| 216 | .Hyper.ssHid.u64Base resq 1
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| 217 | .Hyper.ssHid.u32Limit resd 1
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| 218 | .Hyper.ssHid.Attr resd 1
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| 219 |
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| 220 | .Hyper.dsHid.u64Base resq 1
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| 221 | .Hyper.dsHid.u32Limit resd 1
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| 222 | .Hyper.dsHid.Attr resd 1
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| 223 |
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| 224 | .Hyper.fsHid.u64Base resq 1
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| 225 | .Hyper.fsHid.u32Limit resd 1
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| 226 | .Hyper.fsHid.Attr resd 1
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| 227 |
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| 228 | .Hyper.gsHid.u64Base resq 1
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| 229 | .Hyper.gsHid.u32Limit resd 1
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| 230 | .Hyper.gsHid.Attr resd 1
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| 231 |
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| 232 | .Hyper.cr0 resq 1
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| 233 | .Hyper.cr2 resq 1
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| 234 | .Hyper.cr3 resq 1
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| 235 | .Hyper.cr4 resq 1
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| 236 | .Hyper.cr8 resq 1
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| 237 |
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| 238 | .Hyper.dr0 resq 1
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| 239 | .Hyper.dr1 resq 1
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| 240 | .Hyper.dr2 resq 1
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| 241 | .Hyper.dr3 resq 1
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| 242 | .Hyper.dr4 resq 1
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| 243 | .Hyper.dr5 resq 1
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| 244 | .Hyper.dr6 resq 1
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| 245 | .Hyper.dr7 resq 1
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| 246 |
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| 247 | .Hyper.gdtr resb 10 ; GDT limit + linear address
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| 248 | .Hyper.gdtrPadding resw 1
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| 249 | .Hyper.idtr resb 10 ; IDT limit + linear address
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| 250 | .Hyper.idtrPadding resw 1
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| 251 | .Hyper.ldtr resw 1
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| 252 | .Hyper.ldtrPadding resw 1
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| 253 | .Hyper.tr resw 1
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| 254 | .Hyper.trPadding resw 1
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| 255 |
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| 256 | .Hyper.SysEnter.cs resb 8
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| 257 | .Hyper.SysEnter.eip resb 8
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| 258 | .Hyper.SysEnter.esp resb 8
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| 259 |
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| 260 | .Hyper.msrEFER resb 8
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| 261 | .Hyper.msrSTAR resb 8
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| 262 | .Hyper.msrPAT resb 8
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| 263 | .Hyper.msrLSTAR resb 8
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| 264 | .Hyper.msrCSTAR resb 8
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| 265 | .Hyper.msrSFMASK resb 8
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| 266 | .Hyper.msrKERNELGSBASE resb 8
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| 267 |
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| 268 | .Hyper.ldtrHid.u64Base resq 1
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| 269 | .Hyper.ldtrHid.u32Limit resd 1
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| 270 | .Hyper.ldtrHid.Attr resd 1
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| 271 |
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| 272 | .Hyper.trHid.u64Base resq 1
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| 273 | .Hyper.trHid.u32Limit resd 1
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| 274 | .Hyper.trHid.Attr resd 1
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| 275 |
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| 276 | ; padding
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| 277 | .Hyper.padding resd 6
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| 278 |
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| 279 |
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| 280 |
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| 281 | ;
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| 282 | ; Guest context state
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| 283 | ; (Identical to the two above chunks)
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| 284 | ;
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| 285 | alignb 32
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| 286 | .Guest.fpu resb FPUSTATE_SIZE
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| 287 |
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| 288 | .Guest.edi resq 1
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| 289 | .Guest.esi resq 1
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| 290 | .Guest.ebp resq 1
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| 291 | .Guest.eax resq 1
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| 292 | .Guest.ebx resq 1
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| 293 | .Guest.edx resq 1
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| 294 | .Guest.ecx resq 1
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| 295 | .Guest.esp resq 1
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| 296 | .Guest.lss_esp resd 1
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| 297 | .Guest.ss resw 1
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| 298 | .Guest.ssPadding resw 1
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| 299 | .Guest.gs resw 1
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| 300 | .Guest.gsPadding resw 1
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| 301 | .Guest.fs resw 1
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| 302 | .Guest.fsPadding resw 1
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| 303 | .Guest.es resw 1
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| 304 | .Guest.esPadding resw 1
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| 305 | .Guest.ds resw 1
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| 306 | .Guest.dsPadding resw 1
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| 307 | .Guest.cs resw 1
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| 308 | .Guest.csPadding resw 3
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| 309 | .Guest.eflags resq 1
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| 310 | .Guest.eip resq 1
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| 311 | .Guest.r8 resq 1
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| 312 | .Guest.r9 resq 1
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| 313 | .Guest.r10 resq 1
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| 314 | .Guest.r11 resq 1
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| 315 | .Guest.r12 resq 1
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| 316 | .Guest.r13 resq 1
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| 317 | .Guest.r14 resq 1
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| 318 | .Guest.r15 resq 1
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| 319 |
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| 320 | .Guest.esHid.u64Base resq 1
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| 321 | .Guest.esHid.u32Limit resd 1
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| 322 | .Guest.esHid.Attr resd 1
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| 323 |
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| 324 | .Guest.csHid.u64Base resq 1
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| 325 | .Guest.csHid.u32Limit resd 1
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| 326 | .Guest.csHid.Attr resd 1
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| 327 |
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| 328 | .Guest.ssHid.u64Base resq 1
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| 329 | .Guest.ssHid.u32Limit resd 1
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| 330 | .Guest.ssHid.Attr resd 1
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| 331 |
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| 332 | .Guest.dsHid.u64Base resq 1
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| 333 | .Guest.dsHid.u32Limit resd 1
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| 334 | .Guest.dsHid.Attr resd 1
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| 335 |
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| 336 | .Guest.fsHid.u64Base resq 1
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| 337 | .Guest.fsHid.u32Limit resd 1
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| 338 | .Guest.fsHid.Attr resd 1
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| 339 |
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| 340 | .Guest.gsHid.u64Base resq 1
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| 341 | .Guest.gsHid.u32Limit resd 1
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| 342 | .Guest.gsHid.Attr resd 1
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| 343 |
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| 344 | .Guest.cr0 resq 1
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| 345 | .Guest.cr2 resq 1
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| 346 | .Guest.cr3 resq 1
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| 347 | .Guest.cr4 resq 1
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| 348 | .Guest.cr8 resq 1
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| 349 |
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| 350 | .Guest.dr0 resq 1
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| 351 | .Guest.dr1 resq 1
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| 352 | .Guest.dr2 resq 1
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| 353 | .Guest.dr3 resq 1
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| 354 | .Guest.dr4 resq 1
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| 355 | .Guest.dr5 resq 1
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| 356 | .Guest.dr6 resq 1
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| 357 | .Guest.dr7 resq 1
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| 358 |
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| 359 | .Guest.gdtr resb 10 ; GDT limit + linear address
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| 360 | .Guest.gdtrPadding resw 1
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| 361 | .Guest.idtr resb 10 ; IDT limit + linear address
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| 362 | .Guest.idtrPadding resw 1
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| 363 | .Guest.ldtr resw 1
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| 364 | .Guest.ldtrPadding resw 1
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| 365 | .Guest.tr resw 1
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| 366 | .Guest.trPadding resw 1
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| 367 |
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| 368 | .Guest.SysEnter.cs resb 8
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| 369 | .Guest.SysEnter.eip resb 8
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| 370 | .Guest.SysEnter.esp resb 8
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| 371 |
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| 372 | .Guest.msrEFER resb 8
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| 373 | .Guest.msrSTAR resb 8
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| 374 | .Guest.msrPAT resb 8
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| 375 | .Guest.msrLSTAR resb 8
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| 376 | .Guest.msrCSTAR resb 8
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| 377 | .Guest.msrSFMASK resb 8
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| 378 | .Guest.msrKERNELGSBASE resb 8
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| 379 |
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| 380 | .Guest.ldtrHid.u64Base resq 1
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| 381 | .Guest.ldtrHid.u32Limit resd 1
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| 382 | .Guest.ldtrHid.Attr resd 1
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| 383 |
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| 384 | .Guest.trHid.u64Base resq 1
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| 385 | .Guest.trHid.u32Limit resd 1
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| 386 | .Guest.trHid.Attr resd 1
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| 387 |
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| 388 | ; padding
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| 389 | .Guest.padding resd 6
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| 390 |
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| 391 |
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| 392 |
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| 393 | ;
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| 394 | ; Other stuff.
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| 395 | ;
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| 396 | alignb 32
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| 397 | ; hypervisor core context.
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| 398 | .pHyperCoreR3 RTR3PTR_RES 1
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| 399 | .pHyperCoreR0 RTR0PTR_RES 1
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| 400 | .pHyperCoreGC RTGCPTR32_RES 1
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| 401 | ;...
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| 402 | .fUseFlags resd 1
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| 403 | .fChanged resd 1
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| 404 | .fValidHiddenSelRegs resd 1
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| 405 |
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| 406 | ; CPUID eax=1
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| 407 | .CPUFeatures.edx resd 1
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| 408 | .CPUFeatures.ecx resd 1
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| 409 |
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|---|
| 410 | .enmCPUVendor resd 1
|
|---|
| 411 |
|
|---|
| 412 | ; CR4 masks
|
|---|
| 413 | .CR4.AndMask resd 1
|
|---|
| 414 | .CR4.OrMask resd 1
|
|---|
| 415 | ; entered rawmode?
|
|---|
| 416 | .fRawEntered resb 1
|
|---|
| 417 | %if RTHCPTR_CB == 8
|
|---|
| 418 | .abPadding resb 7
|
|---|
| 419 | %else
|
|---|
| 420 | .abPadding resb 3
|
|---|
| 421 | %endif
|
|---|
| 422 |
|
|---|
| 423 | ; CPUID leafs
|
|---|
| 424 | .aGuestCpuIdStd resb 16*5
|
|---|
| 425 | .aGuestCpuIdExt resb 16*10
|
|---|
| 426 | .aGuestCpuIdCentaur resb 16*4
|
|---|
| 427 | .GuestCpuIdDef resb 16
|
|---|
| 428 |
|
|---|
| 429 | ; CPUMCTX debug stuff...
|
|---|
| 430 | .GuestEntry resb 1056
|
|---|
| 431 |
|
|---|
| 432 | endstruc
|
|---|
| 433 |
|
|---|
