DBGFDisas.cpp@ 10321

Last change on this file since 10321 was 9846, checked in by vboxsync, 16 years ago
Disassembly update for flat addresses & 64 bits mode
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 20.5 KB

Line
1	/* $Id: DBGFDisas.cpp 9846 2008-06-20 10:04:29Z vboxsync $ */
2	/** @file
3	* VMM DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DBGF
26	#include <VBox/dbgf.h>
27	#include <VBox/selm.h>
28	#include <VBox/mm.h>
29	#include <VBox/pgm.h>
30	#include <VBox/cpum.h>
31	#include "DBGFInternal.h"
32	#include <VBox/dis.h>
33	#include <VBox/err.h>
34	#include <VBox/param.h>
35
36	#include <VBox/log.h>
37	#include <iprt/assert.h>
38	#include <iprt/string.h>
39	#include <iprt/alloca.h>
40	#include <iprt/ctype.h>
41
42
43	/*******************************************************************************
44	* Internal Functions *
45	*******************************************************************************/
46	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR pSrc, uint8_t pDest, uint32_t size, void pvUserdata);
47
48
49	/**
50	* Structure used when disassembling and instructions in DBGF.
51	* This is used so the reader function can get the stuff it needs.
52	*/
53	typedef struct
54	{
55	/** The core structure. */
56	DISCPUSTATE Cpu;
57	/** The VM handle. */
58	PVM pVM;
59	/** Pointer to the first byte in the segemnt. */
60	RTGCUINTPTR GCPtrSegBase;
61	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
62	RTGCUINTPTR GCPtrSegEnd;
63	/** The size of the segment minus 1. */
64	RTGCUINTPTR cbSegLimit;
65	/** The guest paging mode. */
66	PGMMODE enmMode;
67	/** Pointer to the current page - HC Ptr. */
68	void const *pvPageHC;
69	/** Pointer to the current page - GC Ptr. */
70	RTGCPTR pvPageGC;
71	/** Pointer to the next instruction (relative to GCPtrSegBase). */
72	RTGCUINTPTR GCPtrNext;
73	/** The lock information that PGMPhysReleasePageMappingLock needs. */
74	PGMPAGEMAPLOCK PageMapLock;
75	/** Whether the PageMapLock is valid or not. */
76	bool fLocked;
77	/** 64 bits mode or not. */
78	bool f64Bits;
79	} DBGFDISASSTATE, *PDBGFDISASSTATE;
80
81
82
83	/**
84	* Calls the dissassembler with the proper reader functions and such for disa
85	*
86	* @returns VBox status code.
87	* @param pVM VM handle
88	* @param pSelInfo The selector info.
89	* @param enmMode The guest paging mode.
90	* @param GCPtr The GC pointer (selector offset).
91	* @param pState The disas CPU state.
92	*/
93	static int dbgfR3DisasInstrFirst(PVM pVM, PSELMSELINFO pSelInfo, PGMMODE enmMode, RTGCPTR GCPtr, PDBGFDISASSTATE pState)
94	{
95	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
96	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
97	pState->cbSegLimit = pSelInfo->cbLimit;
98	pState->enmMode = enmMode;
99	pState->pvPageGC = 0;
100	pState->pvPageHC = NULL;
101	pState->pVM = pVM;
102	pState->fLocked = false;
103	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->Raw.Gen.u1Long;
104	Assert((uintptr_t)GCPtr == GCPtr);
105	uint32_t cbInstr;
106	int rc = DISCoreOneEx(GCPtr,
107	pState->f64Bits
108	? CPUMODE_64BIT
109	: pSelInfo->Raw.Gen.u1DefBig
110	? CPUMODE_32BIT
111	: CPUMODE_16BIT,
112	dbgfR3DisasInstrRead,
113	&pState->Cpu,
114	&pState->Cpu,
115	&cbInstr);
116	if (VBOX_SUCCESS(rc))
117	{
118	pState->GCPtrNext = GCPtr + cbInstr;
119	return VINF_SUCCESS;
120	}
121
122	/* cleanup */
123	if (pState->fLocked)
124	{
125	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
126	pState->fLocked = false;
127	}
128	return rc;
129	}
130
131
132	#if 0
133	/**
134	* Calls the dissassembler for disassembling the next instruction.
135	*
136	* @returns VBox status code.
137	* @param pState The disas CPU state.
138	*/
139	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
140	{
141	uint32_t cbInstr;
142	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
143	if (VBOX_SUCCESS(rc))
144	{
145	pState->GCPtrNext = GCPtr + cbInstr;
146	return VINF_SUCCESS;
147	}
148	return rc;
149	}
150	#endif
151
152
153	/**
154	* Done with the dissassembler state, free associated resources.
155	*
156	* @param pState The disas CPU state ++.
157	*/
158	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
159	{
160	if (pState->fLocked)
161	{
162	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
163	pState->fLocked = false;
164	}
165	}
166
167
168	/**
169	* Instruction reader.
170	*
171	* @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
172	* @param PtrSrc Address to read from.
173	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
174	* @param pu8Dst Where to store the bytes.
175	* @param cbRead Number of bytes to read.
176	* @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
177	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
178	*/
179	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, uint32_t cbRead, void pvDisCpu)
180	{
181	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pvDisCpu;
182	Assert(cbRead > 0);
183	for (;;)
184	{
185	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
186
187	/* Need to update the page translation? */
188	if ( !pState->pvPageHC
189	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
190	{
191	int rc = VINF_SUCCESS;
192
193	/* translate the address */
194	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
195	if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
196	{
197	pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
198	if (!pState->pvPageHC)
199	rc = VERR_INVALID_POINTER;
200	}
201	else
202	{
203	if (pState->fLocked)
204	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
205
206	if (pState->enmMode <= PGMMODE_PROTECTED)
207	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
208	else
209	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
210	pState->fLocked = RT_SUCCESS_NP(rc);
211	}
212	if (VBOX_FAILURE(rc))
213	{
214	pState->pvPageHC = NULL;
215	return rc;
216	}
217	}
218
219	/* check the segemnt limit */
220	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
221	return VERR_OUT_OF_SELECTOR_BOUNDS;
222
223	/* calc how much we can read */
224	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
225	if (!pState->f64Bits)
226	{
227	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
228	if (cb > cbSeg && cbSeg)
229	cb = cbSeg;
230	}
231	if (cb > cbRead)
232	cb = cbRead;
233
234	/* read and advance */
235	memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
236	cbRead -= cb;
237	if (!cbRead)
238	return VINF_SUCCESS;
239	pu8Dst += cb;
240	PtrSrc += cb;
241	}
242	}
243
244
245	/**
246	* @copydoc FNDISGETSYMBOL
247	*/
248	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
249	{
250	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pCpu;
251	PCSELMSELINFO pSelInfo = (PCSELMSELINFO)pvUser;
252	DBGFSYMBOL Sym;
253	RTGCINTPTR off;
254	int rc;
255
256	if (DIS_FMT_SEL_IS_REG(u32Sel))
257	{
258	if (DIS_FMT_SEL_GET_REG(u32Sel) == DIS_SELREG_CS)
259	rc = DBGFR3SymbolByAddr(pState->pVM, uAddress + pSelInfo->GCPtrBase, &off, &Sym);
260	else
261	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
262	}
263	else
264	{
265	if (pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
266	rc = DBGFR3SymbolByAddr(pState->pVM, uAddress + pSelInfo->GCPtrBase, &off, &Sym);
267	else
268	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
269	}
270
271	if (RT_SUCCESS(rc))
272	{
273	size_t cchName = strlen(Sym.szName);
274	if (cchName >= cchBuf)
275	cchName = cchBuf - 1;
276	memcpy(pszBuf, Sym.szName, cchName);
277	pszBuf[cchName] = '\0';
278
279	*poff = off;
280	}
281
282	return rc;
283	}
284
285
286	/**
287	* Disassembles the one instruction according to the specified flags and address.
288	*
289	* @returns VBox status code.
290	* @param pVM VM handle.
291	* @param Sel The code selector. This used to determin the 32/16 bit ness and
292	* calculation of the actual instruction address.
293	* @param GCPtr The code address relative to the base of Sel.
294	* @param fFlags Flags controlling where to start and how to format.
295	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
296	* @param pszOutput Output buffer.
297	* @param cchOutput Size of the output buffer.
298	* @param pcbInstr Where to return the size of the instruction.
299	*/
300	DBGFR3DECL(int) DBGFR3DisasInstrEx(PVM pVM, RTSEL Sel, RTGCPTR GCPtr, unsigned fFlags, char pszOutput, uint32_t cchOutput, uint32_t pcbInstr)
301	{
302	/*
303	* Get the Sel and GCPtr if fFlags requests that.
304	*/
305	PCCPUMCTXCORE pCtxCore = NULL;
306	CPUMSELREGHID *pHiddenSel = NULL;
307	int rc;
308	if (fFlags & (DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_CURRENT_HYPER))
309	{
310	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
311	pCtxCore = CPUMGetGuestCtxCore(pVM);
312	else
313	pCtxCore = CPUMGetHyperCtxCore(pVM);
314	Sel = pCtxCore->cs;
315	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
316	GCPtr = pCtxCore->rip;
317	}
318
319	/*
320	* Read the selector info - assume no stale selectors and nasty stuff like that.
321	* Since the selector flags in the CPUMCTX structures aren't up to date unless
322	* we recently visited REM, we'll not search for the selector there.
323	*/
324	SELMSELINFO SelInfo;
325	const PGMMODE enmMode = PGMGetGuestMode(pVM);
326	bool fRealModeAddress = false;
327
328	if ( pHiddenSel
329	&& CPUMAreHiddenSelRegsValid(pVM))
330	{
331	SelInfo.GCPtrBase = pHiddenSel->u64Base;
332	SelInfo.cbLimit = pHiddenSel->u32Limit;
333	SelInfo.fHyper = false;
334	SelInfo.fRealMode = !!((pCtxCore && pCtxCore->eflags.Bits.u1VM) \|\| enmMode == PGMMODE_REAL);
335	SelInfo.Raw.au32[0] = 0;
336	SelInfo.Raw.au32[1] = 0;
337	SelInfo.Raw.Gen.u16LimitLow = ~0;
338	SelInfo.Raw.Gen.u4LimitHigh = ~0;
339	SelInfo.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
340	SelInfo.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
341	SelInfo.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
342	SelInfo.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
343	SelInfo.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
344	SelInfo.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
345	fRealModeAddress = SelInfo.fRealMode;
346	}
347	else if (Sel == DBGF_SEL_FLAT)
348	{
349	SelInfo.GCPtrBase = 0;
350	SelInfo.cbLimit = ~0;
351	SelInfo.fHyper = false;
352	SelInfo.fRealMode = false;
353	SelInfo.Raw.au32[0] = 0;
354	SelInfo.Raw.au32[1] = 0;
355	SelInfo.Raw.Gen.u16LimitLow = ~0;
356	SelInfo.Raw.Gen.u4LimitHigh = ~0;
357
358	if (CPUMAreHiddenSelRegsValid(pVM))
359	{ /* Assume the current CS defines the execution mode. */
360	pCtxCore = CPUMGetGuestCtxCore(pVM);
361	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
362
363	SelInfo.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
364	SelInfo.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
365	SelInfo.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
366	SelInfo.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
367	SelInfo.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
368	SelInfo.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
369	}
370	else
371	{
372	SelInfo.Raw.Gen.u1Present = 1;
373	SelInfo.Raw.Gen.u1Granularity = 1;
374	SelInfo.Raw.Gen.u1DefBig = 1;
375	SelInfo.Raw.Gen.u1DescType = 1;
376	SelInfo.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
377	}
378	}
379	else if ( !(fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
380	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
381	\|\| enmMode == PGMMODE_REAL) )
382	{ /* V86 mode or real mode - real mode addressing */
383	SelInfo.GCPtrBase = Sel * 16;
384	SelInfo.cbLimit = ~0;
385	SelInfo.fHyper = false;
386	SelInfo.fRealMode = true;
387	SelInfo.Raw.au32[0] = 0;
388	SelInfo.Raw.au32[1] = 0;
389	SelInfo.Raw.Gen.u16LimitLow = ~0;
390	SelInfo.Raw.Gen.u4LimitHigh = ~0;
391	SelInfo.Raw.Gen.u1Present = 1;
392	SelInfo.Raw.Gen.u1Granularity = 1;
393	SelInfo.Raw.Gen.u1DefBig = 0; /* 16 bits */
394	SelInfo.Raw.Gen.u1DescType = 1;
395	SelInfo.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
396	fRealModeAddress = true;
397	}
398	else
399	{
400	rc = SELMR3GetSelectorInfo(pVM, Sel, &SelInfo);
401	if (VBOX_FAILURE(rc))
402	{
403	RTStrPrintf(pszOutput, cchOutput, "Sel=%04x -> %Vrc\n", Sel, rc);
404	return rc;
405	}
406	}
407
408	/*
409	* Disassemble it.
410	*/
411	DBGFDISASSTATE State;
412	rc = dbgfR3DisasInstrFirst(pVM, &SelInfo, enmMode, GCPtr, &State);
413	if (VBOX_FAILURE(rc))
414	{
415	RTStrPrintf(pszOutput, cchOutput, "Disas -> %Vrc\n", rc);
416	return rc;
417	}
418
419	/*
420	* Format it.
421	*/
422	char szBuf[512];
423	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
424	DIS_FMT_FLAGS_RELATIVE_BRANCH,
425	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
426	&SelInfo);
427
428	/*
429	* Print it to the user specified buffer.
430	*/
431	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
432	{
433	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
434	RTStrPrintf(pszOutput, cchOutput, "%s", szBuf);
435	else if (fRealModeAddress)
436	RTStrPrintf(pszOutput, cchOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
437	else if (Sel == DBGF_SEL_FLAT)
438	{
439	if (enmMode >= PGMMODE_AMD64)
440	RTStrPrintf(pszOutput, cchOutput, "%VGv %s", GCPtr, szBuf);
441	else
442	RTStrPrintf(pszOutput, cchOutput, "%VRv %s", (RTRCPTR)GCPtr, szBuf);
443	}
444	else
445	{
446	if (enmMode >= PGMMODE_AMD64)
447	RTStrPrintf(pszOutput, cchOutput, "%04x:%VGv %s", Sel, GCPtr, szBuf);
448	else
449	RTStrPrintf(pszOutput, cchOutput, "%04x:%VRv %s", Sel, (RTRCPTR)GCPtr, szBuf);
450	}
451	}
452	else
453	{
454	uint32_t cbBits = State.Cpu.opsize;
455	uint8_t pau8Bits = (uint8_t )alloca(cbBits);
456	rc = dbgfR3DisasInstrRead(GCPtr, pau8Bits, cbBits, &State);
457	AssertRC(rc);
458	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
459	RTStrPrintf(pszOutput, cchOutput, "%.Vhxs%s %s",
460	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
461	szBuf);
462	else if (fRealModeAddress)
463	RTStrPrintf(pszOutput, cchOutput, "%04x:%04x %.Vhxs%s %s",
464	Sel, (unsigned)GCPtr,
465	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
466	szBuf);
467	else if (Sel == DBGF_SEL_FLAT)
468	{
469	if (enmMode >= PGMMODE_AMD64)
470	RTStrPrintf(pszOutput, cchOutput, "%VGv %.Vhxs%s %s",
471	GCPtr,
472	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
473	szBuf);
474	else
475	RTStrPrintf(pszOutput, cchOutput, "%VRv %.Vhxs%s %s",
476	(RTRCPTR)GCPtr,
477	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
478	szBuf);
479	}
480	else
481	{
482	if (enmMode >= PGMMODE_AMD64)
483	RTStrPrintf(pszOutput, cchOutput, "%04x:%VGv %.Vhxs%s %s",
484	Sel, GCPtr,
485	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
486	szBuf);
487	else
488	RTStrPrintf(pszOutput, cchOutput, "%04x:%VRv %.Vhxs%s %s",
489	Sel, (RTRCPTR)GCPtr,
490	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
491	szBuf);
492	}
493	}
494
495	if (pcbInstr)
496	*pcbInstr = State.Cpu.opsize;
497
498	dbgfR3DisasInstrDone(&State);
499	return VINF_SUCCESS;
500	}
501
502
503	/**
504	* Disassembles an instruction.
505	* Addresses will be tried resolved to symbols
506	*
507	* @returns VBox status code.
508	* @param pVM VM handle.
509	* @param Sel The code selector. This used to determin the 32/16 bit ness and
510	* calculation of the actual instruction address.
511	* @param GCPtr The code address relative to the base of Sel.
512	* @param pszOutput Output buffer.
513	* @param cchOutput Size of the output buffer.
514	*/
515	DBGFR3DECL(int) DBGFR3DisasInstr(PVM pVM, RTSEL Sel, RTGCPTR GCPtr, char *pszOutput, uint32_t cchOutput)
516	{
517	return DBGFR3DisasInstrEx(pVM, Sel, GCPtr, 0, pszOutput, cchOutput, NULL);
518	}
519
520
521	/**
522	* Disassembles the current guest context instruction.
523	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
524	*
525	* @returns VBox status code.
526	* @param pVM VM handle.
527	* @param pszOutput Output buffer.
528	* @param cchOutput Size of the output buffer.
529	*/
530	DBGFR3DECL(int) DBGFR3DisasInstrCurrent(PVM pVM, char *pszOutput, uint32_t cchOutput)
531	{
532	return DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_GUEST, pszOutput, cchOutput, NULL);
533	}
534
535
536	/**
537	* Disassembles the current guest context instruction and writes it to the log.
538	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
539	*
540	* @returns VBox status code.
541	* @param pVM VM handle.
542	* @param pszPrefix Short prefix string to the dissassembly string. (optional)
543	*/
544	DBGFR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVM pVM, const char *pszPrefix)
545	{
546	char szBuf[256];
547	szBuf[0] = '\0';
548	int rc = DBGFR3DisasInstrCurrent(pVM, &szBuf[0], sizeof(szBuf));
549	if (VBOX_FAILURE(rc))
550	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Vrc\n", rc);
551	if (pszPrefix && *pszPrefix)
552	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
553	else
554	RTLogPrintf("%s\n", szBuf);
555	return rc;
556	}
557
558
559
560	/**
561	* Disassembles the specified guest context instruction and writes it to the log.
562	* Addresses will be attempted resolved to symbols.
563	*
564	* @returns VBox status code.
565	* @param pVM VM handle.
566	* @param Sel The code selector. This used to determin the 32/16 bit-ness and
567	* calculation of the actual instruction address.
568	* @param GCPtr The code address relative to the base of Sel.
569	*/
570	DBGFR3DECL(int) DBGFR3DisasInstrLogInternal(PVM pVM, RTSEL Sel, RTGCPTR GCPtr)
571	{
572	char szBuf[256];
573	szBuf[0] = '\0';
574	int rc = DBGFR3DisasInstr(pVM, Sel, GCPtr, &szBuf[0], sizeof(szBuf));
575	if (VBOX_FAILURE(rc))
576	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Vrc\n", Sel, GCPtr, rc);
577	RTLogPrintf("%s\n", szBuf);
578	return rc;
579	}
580

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source: vbox/trunk/src/VBox/VMM/DBGFDisas.cpp@ 10321

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