DBGFDisas.cpp@ 19294

Last change on this file since 19294 was 19294, checked in by vboxsync, 16 years ago
DBGFDisas.cpp: overlooked one SMP todo.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 22.8 KB

Line
1	/* $Id: DBGFDisas.cpp 19294 2009-05-01 16:18:59Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DBGF
26	#include <VBox/dbgf.h>
27	#include <VBox/selm.h>
28	#include <VBox/mm.h>
29	#include <VBox/pgm.h>
30	#include <VBox/cpum.h>
31	#include "DBGFInternal.h"
32	#include <VBox/dis.h>
33	#include <VBox/err.h>
34	#include <VBox/param.h>
35	#include <VBox/vm.h>
36
37	#include <VBox/log.h>
38	#include <iprt/assert.h>
39	#include <iprt/string.h>
40	#include <iprt/alloca.h>
41	#include <iprt/ctype.h>
42
43
44	/*******************************************************************************
45	* Structures and Typedefs *
46	*******************************************************************************/
47	/**
48	* Structure used when disassembling and instructions in DBGF.
49	* This is used so the reader function can get the stuff it needs.
50	*/
51	typedef struct
52	{
53	/** The core structure. */
54	DISCPUSTATE Cpu;
55	/** The VM handle. */
56	PVM pVM;
57	/** The VMCPU handle. */
58	PVMCPU pVCpu;
59	/** Pointer to the first byte in the segemnt. */
60	RTGCUINTPTR GCPtrSegBase;
61	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
62	RTGCUINTPTR GCPtrSegEnd;
63	/** The size of the segment minus 1. */
64	RTGCUINTPTR cbSegLimit;
65	/** The guest paging mode. */
66	PGMMODE enmMode;
67	/** Pointer to the current page - R3 Ptr. */
68	void const *pvPageR3;
69	/** Pointer to the current page - GC Ptr. */
70	RTGCPTR pvPageGC;
71	/** Pointer to the next instruction (relative to GCPtrSegBase). */
72	RTGCUINTPTR GCPtrNext;
73	/** The lock information that PGMPhysReleasePageMappingLock needs. */
74	PGMPAGEMAPLOCK PageMapLock;
75	/** Whether the PageMapLock is valid or not. */
76	bool fLocked;
77	/** 64 bits mode or not. */
78	bool f64Bits;
79	} DBGFDISASSTATE, *PDBGFDISASSTATE;
80
81
82	/*******************************************************************************
83	* Internal Functions *
84	*******************************************************************************/
85	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR pSrc, uint8_t pDest, uint32_t size, void pvUserdata);
86
87
88
89	/**
90	* Calls the dissassembler with the proper reader functions and such for disa
91	*
92	* @returns VBox status code.
93	* @param pVM VM handle
94	* @param pVCpu VMCPU handle
95	* @param pSelInfo The selector info.
96	* @param enmMode The guest paging mode.
97	* @param GCPtr The GC pointer (selector offset).
98	* @param pState The disas CPU state.
99	*/
100	static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PSELMSELINFO pSelInfo, PGMMODE enmMode, RTGCPTR GCPtr, PDBGFDISASSTATE pState)
101	{
102	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
103	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
104	pState->cbSegLimit = pSelInfo->cbLimit;
105	pState->enmMode = enmMode;
106	pState->pvPageGC = 0;
107	pState->pvPageR3 = NULL;
108	pState->pVM = pVM;
109	pState->pVCpu = pVCpu;
110	pState->fLocked = false;
111	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->Raw.Gen.u1Long;
112	uint32_t cbInstr;
113	int rc = DISCoreOneEx(GCPtr,
114	pState->f64Bits
115	? CPUMODE_64BIT
116	: pSelInfo->Raw.Gen.u1DefBig
117	? CPUMODE_32BIT
118	: CPUMODE_16BIT,
119	dbgfR3DisasInstrRead,
120	&pState->Cpu,
121	&pState->Cpu,
122	&cbInstr);
123	if (RT_SUCCESS(rc))
124	{
125	pState->GCPtrNext = GCPtr + cbInstr;
126	return VINF_SUCCESS;
127	}
128
129	/* cleanup */
130	if (pState->fLocked)
131	{
132	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
133	pState->fLocked = false;
134	}
135	return rc;
136	}
137
138
139	#if 0
140	/**
141	* Calls the dissassembler for disassembling the next instruction.
142	*
143	* @returns VBox status code.
144	* @param pState The disas CPU state.
145	*/
146	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
147	{
148	uint32_t cbInstr;
149	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
150	if (RT_SUCCESS(rc))
151	{
152	pState->GCPtrNext = GCPtr + cbInstr;
153	return VINF_SUCCESS;
154	}
155	return rc;
156	}
157	#endif
158
159
160	/**
161	* Done with the dissassembler state, free associated resources.
162	*
163	* @param pState The disas CPU state ++.
164	*/
165	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
166	{
167	if (pState->fLocked)
168	{
169	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
170	pState->fLocked = false;
171	}
172	}
173
174
175	/**
176	* Instruction reader.
177	*
178	* @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
179	* @param PtrSrc Address to read from.
180	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
181	* @param pu8Dst Where to store the bytes.
182	* @param cbRead Number of bytes to read.
183	* @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
184	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
185	*/
186	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, uint32_t cbRead, void pvDisCpu)
187	{
188	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pvDisCpu;
189	Assert(cbRead > 0);
190	for (;;)
191	{
192	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
193
194	/* Need to update the page translation? */
195	if ( !pState->pvPageR3
196	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
197	{
198	int rc = VINF_SUCCESS;
199
200	/* translate the address */
201	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
202	if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
203	{
204	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
205	if (!pState->pvPageR3)
206	rc = VERR_INVALID_POINTER;
207	}
208	else
209	{
210	if (pState->fLocked)
211	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
212
213	if (pState->enmMode <= PGMMODE_PROTECTED)
214	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
215	else
216	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
217	pState->fLocked = RT_SUCCESS_NP(rc);
218	}
219	if (RT_FAILURE(rc))
220	{
221	pState->pvPageR3 = NULL;
222	return rc;
223	}
224	}
225
226	/* check the segemnt limit */
227	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
228	return VERR_OUT_OF_SELECTOR_BOUNDS;
229
230	/* calc how much we can read */
231	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
232	if (!pState->f64Bits)
233	{
234	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
235	if (cb > cbSeg && cbSeg)
236	cb = cbSeg;
237	}
238	if (cb > cbRead)
239	cb = cbRead;
240
241	/* read and advance */
242	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
243	cbRead -= cb;
244	if (!cbRead)
245	return VINF_SUCCESS;
246	pu8Dst += cb;
247	PtrSrc += cb;
248	}
249	}
250
251
252	/**
253	* @copydoc FNDISGETSYMBOL
254	*/
255	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
256	{
257	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pCpu;
258	PCSELMSELINFO pSelInfo = (PCSELMSELINFO)pvUser;
259	DBGFSYMBOL Sym;
260	RTGCINTPTR off;
261	int rc;
262
263	if (DIS_FMT_SEL_IS_REG(u32Sel))
264	{
265	if (DIS_FMT_SEL_GET_REG(u32Sel) == DIS_SELREG_CS)
266	rc = DBGFR3SymbolByAddr(pState->pVM, uAddress + pSelInfo->GCPtrBase, &off, &Sym);
267	else
268	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
269	}
270	else
271	{
272	if (pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
273	rc = DBGFR3SymbolByAddr(pState->pVM, uAddress + pSelInfo->GCPtrBase, &off, &Sym);
274	else
275	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
276	}
277
278	if (RT_SUCCESS(rc))
279	{
280	size_t cchName = strlen(Sym.szName);
281	if (cchName >= cchBuf)
282	cchName = cchBuf - 1;
283	memcpy(pszBuf, Sym.szName, cchName);
284	pszBuf[cchName] = '\0';
285
286	*poff = off;
287	}
288
289	return rc;
290	}
291
292
293	/**
294	* Disassembles the one instruction according to the specified flags and
295	* address, internal worker executing on the EMT of the specified virtual CPU.
296	*
297	* @returns VBox status code.
298	* @param pVM The VM handle.
299	* @param pVCpu The virtual CPU handle.
300	* @param Sel The code selector. This used to determin the 32/16 bit ness and
301	* calculation of the actual instruction address.
302	* @param pGCPtr Pointer to the variable holding the code address
303	* relative to the base of Sel.
304	* @param fFlags Flags controlling where to start and how to format.
305	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
306	* @param pszOutput Output buffer.
307	* @param cchOutput Size of the output buffer.
308	* @param pcbInstr Where to return the size of the instruction.
309	*/
310	static DECLCALLBACK(int)
311	dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, unsigned fFlags,
312	char pszOutput, uint32_t cchOutput, uint32_t pcbInstr)
313	{
314	VMCPU_ASSERT_EMT(pVCpu);
315	RTGCPTR GCPtr = *pGCPtr;
316
317	/*
318	* Get the Sel and GCPtr if fFlags requests that.
319	*/
320	PCCPUMCTXCORE pCtxCore = NULL;
321	CPUMSELREGHID *pHiddenSel = NULL;
322	int rc;
323	if (fFlags & (DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_CURRENT_HYPER))
324	{
325	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
326	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
327	else
328	pCtxCore = CPUMGetHyperCtxCore(pVCpu);
329	Sel = pCtxCore->cs;
330	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
331	GCPtr = pCtxCore->rip;
332	}
333
334	/*
335	* Read the selector info - assume no stale selectors and nasty stuff like that.
336	* Since the selector flags in the CPUMCTX structures aren't up to date unless
337	* we recently visited REM, we'll not search for the selector there.
338	*/
339	SELMSELINFO SelInfo;
340	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
341	bool fRealModeAddress = false;
342
343	if ( pHiddenSel
344	&& CPUMAreHiddenSelRegsValid(pVM))
345	{
346	SelInfo.GCPtrBase = pHiddenSel->u64Base;
347	SelInfo.cbLimit = pHiddenSel->u32Limit;
348	SelInfo.fHyper = false;
349	SelInfo.fRealMode = !!((pCtxCore && pCtxCore->eflags.Bits.u1VM) \|\| enmMode == PGMMODE_REAL);
350	SelInfo.Raw.au32[0] = 0;
351	SelInfo.Raw.au32[1] = 0;
352	SelInfo.Raw.Gen.u16LimitLow = 0xffff;
353	SelInfo.Raw.Gen.u4LimitHigh = 0xf;
354	SelInfo.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
355	SelInfo.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
356	SelInfo.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
357	SelInfo.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
358	SelInfo.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
359	SelInfo.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
360	fRealModeAddress = SelInfo.fRealMode;
361	}
362	else if (Sel == DBGF_SEL_FLAT)
363	{
364	SelInfo.GCPtrBase = 0;
365	SelInfo.cbLimit = ~0;
366	SelInfo.fHyper = false;
367	SelInfo.fRealMode = false;
368	SelInfo.Raw.au32[0] = 0;
369	SelInfo.Raw.au32[1] = 0;
370	SelInfo.Raw.Gen.u16LimitLow = 0xffff;
371	SelInfo.Raw.Gen.u4LimitHigh = 0xf;
372
373	if (CPUMAreHiddenSelRegsValid(pVM))
374	{ /* Assume the current CS defines the execution mode. */
375	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
376	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
377
378	SelInfo.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
379	SelInfo.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
380	SelInfo.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
381	SelInfo.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
382	SelInfo.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
383	SelInfo.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
384	}
385	else
386	{
387	SelInfo.Raw.Gen.u1Present = 1;
388	SelInfo.Raw.Gen.u1Granularity = 1;
389	SelInfo.Raw.Gen.u1DefBig = 1;
390	SelInfo.Raw.Gen.u1DescType = 1;
391	SelInfo.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
392	}
393	}
394	else if ( !(fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
395	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
396	\|\| enmMode == PGMMODE_REAL) )
397	{ /* V86 mode or real mode - real mode addressing */
398	SelInfo.GCPtrBase = Sel * 16;
399	SelInfo.cbLimit = ~0;
400	SelInfo.fHyper = false;
401	SelInfo.fRealMode = true;
402	SelInfo.Raw.au32[0] = 0;
403	SelInfo.Raw.au32[1] = 0;
404	SelInfo.Raw.Gen.u16LimitLow = 0xffff;
405	SelInfo.Raw.Gen.u4LimitHigh = 0xf;
406	SelInfo.Raw.Gen.u1Present = 1;
407	SelInfo.Raw.Gen.u1Granularity = 1;
408	SelInfo.Raw.Gen.u1DefBig = 0; /* 16 bits */
409	SelInfo.Raw.Gen.u1DescType = 1;
410	SelInfo.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
411	fRealModeAddress = true;
412	}
413	else
414	{
415	rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
416	if (RT_FAILURE(rc))
417	{
418	RTStrPrintf(pszOutput, cchOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
419	return rc;
420	}
421	}
422
423	/*
424	* Disassemble it.
425	*/
426	DBGFDISASSTATE State;
427	rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, &State);
428	if (RT_FAILURE(rc))
429	{
430	RTStrPrintf(pszOutput, cchOutput, "Disas -> %Rrc\n", rc);
431	return rc;
432	}
433
434	/*
435	* Format it.
436	*/
437	char szBuf[512];
438	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
439	DIS_FMT_FLAGS_RELATIVE_BRANCH,
440	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
441	&SelInfo);
442
443	/*
444	* Print it to the user specified buffer.
445	*/
446	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
447	{
448	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
449	RTStrPrintf(pszOutput, cchOutput, "%s", szBuf);
450	else if (fRealModeAddress)
451	RTStrPrintf(pszOutput, cchOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
452	else if (Sel == DBGF_SEL_FLAT)
453	{
454	if (enmMode >= PGMMODE_AMD64)
455	RTStrPrintf(pszOutput, cchOutput, "%RGv %s", GCPtr, szBuf);
456	else
457	RTStrPrintf(pszOutput, cchOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
458	}
459	else
460	{
461	if (enmMode >= PGMMODE_AMD64)
462	RTStrPrintf(pszOutput, cchOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
463	else
464	RTStrPrintf(pszOutput, cchOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
465	}
466	}
467	else
468	{
469	uint32_t cbBits = State.Cpu.opsize;
470	uint8_t pau8Bits = (uint8_t )alloca(cbBits);
471	rc = dbgfR3DisasInstrRead(GCPtr, pau8Bits, cbBits, &State);
472	AssertRC(rc);
473	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
474	RTStrPrintf(pszOutput, cchOutput, "%.Rhxs%s %s",
475	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
476	szBuf);
477	else if (fRealModeAddress)
478	RTStrPrintf(pszOutput, cchOutput, "%04x:%04x %.Rhxs%s %s",
479	Sel, (unsigned)GCPtr,
480	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
481	szBuf);
482	else if (Sel == DBGF_SEL_FLAT)
483	{
484	if (enmMode >= PGMMODE_AMD64)
485	RTStrPrintf(pszOutput, cchOutput, "%RGv %.Rhxs%s %s",
486	GCPtr,
487	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
488	szBuf);
489	else
490	RTStrPrintf(pszOutput, cchOutput, "%08RX32 %.Rhxs%s %s",
491	(uint32_t)GCPtr,
492	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
493	szBuf);
494	}
495	else
496	{
497	if (enmMode >= PGMMODE_AMD64)
498	RTStrPrintf(pszOutput, cchOutput, "%04x:%RGv %.Rhxs%s %s",
499	Sel, GCPtr,
500	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
501	szBuf);
502	else
503	RTStrPrintf(pszOutput, cchOutput, "%04x:%08RX32 %.Rhxs%s %s",
504	Sel, (uint32_t)GCPtr,
505	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
506	szBuf);
507	}
508	}
509
510	if (pcbInstr)
511	*pcbInstr = State.Cpu.opsize;
512
513	dbgfR3DisasInstrDone(&State);
514	return VINF_SUCCESS;
515	}
516
517
518	/**
519	* Disassembles the one instruction according to the specified flags and address.
520	*
521	* @returns VBox status code.
522	* @param pVM VM handle.
523	* @param idCpu The ID of virtual CPU.
524	* @param Sel The code selector. This used to determin the 32/16 bit ness and
525	* calculation of the actual instruction address.
526	* @param GCPtr The code address relative to the base of Sel.
527	* @param fFlags Flags controlling where to start and how to format.
528	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
529	* @param pszOutput Output buffer.
530	* @param cchOutput Size of the output buffer.
531	* @param pcbInstr Where to return the size of the instruction.
532	*
533	* @remarks May have to switch to the EMT of the virtual CPU in order to do
534	* address conversion.
535	*/
536	VMMR3DECL(int) DBGFR3DisasInstrEx(PVM pVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, unsigned fFlags,
537	char pszOutput, uint32_t cchOutput, uint32_t pcbInstr)
538	{
539	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
540	AssertReturn(idCpu < pVM->cCPUs, VERR_INVALID_CPU_ID);
541
542	/*
543	* Optimize the common case where we're called on the EMT of idCpu since
544	* we're using this all the time when logging.
545	*/
546	int rc;
547	PVMCPU pVCpu = VMMGetCpu(pVM);
548	if ( pVCpu
549	&& pVCpu->idCpu == idCpu)
550	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cchOutput, pcbInstr);
551	else
552	{
553	PVMREQ pReq = NULL;
554	rc = VMR3ReqCall(pVM, VMREQDEST_FROM_ID(idCpu), &pReq, RT_INDEFINITE_WAIT,
555	(PFNRT)dbgfR3DisasInstrExOnVCpu, 8,
556	pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cchOutput, pcbInstr);
557	if (RT_SUCCESS(rc))
558	{
559	rc = pReq->iStatus;
560	VMR3ReqFree(pReq);
561	}
562	}
563	return rc;
564	}
565
566
567	/**
568	* Disassembles the current guest context instruction.
569	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
570	*
571	* @returns VBox status code.
572	* @param pVM VM handle.
573	* @param pszOutput Output buffer.
574	* @param cchOutput Size of the output buffer.
575	*/
576	VMMR3DECL(int) DBGFR3DisasInstrCurrent(PVM pVM, char *pszOutput, uint32_t cchOutput)
577	{
578	*pszOutput = '\0';
579	PVMCPU pVCpu = VMMGetCpu(pVM);
580	AssertReturn(pVCpu, VERR_INVALID_CONTEXT);
581	return DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, 0, 0, DBGF_DISAS_FLAGS_CURRENT_GUEST,
582	pszOutput, cchOutput, NULL);
583	}
584
585
586	/**
587	* Disassembles the current guest context instruction and writes it to the log.
588	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
589	*
590	* @returns VBox status code.
591	* @param pVM VM handle.
592	* @param pszPrefix Short prefix string to the dissassembly string. (optional)
593	*/
594	VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVM pVM, const char *pszPrefix)
595	{
596	char szBuf[256];
597	szBuf[0] = '\0';
598	int rc = DBGFR3DisasInstrCurrent(pVM, &szBuf[0], sizeof(szBuf));
599	if (RT_FAILURE(rc))
600	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
601	if (pszPrefix && *pszPrefix)
602	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
603	else
604	RTLogPrintf("%s\n", szBuf);
605	return rc;
606	}
607
608
609
610	/**
611	* Disassembles the specified guest context instruction and writes it to the log.
612	* Addresses will be attempted resolved to symbols.
613	*
614	* @returns VBox status code.
615	* @param pVM VM handle.
616	* @param pVCpu The virtual CPU handle, defaults to CPU 0 if NULL.
617	* @param Sel The code selector. This used to determin the 32/16 bit-ness and
618	* calculation of the actual instruction address.
619	* @param GCPtr The code address relative to the base of Sel.
620	*/
621	VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVM pVM, RTSEL Sel, RTGCPTR GCPtr)
622	{
623	PVMCPU pVCpu = VMMGetCpu(pVM);
624	AssertReturn(pVCpu, VERR_INVALID_CONTEXT);
625
626	char szBuf[256];
627	szBuf[0] = '\0';
628	int rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, Sel, GCPtr, 0, &szBuf[0], sizeof(szBuf), NULL);
629	if (RT_FAILURE(rc))
630	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
631	RTLogPrintf("%s\n", szBuf);
632	return rc;
633	}
634

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/DBGFDisas.cpp@ 19294

Download in other formats: