DBGFDisas.cpp@ 30454

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1	/* $Id: DBGFDisas.cpp 30454 2010-06-27 20:00:33Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DBGF
22	#include <VBox/dbgf.h>
23	#include <VBox/selm.h>
24	#include <VBox/mm.h>
25	#include <VBox/pgm.h>
26	#include <VBox/cpum.h>
27	#include "DBGFInternal.h"
28	#include <VBox/dis.h>
29	#include <VBox/err.h>
30	#include <VBox/param.h>
31	#include <VBox/vm.h>
32
33	#include <VBox/log.h>
34	#include <iprt/assert.h>
35	#include <iprt/string.h>
36	#include <iprt/alloca.h>
37	#include <iprt/ctype.h>
38
39
40	/*******************************************************************************
41	* Structures and Typedefs *
42	*******************************************************************************/
43	/**
44	* Structure used when disassembling and instructions in DBGF.
45	* This is used so the reader function can get the stuff it needs.
46	*/
47	typedef struct
48	{
49	/** The core structure. */
50	DISCPUSTATE Cpu;
51	/** The VM handle. */
52	PVM pVM;
53	/** The VMCPU handle. */
54	PVMCPU pVCpu;
55	/** The address space for resolving symbol. */
56	RTDBGAS hAs;
57	/** Pointer to the first byte in the segemnt. */
58	RTGCUINTPTR GCPtrSegBase;
59	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
60	RTGCUINTPTR GCPtrSegEnd;
61	/** The size of the segment minus 1. */
62	RTGCUINTPTR cbSegLimit;
63	/** The guest paging mode. */
64	PGMMODE enmMode;
65	/** Pointer to the current page - R3 Ptr. */
66	void const *pvPageR3;
67	/** Pointer to the current page - GC Ptr. */
68	RTGCPTR pvPageGC;
69	/** Pointer to the next instruction (relative to GCPtrSegBase). */
70	RTGCUINTPTR GCPtrNext;
71	/** The lock information that PGMPhysReleasePageMappingLock needs. */
72	PGMPAGEMAPLOCK PageMapLock;
73	/** Whether the PageMapLock is valid or not. */
74	bool fLocked;
75	/** 64 bits mode or not. */
76	bool f64Bits;
77	} DBGFDISASSTATE, *PDBGFDISASSTATE;
78
79
80	/*******************************************************************************
81	* Internal Functions *
82	*******************************************************************************/
83	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR pSrc, uint8_t pDest, uint32_t size, void pvUserdata);
84
85
86
87	/**
88	* Calls the dissassembler with the proper reader functions and such for disa
89	*
90	* @returns VBox status code.
91	* @param pVM VM handle
92	* @param pVCpu VMCPU handle
93	* @param pSelInfo The selector info.
94	* @param enmMode The guest paging mode.
95	* @param fFlags DBGF_DISAS_FLAGS_XXX.
96	* @param GCPtr The GC pointer (selector offset).
97	* @param pState The disas CPU state.
98	*/
99	static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
100	RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
101	{
102	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
103	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
104	pState->cbSegLimit = pSelInfo->cbLimit;
105	pState->enmMode = enmMode;
106	pState->pvPageGC = 0;
107	pState->pvPageR3 = NULL;
108	pState->hAs = pSelInfo->fFlags & DBGFSELINFO_FLAGS_HYPER /** @todo Deal more explicitly with RC in DBGFR3Disas. /
109	? DBGF_AS_RC_AND_GC_GLOBAL
110	: DBGF_AS_GLOBAL;
111	pState->pVM = pVM;
112	pState->pVCpu = pVCpu;
113	pState->fLocked = false;
114	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
115
116	DISCPUMODE enmCpuMode;
117	switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
118	{
119	default:
120	AssertFailed();
121	case DBGF_DISAS_FLAGS_DEFAULT_MODE:
122	enmCpuMode = pState->f64Bits
123	? CPUMODE_64BIT
124	: pSelInfo->u.Raw.Gen.u1DefBig
125	? CPUMODE_32BIT
126	: CPUMODE_16BIT;
127	break;
128	case DBGF_DISAS_FLAGS_16BIT_MODE:
129	case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
130	enmCpuMode = CPUMODE_16BIT;
131	break;
132	case DBGF_DISAS_FLAGS_32BIT_MODE:
133	enmCpuMode = CPUMODE_32BIT;
134	break;
135	case DBGF_DISAS_FLAGS_64BIT_MODE:
136	enmCpuMode = CPUMODE_64BIT;
137	break;
138	}
139
140	uint32_t cbInstr;
141	int rc = DISCoreOneEx(GCPtr,
142	enmCpuMode,
143	dbgfR3DisasInstrRead,
144	&pState->Cpu,
145	&pState->Cpu,
146	&cbInstr);
147	if (RT_SUCCESS(rc))
148	{
149	pState->GCPtrNext = GCPtr + cbInstr;
150	return VINF_SUCCESS;
151	}
152
153	/* cleanup */
154	if (pState->fLocked)
155	{
156	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
157	pState->fLocked = false;
158	}
159	return rc;
160	}
161
162
163	#if 0
164	/**
165	* Calls the dissassembler for disassembling the next instruction.
166	*
167	* @returns VBox status code.
168	* @param pState The disas CPU state.
169	*/
170	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
171	{
172	uint32_t cbInstr;
173	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
174	if (RT_SUCCESS(rc))
175	{
176	pState->GCPtrNext = GCPtr + cbInstr;
177	return VINF_SUCCESS;
178	}
179	return rc;
180	}
181	#endif
182
183
184	/**
185	* Done with the dissassembler state, free associated resources.
186	*
187	* @param pState The disas CPU state ++.
188	*/
189	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
190	{
191	if (pState->fLocked)
192	{
193	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
194	pState->fLocked = false;
195	}
196	}
197
198
199	/**
200	* Instruction reader.
201	*
202	* @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
203	* @param PtrSrc Address to read from.
204	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
205	* @param pu8Dst Where to store the bytes.
206	* @param cbRead Number of bytes to read.
207	* @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
208	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
209	*/
210	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, uint32_t cbRead, void pvDisCpu)
211	{
212	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pvDisCpu;
213	Assert(cbRead > 0);
214	for (;;)
215	{
216	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
217
218	/* Need to update the page translation? */
219	if ( !pState->pvPageR3
220	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
221	{
222	int rc = VINF_SUCCESS;
223
224	/* translate the address */
225	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
226	if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
227	{
228	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
229	if (!pState->pvPageR3)
230	rc = VERR_INVALID_POINTER;
231	}
232	else
233	{
234	if (pState->fLocked)
235	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
236
237	if (pState->enmMode <= PGMMODE_PROTECTED)
238	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
239	else
240	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
241	pState->fLocked = RT_SUCCESS_NP(rc);
242	}
243	if (RT_FAILURE(rc))
244	{
245	pState->pvPageR3 = NULL;
246	return rc;
247	}
248	}
249
250	/* check the segemnt limit */
251	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
252	return VERR_OUT_OF_SELECTOR_BOUNDS;
253
254	/* calc how much we can read */
255	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
256	if (!pState->f64Bits)
257	{
258	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
259	if (cb > cbSeg && cbSeg)
260	cb = cbSeg;
261	}
262	if (cb > cbRead)
263	cb = cbRead;
264
265	/* read and advance */
266	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
267	cbRead -= cb;
268	if (!cbRead)
269	return VINF_SUCCESS;
270	pu8Dst += cb;
271	PtrSrc += cb;
272	}
273	}
274
275
276	/**
277	* @copydoc FNDISGETSYMBOL
278	*/
279	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
280	{
281	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pCpu;
282	PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
283	DBGFADDRESS Addr;
284	RTDBGSYMBOL Sym;
285	RTGCINTPTR off;
286	int rc;
287
288	if ( DIS_FMT_SEL_IS_REG(u32Sel)
289	? DIS_FMT_SEL_GET_REG(u32Sel) == DIS_SELREG_CS
290	: pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
291	{
292	rc = DBGFR3AddrFromSelInfoOff(pState->pVM, &Addr, pSelInfo, uAddress);
293	if (RT_SUCCESS(rc))
294	rc = DBGFR3AsSymbolByAddr(pState->pVM, pState->hAs, &Addr, &off, &Sym, NULL /phMod/);
295	}
296	else
297	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
298	if (RT_SUCCESS(rc))
299	{
300	size_t cchName = strlen(Sym.szName);
301	if (cchName >= cchBuf)
302	cchName = cchBuf - 1;
303	memcpy(pszBuf, Sym.szName, cchName);
304	pszBuf[cchName] = '\0';
305
306	*poff = off;
307	}
308
309	return rc;
310	}
311
312
313	/**
314	* Disassembles the one instruction according to the specified flags and
315	* address, internal worker executing on the EMT of the specified virtual CPU.
316	*
317	* @returns VBox status code.
318	* @param pVM The VM handle.
319	* @param pVCpu The virtual CPU handle.
320	* @param Sel The code selector. This used to determin the 32/16 bit ness and
321	* calculation of the actual instruction address.
322	* @param pGCPtr Pointer to the variable holding the code address
323	* relative to the base of Sel.
324	* @param fFlags Flags controlling where to start and how to format.
325	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
326	* @param pszOutput Output buffer.
327	* @param cbOutput Size of the output buffer.
328	* @param pcbInstr Where to return the size of the instruction.
329	*/
330	static DECLCALLBACK(int)
331	dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
332	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
333	{
334	VMCPU_ASSERT_EMT(pVCpu);
335	RTGCPTR GCPtr = *pGCPtr;
336
337	/*
338	* Get the Sel and GCPtr if fFlags requests that.
339	*/
340	PCCPUMCTXCORE pCtxCore = NULL;
341	PCPUMSELREGHID pHiddenSel = NULL;
342	int rc;
343	if (fFlags & (DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_CURRENT_HYPER))
344	{
345	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
346	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
347	else
348	pCtxCore = CPUMGetHyperCtxCore(pVCpu);
349	Sel = pCtxCore->cs;
350	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
351	GCPtr = pCtxCore->rip;
352	}
353
354	/*
355	* Read the selector info - assume no stale selectors and nasty stuff like that.
356	* Since the selector flags in the CPUMCTX structures aren't up to date unless
357	* we recently visited REM, we'll not search for the selector there.
358	*/
359	DBGFSELINFO SelInfo;
360	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
361	bool fRealModeAddress = false;
362
363	if ( pHiddenSel
364	&& CPUMAreHiddenSelRegsValid(pVCpu))
365	{
366	SelInfo.Sel = Sel;
367	SelInfo.SelGate = 0;
368	SelInfo.GCPtrBase = pHiddenSel->u64Base;
369	SelInfo.cbLimit = pHiddenSel->u32Limit;
370	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
371	? DBGFSELINFO_FLAGS_LONG_MODE
372	: enmMode != PGMMODE_REAL && (!pCtxCore \|\| !pCtxCore->eflags.Bits.u1VM)
373	? DBGFSELINFO_FLAGS_PROT_MODE
374	: DBGFSELINFO_FLAGS_REAL_MODE;
375
376	SelInfo.u.Raw.au32[0] = 0;
377	SelInfo.u.Raw.au32[1] = 0;
378	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
379	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
380	SelInfo.u.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
381	SelInfo.u.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
382	SelInfo.u.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
383	SelInfo.u.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
384	SelInfo.u.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
385	SelInfo.u.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
386	fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
387	}
388	else if (Sel == DBGF_SEL_FLAT)
389	{
390	SelInfo.Sel = Sel;
391	SelInfo.SelGate = 0;
392	SelInfo.GCPtrBase = 0;
393	SelInfo.cbLimit = ~0;
394	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
395	? DBGFSELINFO_FLAGS_LONG_MODE
396	: enmMode != PGMMODE_REAL
397	? DBGFSELINFO_FLAGS_PROT_MODE
398	: DBGFSELINFO_FLAGS_REAL_MODE;
399	SelInfo.u.Raw.au32[0] = 0;
400	SelInfo.u.Raw.au32[1] = 0;
401	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
402	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
403
404	if (CPUMAreHiddenSelRegsValid(pVCpu))
405	{ /* Assume the current CS defines the execution mode. */
406	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
407	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
408
409	SelInfo.u.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
410	SelInfo.u.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
411	SelInfo.u.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
412	SelInfo.u.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
413	SelInfo.u.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
414	SelInfo.u.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
415	}
416	else
417	{
418	SelInfo.u.Raw.Gen.u1Present = 1;
419	SelInfo.u.Raw.Gen.u1Granularity = 1;
420	SelInfo.u.Raw.Gen.u1DefBig = 1;
421	SelInfo.u.Raw.Gen.u1DescType = 1;
422	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
423	}
424	}
425	else if ( !(fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
426	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
427	\|\| enmMode == PGMMODE_REAL
428	\|\| (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE
429	)
430	)
431	{ /* V86 mode or real mode - real mode addressing */
432	SelInfo.Sel = Sel;
433	SelInfo.SelGate = 0;
434	SelInfo.GCPtrBase = Sel * 16;
435	SelInfo.cbLimit = ~0;
436	SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
437	SelInfo.u.Raw.au32[0] = 0;
438	SelInfo.u.Raw.au32[1] = 0;
439	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
440	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
441	SelInfo.u.Raw.Gen.u1Present = 1;
442	SelInfo.u.Raw.Gen.u1Granularity = 1;
443	SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
444	SelInfo.u.Raw.Gen.u1DescType = 1;
445	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
446	fRealModeAddress = true;
447	}
448	else
449	{
450	rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
451	if (RT_FAILURE(rc))
452	{
453	RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
454	return rc;
455	}
456	}
457
458	/*
459	* Disassemble it.
460	*/
461	DBGFDISASSTATE State;
462	rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
463	if (RT_FAILURE(rc))
464	{
465	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
466	return rc;
467	}
468
469	/*
470	* Format it.
471	*/
472	char szBuf[512];
473	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
474	DIS_FMT_FLAGS_RELATIVE_BRANCH,
475	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
476	&SelInfo);
477
478	/*
479	* Print it to the user specified buffer.
480	*/
481	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
482	{
483	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
484	RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
485	else if (fRealModeAddress)
486	RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
487	else if (Sel == DBGF_SEL_FLAT)
488	{
489	if (enmMode >= PGMMODE_AMD64)
490	RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
491	else
492	RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
493	}
494	else
495	{
496	if (enmMode >= PGMMODE_AMD64)
497	RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
498	else
499	RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
500	}
501	}
502	else
503	{
504	uint32_t cbBits = State.Cpu.opsize;
505	uint8_t pau8Bits = (uint8_t )alloca(cbBits);
506	rc = dbgfR3DisasInstrRead(GCPtr, pau8Bits, cbBits, &State);
507	AssertRC(rc);
508	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
509	RTStrPrintf(pszOutput, cbOutput, "%.Rhxs%s %s",
510	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
511	szBuf);
512	else if (fRealModeAddress)
513	RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.Rhxs%s %s",
514	Sel, (unsigned)GCPtr,
515	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
516	szBuf);
517	else if (Sel == DBGF_SEL_FLAT)
518	{
519	if (enmMode >= PGMMODE_AMD64)
520	RTStrPrintf(pszOutput, cbOutput, "%RGv %.Rhxs%s %s",
521	GCPtr,
522	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
523	szBuf);
524	else
525	RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.Rhxs%s %s",
526	(uint32_t)GCPtr,
527	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
528	szBuf);
529	}
530	else
531	{
532	if (enmMode >= PGMMODE_AMD64)
533	RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.Rhxs%s %s",
534	Sel, GCPtr,
535	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
536	szBuf);
537	else
538	RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.Rhxs%s %s",
539	Sel, (uint32_t)GCPtr,
540	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
541	szBuf);
542	}
543	}
544
545	if (pcbInstr)
546	*pcbInstr = State.Cpu.opsize;
547
548	dbgfR3DisasInstrDone(&State);
549	return VINF_SUCCESS;
550	}
551
552
553	/**
554	* Disassembles the one instruction according to the specified flags and address.
555	*
556	* @returns VBox status code.
557	* @param pVM VM handle.
558	* @param idCpu The ID of virtual CPU.
559	* @param Sel The code selector. This used to determin the 32/16 bit ness and
560	* calculation of the actual instruction address.
561	* @param GCPtr The code address relative to the base of Sel.
562	* @param fFlags Flags controlling where to start and how to format.
563	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
564	* @param pszOutput Output buffer. This will always be properly
565	* terminated if @a cbOutput is greater than zero.
566	* @param cbOutput Size of the output buffer.
567	* @param pcbInstr Where to return the size of the instruction.
568	*
569	* @remarks May have to switch to the EMT of the virtual CPU in order to do
570	* address conversion.
571	*/
572	VMMR3DECL(int) DBGFR3DisasInstrEx(PVM pVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
573	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
574	{
575	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
576	*pszOutput = '\0';
577	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
578	AssertReturn(idCpu < pVM->cCpus, VERR_INVALID_CPU_ID);
579	AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
580	AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
581
582	/*
583	* Optimize the common case where we're called on the EMT of idCpu since
584	* we're using this all the time when logging.
585	*/
586	int rc;
587	PVMCPU pVCpu = VMMGetCpu(pVM);
588	if ( pVCpu
589	&& pVCpu->idCpu == idCpu)
590	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
591	else
592	rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 8,
593	pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
594	return rc;
595	}
596
597
598	/**
599	* Disassembles the current guest context instruction.
600	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
601	*
602	* @returns VBox status code.
603	* @param pVCpu VMCPU handle.
604	* @param pszOutput Output buffer. This will always be properly
605	* terminated if @a cbOutput is greater than zero.
606	* @param cbOutput Size of the output buffer.
607	*/
608	VMMR3DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
609	{
610	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
611	*pszOutput = '\0';
612	AssertReturn(pVCpu, VERR_INVALID_CONTEXT);
613	return DBGFR3DisasInstrEx(pVCpu->pVMR3, pVCpu->idCpu, 0, 0,
614	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
615	pszOutput, cbOutput, NULL);
616	}
617
618
619	/**
620	* Disassembles the current guest context instruction and writes it to the log.
621	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
622	*
623	* @returns VBox status code.
624	* @param pVCpu VMCPU handle.
625	* @param pszPrefix Short prefix string to the dissassembly string. (optional)
626	*/
627	VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
628	{
629	char szBuf[256];
630	szBuf[0] = '\0';
631	int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
632	if (RT_FAILURE(rc))
633	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
634	if (pszPrefix && *pszPrefix)
635	RTLogPrintf("%s-CPU%d: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
636	else
637	RTLogPrintf("%s\n", szBuf);
638	return rc;
639	}
640
641
642
643	/**
644	* Disassembles the specified guest context instruction and writes it to the log.
645	* Addresses will be attempted resolved to symbols.
646	*
647	* @returns VBox status code.
648	* @param pVM VM handle.
649	* @param pVCpu The virtual CPU handle, defaults to CPU 0 if NULL.
650	* @param Sel The code selector. This used to determin the 32/16 bit-ness and
651	* calculation of the actual instruction address.
652	* @param GCPtr The code address relative to the base of Sel.
653	*/
654	VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr)
655	{
656	char szBuf[256];
657	int rc = DBGFR3DisasInstrEx(pVCpu->pVMR3, pVCpu->idCpu, Sel, GCPtr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
658	&szBuf[0], sizeof(szBuf), NULL);
659	if (RT_FAILURE(rc))
660	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
661	RTLogPrintf("%s\n", szBuf);
662	return rc;
663	}
664

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source: vbox/trunk/src/VBox/VMM/DBGFDisas.cpp@ 30454

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