| 1 | /* $Id: Docs-RawMode.cpp 80045 2019-07-29 14:38:19Z vboxsync $ */
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| 2 | /** @file
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| 3 | * This file contains the documentation of the raw-mode execution.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2019 Oracle Corporation
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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| 18 |
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| 19 |
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| 20 | /** @page pg_raw Raw-mode Code Execution
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| 21 | *
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| 22 | * VirtualBox 0.0 thru 6.0 implemented a mode of guest code execution that
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| 23 | * allowed executing mostly raw guest code directly the host CPU but without any
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| 24 | * support from VT-x or AMD-V. It was implemented for AMD64, AMD-V and VT-x
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| 25 | * were available (former) or even specified (latter two). This mode was
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| 26 | * removed in 6.1 (code ripped out) as it was mostly unused by that point and
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| 27 | * not worth the effort of maintaining.
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| 28 | *
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| 29 | * A future VirtualBox version may reintroduce a new kind of raw-mode for
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| 30 | * emulating non-x86 architectures, making use of the host MMU to efficiently
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| 31 | * emulate the target MMU. This is just a wild idea at this point.
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| 32 | *
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| 33 | *
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| 34 | * @section sec_old_rawmode Old Raw-mode
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| 35 | *
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| 36 | * Running guest code unmodified on the host CPU is reasonably unproblematic for
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| 37 | * ring-3 code when it runs without IOPL=3. There will be some information
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| 38 | * leaks thru CPUID, a bunch of 286 area unprivileged instructions revealing
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| 39 | * privileged information (like SGDT, SIDT, SLDT, STR, SMSW), and hypervisor
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| 40 | * selectors can probably be identified using VERR, VERW and such instructions.
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| 41 | * However, it generally works fine for half friendly software when the CPUID
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| 42 | * difference between the target and host isn't too big.
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| 43 | *
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| 44 | * Kernel code can be executed on the host CPU too, however it needs to be
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| 45 | * pushed up a ring (guest ring-0 to ring-1, guest ring-1 to ring2) to let the
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| 46 | * hypervisor (VMMRC.rc) be in charge of ring-0. Ring compression causes
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| 47 | * issues when CS or SS are pushed and inspected by the guest, since the values
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| 48 | * will have bit 0 set whereas the guest expects that bit to be cleared. In
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| 49 | * addition there are problematic instructions like POPF and IRET that the guest
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| 50 | * code uses to restore/modify EFLAGS.IF state, however the CPU just silently
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| 51 | * ignores EFLAGS.IF when it isn't running in ring-0 (or with an appropriate
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| 52 | * IOPL), which causes major headache. The SIDT, SGDT, STR, SLDT and SMSW
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| 53 | * instructions also causes problems since they will return information about
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| 54 | * the hypervisor rather than the guest state and cannot be trapped.
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| 55 | *
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| 56 | * So, guest kernel code needed to be scanned (by CSAM) and problematic
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| 57 | * instructions or sequences patched or recompiled (by PATM).
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| 58 | *
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| 59 | * The raw-mode execution operates in a slightly modified guest memory context,
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| 60 | * so memory accesses can be done directly without any checking or masking. The
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| 61 | * modification was to insert the hypervisor in an unused portion of the the
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| 62 | * page tables, making it float around and require it to be relocated when the
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| 63 | * guest mapped code into the area it was occupying.
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| 64 | *
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| 65 | * The old raw-mode code was 32-bit only because its inception predates the
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| 66 | * availability of the AMD64 architecture and the promise of AMD-V and VT-x made
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| 67 | * it unnecessary to do a 64-bit version of the mode. (A long-mode port of the
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| 68 | * raw-mode execution hypvisor could in theory have been used for both 32-bit
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| 69 | * and 64-bit guest, making the relocating unnecessary for 32-bit guests,
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| 70 | * however v8086 mode does not work when the CPU is operating in long-mode made
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| 71 | * it a little less attractive.)
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| 72 | *
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| 73 | *
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| 74 | * @section sec_rawmode_v2 Raw-mode v2
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| 75 | *
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| 76 | * The vision for the reinvention of raw-mode execution is to put it inside
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| 77 | * VT-x/AMD-V and run non-native instruction sets via a recompiler.
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| 78 | *
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| 79 | * The main motivation is TLB emulation using the host MMU. An added benefit is
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| 80 | * would be that the non-native instruction sets would be add-ons put on top of
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| 81 | * the existing x86/AMD64 virtualization product and therefore not require a
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| 82 | * complete separate product build.
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| 83 | *
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| 84 | *
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| 85 | * Outline:
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| 86 | *
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| 87 | * - Plug-in based, so the target architecture specific stuff is mostly in
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| 88 | * separate modules (ring-3, ring-0 (optional) and raw-mode images).
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| 89 | *
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| 90 | * - Only 64-bit mode code (no problem since VirtualBox requires a 64-bit host
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| 91 | * since 6.0). So, not reintroducing structure alignment pain from old RC.
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| 92 | *
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| 93 | * - Map the RC-hypervisor modules as ROM, using the shadowing feature for the
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| 94 | * data sections.
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| 95 | *
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| 96 | * - Use MMIO2-like regions for all the memory that the RC-hypervisor needs,
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| 97 | * all shared with the associated host side plug-in components.
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| 98 | *
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| 99 | * - The ROM and MMIO2 regions does not directly end up in the saved state, the
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| 100 | * state is instead saved by the ring-3 architecture module.
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| 101 | *
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| 102 | * - Device access thru MMIO mappings could be done transparently thru to the
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| 103 | * x86/AMD64 core VMM. It would however be possible to reintroduce the RC
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| 104 | * side device handling, as that will not be removed in the old-RC cleanup.
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| 105 | *
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| 106 | * - Virtual memory managed by the RC-hypervisor, optionally with help of the
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| 107 | * ring-3 and/or ring-0 architecture modules.
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| 108 | *
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| 109 | * - The mapping of the RC modules and memory will probably have to runtime
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| 110 | * relocatable again, like it was in the old RC. Though initially and for
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| 111 | * 32-bit target architectures, we will probably use a fixed mapping.
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| 112 | *
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| 113 | * - Memory accesses must unfortunately be range checked before being issued,
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| 114 | * in order to prevent the guest code from accessing the hypervisor. The
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| 115 | * recompiled code must be able to run, modify state, call ROM code, update
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| 116 | * statistics and such, so we cannot use page table stuff protect the
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| 117 | * hypervisor code & data. (If long mode implement segment limits, we
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| 118 | * could've used that, but it doesn't.)
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| 119 | *
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| 120 | * - The RC-hypervisor will make hypercalls to communicate with the ring-0 and
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| 121 | * ring-3 host code.
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| 122 | *
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| 123 | * - The host side should be able to dig out the current guest state from
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| 124 | * information (think AMD64 unwinding) stored in translation blocks.
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| 125 | *
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| 126 | * - Non-atomic state updates outside TBs could be flagged so the host know
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| 127 | * how to roll the back.
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| 128 | *
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| 129 | * - SMP must be taken into account early on.
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| 130 | *
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| 131 | * - As must existing IEM-based recompiler ideas, preferrably sharing code
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| 132 | * (basically compiling IEM targetting the other architecture).
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| 133 | *
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| 134 | * The actual implementation will depend a lot on which architectures are
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| 135 | * targeted and how they can be mapped onto AMD64/x86. It is possible that
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| 136 | * there are some significan roadblocks preventing us from using the host MMU
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| 137 | * efficiently even. AMD64 is for instance rather low on virtual address space
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| 138 | * compared to several other 64-bit architectures, which means we'll generate a
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| 139 | * lot of \#GPs when the guest tries to access spaced reserved on AMD64. The
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| 140 | * proposed 5-level page tables will help with this, of course, but that need to
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| 141 | * get into silicon and into user computers for it to be really helpful.
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| 142 | *
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| 143 | * One thing that helps a lot is that we don't have to consider 32-bit x86 any
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| 144 | * more, meaning that the recompiler only need to generate 64-bit code and can
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| 145 | * assume having 15-16 GPRs at its disposal.
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| 146 | *
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| 147 | */
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| 148 |
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