VirtualBox

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 33995

Last change on this file since 33995 was 33595, checked in by vboxsync, 14 years ago

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1/* $Id: EM.cpp 33595 2010-10-29 10:35:00Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_em EM - The Execution Monitor / Manager
19 *
20 * The Execution Monitor/Manager is responsible for running the VM, scheduling
21 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22 * Interpreted), and keeping the CPU states in sync. The function
23 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24 * modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
25 * emR3RemExecute).
26 *
27 * The interpreted execution is only used to avoid switching between
28 * raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
29 * The interpretation is thus implemented as part of EM.
30 *
31 * @see grp_em
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_EM
38#include <VBox/em.h>
39#include <VBox/vmm.h>
40#include <VBox/patm.h>
41#include <VBox/csam.h>
42#include <VBox/selm.h>
43#include <VBox/trpm.h>
44#include <VBox/iom.h>
45#include <VBox/dbgf.h>
46#include <VBox/pgm.h>
47#include <VBox/rem.h>
48#include <VBox/tm.h>
49#include <VBox/mm.h>
50#include <VBox/ssm.h>
51#include <VBox/pdmapi.h>
52#include <VBox/pdmcritsect.h>
53#include <VBox/pdmqueue.h>
54#include <VBox/hwaccm.h>
55#include <VBox/patm.h>
56#include "EMInternal.h"
57#include "include/internal/em.h"
58#include <VBox/vm.h>
59#include <VBox/cpumdis.h>
60#include <VBox/dis.h>
61#include <VBox/disopcode.h>
62#include <VBox/dbgf.h>
63
64#include <iprt/asm.h>
65#include <iprt/string.h>
66#include <iprt/stream.h>
67#include <iprt/thread.h>
68
69
70/*******************************************************************************
71* Defined Constants And Macros *
72*******************************************************************************/
73#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
74#define EM_NOTIFY_HWACCM
75#endif
76
77
78/*******************************************************************************
79* Internal Functions *
80*******************************************************************************/
81static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
82static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
83static const char *emR3GetStateName(EMSTATE enmState);
84static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
85static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
86static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
87int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
88
89
90/**
91 * Initializes the EM.
92 *
93 * @returns VBox status code.
94 * @param pVM The VM to operate on.
95 */
96VMMR3DECL(int) EMR3Init(PVM pVM)
97{
98 LogFlow(("EMR3Init\n"));
99 /*
100 * Assert alignment and sizes.
101 */
102 AssertCompileMemberAlignment(VM, em.s, 32);
103 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
104 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
105 AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
106
107 /*
108 * Init the structure.
109 */
110 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
111 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
112 if (RT_FAILURE(rc))
113 pVM->fRawR3Enabled = true;
114 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
115 if (RT_FAILURE(rc))
116 pVM->fRawR0Enabled = true;
117 Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
118
119 /*
120 * Initialize the REM critical section.
121 */
122 rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
123 AssertRCReturn(rc, rc);
124
125 /*
126 * Saved state.
127 */
128 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
129 NULL, NULL, NULL,
130 NULL, emR3Save, NULL,
131 NULL, emR3Load, NULL);
132 if (RT_FAILURE(rc))
133 return rc;
134
135 for (VMCPUID i = 0; i < pVM->cCpus; i++)
136 {
137 PVMCPU pVCpu = &pVM->aCpus[i];
138
139 pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
140
141 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
142 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
143 pVCpu->em.s.fForceRAW = false;
144
145 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
146 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
147 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
148
149 /* Force reset of the time slice. */
150 pVCpu->em.s.u64TimeSliceStart = 0;
151
152# define EM_REG_COUNTER(a, b, c) \
153 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
154 AssertRC(rc);
155
156# define EM_REG_COUNTER_USED(a, b, c) \
157 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
158 AssertRC(rc);
159
160# define EM_REG_PROFILE(a, b, c) \
161 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
162 AssertRC(rc);
163
164# define EM_REG_PROFILE_ADV(a, b, c) \
165 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
166 AssertRC(rc);
167
168 /*
169 * Statistics.
170 */
171#ifdef VBOX_WITH_STATISTICS
172 PEMSTATS pStats;
173 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
174 if (RT_FAILURE(rc))
175 return rc;
176
177 pVCpu->em.s.pStatsR3 = pStats;
178 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
179 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
180
181 EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
182 EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
183
184 EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
185 EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
186
187 EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
188 EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
189 EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
190 EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
191 EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
192 EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
193 EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
194 EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
195 EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
196 EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
197 EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
198 EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
199 EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
200 EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
201 EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
202 EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
203 EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
204 EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
205 EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
206 EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
207 EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
208 EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
209 EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
210 EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
211 EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
212 EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
213 EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
214 EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
215 EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
216 EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
217 EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
218 EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
219 EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
220 EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
221 EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
222 EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
223 EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
224 EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
225 EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
226 EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
227 EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
228 EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
229 EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
230 EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
231 EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
232 EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
233 EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
234 EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
235 EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
236 EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
237 EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
238 EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
239 EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
240 EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
241 EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
242 EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
243 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
244 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
245 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
246 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
247 EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
248 EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
249 EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
250 EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
251 EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
252 EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
253 EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
254 EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
255 EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
256 EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
257 EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
258 EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
259
260 EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
261 EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
262
263 EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
264 EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
265 EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
266 EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
267 EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
268 EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
269 EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
270 EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
271 EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
272 EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
273 EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
274 EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
275 EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
276 EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
277 EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
278 EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
279 EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
280 EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
281 EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
282 EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
283 EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
284 EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
285 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
286 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
287 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
288 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
289 EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
290 EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
291 EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
292 EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
293 EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
294 EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
295 EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
296 EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
297 EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
298 EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
299 EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
300 EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
301 EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
302 EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
303 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
304 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
305 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
306 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
307 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
308 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
309 EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
310 EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
311 EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
312 EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
313
314 EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
315 EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
316 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
317 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
318 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
319 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
320 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
321 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
322 EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
323 EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
324 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
325 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
326 EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
327 EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
328 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
329 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
330 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
331 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
332 EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
333 EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
334 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
335 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
336 EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
337 EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
338 EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
339 EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
340 EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
341 EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
342
343 EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
344 EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
345 EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
346 EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
347
348 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
349 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
350 EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
351 EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
352 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "Number of restarted i/o instructions.");
353 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
354 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
355 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
356 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 read instructions.");
357 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 read instructions.");
358 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 read instructions.");
359 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 read instructions.");
360 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 read instructions.");
361 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 write instructions.");
362 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 write instructions.");
363 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 write instructions.");
364 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 write instructions.");
365 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 write instructions.");
366 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
367 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
368 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
369 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
370 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
371 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
372 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
373 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
374 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
375
376 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
377 pVCpu->em.s.pCliStatTree = 0;
378
379 /* these should be considered for release statistics. */
380 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
381 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
382 EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
383 EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
384 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
385 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
386 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
387 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
388 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
389 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
390
391#endif /* VBOX_WITH_STATISTICS */
392
393 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
394 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
395 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatCapped, "/PROF/CPU%d/EM/Capped", "Profiling capped state (sleep).");
396 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
397 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
398
399 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
400 }
401
402 return VINF_SUCCESS;
403}
404
405
406/**
407 * Initializes the per-VCPU EM.
408 *
409 * @returns VBox status code.
410 * @param pVM The VM to operate on.
411 */
412VMMR3DECL(int) EMR3InitCPU(PVM pVM)
413{
414 LogFlow(("EMR3InitCPU\n"));
415 return VINF_SUCCESS;
416}
417
418
419/**
420 * Applies relocations to data and code managed by this
421 * component. This function will be called at init and
422 * whenever the VMM need to relocate it self inside the GC.
423 *
424 * @param pVM The VM.
425 */
426VMMR3DECL(void) EMR3Relocate(PVM pVM)
427{
428 LogFlow(("EMR3Relocate\n"));
429 for (VMCPUID i = 0; i < pVM->cCpus; i++)
430 {
431 PVMCPU pVCpu = &pVM->aCpus[i];
432 if (pVCpu->em.s.pStatsR3)
433 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
434 }
435}
436
437
438/**
439 * Reset the EM state for a CPU.
440 *
441 * Called by EMR3Reset and hot plugging.
442 *
443 * @param pVCpu The virtual CPU.
444 */
445VMMR3DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
446{
447 pVCpu->em.s.fForceRAW = false;
448
449 /* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
450 out of the HALTED state here so that enmPrevState doesn't end up as
451 HALTED when EMR3Execute returns. */
452 if (pVCpu->em.s.enmState == EMSTATE_HALTED)
453 {
454 Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
455 pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
456 }
457}
458
459
460/**
461 * Reset notification.
462 *
463 * @param pVM The VM handle.
464 */
465VMMR3DECL(void) EMR3Reset(PVM pVM)
466{
467 Log(("EMR3Reset: \n"));
468 for (VMCPUID i = 0; i < pVM->cCpus; i++)
469 EMR3ResetCpu(&pVM->aCpus[i]);
470}
471
472
473/**
474 * Terminates the EM.
475 *
476 * Termination means cleaning up and freeing all resources,
477 * the VM it self is at this point powered off or suspended.
478 *
479 * @returns VBox status code.
480 * @param pVM The VM to operate on.
481 */
482VMMR3DECL(int) EMR3Term(PVM pVM)
483{
484 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
485
486 PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
487 return VINF_SUCCESS;
488}
489
490/**
491 * Terminates the per-VCPU EM.
492 *
493 * Termination means cleaning up and freeing all resources,
494 * the VM it self is at this point powered off or suspended.
495 *
496 * @returns VBox status code.
497 * @param pVM The VM to operate on.
498 */
499VMMR3DECL(int) EMR3TermCPU(PVM pVM)
500{
501 return 0;
502}
503
504/**
505 * Execute state save operation.
506 *
507 * @returns VBox status code.
508 * @param pVM VM Handle.
509 * @param pSSM SSM operation handle.
510 */
511static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
512{
513 for (VMCPUID i = 0; i < pVM->cCpus; i++)
514 {
515 PVMCPU pVCpu = &pVM->aCpus[i];
516
517 int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
518 AssertRCReturn(rc, rc);
519
520 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
521 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
522 rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
523 AssertRCReturn(rc, rc);
524
525 /* Save mwait state. */
526 rc = SSMR3PutU32(pSSM, pVCpu->em.s.mwait.fWait);
527 AssertRCReturn(rc, rc);
528 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMWaitEAX);
529 AssertRCReturn(rc, rc);
530 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMWaitECX);
531 AssertRCReturn(rc, rc);
532 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMonitorEAX);
533 AssertRCReturn(rc, rc);
534 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMonitorECX);
535 AssertRCReturn(rc, rc);
536 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.mwait.uMonitorEDX);
537 AssertRCReturn(rc, rc);
538 }
539 return VINF_SUCCESS;
540}
541
542
543/**
544 * Execute state load operation.
545 *
546 * @returns VBox status code.
547 * @param pVM VM Handle.
548 * @param pSSM SSM operation handle.
549 * @param uVersion Data layout version.
550 * @param uPass The data pass.
551 */
552static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
553{
554 /*
555 * Validate version.
556 */
557 if ( uVersion != EM_SAVED_STATE_VERSION
558 && uVersion != EM_SAVED_STATE_VERSION_PRE_MWAIT
559 && uVersion != EM_SAVED_STATE_VERSION_PRE_SMP)
560 {
561 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
562 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
563 }
564 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
565
566 /*
567 * Load the saved state.
568 */
569 for (VMCPUID i = 0; i < pVM->cCpus; i++)
570 {
571 PVMCPU pVCpu = &pVM->aCpus[i];
572
573 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
574 if (RT_FAILURE(rc))
575 pVCpu->em.s.fForceRAW = false;
576 AssertRCReturn(rc, rc);
577
578 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
579 {
580 AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
581 rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
582 AssertRCReturn(rc, rc);
583 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
584
585 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
586 }
587 if (uVersion > EM_SAVED_STATE_VERSION_PRE_MWAIT)
588 {
589 /* Load mwait state. */
590 rc = SSMR3GetU32(pSSM, &pVCpu->em.s.mwait.fWait);
591 AssertRCReturn(rc, rc);
592 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMWaitEAX);
593 AssertRCReturn(rc, rc);
594 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMWaitECX);
595 AssertRCReturn(rc, rc);
596 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMonitorEAX);
597 AssertRCReturn(rc, rc);
598 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMonitorECX);
599 AssertRCReturn(rc, rc);
600 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.mwait.uMonitorEDX);
601 AssertRCReturn(rc, rc);
602 }
603
604 Assert(!pVCpu->em.s.pCliStatTree);
605 }
606 return VINF_SUCCESS;
607}
608
609
610/**
611 * Raise a fatal error.
612 *
613 * Safely terminate the VM with full state report and stuff. This function
614 * will naturally never return.
615 *
616 * @param pVCpu VMCPU handle.
617 * @param rc VBox status code.
618 */
619VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
620{
621 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
622 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
623 AssertReleaseMsgFailed(("longjmp returned!\n"));
624}
625
626
627/**
628 * Gets the EM state name.
629 *
630 * @returns pointer to read only state name,
631 * @param enmState The state.
632 */
633static const char *emR3GetStateName(EMSTATE enmState)
634{
635 switch (enmState)
636 {
637 case EMSTATE_NONE: return "EMSTATE_NONE";
638 case EMSTATE_RAW: return "EMSTATE_RAW";
639 case EMSTATE_HWACC: return "EMSTATE_HWACC";
640 case EMSTATE_REM: return "EMSTATE_REM";
641 case EMSTATE_PARAV: return "EMSTATE_PARAV";
642 case EMSTATE_HALTED: return "EMSTATE_HALTED";
643 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
644 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
645 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
646 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
647 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
648 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
649 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
650 default: return "Unknown!";
651 }
652}
653
654
655/**
656 * Debug loop.
657 *
658 * @returns VBox status code for EM.
659 * @param pVM VM handle.
660 * @param pVCpu VMCPU handle.
661 * @param rc Current EM VBox status code..
662 */
663static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
664{
665 for (;;)
666 {
667 Log(("emR3Debug: rc=%Rrc\n", rc));
668 const int rcLast = rc;
669
670 /*
671 * Debug related RC.
672 */
673 switch (rc)
674 {
675 /*
676 * Single step an instruction.
677 */
678 case VINF_EM_DBG_STEP:
679 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
680 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
681 || pVCpu->em.s.fForceRAW /* paranoia */)
682 rc = emR3RawStep(pVM, pVCpu);
683 else
684 {
685 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
686 rc = emR3RemStep(pVM, pVCpu);
687 }
688 break;
689
690 /*
691 * Simple events: stepped, breakpoint, stop/assertion.
692 */
693 case VINF_EM_DBG_STEPPED:
694 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
695 break;
696
697 case VINF_EM_DBG_BREAKPOINT:
698 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
699 break;
700
701 case VINF_EM_DBG_STOP:
702 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
703 break;
704
705 case VINF_EM_DBG_HYPER_STEPPED:
706 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
707 break;
708
709 case VINF_EM_DBG_HYPER_BREAKPOINT:
710 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
711 break;
712
713 case VINF_EM_DBG_HYPER_ASSERTION:
714 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
715 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
716 break;
717
718 /*
719 * Guru meditation.
720 */
721 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
722 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
723 break;
724 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
725 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
726 break;
727
728 default: /** @todo don't use default for guru, but make special errors code! */
729 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
730 break;
731 }
732
733 /*
734 * Process the result.
735 */
736 do
737 {
738 switch (rc)
739 {
740 /*
741 * Continue the debugging loop.
742 */
743 case VINF_EM_DBG_STEP:
744 case VINF_EM_DBG_STOP:
745 case VINF_EM_DBG_STEPPED:
746 case VINF_EM_DBG_BREAKPOINT:
747 case VINF_EM_DBG_HYPER_STEPPED:
748 case VINF_EM_DBG_HYPER_BREAKPOINT:
749 case VINF_EM_DBG_HYPER_ASSERTION:
750 break;
751
752 /*
753 * Resuming execution (in some form) has to be done here if we got
754 * a hypervisor debug event.
755 */
756 case VINF_SUCCESS:
757 case VINF_EM_RESUME:
758 case VINF_EM_SUSPEND:
759 case VINF_EM_RESCHEDULE:
760 case VINF_EM_RESCHEDULE_RAW:
761 case VINF_EM_RESCHEDULE_REM:
762 case VINF_EM_HALT:
763 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
764 {
765 rc = emR3RawResumeHyper(pVM, pVCpu);
766 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
767 continue;
768 }
769 if (rc == VINF_SUCCESS)
770 rc = VINF_EM_RESCHEDULE;
771 return rc;
772
773 /*
774 * The debugger isn't attached.
775 * We'll simply turn the thing off since that's the easiest thing to do.
776 */
777 case VERR_DBGF_NOT_ATTACHED:
778 switch (rcLast)
779 {
780 case VINF_EM_DBG_HYPER_STEPPED:
781 case VINF_EM_DBG_HYPER_BREAKPOINT:
782 case VINF_EM_DBG_HYPER_ASSERTION:
783 case VERR_TRPM_PANIC:
784 case VERR_TRPM_DONT_PANIC:
785 case VERR_VMM_RING0_ASSERTION:
786 case VERR_VMM_HYPER_CR3_MISMATCH:
787 case VERR_VMM_RING3_CALL_DISABLED:
788 return rcLast;
789 }
790 return VINF_EM_OFF;
791
792 /*
793 * Status codes terminating the VM in one or another sense.
794 */
795 case VINF_EM_TERMINATE:
796 case VINF_EM_OFF:
797 case VINF_EM_RESET:
798 case VINF_EM_NO_MEMORY:
799 case VINF_EM_RAW_STALE_SELECTOR:
800 case VINF_EM_RAW_IRET_TRAP:
801 case VERR_TRPM_PANIC:
802 case VERR_TRPM_DONT_PANIC:
803 case VERR_VMM_RING0_ASSERTION:
804 case VERR_VMM_HYPER_CR3_MISMATCH:
805 case VERR_VMM_RING3_CALL_DISABLED:
806 case VERR_INTERNAL_ERROR:
807 case VERR_INTERNAL_ERROR_2:
808 case VERR_INTERNAL_ERROR_3:
809 case VERR_INTERNAL_ERROR_4:
810 case VERR_INTERNAL_ERROR_5:
811 case VERR_IPE_UNEXPECTED_STATUS:
812 case VERR_IPE_UNEXPECTED_INFO_STATUS:
813 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
814 return rc;
815
816 /*
817 * The rest is unexpected, and will keep us here.
818 */
819 default:
820 AssertMsgFailed(("Unexpected rc %Rrc!\n", rc));
821 break;
822 }
823 } while (false);
824 } /* debug for ever */
825}
826
827/**
828 * Steps recompiled code.
829 *
830 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
831 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
832 *
833 * @param pVM VM handle.
834 * @param pVCpu VMCPU handle.
835 */
836static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
837{
838 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
839
840 EMRemLock(pVM);
841
842 /*
843 * Switch to REM, step instruction, switch back.
844 */
845 int rc = REMR3State(pVM, pVCpu);
846 if (RT_SUCCESS(rc))
847 {
848 rc = REMR3Step(pVM, pVCpu);
849 REMR3StateBack(pVM, pVCpu);
850 }
851 EMRemUnlock(pVM);
852
853 LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
854 return rc;
855}
856
857
858/**
859 * emR3RemExecute helper that syncs the state back from REM and leave the REM
860 * critical section.
861 *
862 * @returns false - new fInREMState value.
863 * @param pVM The VM handle.
864 * @param pVCpu The virtual CPU handle.
865 */
866DECLINLINE(bool) emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu)
867{
868 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, a);
869 REMR3StateBack(pVM, pVCpu);
870 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, a);
871
872 EMRemUnlock(pVM);
873 return false;
874}
875
876
877/**
878 * Executes recompiled code.
879 *
880 * This function contains the recompiler version of the inner
881 * execution loop (the outer loop being in EMR3ExecuteVM()).
882 *
883 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
884 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
885 *
886 * @param pVM VM handle.
887 * @param pVCpu VMCPU handle.
888 * @param pfFFDone Where to store an indicator telling whether or not
889 * FFs were done before returning.
890 *
891 */
892static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
893{
894#ifdef LOG_ENABLED
895 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
896 uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
897
898 if (pCtx->eflags.Bits.u1VM)
899 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
900 else
901 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, pCtx->eflags.u));
902#endif
903 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
904
905#if defined(VBOX_STRICT) && defined(DEBUG_bird)
906 AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
907 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo #1419 - get flat address. */
908 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
909#endif
910
911 /*
912 * Spin till we get a forced action which returns anything but VINF_SUCCESS
913 * or the REM suggests raw-mode execution.
914 */
915 *pfFFDone = false;
916 bool fInREMState = false;
917 int rc = VINF_SUCCESS;
918 for (;;)
919 {
920 /*
921 * Lock REM and update the state if not already in sync.
922 *
923 * Note! Big lock, but you are not supposed to own any lock when
924 * coming in here.
925 */
926 if (!fInREMState)
927 {
928 EMRemLock(pVM);
929 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
930
931 /* Flush the recompiler translation blocks if the VCPU has changed,
932 also force a full CPU state resync. */
933 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
934 {
935 REMFlushTBs(pVM);
936 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
937 }
938 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
939
940 rc = REMR3State(pVM, pVCpu);
941
942 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
943 if (RT_FAILURE(rc))
944 break;
945 fInREMState = true;
946
947 /*
948 * We might have missed the raising of VMREQ, TIMER and some other
949 * important FFs while we were busy switching the state. So, check again.
950 */
951 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_RESET)
952 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
953 {
954 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
955 goto l_REMDoForcedActions;
956 }
957 }
958
959
960 /*
961 * Execute REM.
962 */
963 if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
964 {
965 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
966 rc = REMR3Run(pVM, pVCpu);
967 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
968 }
969 else
970 {
971 /* Give up this time slice; virtual time continues */
972 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
973 RTThreadSleep(5);
974 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
975 rc = VINF_SUCCESS;
976 }
977
978 /*
979 * Deal with high priority post execution FFs before doing anything
980 * else. Sync back the state and leave the lock to be on the safe side.
981 */
982 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
983 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
984 {
985 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
986 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
987 }
988
989 /*
990 * Process the returned status code.
991 */
992 if (rc != VINF_SUCCESS)
993 {
994 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
995 break;
996 if (rc != VINF_REM_INTERRUPED_FF)
997 {
998 /*
999 * Anything which is not known to us means an internal error
1000 * and the termination of the VM!
1001 */
1002 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1003 break;
1004 }
1005 }
1006
1007
1008 /*
1009 * Check and execute forced actions.
1010 *
1011 * Sync back the VM state and leave the lock before calling any of
1012 * these, you never know what's going to happen here.
1013 */
1014#ifdef VBOX_HIGH_RES_TIMERS_HACK
1015 TMTimerPollVoid(pVM, pVCpu);
1016#endif
1017 AssertCompile((VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
1018 if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
1019 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)))
1020 {
1021l_REMDoForcedActions:
1022 if (fInREMState)
1023 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1024 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1025 rc = emR3ForcedActions(pVM, pVCpu, rc);
1026 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1027 if ( rc != VINF_SUCCESS
1028 && rc != VINF_EM_RESCHEDULE_REM)
1029 {
1030 *pfFFDone = true;
1031 break;
1032 }
1033 }
1034
1035 } /* The Inner Loop, recompiled execution mode version. */
1036
1037
1038 /*
1039 * Returning. Sync back the VM state if required.
1040 */
1041 if (fInREMState)
1042 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1043
1044 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1045 return rc;
1046}
1047
1048
1049#ifdef DEBUG
1050
1051int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1052{
1053 EMSTATE enmOldState = pVCpu->em.s.enmState;
1054
1055 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1056
1057 Log(("Single step BEGIN:\n"));
1058 for (uint32_t i = 0; i < cIterations; i++)
1059 {
1060 DBGFR3PrgStep(pVCpu);
1061 DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1062 emR3RemStep(pVM, pVCpu);
1063 if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1064 break;
1065 }
1066 Log(("Single step END:\n"));
1067 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1068 pVCpu->em.s.enmState = enmOldState;
1069 return VINF_EM_RESCHEDULE;
1070}
1071
1072#endif /* DEBUG */
1073
1074
1075/**
1076 * Decides whether to execute RAW, HWACC or REM.
1077 *
1078 * @returns new EM state
1079 * @param pVM The VM.
1080 * @param pVCpu The VMCPU handle.
1081 * @param pCtx The CPU context.
1082 */
1083EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1084{
1085 /*
1086 * When forcing raw-mode execution, things are simple.
1087 */
1088 if (pVCpu->em.s.fForceRAW)
1089 return EMSTATE_RAW;
1090
1091 /*
1092 * We stay in the wait for SIPI state unless explicitly told otherwise.
1093 */
1094 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1095 return EMSTATE_WAIT_SIPI;
1096
1097 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1098 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1099 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1100
1101 X86EFLAGS EFlags = pCtx->eflags;
1102 if (HWACCMIsEnabled(pVM))
1103 {
1104 /* Hardware accelerated raw-mode:
1105 *
1106 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1107 */
1108 if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
1109 return EMSTATE_HWACC;
1110
1111 /* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
1112 * off monitoring features essential for raw mode! */
1113 return EMSTATE_REM;
1114 }
1115
1116 /*
1117 * Standard raw-mode:
1118 *
1119 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1120 * or 32 bits protected mode ring 0 code
1121 *
1122 * The tests are ordered by the likelihood of being true during normal execution.
1123 */
1124 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1125 {
1126 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1127 return EMSTATE_REM;
1128 }
1129
1130#ifndef VBOX_RAW_V86
1131 if (EFlags.u32 & X86_EFL_VM) {
1132 Log2(("raw mode refused: VM_MASK\n"));
1133 return EMSTATE_REM;
1134 }
1135#endif
1136
1137 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1138 uint32_t u32CR0 = pCtx->cr0;
1139 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1140 {
1141 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1142 return EMSTATE_REM;
1143 }
1144
1145 if (pCtx->cr4 & X86_CR4_PAE)
1146 {
1147 uint32_t u32Dummy, u32Features;
1148
1149 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1150 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1151 return EMSTATE_REM;
1152 }
1153
1154 unsigned uSS = pCtx->ss;
1155 if ( pCtx->eflags.Bits.u1VM
1156 || (uSS & X86_SEL_RPL) == 3)
1157 {
1158 if (!EMIsRawRing3Enabled(pVM))
1159 return EMSTATE_REM;
1160
1161 if (!(EFlags.u32 & X86_EFL_IF))
1162 {
1163 Log2(("raw mode refused: IF (RawR3)\n"));
1164 return EMSTATE_REM;
1165 }
1166
1167 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1168 {
1169 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1170 return EMSTATE_REM;
1171 }
1172 }
1173 else
1174 {
1175 if (!EMIsRawRing0Enabled(pVM))
1176 return EMSTATE_REM;
1177
1178 /* Only ring 0 supervisor code. */
1179 if ((uSS & X86_SEL_RPL) != 0)
1180 {
1181 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1182 return EMSTATE_REM;
1183 }
1184
1185 // Let's start with pure 32 bits ring 0 code first
1186 /** @todo What's pure 32-bit mode? flat? */
1187 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
1188 || !(pCtx->csHid.Attr.n.u1DefBig))
1189 {
1190 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1191 return EMSTATE_REM;
1192 }
1193
1194 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1195 if (!(u32CR0 & X86_CR0_WP))
1196 {
1197 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1198 return EMSTATE_REM;
1199 }
1200
1201 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1202 {
1203 Log2(("raw r0 mode forced: patch code\n"));
1204 return EMSTATE_RAW;
1205 }
1206
1207#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1208 if (!(EFlags.u32 & X86_EFL_IF))
1209 {
1210 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1211 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1212 return EMSTATE_REM;
1213 }
1214#endif
1215
1216 /** @todo still necessary??? */
1217 if (EFlags.Bits.u2IOPL != 0)
1218 {
1219 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1220 return EMSTATE_REM;
1221 }
1222 }
1223
1224 Assert(PGMPhysIsA20Enabled(pVCpu));
1225 return EMSTATE_RAW;
1226}
1227
1228
1229/**
1230 * Executes all high priority post execution force actions.
1231 *
1232 * @returns rc or a fatal status code.
1233 *
1234 * @param pVM VM handle.
1235 * @param pVCpu VMCPU handle.
1236 * @param rc The current rc.
1237 */
1238int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1239{
1240 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1241 PDMCritSectFF(pVCpu);
1242
1243 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1244 CSAMR3DoPendingAction(pVM, pVCpu);
1245
1246 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1247 {
1248 if ( rc > VINF_EM_NO_MEMORY
1249 && rc <= VINF_EM_LAST)
1250 rc = VINF_EM_NO_MEMORY;
1251 }
1252
1253 return rc;
1254}
1255
1256
1257/**
1258 * Executes all pending forced actions.
1259 *
1260 * Forced actions can cause execution delays and execution
1261 * rescheduling. The first we deal with using action priority, so
1262 * that for instance pending timers aren't scheduled and ran until
1263 * right before execution. The rescheduling we deal with using
1264 * return codes. The same goes for VM termination, only in that case
1265 * we exit everything.
1266 *
1267 * @returns VBox status code of equal or greater importance/severity than rc.
1268 * The most important ones are: VINF_EM_RESCHEDULE,
1269 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1270 *
1271 * @param pVM VM handle.
1272 * @param pVCpu VMCPU handle.
1273 * @param rc The current rc.
1274 *
1275 */
1276int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1277{
1278 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1279#ifdef VBOX_STRICT
1280 int rcIrq = VINF_SUCCESS;
1281#endif
1282 int rc2;
1283#define UPDATE_RC() \
1284 do { \
1285 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1286 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1287 break; \
1288 if (!rc || rc2 < rc) \
1289 rc = rc2; \
1290 } while (0)
1291
1292 /*
1293 * Post execution chunk first.
1294 */
1295 if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1296 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
1297 {
1298 /*
1299 * EMT Rendezvous (must be serviced before termination).
1300 */
1301 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1302 {
1303 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1304 UPDATE_RC();
1305 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1306 * stopped/reset before the next VM state change is made. We need a better
1307 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1308 * && rc >= VINF_EM_SUSPEND). */
1309 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1310 {
1311 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1312 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1313 return rc;
1314 }
1315 }
1316
1317 /*
1318 * State change request (cleared by vmR3SetStateLocked).
1319 */
1320 if (VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1321 {
1322 VMSTATE enmState = VMR3GetState(pVM);
1323 switch (enmState)
1324 {
1325 case VMSTATE_FATAL_ERROR:
1326 case VMSTATE_FATAL_ERROR_LS:
1327 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1328 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1329 return VINF_EM_SUSPEND;
1330
1331 case VMSTATE_DESTROYING:
1332 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1333 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1334 return VINF_EM_TERMINATE;
1335
1336 default:
1337 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1338 }
1339 }
1340
1341 /*
1342 * Debugger Facility polling.
1343 */
1344 if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
1345 {
1346 rc2 = DBGFR3VMMForcedAction(pVM);
1347 UPDATE_RC();
1348 }
1349
1350 /*
1351 * Postponed reset request.
1352 */
1353 if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET))
1354 {
1355 rc2 = VMR3Reset(pVM);
1356 UPDATE_RC();
1357 }
1358
1359 /*
1360 * CSAM page scanning.
1361 */
1362 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1363 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1364 {
1365 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1366
1367 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1368 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1369
1370 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1371 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1372 }
1373
1374 /*
1375 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1376 */
1377 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1378 {
1379 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1380 UPDATE_RC();
1381 if (rc == VINF_EM_NO_MEMORY)
1382 return rc;
1383 }
1384
1385 /* check that we got them all */
1386 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1387 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_CSAM_SCAN_PAGE);
1388 }
1389
1390 /*
1391 * Normal priority then.
1392 * (Executed in no particular order.)
1393 */
1394 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1395 {
1396 /*
1397 * PDM Queues are pending.
1398 */
1399 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1400 PDMR3QueueFlushAll(pVM);
1401
1402 /*
1403 * PDM DMA transfers are pending.
1404 */
1405 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1406 PDMR3DmaRun(pVM);
1407
1408 /*
1409 * EMT Rendezvous (make sure they are handled before the requests).
1410 */
1411 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1412 {
1413 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1414 UPDATE_RC();
1415 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1416 * stopped/reset before the next VM state change is made. We need a better
1417 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1418 * && rc >= VINF_EM_SUSPEND). */
1419 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1420 {
1421 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1422 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1423 return rc;
1424 }
1425 }
1426
1427 /*
1428 * Requests from other threads.
1429 */
1430 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1431 {
1432 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY);
1433 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1434 {
1435 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1436 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1437 return rc2;
1438 }
1439 UPDATE_RC();
1440 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1441 * stopped/reset before the next VM state change is made. We need a better
1442 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1443 * && rc >= VINF_EM_SUSPEND). */
1444 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1445 {
1446 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1447 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1448 return rc;
1449 }
1450 }
1451
1452 /* Replay the handler notification changes. */
1453 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1454 {
1455 /* Try not to cause deadlocks. */
1456 if ( pVM->cCpus == 1
1457 || ( !PGMIsLockOwner(pVM)
1458 && !IOMIsLockOwner(pVM))
1459 )
1460 {
1461 EMRemLock(pVM);
1462 REMR3ReplayHandlerNotifications(pVM);
1463 EMRemUnlock(pVM);
1464 }
1465 }
1466
1467 /* check that we got them all */
1468 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
1469 }
1470
1471 /*
1472 * Normal priority then. (per-VCPU)
1473 * (Executed in no particular order.)
1474 */
1475 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1476 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1477 {
1478 /*
1479 * Requests from other threads.
1480 */
1481 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1482 {
1483 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu);
1484 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1485 {
1486 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1487 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1488 return rc2;
1489 }
1490 UPDATE_RC();
1491 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1492 * stopped/reset before the next VM state change is made. We need a better
1493 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1494 * && rc >= VINF_EM_SUSPEND). */
1495 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1496 {
1497 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1498 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1499 return rc;
1500 }
1501 }
1502
1503 /* check that we got them all */
1504 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1505 }
1506
1507 /*
1508 * High priority pre execution chunk last.
1509 * (Executed in ascending priority order.)
1510 */
1511 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1512 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1513 {
1514 /*
1515 * Timers before interrupts.
1516 */
1517 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
1518 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1519 TMR3TimerQueuesDo(pVM);
1520
1521 /*
1522 * The instruction following an emulated STI should *always* be executed!
1523 */
1524 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1525 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1526 {
1527 Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1528 if (CPUMGetGuestEIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1529 {
1530 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
1531 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1532 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1533 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1534 */
1535 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1536 }
1537 if (HWACCMR3IsActive(pVCpu))
1538 rc2 = VINF_EM_RESCHEDULE_HWACC;
1539 else
1540 rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
1541
1542 UPDATE_RC();
1543 }
1544
1545 /*
1546 * Interrupts.
1547 */
1548 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1549 && !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1550 && (!rc || rc >= VINF_EM_RESCHEDULE_HWACC)
1551 && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1552 && PATMAreInterruptsEnabled(pVM)
1553 && !HWACCMR3IsEventPending(pVCpu))
1554 {
1555 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1556 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1557 {
1558 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1559 /** @todo this really isn't nice, should properly handle this */
1560 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1561#ifdef VBOX_STRICT
1562 rcIrq = rc2;
1563#endif
1564 UPDATE_RC();
1565 }
1566 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1567 else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1568 {
1569 rc2 = VINF_EM_RESCHEDULE_REM;
1570 UPDATE_RC();
1571 }
1572 }
1573
1574 /*
1575 * Allocate handy pages.
1576 */
1577 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1578 {
1579 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1580 UPDATE_RC();
1581 }
1582
1583 /*
1584 * Debugger Facility request.
1585 */
1586 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1587 {
1588 rc2 = DBGFR3VMMForcedAction(pVM);
1589 UPDATE_RC();
1590 }
1591
1592 /*
1593 * EMT Rendezvous (must be serviced before termination).
1594 */
1595 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1596 {
1597 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1598 UPDATE_RC();
1599 /** @todo HACK ALERT! The following test is to make sure EM+TM thinks the VM is
1600 * stopped/reset before the next VM state change is made. We need a better
1601 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1602 * && rc >= VINF_EM_SUSPEND). */
1603 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1604 {
1605 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1606 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1607 return rc;
1608 }
1609 }
1610
1611 /*
1612 * State change request (cleared by vmR3SetStateLocked).
1613 */
1614 if (VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1615 {
1616 VMSTATE enmState = VMR3GetState(pVM);
1617 switch (enmState)
1618 {
1619 case VMSTATE_FATAL_ERROR:
1620 case VMSTATE_FATAL_ERROR_LS:
1621 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1622 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1623 return VINF_EM_SUSPEND;
1624
1625 case VMSTATE_DESTROYING:
1626 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1627 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1628 return VINF_EM_TERMINATE;
1629
1630 default:
1631 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1632 }
1633 }
1634
1635 /*
1636 * Out of memory? Since most of our fellow high priority actions may cause us
1637 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
1638 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
1639 * than us since we can terminate without allocating more memory.
1640 */
1641 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1642 {
1643 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1644 UPDATE_RC();
1645 if (rc == VINF_EM_NO_MEMORY)
1646 return rc;
1647 }
1648
1649 /*
1650 * If the virtual sync clock is still stopped, make TM restart it.
1651 */
1652 if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
1653 TMR3VirtualSyncFF(pVM, pVCpu);
1654
1655#ifdef DEBUG
1656 /*
1657 * Debug, pause the VM.
1658 */
1659 if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
1660 {
1661 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
1662 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
1663 return VINF_EM_SUSPEND;
1664 }
1665#endif
1666
1667 /* check that we got them all */
1668 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1669 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_INHIBIT_INTERRUPTS));
1670 }
1671
1672#undef UPDATE_RC
1673 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1674 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1675 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
1676 return rc;
1677}
1678
1679
1680/**
1681 * Check if the preset execution time cap restricts guest execution scheduling.
1682 *
1683 * @returns true if allowed, false otherwise
1684 * @param pVM The VM to operate on.
1685 * @param pVCpu The VMCPU to operate on.
1686 *
1687 */
1688VMMR3DECL(bool) EMR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu)
1689{
1690 uint64_t u64UserTime, u64KernelTime;
1691
1692 if ( pVM->uCpuExecutionCap != 100
1693 && RT_SUCCESS(RTThreadGetExecutionTimeMilli(&u64KernelTime, &u64UserTime)))
1694 {
1695 uint64_t u64TimeNow = RTTimeMilliTS();
1696 if (pVCpu->em.s.u64TimeSliceStart + EM_TIME_SLICE < u64TimeNow)
1697 {
1698 /* New time slice. */
1699 pVCpu->em.s.u64TimeSliceStart = u64TimeNow;
1700 pVCpu->em.s.u64TimeSliceStartExec = u64KernelTime + u64UserTime;
1701 pVCpu->em.s.u64TimeSliceExec = 0;
1702 }
1703 pVCpu->em.s.u64TimeSliceExec = u64KernelTime + u64UserTime - pVCpu->em.s.u64TimeSliceStartExec;
1704
1705 Log2(("emR3IsExecutionAllowed: start=%RX64 startexec=%RX64 exec=%RX64 (cap=%x)\n", pVCpu->em.s.u64TimeSliceStart, pVCpu->em.s.u64TimeSliceStartExec, pVCpu->em.s.u64TimeSliceExec, (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100));
1706 if (pVCpu->em.s.u64TimeSliceExec >= (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100)
1707 return false;
1708 }
1709 return true;
1710}
1711
1712
1713/**
1714 * Execute VM.
1715 *
1716 * This function is the main loop of the VM. The emulation thread
1717 * calls this function when the VM has been successfully constructed
1718 * and we're ready for executing the VM.
1719 *
1720 * Returning from this function means that the VM is turned off or
1721 * suspended (state already saved) and deconstruction in next in line.
1722 *
1723 * All interaction from other thread are done using forced actions
1724 * and signaling of the wait object.
1725 *
1726 * @returns VBox status code, informational status codes may indicate failure.
1727 * @param pVM The VM to operate on.
1728 * @param pVCpu The VMCPU to operate on.
1729 */
1730VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
1731{
1732 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
1733 pVM,
1734 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
1735 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
1736 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
1737 pVCpu->em.s.fForceRAW));
1738 VM_ASSERT_EMT(pVM);
1739 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
1740 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
1741 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
1742 ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
1743
1744 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
1745 if (rc == 0)
1746 {
1747 /*
1748 * Start the virtual time.
1749 */
1750 TMR3NotifyResume(pVM, pVCpu);
1751
1752 /*
1753 * The Outer Main Loop.
1754 */
1755 bool fFFDone = false;
1756
1757 /* Reschedule right away to start in the right state. */
1758 rc = VINF_SUCCESS;
1759
1760 /* If resuming after a pause or a state load, restore the previous
1761 state or else we'll start executing code. Else, just reschedule. */
1762 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
1763 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1764 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
1765 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
1766 else
1767 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1768
1769 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1770 for (;;)
1771 {
1772 /*
1773 * Before we can schedule anything (we're here because
1774 * scheduling is required) we must service any pending
1775 * forced actions to avoid any pending action causing
1776 * immediate rescheduling upon entering an inner loop
1777 *
1778 * Do forced actions.
1779 */
1780 if ( !fFFDone
1781 && rc != VINF_EM_TERMINATE
1782 && rc != VINF_EM_OFF
1783 && ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
1784 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK)))
1785 {
1786 rc = emR3ForcedActions(pVM, pVCpu, rc);
1787 if ( ( rc == VINF_EM_RESCHEDULE_REM
1788 || rc == VINF_EM_RESCHEDULE_HWACC)
1789 && pVCpu->em.s.fForceRAW)
1790 rc = VINF_EM_RESCHEDULE_RAW;
1791 }
1792 else if (fFFDone)
1793 fFFDone = false;
1794
1795 /*
1796 * Now what to do?
1797 */
1798 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
1799 switch (rc)
1800 {
1801 /*
1802 * Keep doing what we're currently doing.
1803 */
1804 case VINF_SUCCESS:
1805 break;
1806
1807 /*
1808 * Reschedule - to raw-mode execution.
1809 */
1810 case VINF_EM_RESCHEDULE_RAW:
1811 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVCpu->em.s.enmState, EMSTATE_RAW));
1812 pVCpu->em.s.enmState = EMSTATE_RAW;
1813 break;
1814
1815 /*
1816 * Reschedule - to hardware accelerated raw-mode execution.
1817 */
1818 case VINF_EM_RESCHEDULE_HWACC:
1819 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVCpu->em.s.enmState, EMSTATE_HWACC));
1820 Assert(!pVCpu->em.s.fForceRAW);
1821 pVCpu->em.s.enmState = EMSTATE_HWACC;
1822 break;
1823
1824 /*
1825 * Reschedule - to recompiled execution.
1826 */
1827 case VINF_EM_RESCHEDULE_REM:
1828 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVCpu->em.s.enmState, EMSTATE_REM));
1829 pVCpu->em.s.enmState = EMSTATE_REM;
1830 break;
1831
1832 /*
1833 * Resume.
1834 */
1835 case VINF_EM_RESUME:
1836 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVCpu->em.s.enmState));
1837 /* Don't reschedule in the halted or wait for SIPI case. */
1838 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1839 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
1840 break;
1841 /* fall through and get scheduled. */
1842
1843 /*
1844 * Reschedule.
1845 */
1846 case VINF_EM_RESCHEDULE:
1847 {
1848 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1849 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, emR3GetStateName(enmState)));
1850 pVCpu->em.s.enmState = enmState;
1851 break;
1852 }
1853
1854 /*
1855 * Halted.
1856 */
1857 case VINF_EM_HALT:
1858 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_HALTED));
1859 pVCpu->em.s.enmState = EMSTATE_HALTED;
1860 break;
1861
1862 /*
1863 * Switch to the wait for SIPI state (application processor only)
1864 */
1865 case VINF_EM_WAIT_SIPI:
1866 Assert(pVCpu->idCpu != 0);
1867 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_WAIT_SIPI));
1868 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
1869 break;
1870
1871
1872 /*
1873 * Suspend.
1874 */
1875 case VINF_EM_SUSPEND:
1876 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
1877 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1878 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
1879 break;
1880
1881 /*
1882 * Reset.
1883 * We might end up doing a double reset for now, we'll have to clean up the mess later.
1884 */
1885 case VINF_EM_RESET:
1886 {
1887 if (pVCpu->idCpu == 0)
1888 {
1889 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1890 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, emR3GetStateName(enmState)));
1891 pVCpu->em.s.enmState = enmState;
1892 }
1893 else
1894 {
1895 /* All other VCPUs go into the wait for SIPI state. */
1896 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
1897 }
1898 break;
1899 }
1900
1901 /*
1902 * Power Off.
1903 */
1904 case VINF_EM_OFF:
1905 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
1906 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
1907 TMR3NotifySuspend(pVM, pVCpu);
1908 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1909 return rc;
1910
1911 /*
1912 * Terminate the VM.
1913 */
1914 case VINF_EM_TERMINATE:
1915 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
1916 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
1917 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
1918 TMR3NotifySuspend(pVM, pVCpu);
1919 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1920 return rc;
1921
1922
1923 /*
1924 * Out of memory, suspend the VM and stuff.
1925 */
1926 case VINF_EM_NO_MEMORY:
1927 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
1928 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1929 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
1930 TMR3NotifySuspend(pVM, pVCpu);
1931 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1932
1933 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
1934 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
1935 if (rc != VINF_EM_SUSPEND)
1936 {
1937 if (RT_SUCCESS_NP(rc))
1938 {
1939 AssertLogRelMsgFailed(("%Rrc\n", rc));
1940 rc = VERR_EM_INTERNAL_ERROR;
1941 }
1942 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1943 }
1944 return rc;
1945
1946 /*
1947 * Guest debug events.
1948 */
1949 case VINF_EM_DBG_STEPPED:
1950 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
1951 case VINF_EM_DBG_STOP:
1952 case VINF_EM_DBG_BREAKPOINT:
1953 case VINF_EM_DBG_STEP:
1954 if (pVCpu->em.s.enmState == EMSTATE_RAW)
1955 {
1956 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
1957 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1958 }
1959 else
1960 {
1961 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
1962 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1963 }
1964 break;
1965
1966 /*
1967 * Hypervisor debug events.
1968 */
1969 case VINF_EM_DBG_HYPER_STEPPED:
1970 case VINF_EM_DBG_HYPER_BREAKPOINT:
1971 case VINF_EM_DBG_HYPER_ASSERTION:
1972 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_HYPER));
1973 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
1974 break;
1975
1976 /*
1977 * Guru mediations.
1978 */
1979 case VERR_VMM_RING0_ASSERTION:
1980 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
1981 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1982 break;
1983
1984 /*
1985 * Any error code showing up here other than the ones we
1986 * know and process above are considered to be FATAL.
1987 *
1988 * Unknown warnings and informational status codes are also
1989 * included in this.
1990 */
1991 default:
1992 if (RT_SUCCESS_NP(rc))
1993 {
1994 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
1995 rc = VERR_EM_INTERNAL_ERROR;
1996 }
1997 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
1998 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1999 break;
2000 }
2001
2002 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
2003 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2004
2005 /*
2006 * Act on the state.
2007 */
2008 switch (pVCpu->em.s.enmState)
2009 {
2010 /*
2011 * Execute raw.
2012 */
2013 case EMSTATE_RAW:
2014 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
2015 break;
2016
2017 /*
2018 * Execute hardware accelerated raw.
2019 */
2020 case EMSTATE_HWACC:
2021 rc = emR3HwAccExecute(pVM, pVCpu, &fFFDone);
2022 break;
2023
2024 /*
2025 * Execute recompiled.
2026 */
2027 case EMSTATE_REM:
2028 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
2029 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
2030 break;
2031
2032 /*
2033 * Application processor execution halted until SIPI.
2034 */
2035 case EMSTATE_WAIT_SIPI:
2036 /* no break */
2037 /*
2038 * hlt - execution halted until interrupt.
2039 */
2040 case EMSTATE_HALTED:
2041 {
2042 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
2043 if (pVCpu->em.s.mwait.fWait & EMMWAIT_FLAG_ACTIVE)
2044 {
2045 /* mwait has a special extension where it's woken up when an interrupt is pending even when IF=0. */
2046 rc = VMR3WaitHalted(pVM, pVCpu, !(pVCpu->em.s.mwait.fWait & EMMWAIT_FLAG_BREAKIRQIF0) && !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2047 pVCpu->em.s.mwait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
2048 }
2049 else
2050 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2051
2052 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
2053 break;
2054 }
2055
2056 /*
2057 * Suspended - return to VM.cpp.
2058 */
2059 case EMSTATE_SUSPENDED:
2060 TMR3NotifySuspend(pVM, pVCpu);
2061 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2062 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2063 return VINF_EM_SUSPEND;
2064
2065 /*
2066 * Debugging in the guest.
2067 */
2068 case EMSTATE_DEBUG_GUEST_REM:
2069 case EMSTATE_DEBUG_GUEST_RAW:
2070 TMR3NotifySuspend(pVM, pVCpu);
2071 rc = emR3Debug(pVM, pVCpu, rc);
2072 TMR3NotifyResume(pVM, pVCpu);
2073 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2074 break;
2075
2076 /*
2077 * Debugging in the hypervisor.
2078 */
2079 case EMSTATE_DEBUG_HYPER:
2080 {
2081 TMR3NotifySuspend(pVM, pVCpu);
2082 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2083
2084 rc = emR3Debug(pVM, pVCpu, rc);
2085 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2086 if (rc != VINF_SUCCESS)
2087 {
2088 /* switch to guru meditation mode */
2089 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2090 VMMR3FatalDump(pVM, pVCpu, rc);
2091 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2092 return rc;
2093 }
2094
2095 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2096 TMR3NotifyResume(pVM, pVCpu);
2097 break;
2098 }
2099
2100 /*
2101 * Guru meditation takes place in the debugger.
2102 */
2103 case EMSTATE_GURU_MEDITATION:
2104 {
2105 TMR3NotifySuspend(pVM, pVCpu);
2106 VMMR3FatalDump(pVM, pVCpu, rc);
2107 emR3Debug(pVM, pVCpu, rc);
2108 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2109 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2110 return rc;
2111 }
2112
2113 /*
2114 * The states we don't expect here.
2115 */
2116 case EMSTATE_NONE:
2117 case EMSTATE_TERMINATING:
2118 default:
2119 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2120 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2121 TMR3NotifySuspend(pVM, pVCpu);
2122 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2123 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2124 return VERR_EM_INTERNAL_ERROR;
2125 }
2126 } /* The Outer Main Loop */
2127 }
2128 else
2129 {
2130 /*
2131 * Fatal error.
2132 */
2133 Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2134 TMR3NotifySuspend(pVM, pVCpu);
2135 VMMR3FatalDump(pVM, pVCpu, rc);
2136 emR3Debug(pVM, pVCpu, rc);
2137 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2138 /** @todo change the VM state! */
2139 return rc;
2140 }
2141
2142 /* (won't ever get here). */
2143 AssertFailed();
2144}
2145
2146/**
2147 * Notify EM of a state change (used by FTM)
2148 *
2149 * @param pVM VM Handle.
2150 */
2151VMMR3DECL(int) EMR3NotifySuspend(PVM pVM)
2152{
2153 PVMCPU pVCpu = VMMGetCpu(pVM);
2154
2155 TMR3NotifySuspend(pVM, pVCpu); /* Stop the virtual time. */
2156 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
2157 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2158 return VINF_SUCCESS;
2159}
2160
2161/**
2162 * Notify EM of a state change (used by FTM)
2163 *
2164 * @param pVM VM Handle.
2165 */
2166VMMR3DECL(int) EMR3NotifyResume(PVM pVM)
2167{
2168 PVMCPU pVCpu = VMMGetCpu(pVM);
2169 EMSTATE enmCurState = pVCpu->em.s.enmState;
2170
2171 TMR3NotifyResume(pVM, pVCpu); /* Resume the virtual time. */
2172 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2173 pVCpu->em.s.enmPrevState = enmCurState;
2174 return VINF_SUCCESS;
2175}
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