EM.cpp@ 1073

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1	/* $Id: EM.cpp 1057 2007-02-23 20:38:37Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor/Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_em EM - The Execution Monitor/Manager
24	*
25	* The Execution Monitor/Manager is responsible for running the VM, scheduling
26	* the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27	* the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28	* the VM.
29	*
30	*/
31
32	/*******************************************************************************
33	* Header Files *
34	*******************************************************************************/
35	#define LOG_GROUP LOG_GROUP_EM
36	#include <VBox/em.h>
37	#include <VBox/vmm.h>
38	#include <VBox/patm.h>
39	#include <VBox/csam.h>
40	#include <VBox/selm.h>
41	#include <VBox/trpm.h>
42	#include <VBox/iom.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/pgm.h>
45	#include <VBox/rem.h>
46	#include <VBox/tm.h>
47	#include <VBox/mm.h>
48	#include <VBox/pdm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/patm.h>
51	#include "EMInternal.h"
52	#include <VBox/vm.h>
53	#include <VBox/cpumdis.h>
54	#include <VBox/dis.h>
55	#include <VBox/disopcode.h>
56	#include <VBox/dbgf.h>
57
58	#include <VBox/log.h>
59	#include <iprt/thread.h>
60	#include <iprt/assert.h>
61	#include <iprt/asm.h>
62	#include <iprt/semaphore.h>
63	#include <iprt/string.h>
64	#include <iprt/avl.h>
65	#include <iprt/stream.h>
66	#include <VBox/param.h>
67	#include <VBox/err.h>
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
74	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
75	static int emR3Debug(PVM pVM, int rc);
76	static int emR3RemStep(PVM pVM);
77	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
78	static int emR3RawResumeHyper(PVM pVM);
79	static int emR3RawStep(PVM pVM);
80	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
81	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
82	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
83	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
84	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
85	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
86	static int emR3ForcedActions(PVM pVM, int rc);
87	static int emR3RawGuestTrap(PVM pVM);
88
89
90	/**
91	* Initializes the EM.
92	*
93	* @returns VBox status code.
94	* @param pVM The VM to operate on.
95	*/
96	EMR3DECL(int) EMR3Init(PVM pVM)
97	{
98	LogFlow(("EMR3Init\n"));
99	/*
100	* Assert alignment and sizes.
101	*/
102	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
103	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
104	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
105	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
106
107	/*
108	* Init the structure.
109	*/
110	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
111	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
112	if (VBOX_FAILURE(rc))
113	pVM->fRawR3Enabled = true;
114	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
115	if (VBOX_FAILURE(rc))
116	pVM->fRawR0Enabled = true;
117	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
118	pVM->em.s.enmState = EMSTATE_NONE;
119	pVM->em.s.fForceRAW = false;
120
121	rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
122	AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
123	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
124	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
125
126	/*
127	* Saved state.
128	*/
129	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
130	NULL, emR3Save, NULL,
131	NULL, emR3Load, NULL);
132	if (VBOX_FAILURE(rc))
133	return rc;
134
135	/*
136	* Statistics.
137	*/
138	#ifdef VBOX_WITH_STATISTICS
139	PEMSTATS pStats;
140	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
141	if (VBOX_FAILURE(rc))
142	return rc;
143	pVM->em.s.pStatsHC = pStats;
144	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
145
146	STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
147	STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
148
149	STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
150	STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
151
152	STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
153	STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
154	STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
155	STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
156	STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
157	STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
158	STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
159	STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
160	STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
161	STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
162	STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
163	STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
164	STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
165	STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
185	//STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
196
197	STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
198	STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
199
200	STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
204	STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
205	STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
206	STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
207	STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
208	STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
237	//STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
238
239	STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
240	STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
241	STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
246	STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
247	STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
248	STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
249	STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
261
262	STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
263	STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
264	STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
265	STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
266
267	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
268	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
269	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
270	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
271	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
272	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
273	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
274	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
275	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
276	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
277	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
278	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
279	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
280	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
281	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
282	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
283	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
284	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
285	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
286	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
287	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
288	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
289	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
290	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
291	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
292	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
293
294	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
295	pVM->em.s.pCliStatTree = 0;
296	#endif /* VBOX_WITH_STATISTICS */
297
298	/* these should be considered for release statistics. */
299	STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
300	STAM_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
301	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
302	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
303	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
304	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
305	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
306	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
307	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
308	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
309	STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
310	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
311	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
312	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
313	STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
314	STAM_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
315
316
317	return VINF_SUCCESS;
318	}
319
320
321
322	/**
323	* Applies relocations to data and code managed by this
324	* component. This function will be called at init and
325	* whenever the VMM need to relocate it self inside the GC.
326	*
327	* @param pVM The VM.
328	*/
329	EMR3DECL(void) EMR3Relocate(PVM pVM)
330	{
331	LogFlow(("EMR3Relocate\n"));
332	if (pVM->em.s.pStatsHC)
333	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
334	}
335
336
337	/**
338	* Reset notification.
339	*
340	* @param pVM
341	*/
342	EMR3DECL(void) EMR3Reset(PVM pVM)
343	{
344	LogFlow(("EMR3Reset: \n"));
345	pVM->em.s.fForceRAW = false;
346	}
347
348
349	/**
350	* Terminates the EM.
351	*
352	* Termination means cleaning up and freeing all resources,
353	* the VM it self is at this point powered off or suspended.
354	*
355	* @returns VBox status code.
356	* @param pVM The VM to operate on.
357	*/
358	EMR3DECL(int) EMR3Term(PVM pVM)
359	{
360	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
361
362	return VINF_SUCCESS;
363	}
364
365
366	/**
367	* Execute state save operation.
368	*
369	* @returns VBox status code.
370	* @param pVM VM Handle.
371	* @param pSSM SSM operation handle.
372	*/
373	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
374	{
375	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
376	}
377
378
379	/**
380	* Execute state load operation.
381	*
382	* @returns VBox status code.
383	* @param pVM VM Handle.
384	* @param pSSM SSM operation handle.
385	* @param u32Version Data layout version.
386	*/
387	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
388	{
389	/*
390	* Validate version.
391	*/
392	if (u32Version != EM_SAVED_STATE_VERSION)
393	{
394	Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
395	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
396	}
397
398	/*
399	* Load the saved state.
400	*/
401	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
402	if (VBOX_FAILURE(rc))
403	pVM->em.s.fForceRAW = false;
404
405	Assert(pVM->em.s.pCliStatTree == 0);
406	return rc;
407	}
408
409
410	/**
411	* Enables or disables a set of raw-mode execution modes.
412	*
413	* @returns VINF_SUCCESS on success.
414	* @returns VINF_RESCHEDULE if a rescheduling might be required.
415	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
416	*
417	* @param pVM The VM to operate on.
418	* @param enmMode The execution mode change.
419	* @thread The emulation thread.
420	*/
421	EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
422	{
423	switch (enmMode)
424	{
425	case EMRAW_NONE:
426	pVM->fRawR3Enabled = false;
427	pVM->fRawR0Enabled = false;
428	break;
429	case EMRAW_RING3_ENABLE:
430	pVM->fRawR3Enabled = true;
431	break;
432	case EMRAW_RING3_DISABLE:
433	pVM->fRawR3Enabled = false;
434	break;
435	case EMRAW_RING0_ENABLE:
436	pVM->fRawR0Enabled = true;
437	break;
438	case EMRAW_RING0_DISABLE:
439	pVM->fRawR0Enabled = false;
440	break;
441	default:
442	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
443	return VERR_INVALID_PARAMETER;
444	}
445	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
446	pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
447	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
448	}
449
450
451	/**
452	* Raise a fatal error.
453	*
454	* Safely terminate the VM with full state report and stuff. This function
455	* will naturally never return.
456	*
457	* @param pVM VM handle.
458	* @param rc VBox status code.
459	*/
460	EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
461	{
462	longjmp(pVM->em.s.u.FatalLongJump, rc);
463	AssertReleaseMsgFailed(("longjmp returned!\n"));
464	}
465
466
467	/**
468	* Gets the EM state name.
469	*
470	* @returns pointer to read only state name,
471	* @param enmState The state.
472	*/
473	EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
474	{
475	switch (enmState)
476	{
477	case EMSTATE_RAW: return "EMSTATE_RAW";
478	case EMSTATE_HWACC: return "EMSTATE_HWACC";
479	case EMSTATE_REM: return "EMSTATE_REM";
480	case EMSTATE_HALTED: return "EMSTATE_HALTED";
481	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
482	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
483	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
484	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
485	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
486	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
487	default: return "Unknown!";
488	}
489	}
490
491
492	#ifdef VBOX_WITH_STATISTICS
493	/**
494	* Just a braindead function to keep track of cli addresses.
495	* @param pVM VM handle.
496	* @param pInstrGC The EIP of the cli instruction.
497	*/
498	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
499	{
500	PCLISTAT pRec;
501
502	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
503	if (!pRec)
504	{
505	/* New cli instruction; insert into the tree. */
506	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
507	Assert(pRec);
508	if (!pRec)
509	return;
510	pRec->Core.Key = (AVLPVKEY)pInstrGC;
511
512	char szCliStatName[32];
513	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
514	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
515
516	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
517	Assert(fRc); NOREF(fRc);
518	}
519	STAM_COUNTER_INC(&pRec->Counter);
520	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
521	}
522	#endif /* VBOX_WITH_STATISTICS */
523
524
525	/**
526	* Debug loop.
527	*
528	* @returns VBox status code for EM.
529	* @param pVM VM handle.
530	* @param rc Current EM VBox status code..
531	*/
532	static int emR3Debug(PVM pVM, int rc)
533	{
534	for (;;)
535	{
536	Log(("emR3Debug: rc=%Vrc\n", rc));
537	const int rcLast = rc;
538
539	/*
540	* Debug related RC.
541	*/
542	switch (rc)
543	{
544	/*
545	* Single step an instruction.
546	*/
547	case VINF_EM_DBG_STEP:
548	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
549	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
550	\|\| pVM->em.s.fForceRAW /* paranoia */)
551	rc = emR3RawStep(pVM);
552	else
553	{
554	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
555	rc = emR3RemStep(pVM);
556	}
557	break;
558
559	/*
560	* Simple events: stepped, breakpoint, stop/assertion.
561	*/
562	case VINF_EM_DBG_STEPPED:
563	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
564	break;
565
566	case VINF_EM_DBG_BREAKPOINT:
567	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
568	break;
569
570	case VINF_EM_DBG_STOP:
571	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
572	break;
573
574	case VINF_EM_DBG_HYPER_STEPPED:
575	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
576	break;
577
578	case VINF_EM_DBG_HYPER_BREAKPOINT:
579	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
580	break;
581
582	case VINF_EM_DBG_HYPER_ASSERTION:
583	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
584	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
585	break;
586
587	/*
588	* Guru meditation.
589	*/
590	default: /** @todo don't use default for guru, but make special errors code! */
591	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
592	break;
593	}
594
595	/*
596	* Process the result.
597	*/
598	do
599	{
600	switch (rc)
601	{
602	/*
603	* Continue the debugging loop.
604	*/
605	case VINF_EM_DBG_STEP:
606	case VINF_EM_DBG_STOP:
607	case VINF_EM_DBG_STEPPED:
608	case VINF_EM_DBG_BREAKPOINT:
609	case VINF_EM_DBG_HYPER_STEPPED:
610	case VINF_EM_DBG_HYPER_BREAKPOINT:
611	case VINF_EM_DBG_HYPER_ASSERTION:
612	break;
613
614	/*
615	* Resuming execution (in some form) has to be done here if we got
616	* a hypervisor debug event.
617	*/
618	case VINF_SUCCESS:
619	case VINF_EM_RESUME:
620	case VINF_EM_SUSPEND:
621	case VINF_EM_RESCHEDULE:
622	case VINF_EM_RESCHEDULE_RAW:
623	case VINF_EM_RESCHEDULE_REM:
624	case VINF_EM_HALT:
625	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
626	{
627	rc = emR3RawResumeHyper(pVM);
628	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
629	continue;
630	}
631	if (rc == VINF_SUCCESS)
632	rc = VINF_EM_RESCHEDULE;
633	return rc;
634
635	/*
636	* The debugger isn't attached.
637	* We'll simply turn the thing off since that's the easiest thing to do.
638	*/
639	case VERR_DBGF_NOT_ATTACHED:
640	switch (rcLast)
641	{
642	case VINF_EM_DBG_HYPER_ASSERTION:
643	case VINF_EM_DBG_HYPER_STEPPED:
644	case VINF_EM_DBG_HYPER_BREAKPOINT:
645	return rcLast;
646	}
647	return VINF_EM_OFF;
648
649	/*
650	* Status codes terminating the VM in one or another sense.
651	*/
652	case VINF_EM_TERMINATE:
653	case VINF_EM_OFF:
654	case VINF_EM_RESET:
655	case VINF_EM_RAW_STALE_SELECTOR:
656	case VINF_EM_RAW_IRET_TRAP:
657	case VERR_TRPM_PANIC:
658	case VERR_TRPM_DONT_PANIC:
659	case VERR_INTERNAL_ERROR:
660	return rc;
661
662	/*
663	* The rest is unexpected, and will keep us here.
664	*/
665	default:
666	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
667	break;
668	}
669	} while (false);
670	} /* debug for ever */
671	}
672
673
674	/**
675	* Steps recompiled code.
676	*
677	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
678	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
679	*
680	* @param pVM VM handle.
681	*/
682	static int emR3RemStep(PVM pVM)
683	{
684	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
685
686	/*
687	* Switch to REM, step instruction, switch back.
688	*/
689	int rc = REMR3State(pVM);
690	if (VBOX_SUCCESS(rc))
691	{
692	rc = REMR3Step(pVM);
693	REMR3StateBack(pVM);
694	}
695	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
696	return rc;
697	}
698
699	/**
700	* Executes recompiled code.
701	*
702	* This function contains the recompiler version of the inner
703	* execution loop (the outer loop being in EMR3ExecuteVM()).
704	*
705	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
706	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
707	*
708	* @param pVM VM handle.
709	* @param pfFFDone Where to store an indicator telling wheter or not
710	* FFs were done before returning.
711	*
712	*/
713	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
714	{
715	#ifdef LOG_ENABLED
716	PCPUMCTX pCtx = pVM->em.s.pCtx;
717	if ((pCtx->ss & X86_SEL_RPL) == 0)
718	Log(("EMR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
719	#endif
720	STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
721
722	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
723	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
724	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
725	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
726	#endif
727
728	/*
729	* Spin till we get a forced action which returns anything but VINF_SUCCESS
730	* or the REM suggests raw-mode execution.
731	*/
732	*pfFFDone = false;
733	bool fInREMState = false;
734	int rc = VINF_SUCCESS;
735	for (;;)
736	{
737	/*
738	* Update REM state if not already in sync.
739	*/
740	if (!fInREMState)
741	{
742	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
743	rc = REMR3State(pVM);
744	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
745	if (VBOX_FAILURE(rc))
746	break;
747	fInREMState = true;
748
749	/*
750	* We might have missed the raising of VMREQ, TIMER and some other
751	* imporant FFs while we were busy switching the state. So, check again.
752	*/
753	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
754	{
755	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
756	goto l_REMDoForcedActions;
757	}
758	}
759
760
761	/*
762	* Execute REM.
763	*/
764	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
765	rc = REMR3Run(pVM);
766	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
767
768
769	/*
770	* Deal with high priority post execution FFs before doing anything else.
771	*/
772	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
773	rc = emR3HighPriorityPostForcedActions(pVM, rc);
774
775	/*
776	* Process the returned status code.
777	* (Try keep this short! Call functions!)
778	*/
779	if (rc != VINF_SUCCESS)
780	{
781	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
782	break;
783	if (rc != VINF_REM_INTERRUPED_FF)
784	{
785	/*
786	* Anything which is not known to us means an internal error
787	* and the termination of the VM!
788	*/
789	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
790	break;
791	}
792	}
793
794
795	/*
796	* Check and execute forced actions.
797	* Sync back the VM state before calling any of these.
798	*/
799	#ifdef VBOX_HIGH_RES_TIMERS_HACK
800	TMTimerPoll(pVM);
801	#endif
802	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_FLUSH_DIRTY_PAGE \| VM_FF_CSAM_SCAN_PAGE)))
803	{
804	l_REMDoForcedActions:
805	if (fInREMState)
806	{
807	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
808	REMR3StateBack(pVM);
809	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
810	fInREMState = false;
811	}
812	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
813	rc = emR3ForcedActions(pVM, rc);
814	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
815	if ( rc != VINF_SUCCESS
816	&& rc != VINF_EM_RESCHEDULE_REM)
817	{
818	*pfFFDone = true;
819	break;
820	}
821	}
822
823	} /* The Inner Loop, recompiled execution mode version. */
824
825
826	/*
827	* Returning. Sync back the VM state if required.
828	*/
829	if (fInREMState)
830	{
831	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
832	REMR3StateBack(pVM);
833	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
834	}
835
836	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
837	return rc;
838	}
839
840
841	/**
842	* Resumes executing hypervisor after a debug event.
843	*
844	* This is kind of special since our current guest state is
845	* potentially out of sync.
846	*
847	* @returns VBox status code.
848	* @param pVM The VM handle.
849	*/
850	static int emR3RawResumeHyper(PVM pVM)
851	{
852	int rc;
853	PCPUMCTX pCtx = pVM->em.s.pCtx;
854	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
855	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
856
857	/*
858	* Resume execution.
859	*/
860	CPUMRawEnter(pVM, NULL);
861	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
862	rc = VMMR3ResumeHyper(pVM);
863	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
864	rc = CPUMRawLeave(pVM, NULL, rc);
865	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
866
867	/*
868	* Deal with the return code.
869	*/
870	rc = emR3HighPriorityPostForcedActions(pVM, rc);
871	rc = emR3RawHandleRC(pVM, pCtx, rc);
872	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
873	return rc;
874	}
875
876
877	/**
878	* Steps rawmode.
879	*
880	* @returns VBox status code.
881	* @param pVM The VM handle.
882	*/
883	static int emR3RawStep(PVM pVM)
884	{
885	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
886	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
887	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
888	int rc;
889	PCPUMCTX pCtx = pVM->em.s.pCtx;
890	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
891	#ifndef DEBUG_sandervl
892	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
893	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
894	#endif
895	if (fGuest)
896	{
897	/*
898	* Check vital forced actions, but ignore pending interrupts and timers.
899	*/
900	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
901	{
902	rc = emR3RawForcedActions(pVM, pCtx);
903	if (VBOX_FAILURE(rc))
904	return rc;
905	}
906
907	/*
908	* Set flags for single stepping.
909	*/
910	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
911	}
912	else
913	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
914
915	/*
916	* Single step.
917	* We do not start time or anything, if anything we should just do a few nanoseconds.
918	*/
919	CPUMRawEnter(pVM, NULL);
920	do
921	{
922	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
923	rc = VMMR3ResumeHyper(pVM);
924	else
925	rc = VMMR3RawRunGC(pVM);
926	#ifndef DEBUG_sandervl
927	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
928	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
929	#endif
930	} while ( rc == VINF_SUCCESS
931	\|\| rc == VINF_EM_RAW_INTERRUPT);
932	rc = CPUMRawLeave(pVM, NULL, rc);
933	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
934
935	/*
936	* Make sure the trap flag is cleared.
937	* (Too bad if the guest is trying to single step too.)
938	*/
939	if (fGuest)
940	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
941	else
942	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
943
944	/*
945	* Deal with the return codes.
946	*/
947	rc = emR3HighPriorityPostForcedActions(pVM, rc);
948	rc = emR3RawHandleRC(pVM, pCtx, rc);
949	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
950	return rc;
951	}
952
953	#ifdef DEBUG_sandervl
954	void emR3SingleStepExec(PVM pVM, uint32_t cIterations)
955	{
956	EMSTATE enmOldState = pVM->em.s.enmState;
957	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
958
959	Log(("Single step BEGIN:\n"));
960	for(uint32_t i=0;i<cIterations;i++)
961	{
962	DBGFR3PrgStep(pVM);
963	emR3RawStep(pVM);
964	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
965	}
966	Log(("Single step END:\n"));
967	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
968	pVM->em.s.enmState = enmOldState;
969	}
970	#endif
971
972	/**
973	* Executes one (or perhaps a few more) instruction(s).
974	*
975	* @returns VBox status code suitable for EM.
976	*
977	* @param pVM VM handle.
978	* @param rcGC GC return code
979	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
980	* instruction and prefix the log output with this text.
981	*/
982	#ifdef LOG_ENABLED
983	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
984	#else
985	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
986	#endif
987	{
988	PCPUMCTX pCtx = pVM->em.s.pCtx;
989	int rc;
990
991	/*
992	*
993	* The simple solution is to use the recompiler.
994	* The better solution is to disassemble the current instruction and
995	* try handle as many as possible without using REM.
996	*
997	*/
998
999	#ifdef LOG_ENABLED
1000	/*
1001	* Disassemble the instruction if requested.
1002	*/
1003	if (pszPrefix)
1004	{
1005	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1006	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1007	}
1008	#endif /* LOG_ENABLED */
1009
1010
1011	Assert((pCtx->ss & X86_SEL_RPL) != 1);
1012
1013	/*
1014	* PATM is making life more interesting.
1015	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1016	* tell PATM there is a trap in this code and have it take the appropriate actions
1017	* to allow us execute the code in REM.
1018	*/
1019	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1020	{
1021	Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
1022
1023	RTGCPTR pNewEip;
1024	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1025	switch (rc)
1026	{
1027	/*
1028	* It's not very useful to emulate a single instruction and then go back to raw
1029	* mode; just execute the whole block until IF is set again.
1030	*/
1031	case VINF_SUCCESS:
1032	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1033	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1034	pCtx->eip = pNewEip;
1035	Assert(pCtx->eip);
1036
1037	if (pCtx->eflags.Bits.u1IF)
1038	{
1039	/*
1040	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1041	*/
1042	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1043	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1044	}
1045	#if 0 /** @note no noticable change; revisit later when we can emulate iret ourselves. */
1046	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1047	{
1048	/* special case: iret, that sets IF, detected a pending irq/event */
1049	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1050	}
1051	#endif
1052	return VINF_EM_RESCHEDULE_REM;
1053
1054	/*
1055	* One instruction.
1056	*/
1057	case VINF_PATCH_EMULATE_INSTR:
1058	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1059	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1060	pCtx->eip = pNewEip;
1061	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1062
1063	/*
1064	* The patch was disabled, hand it to the REM.
1065	*/
1066	case VERR_PATCH_DISABLED:
1067	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1068	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1069	pCtx->eip = pNewEip;
1070	if (pCtx->eflags.Bits.u1IF)
1071	{
1072	/*
1073	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1074	*/
1075	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1076	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1077	}
1078	return VINF_EM_RESCHEDULE_REM;
1079
1080	/* Force continued patch exection; usually due to write monitored stack. */
1081	case VINF_PATCH_CONTINUE:
1082	return VINF_SUCCESS;
1083
1084	default:
1085	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1086	return VERR_INTERNAL_ERROR;
1087	}
1088	}
1089
1090	#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1091	DISCPUSTATE Cpu;
1092	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1093	if (VBOX_SUCCESS(rc))
1094	{
1095	uint32_t size;
1096
1097	switch (Cpu.pCurInstr->opcode)
1098	{
1099	case OP_MOV:
1100	case OP_AND:
1101	case OP_OR:
1102	case OP_XOR:
1103	case OP_POP:
1104	case OP_INC:
1105	case OP_DEC:
1106	case OP_XCHG:
1107	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1108	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1109	if (VBOX_SUCCESS(rc))
1110	{
1111	pCtx->eip += Cpu.opsize;
1112	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1113	return rc;
1114	}
1115	if (rc != VERR_EM_INTERPRETER)
1116	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1117	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1118	break;
1119	}
1120	}
1121	#endif
1122	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1123	rc = REMR3EmulateInstruction(pVM);
1124	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1125
1126	return rc;
1127	}
1128
1129
1130	/**
1131	* Executes one (or perhaps a few more) instruction(s).
1132	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1133	*
1134	* @returns VBox status code suitable for EM.
1135	* @param pVM VM handle.
1136	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1137	* instruction and prefix the log output with this text.
1138	* @param rcGC GC return code
1139	*/
1140	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1141	{
1142	#ifdef LOG_ENABLED
1143	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1144	#else
1145	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1146	#endif
1147	}
1148
1149	/**
1150	* Executes one (or perhaps a few more) IO instruction(s).
1151	*
1152	* @returns VBox status code suitable for EM.
1153	* @param pVM VM handle.
1154	*/
1155	int emR3RawExecuteIOInstruction(PVM pVM)
1156	{
1157	int rc;
1158	PCPUMCTX pCtx = pVM->em.s.pCtx;
1159
1160	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1161
1162	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1163	* as io instructions tend to come in packages of more than one
1164	*/
1165	DISCPUSTATE Cpu;
1166	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1167	if (VBOX_SUCCESS(rc))
1168	{
1169	#ifdef VBOX_WITH_STATISTICS
1170	switch (Cpu.pCurInstr->opcode)
1171	{
1172	case OP_INSB:
1173	case OP_INSWD:
1174	case OP_IN:
1175	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1176	break;
1177
1178	case OP_OUTSB:
1179	case OP_OUTSWD:
1180	case OP_OUT:
1181	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1182	break;
1183	}
1184	#endif
1185
1186	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1187	{
1188	OP_PARAMVAL ParmVal;
1189	int rc;
1190	switch (Cpu.pCurInstr->opcode)
1191	{
1192	case OP_IN:
1193	{
1194	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal, PARAM_SOURCE);
1195	if ( VBOX_FAILURE(rc)
1196	\|\| ParmVal.type != PARMTYPE_IMMEDIATE)
1197	break;
1198
1199	if (!(Cpu.param1.flags & (USE_REG_GEN8 \| USE_REG_GEN16 \| USE_REG_GEN32)))
1200	break;
1201
1202	/* Make sure port access is allowed */
1203	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1204	if (rc != VINF_SUCCESS)
1205	{
1206	if (rc == VINF_EM_RAW_GUEST_TRAP)
1207	rc = emR3RawGuestTrap(pVM);
1208
1209	return rc;
1210	}
1211
1212	uint32_t u32Value = 0;
1213	switch (Cpu.param1.size)
1214	{
1215	case 1:
1216	Assert(Cpu.param1.base.reg_gen8 == USE_REG_AL);
1217	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint8_t));
1218	if (VBOX_SUCCESS(rc))
1219	{
1220	pCtx->eax = (pCtx->eax & ~0xFF) \| (uint8_t)u32Value;
1221	Log(("EMU: in8 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFF));
1222	pCtx->eip += Cpu.opsize;
1223	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1224	return rc;
1225	}
1226	AssertRC(rc);
1227	break;
1228
1229	case 2:
1230	Assert(Cpu.param1.base.reg_gen16 == USE_REG_AX);
1231	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint16_t));
1232	if (VBOX_SUCCESS(rc))
1233	{
1234	pCtx->eax = (pCtx->eax & ~0xFFFF) \| (uint16_t)u32Value;
1235	Log(("EMU: in16 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFFFF));
1236	pCtx->eip += Cpu.opsize;
1237	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1238	return rc;
1239	}
1240	AssertRC(rc);
1241	break;
1242
1243	case 4:
1244	Assert(Cpu.param1.base.reg_gen32 == USE_REG_EAX);
1245	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint32_t));
1246	if (VBOX_SUCCESS(rc))
1247	{
1248	pCtx->eax = u32Value;
1249	Log(("EMU: in32 %x, %x\n", ParmVal.val.val16, pCtx->eax));
1250	pCtx->eip += Cpu.opsize;
1251	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1252	return rc;
1253	}
1254	AssertRC(rc);
1255	break;
1256
1257	default:
1258	AssertMsgFailed(("Unexpected port size %d\n", ParmVal.size));
1259	break;
1260	}
1261	break;
1262	}
1263
1264	case OP_OUT:
1265	{
1266	// it really is the destination, but we're interested in the destination value. hence we specify PARAM_SOURCE (bit of a hack)
1267	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &ParmVal, PARAM_SOURCE);
1268	if ( VBOX_FAILURE(rc)
1269	\|\| ParmVal.type != PARMTYPE_IMMEDIATE)
1270	break;
1271	OP_PARAMVAL ParmVal2;
1272	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal2, PARAM_SOURCE);
1273	if ( VBOX_FAILURE(rc)
1274	\|\| ParmVal2.type != PARMTYPE_IMMEDIATE)
1275	break;
1276
1277	/* Make sure port access is allowed */
1278	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1279	if (rc != VINF_SUCCESS)
1280	{
1281	if (rc == VINF_EM_RAW_GUEST_TRAP)
1282	rc = emR3RawGuestTrap(pVM);
1283
1284	return rc;
1285	}
1286
1287	AssertMsg(Cpu.param2.size == ParmVal2.size, ("size %d vs %d\n", Cpu.param2.size, ParmVal2.size));
1288	switch (ParmVal2.size)
1289	{
1290	case 1:
1291	Log(("EMU: out8 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val8));
1292	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val8, sizeof(ParmVal2.val.val8));
1293	if (VBOX_SUCCESS(rc))
1294	{
1295	pCtx->eip += Cpu.opsize;
1296	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1297	return rc;
1298	}
1299	AssertRC(rc);
1300	break;
1301
1302	case 2:
1303	Log(("EMU: out16 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val16));
1304	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val16, sizeof(ParmVal2.val.val16));
1305	if (VBOX_SUCCESS(rc))
1306	{
1307	pCtx->eip += Cpu.opsize;
1308	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1309	return rc;
1310	}
1311	AssertRC(rc);
1312	break;
1313
1314	case 4:
1315	Log(("EMU: out32 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val32));
1316	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val32, sizeof(ParmVal2.val.val32));
1317	if (VBOX_SUCCESS(rc))
1318	{
1319	pCtx->eip += Cpu.opsize;
1320	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1321	return rc;
1322	}
1323	AssertRC(rc);
1324	break;
1325
1326	default:
1327	AssertMsgFailed(("Unexpected port size %d\n", ParmVal2.size));
1328	break;
1329	}
1330	break;
1331	}
1332
1333	default:
1334	break;
1335	}
1336	}//if(!(Cpu.prefix & (PREFIX_REP\|PREFIX_REPNE))
1337	else if (Cpu.prefix & PREFIX_REP)
1338	{
1339	switch (Cpu.pCurInstr->opcode)
1340	{
1341	case OP_INSB:
1342	case OP_INSWD:
1343	{
1344	/*
1345	* Do not optimize the destination address decrement case (not worth the effort)
1346	* and likewise for 16 bit address size (would need to use and update only cx/di).
1347	*/
1348	if (pCtx->eflags.Bits.u1DF \|\| Cpu.addrmode != CPUMODE_32BIT)
1349	break;
1350	/*
1351	* Get port number and transfer count directly from the registers (no need to bother the
1352	* disassembler). And get the I/O register size from the opcode / prefix.
1353	*/
1354	uint32_t uPort = pCtx->edx & 0xffff;
1355	RTGCUINTREG cTransfers = pCtx->ecx;
1356	unsigned cbUnit;
1357	if (Cpu.pCurInstr->opcode == OP_INSB)
1358	cbUnit = 1;
1359	else
1360	cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1361
1362	RTGCPTR GCPtrDst = pCtx->edi;
1363	/* Access verification first; we can't recover from traps inside this instruction, as the port read cannot be repeated. */
1364	rc = PGMVerifyAccess(pVM, GCPtrDst, cTransfers * cbUnit,
1365	X86_PTE_RW \| (((pCtx->ss & X86_SEL_RPL) == 3) ? X86_PTE_US : 0));
1366	if (rc != VINF_SUCCESS)
1367	{
1368	Log(("EMU: rep ins%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1369	break;
1370	}
1371
1372	Log(("EMU: rep ins%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1373
1374	/* Make sure port access is allowed */
1375	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1376	if (rc != VINF_SUCCESS)
1377	{
1378	if (rc == VINF_EM_RAW_GUEST_TRAP)
1379	rc = emR3RawGuestTrap(pVM);
1380
1381	return rc;
1382	}
1383
1384	/*
1385	* If the device supports string transfers, ask it to do as
1386	* much as it wants. The rest is done with single-word transfers.
1387	*/
1388	rc = IOMIOPortReadString(pVM, uPort, &GCPtrDst, &cTransfers, cbUnit);
1389	AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1390
1391	while (cTransfers && rc == VINF_SUCCESS)
1392	{
1393	uint32_t u32Value;
1394	rc = IOMIOPortRead(pVM, uPort, &u32Value, cbUnit);
1395	AssertRC(rc);
1396	int rc2 = PGMPhysWriteGCPtrDirty(pVM, GCPtrDst, &u32Value, cbUnit);
1397	AssertRC(rc2);
1398	GCPtrDst += cbUnit;
1399	cTransfers--;
1400	}
1401	pCtx->edi += (pCtx->ecx - cTransfers) * cbUnit;
1402	pCtx->ecx = cTransfers;
1403	if (!cTransfers && VBOX_SUCCESS(rc))
1404	pCtx->eip += Cpu.opsize;
1405	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1406	return rc;
1407	}
1408	case OP_OUTSB:
1409	case OP_OUTSWD:
1410	{
1411	/*
1412	* Do not optimize the source address decrement case (not worth the effort)
1413	* and likewise for 16 bit address size (would need to use and update only cx/si).
1414	*/
1415	if (pCtx->eflags.Bits.u1DF \|\| Cpu.addrmode != CPUMODE_32BIT)
1416	break;
1417	/*
1418	* Get port number and transfer count directly from the registers (no need to bother the
1419	* disassembler). And get the I/O register size from the opcode / prefix.
1420	*/
1421	uint32_t uPort = pCtx->edx & 0xffff;
1422	RTGCUINTREG cTransfers = pCtx->ecx;
1423	unsigned cbUnit;
1424	if (Cpu.pCurInstr->opcode == OP_OUTSB)
1425	cbUnit = 1;
1426	else
1427	cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1428
1429	RTGCPTR GCPtrSrc = pCtx->esi;
1430	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1431	rc = PGMVerifyAccess(pVM, GCPtrSrc, cTransfers * cbUnit, (((pCtx->ss & X86_SEL_RPL) == 3) ? X86_PTE_US : 0));
1432	if (rc != VINF_SUCCESS)
1433	{
1434	Log(("EMU: rep outs%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1435	break;
1436	}
1437
1438	Log(("EMU: rep outs%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1439
1440	/* Make sure port access is allowed */
1441	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1442	if (rc != VINF_SUCCESS)
1443	{
1444	if (rc == VINF_EM_RAW_GUEST_TRAP)
1445	rc = emR3RawGuestTrap(pVM);
1446
1447	return rc;
1448	}
1449
1450	/*
1451	* If the device supports string transfers, ask it to do as
1452	* much as it wants. The rest is done with single-word transfers.
1453	*/
1454	rc = IOMIOPortWriteString(pVM, uPort, &GCPtrSrc, &cTransfers, cbUnit);
1455	AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1456
1457	while (cTransfers && rc == VINF_SUCCESS)
1458	{
1459	uint32_t u32Value;
1460	rc = PGMPhysReadGCPtr(pVM, &u32Value, GCPtrSrc, cbUnit);
1461	Assert(rc == VINF_SUCCESS);
1462	rc = IOMIOPortWrite(pVM, uPort, u32Value, cbUnit);
1463	AssertRC(rc);
1464	GCPtrSrc += cbUnit;
1465	cTransfers--;
1466	}
1467	pCtx->esi += (pCtx->ecx - cTransfers) * cbUnit;
1468	pCtx->ecx = cTransfers;
1469	if (!cTransfers && VBOX_SUCCESS(rc))
1470	pCtx->eip += Cpu.opsize;
1471	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1472	return rc;
1473	}
1474	}
1475	}//if(Cpu.prefix & PREFIX_REP)
1476	}
1477
1478	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1479	return emR3RawExecuteInstruction(pVM, "IO: ");
1480	}
1481
1482
1483	/**
1484	* Handle a guest context trap.
1485	*
1486	* @returns VBox status code suitable for EM.
1487	* @param pVM VM handle.
1488	*/
1489	static int emR3RawGuestTrap(PVM pVM)
1490	{
1491	PCPUMCTX pCtx = pVM->em.s.pCtx;
1492
1493	/*
1494	* Get the trap info.
1495	*/
1496	uint8_t u8TrapNo;
1497	bool fSoftwareInterrupt;
1498	RTGCUINT uErrorCode;
1499	RTGCUINTPTR uCR2;
1500	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
1501	if (VBOX_FAILURE(rc))
1502	{
1503	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1504	return rc;
1505	}
1506
1507	/* Traps can be directly forwarded in hardware accelerated mode. */
1508	if (HWACCMR3IsActive(pVM))
1509	{
1510	#ifdef LOGGING_ENABLED
1511	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1512	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1513	#endif
1514	return VINF_EM_RESCHEDULE_HWACC;
1515	}
1516
1517	/** Scan kernel code that traps; we might not get another chance. */
1518	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1519	&& pCtx->eflags.Bits.u1VM == 0)
1520	{
1521	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1522	CSAMR3CheckCode(pVM, pCtx, pCtx->eip);
1523	}
1524
1525	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1526	{
1527	DISCPUSTATE cpu;
1528
1529	/* If MONITOR & MWAIT are supported, then interpret them here. */
1530	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1531	if ( VBOX_SUCCESS(rc)
1532	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1533	{
1534	uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1535
1536	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1537
1538	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1539	{
1540	rc = TRPMResetTrap(pVM);
1541	AssertRC(rc);
1542
1543	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1544	if (VBOX_SUCCESS(rc))
1545	{
1546	pCtx->eip += cpu.opsize;
1547	return rc;
1548	}
1549	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1550	}
1551	}
1552	}
1553	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1554	{
1555	DISCPUSTATE cpu;
1556
1557	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1558	if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1559	{
1560	/*
1561	* We should really check the TSS for the IO bitmap, but it's not like this
1562	* lazy approach really makes things worse.
1563	*/
1564	rc = TRPMResetTrap(pVM);
1565	AssertRC(rc);
1566	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1567	}
1568	}
1569
1570	#ifdef LOG_ENABLED
1571	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1572	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1573
1574	/* Get guest page information. */
1575	uint64_t fFlags = 0;
1576	RTGCPHYS GCPhys = 0;
1577	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1578	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1579	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, fSoftwareInterrupt ? " software" : "", GCPhys, fFlags,
1580	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1581	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1582	#endif
1583
1584	/*
1585	* #PG has CR2.
1586	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1587	*/
1588	if (u8TrapNo == 14 /* #PG */)
1589	pCtx->cr2 = uCR2;
1590
1591	return VINF_EM_RESCHEDULE_REM;
1592	}
1593
1594
1595	/**
1596	* Handle a ring switch trap.
1597	* Need to do statistics and to install patches. The result is going to REM.
1598	*
1599	* @returns VBox status code suitable for EM.
1600	* @param pVM VM handle.
1601	*/
1602	int emR3RawRingSwitch(PVM pVM)
1603	{
1604	int rc;
1605	DISCPUSTATE Cpu;
1606	PCPUMCTX pCtx = pVM->em.s.pCtx;
1607
1608	/*
1609	* sysenter, syscall & callgate
1610	*/
1611	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1612	if (VBOX_SUCCESS(rc))
1613	{
1614	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1615	{
1616	if (pCtx->SysEnter.cs != 0)
1617	{
1618	rc = PATMR3InstallPatch(pVM, pCtx->eip, SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1619	if (VBOX_SUCCESS(rc))
1620	{
1621	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1622	return VINF_EM_RESCHEDULE_RAW;
1623	}
1624	}
1625	}
1626
1627	#ifdef VBOX_WITH_STATISTICS
1628	switch (Cpu.pCurInstr->opcode)
1629	{
1630	case OP_SYSENTER:
1631	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1632	break;
1633	case OP_SYSEXIT:
1634	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1635	break;
1636	case OP_SYSCALL:
1637	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1638	break;
1639	case OP_SYSRET:
1640	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1641	break;
1642	}
1643	#endif
1644	}
1645	else
1646	AssertRC(rc);
1647
1648	/* go to the REM to emulate a single instruction */
1649	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1650	}
1651
1652	/**
1653	* Handle a trap (#PF or #GP) in patch code
1654	*
1655	* @returns VBox status code suitable for EM.
1656	* @param pVM VM handle.
1657	* @param pCtx CPU context
1658	* @param gcret GC return code
1659	*/
1660	int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1661	{
1662	uint8_t u8TrapNo;
1663	int rc;
1664	bool fSoftwareInterrupt;
1665	RTGCUINT uErrorCode;
1666	RTGCUINTPTR uCR2;
1667
1668	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1669
1670	if (gcret == VINF_PATM_PATCH_INT3)
1671	{
1672	u8TrapNo = 3;
1673	uCR2 = 0;
1674	uErrorCode = 0;
1675	}
1676	else
1677	if (gcret == VINF_PATM_PATCH_TRAP_GP)
1678	{
1679	/* No active trap in this case. Kind of ugly. */
1680	u8TrapNo = X86_XCPT_GP;
1681	uCR2 = 0;
1682	uErrorCode = 0;
1683	}
1684	else
1685	{
1686	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
1687	if (VBOX_FAILURE(rc))
1688	{
1689	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1690	return rc;
1691	}
1692	/* Reset the trap as we'll execute the original instruction again. */
1693	TRPMResetTrap(pVM);
1694	}
1695
1696	/*
1697	* Deal with traps inside patch code.
1698	* (This code won't run outside GC.)
1699	*/
1700	if (u8TrapNo != 1)
1701	{
1702	#ifdef LOG_ENABLED
1703	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1704	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1705	#endif
1706	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1707	pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1708
1709	RTGCPTR pNewEip;
1710	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1711	switch (rc)
1712	{
1713	/*
1714	* Execute the faulting instruction.
1715	*/
1716	case VINF_SUCCESS:
1717	{
1718	/** @todo execute a whole block */
1719	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1720	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1721	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1722
1723	pCtx->eip = pNewEip;
1724	AssertRelease(pCtx->eip);
1725
1726	if (pCtx->eflags.Bits.u1IF)
1727	{
1728	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1729	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1730	*/
1731	if ( u8TrapNo == X86_XCPT_GP
1732	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1733	{
1734	/** @todo move to PATMR3HandleTrap */
1735	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1736	PATMR3RemovePatch(pVM, pCtx->eip);
1737	}
1738
1739	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1740	/** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1741
1742	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1743	/* Interrupts are enabled; just go back to the original instruction.
1744	return VINF_SUCCESS; */
1745	}
1746	return VINF_EM_RESCHEDULE_REM;
1747	}
1748
1749	/*
1750	* One instruction.
1751	*/
1752	case VINF_PATCH_EMULATE_INSTR:
1753	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1754	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1755	pCtx->eip = pNewEip;
1756	AssertRelease(pCtx->eip);
1757	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1758
1759	/*
1760	* The patch was disabled, hand it to the REM.
1761	*/
1762	case VERR_PATCH_DISABLED:
1763	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1764	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1765	pCtx->eip = pNewEip;
1766	AssertRelease(pCtx->eip);
1767
1768	if (pCtx->eflags.Bits.u1IF)
1769	{
1770	/*
1771	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1772	*/
1773	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1774	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1775	}
1776	return VINF_EM_RESCHEDULE_REM;
1777
1778	/* Force continued patch exection; usually due to write monitored stack. */
1779	case VINF_PATCH_CONTINUE:
1780	return VINF_SUCCESS;
1781
1782	/*
1783	* Anything else is fatal.
1784	*/
1785	default:
1786	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1787	return VERR_INTERNAL_ERROR;
1788	}
1789	}
1790	return VINF_SUCCESS;
1791	}
1792
1793
1794	/**
1795	* Handle a privileged instruction.
1796	*
1797	* @returns VBox status code suitable for EM.
1798	* @param pVM VM handle.
1799	*/
1800	int emR3RawPrivileged(PVM pVM)
1801	{
1802	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1803	PCPUMCTX pCtx = pVM->em.s.pCtx;
1804
1805	if (PATMIsEnabled(pVM))
1806	{
1807	/*
1808	* Check if in patch code.
1809	*/
1810	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1811	{
1812	#ifdef LOG_ENABLED
1813	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1814	#endif
1815	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1816	return VERR_EM_RAW_PATCH_CONFLICT;
1817	}
1818	if ( (pCtx->ss & X86_SEL_RPL) == 0
1819	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1820	{
1821	int rc = PATMR3InstallPatch(pVM, pCtx->eip, SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1822	if (VBOX_SUCCESS(rc))
1823	{
1824	#ifdef LOG_ENABLED
1825	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1826	#endif
1827	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1828	return VINF_SUCCESS;
1829	}
1830	}
1831	}
1832
1833	#ifdef LOG_ENABLED
1834	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1835	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1836	#endif
1837
1838	/*
1839	* Instruction statistics and logging.
1840	*/
1841	DISCPUSTATE Cpu;
1842	int rc;
1843
1844	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1845	if (VBOX_SUCCESS(rc))
1846	{
1847	#ifdef VBOX_WITH_STATISTICS
1848	PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1849	switch (Cpu.pCurInstr->opcode)
1850	{
1851	case OP_INVLPG:
1852	STAM_COUNTER_INC(&pStats->StatInvlpg);
1853	break;
1854	case OP_IRET:
1855	STAM_COUNTER_INC(&pStats->StatIret);
1856	break;
1857	case OP_CLI:
1858	STAM_COUNTER_INC(&pStats->StatCli);
1859	emR3RecordCli(pVM, pCtx->eip);
1860	break;
1861	case OP_STI:
1862	STAM_COUNTER_INC(&pStats->StatSti);
1863	break;
1864	case OP_INSB:
1865	case OP_INSWD:
1866	case OP_IN:
1867	case OP_OUTSB:
1868	case OP_OUTSWD:
1869	case OP_OUT:
1870	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1871	break;
1872
1873	case OP_MOV_CR:
1874	if (Cpu.param1.flags & USE_REG_GEN32)
1875	{
1876	//read
1877	Assert(Cpu.param2.flags & USE_REG_CR);
1878	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1879	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1880	}
1881	else
1882	{
1883	//write
1884	Assert(Cpu.param1.flags & USE_REG_CR);
1885	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1886	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1887	}
1888	break;
1889
1890	case OP_MOV_DR:
1891	STAM_COUNTER_INC(&pStats->StatMovDRx);
1892	break;
1893	case OP_LLDT:
1894	STAM_COUNTER_INC(&pStats->StatMovLldt);
1895	break;
1896	case OP_LIDT:
1897	STAM_COUNTER_INC(&pStats->StatMovLidt);
1898	break;
1899	case OP_LGDT:
1900	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1901	break;
1902	case OP_SYSENTER:
1903	STAM_COUNTER_INC(&pStats->StatSysEnter);
1904	break;
1905	case OP_SYSEXIT:
1906	STAM_COUNTER_INC(&pStats->StatSysExit);
1907	break;
1908	case OP_SYSCALL:
1909	STAM_COUNTER_INC(&pStats->StatSysCall);
1910	break;
1911	case OP_SYSRET:
1912	STAM_COUNTER_INC(&pStats->StatSysRet);
1913	break;
1914	case OP_HLT:
1915	STAM_COUNTER_INC(&pStats->StatHlt);
1916	break;
1917	default:
1918	STAM_COUNTER_INC(&pStats->StatMisc);
1919	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1920	break;
1921	}
1922	#endif
1923	if ( (pCtx->ss & X86_SEL_RPL) == 0
1924	&& SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid))
1925	{
1926	uint32_t size;
1927
1928	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1929	switch (Cpu.pCurInstr->opcode)
1930	{
1931	case OP_CLI:
1932	pCtx->eflags.u32 &= ~X86_EFL_IF;
1933	Assert(Cpu.opsize == 1);
1934	pCtx->eip += Cpu.opsize;
1935	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1936	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1937
1938	case OP_STI:
1939	pCtx->eflags.u32 \|= X86_EFL_IF;
1940	EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
1941	Assert(Cpu.opsize == 1);
1942	pCtx->eip += Cpu.opsize;
1943	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1944	return VINF_SUCCESS;
1945
1946	case OP_HLT:
1947	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1948	{
1949	PATMTRANSSTATE enmState;
1950	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1951
1952	if (enmState == PATMTRANS_OVERWRITTEN)
1953	{
1954	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1955	Assert(rc == VERR_PATCH_DISABLED);
1956	/* Conflict detected, patch disabled */
1957	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1958
1959	enmState = PATMTRANS_SAFE;
1960	}
1961
1962	/* The translation had better be successful. Otherwise we can't recover. */
1963	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1964	if (enmState != PATMTRANS_OVERWRITTEN)
1965	pCtx->eip = pOrgInstrGC;
1966	}
1967	/* no break; we could just return VINF_EM_HALT here */
1968
1969	case OP_MOV_CR:
1970	case OP_MOV_DR:
1971	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1972	if (VBOX_SUCCESS(rc))
1973	{
1974	pCtx->eip += Cpu.opsize;
1975	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1976
1977	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1978	&& Cpu.param1.flags == USE_REG_CR /* write */
1979	)
1980	{
1981	/* Reschedule is necessary as the execution/paging mode might have changed. */
1982	return VINF_EM_RESCHEDULE;
1983	}
1984	return rc; /* can return VINF_EM_HALT as well. */
1985	}
1986	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1987	break; /* fall back to the recompiler */
1988	}
1989	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1990	}
1991	}
1992
1993	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1994	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1995
1996	return emR3RawExecuteInstruction(pVM, "PRIV");
1997	}
1998
1999
2000	/**
2001	* Update the forced rawmode execution modifier.
2002	*
2003	* This function is called when we're returning from the raw-mode loop(s). If we're
2004	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2005	* if not in patch code, the flag will be cleared.
2006	*
2007	* We should never interrupt patch code while it's being executed. Cli patches can
2008	* contain big code blocks, but they are always executed with IF=0. Other patches
2009	* replace single instructions and should be atomic.
2010	*
2011	* @returns Updated rc.
2012	*
2013	* @param pVM The VM handle.
2014	* @param pCtx The guest CPU context.
2015	* @param rc The result code.
2016	*/
2017	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2018	{
2019	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2020	{
2021	/* ignore reschedule attempts. */
2022	switch (rc)
2023	{
2024	case VINF_EM_RESCHEDULE:
2025	case VINF_EM_RESCHEDULE_REM:
2026	rc = VINF_SUCCESS;
2027	break;
2028	}
2029	pVM->em.s.fForceRAW = true;
2030	}
2031	else
2032	pVM->em.s.fForceRAW = false;
2033	return rc;
2034	}
2035
2036
2037	/**
2038	* Process a subset of the raw-mode return code.
2039	*
2040	* Since we have to share this with raw-mode single stepping, this inline
2041	* function has been created to avoid code duplication.
2042	*
2043	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2044	* @returns VBox status code to return to the EM main loop.
2045	*
2046	* @param pVM The VM handle
2047	* @param rc The return code.
2048	* @param pCtx The guest cpu context.
2049	*/
2050	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2051	{
2052	switch (rc)
2053	{
2054	/*
2055	* Common & simple ones.
2056	*/
2057	case VINF_SUCCESS:
2058	break;
2059	case VINF_EM_RESCHEDULE_RAW:
2060	case VINF_EM_RESCHEDULE_HWACC:
2061	case VINF_EM_RAW_INTERRUPT:
2062	case VINF_EM_RAW_TO_R3:
2063	case VINF_EM_RAW_TIMER_PENDING:
2064	case VINF_EM_PENDING_REQUEST:
2065	rc = VINF_SUCCESS;
2066	break;
2067
2068	/*
2069	* Privileged instruction.
2070	*/
2071	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2072	case VINF_PATM_PATCH_TRAP_GP:
2073	rc = emR3RawPrivileged(pVM);
2074	break;
2075
2076	/*
2077	* Got a trap which needs dispatching.
2078	*/
2079	case VINF_EM_RAW_GUEST_TRAP:
2080	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2081	{
2082	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2083	rc = VERR_EM_RAW_PATCH_CONFLICT;
2084	break;
2085	}
2086	uint8_t u8Interrupt;
2087
2088	Assert(TRPMHasTrap(pVM));
2089	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2090
2091	if (TRPMHasTrap(pVM))
2092	{
2093	u8Interrupt = TRPMGetTrapNo(pVM);
2094
2095	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2096	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2097	{
2098	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2099	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2100	/** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2101	}
2102	}
2103	rc = emR3RawGuestTrap(pVM);
2104	break;
2105
2106	/*
2107	* Trap in patch code.
2108	*/
2109	case VINF_PATM_PATCH_TRAP_PF:
2110	case VINF_PATM_PATCH_INT3:
2111	rc = emR3PatchTrap(pVM, pCtx, rc);
2112	break;
2113
2114	case VINF_PATM_DUPLICATE_FUNCTION:
2115	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2116	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2117	AssertRC(rc);
2118	rc = VINF_SUCCESS;
2119	break;
2120
2121	case VINF_PATM_CHECK_PATCH_PAGE:
2122	rc = PATMR3HandleMonitoredPage(pVM);
2123	AssertRC(rc);
2124	rc = VINF_SUCCESS;
2125	break;
2126
2127	/*
2128	* Patch manager.
2129	*/
2130	case VERR_EM_RAW_PATCH_CONFLICT:
2131	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2132	break;
2133
2134	/*
2135	* Memory mapped I/O access - attempt to patch the instruction
2136	*/
2137	case VINF_PATM_HC_MMIO_PATCH_READ:
2138	rc = PATMR3InstallPatch(pVM, pCtx->eip, PATMFL_MMIO_ACCESS \| (SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2139	if (VBOX_FAILURE(rc))
2140	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2141	break;
2142
2143	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2144	AssertFailed(); /* not yet implemented. */
2145	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2146	break;
2147
2148	/*
2149	* Conflict or out of page tables.
2150	*
2151	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2152	* do here is to execute the pending forced actions.
2153	*/
2154	case VINF_PGM_SYNC_CR3:
2155	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2156	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2157	rc = VINF_SUCCESS;
2158	break;
2159
2160	/*
2161	* Paging mode change.
2162	*/
2163	case VINF_PGM_CHANGE_MODE:
2164	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2165	if (VBOX_SUCCESS(rc))
2166	rc = VINF_EM_RESCHEDULE;
2167	break;
2168
2169	/*
2170	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2171	*/
2172	case VINF_CSAM_PENDING_ACTION:
2173	rc = VINF_SUCCESS;
2174	break;
2175
2176	/*
2177	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2178	*/
2179	case VINF_EM_RAW_INTERRUPT_PENDING:
2180	case VINF_EM_RAW_RING_SWITCH_INT:
2181	{
2182	uint8_t u8Interrupt;
2183
2184	Assert(TRPMHasTrap(pVM));
2185	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2186
2187	if (TRPMHasTrap(pVM))
2188	{
2189	u8Interrupt = TRPMGetTrapNo(pVM);
2190
2191	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2192	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2193	{
2194	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2195	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2196	/** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2197	}
2198	}
2199	rc = VINF_EM_RESCHEDULE_REM;
2200	break;
2201	}
2202
2203	/*
2204	* Other ring switch types.
2205	*/
2206	case VINF_EM_RAW_RING_SWITCH:
2207	rc = emR3RawRingSwitch(pVM);
2208	break;
2209
2210	/*
2211	* REMGCNotifyInvalidatePage() failed because of overflow.
2212	*/
2213	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2214	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2215	REMR3ReplayInvalidatedPages(pVM);
2216	break;
2217
2218	/*
2219	* I/O Port access - emulate the instruction.
2220	*/
2221	case VINF_IOM_HC_IOPORT_READ:
2222	case VINF_IOM_HC_IOPORT_WRITE:
2223	case VINF_IOM_HC_IOPORT_READWRITE:
2224	rc = emR3RawExecuteIOInstruction(pVM);
2225	break;
2226
2227	/*
2228	* Memory mapped I/O access - emulate the instruction.
2229	*/
2230	case VINF_IOM_HC_MMIO_READ:
2231	case VINF_IOM_HC_MMIO_WRITE:
2232	case VINF_IOM_HC_MMIO_READ_WRITE:
2233	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2234	break;
2235
2236	/*
2237	* Execute instruction.
2238	*/
2239	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2240	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2241	break;
2242	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2243	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2244	break;
2245	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2246	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2247	break;
2248	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2249	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2250	break;
2251	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2252	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2253	break;
2254
2255	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2256	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2257	rc = emR3RawPrivileged(pVM);
2258	break;
2259
2260	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2261	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2262	break;
2263
2264	case VINF_EM_RAW_EMULATE_INSTR:
2265	case VINF_PATCH_EMULATE_INSTR:
2266	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2267	break;
2268
2269	/*
2270	* Stale selector and iret traps => REM.
2271	*/
2272	case VINF_EM_RAW_STALE_SELECTOR:
2273	case VINF_EM_RAW_IRET_TRAP:
2274	/* We will not go to the recompiler if EIP points to patch code. */
2275	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2276	{
2277	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2278	}
2279	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2280	rc = VINF_EM_RESCHEDULE_REM;
2281	break;
2282
2283	/*
2284	* Up a level.
2285	*/
2286	case VINF_EM_TERMINATE:
2287	case VINF_EM_OFF:
2288	case VINF_EM_RESET:
2289	case VINF_EM_SUSPEND:
2290	case VINF_EM_HALT:
2291	case VINF_EM_RESUME:
2292	case VINF_EM_RESCHEDULE:
2293	case VINF_EM_RESCHEDULE_REM:
2294	break;
2295
2296	/*
2297	* Up a level and invoke the debugger.
2298	*/
2299	case VINF_EM_DBG_STEPPED:
2300	case VINF_EM_DBG_BREAKPOINT:
2301	case VINF_EM_DBG_STEP:
2302	case VINF_EM_DBG_HYPER_ASSERTION:
2303	case VINF_EM_DBG_HYPER_BREAKPOINT:
2304	case VINF_EM_DBG_HYPER_STEPPED:
2305	case VINF_EM_DBG_STOP:
2306	break;
2307
2308	/*
2309	* Up a level, dump and debug.
2310	*/
2311	case VERR_TRPM_DONT_PANIC:
2312	case VERR_TRPM_PANIC:
2313	break;
2314
2315	/*
2316	* Anything which is not known to us means an internal error
2317	* and the termination of the VM!
2318	*/
2319	default:
2320	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2321	break;
2322	}
2323	return rc;
2324	}
2325
2326
2327	/**
2328	* Process raw-mode specific forced actions.
2329	*
2330	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2331	*
2332	* @returns VBox status code.
2333	* Only the normal success/failure stuff, no VINF_EM_*.
2334	* @param pVM The VM handle.
2335	* @param pCtx The guest CPUM register context.
2336	*/
2337	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2338	{
2339	/*
2340	* Note that the order is vitally important!
2341	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2342	*/
2343
2344
2345	/*
2346	* Sync selector tables.
2347	*/
2348	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2349	{
2350	int rc = SELMR3UpdateFromCPUM(pVM);
2351	if (VBOX_FAILURE(rc))
2352	return rc;
2353	}
2354
2355	/*
2356	* Sync IDT.
2357	*/
2358	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2359	{
2360	int rc = TRPMR3SyncIDT(pVM);
2361	if (VBOX_FAILURE(rc))
2362	return rc;
2363	}
2364
2365	/*
2366	* Sync TSS.
2367	*/
2368	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2369	{
2370	int rc = SELMR3SyncTSS(pVM);
2371	if (VBOX_FAILURE(rc))
2372	return rc;
2373	}
2374
2375	/*
2376	* Sync page directory.
2377	*/
2378	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2379	{
2380	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2381	if (VBOX_FAILURE(rc))
2382	return rc;
2383
2384	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2385
2386	/* Prefetch pages for EIP and ESP */
2387	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2388	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip));
2389	if (rc == VINF_SUCCESS)
2390	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2391	if (rc != VINF_SUCCESS)
2392	{
2393	if (rc != VINF_PGM_SYNC_CR3)
2394	return rc;
2395	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2396	if (VBOX_FAILURE(rc))
2397	return rc;
2398	}
2399	/** @todo maybe prefetch the supervisor stack page as well */
2400	}
2401
2402	return VINF_SUCCESS;
2403	}
2404
2405
2406	/**
2407	* Executes raw code.
2408	*
2409	* This function contains the raw-mode version of the inner
2410	* execution loop (the outer loop being in EMR3ExecuteVM()).
2411	*
2412	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2413	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2414	*
2415	* @param pVM VM handle.
2416	* @param pfFFDone Where to store an indicator telling whether or not
2417	* FFs were done before returning.
2418	*/
2419	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2420	{
2421	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2422
2423	int rc = VERR_INTERNAL_ERROR;
2424	PCPUMCTX pCtx = pVM->em.s.pCtx;
2425	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2426	pVM->em.s.fForceRAW = false;
2427	*pfFFDone = false;
2428
2429
2430	/*
2431	*
2432	* Spin till we get a forced action or raw mode status code resulting in
2433	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2434	*
2435	*/
2436	for (;;)
2437	{
2438	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2439
2440	/*
2441	* Check various preconditions.
2442	*/
2443	#ifdef VBOX_STRICT
2444	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2445	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2446	Assert((pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2447	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2448	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2449	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2450	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2451	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2452	{
2453	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2454	return VERR_INTERNAL_ERROR;
2455	}
2456	#endif /* VBOX_STRICT */
2457
2458	/*
2459	* Process high priority pre-execution raw-mode FFs.
2460	*/
2461	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2462	{
2463	rc = emR3RawForcedActions(pVM, pCtx);
2464	if (VBOX_FAILURE(rc))
2465	break;
2466	}
2467
2468	/*
2469	* If we're going to execute ring-0 code, the guest state needs to
2470	* be modified a bit and some of the state components (IF, SS/CS RPL,
2471	* and perhaps EIP) needs to be stored with PATM.
2472	*/
2473	rc = CPUMRawEnter(pVM, NULL);
2474	if (rc != VINF_SUCCESS)
2475	{
2476	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2477	break;
2478	}
2479
2480	/*
2481	* Scan code before executing it. Don't bother with user mode or V86 code
2482	*/
2483	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2484	&& pCtx->eflags.Bits.u1VM == 0
2485	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2486	{
2487	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2488	CSAMR3CheckCode(pVM, pCtx, pCtx->eip);
2489	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2490	}
2491
2492	#ifdef LOG_ENABLED
2493	/*
2494	* Log important stuff before entering GC.
2495	*/
2496	bool fSingleStep = false;
2497	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2498	if ((pCtx->ss & X86_SEL_RPL) == 1 && !fSingleStep)
2499	{
2500	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2501	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2502	}
2503	else if ((pCtx->ss & X86_SEL_RPL) == 3 && !fSingleStep && pCtx->eflags.Bits.u1VM)
2504	Log(("RV86: %08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2505	else if ((pCtx->ss & X86_SEL_RPL) == 3 && !fSingleStep)
2506	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2507	#endif /* LOG_ENABLED */
2508
2509
2510
2511	/*
2512	* Execute the code.
2513	*/
2514	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2515	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2516	VMMR3Unlock(pVM);
2517	rc = VMMR3RawRunGC(pVM);
2518	VMMR3Lock(pVM);
2519	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2520	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2521
2522	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2523	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2524
2525
2526	/*
2527	* Restore the real CPU state and deal with high priority post
2528	* execution FFs before doing anything else.
2529	*/
2530	rc = CPUMRawLeave(pVM, NULL, rc);
2531	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2532	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2533	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2534
2535	#ifdef PGM_CACHE_VERY_STRICT
2536	/*
2537	* Page manager cache checks.
2538	*/
2539	if ( rc == VINF_EM_RAW_INTERRUPT
2540	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2541	\|\| rc == VINF_IOM_HC_IOPORT_READ
2542	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2543	\|\| rc == VINF_IOM_HC_IOPORT_READWRITE
2544	//\|\| rc == VINF_PATM_PATCH_INT3
2545	)
2546	pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2547	#endif
2548
2549	#ifdef VBOX_STRICT
2550	/*
2551	* Assert TSS consistency & rc vs patch code.
2552	*/
2553	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2554	&& EMIsRawRing0Enabled(pVM))
2555	SELMR3CheckTSS(pVM);
2556	switch (rc)
2557	{
2558	case VINF_SUCCESS:
2559	case VINF_EM_RAW_INTERRUPT:
2560	case VINF_PATM_PATCH_TRAP_PF:
2561	case VINF_PATM_PATCH_TRAP_GP:
2562	case VINF_PATM_PATCH_INT3:
2563	case VINF_PATM_CHECK_PATCH_PAGE:
2564	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2565	case VINF_EM_RAW_GUEST_TRAP:
2566	case VINF_EM_RESCHEDULE_RAW:
2567	break;
2568
2569	default:
2570	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2571	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2572	break;
2573	}
2574	/*
2575	* Let's go paranoid!
2576	*/
2577	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2578	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2579	{
2580	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2581	return VERR_INTERNAL_ERROR;
2582	}
2583	#endif /* VBOX_STRICT */
2584
2585	/*
2586	* Process the returned status code.
2587	*/
2588	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2589	{
2590	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2591	break;
2592	}
2593	rc = emR3RawHandleRC(pVM, pCtx, rc);
2594	if (rc != VINF_SUCCESS)
2595	{
2596	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2597	if (rc != VINF_SUCCESS)
2598	{
2599	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2600	break;
2601	}
2602	}
2603
2604	/*
2605	* Check and execute forced actions.
2606	*/
2607	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2608	TMTimerPoll(pVM);
2609	#endif
2610	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2611	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2612	{
2613	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2614
2615	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2616	rc = emR3ForcedActions(pVM, rc);
2617	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2618	if ( rc != VINF_SUCCESS
2619	&& rc != VINF_EM_RESCHEDULE_RAW)
2620	{
2621	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2622	if (rc != VINF_SUCCESS)
2623	{
2624	*pfFFDone = true;
2625	break;
2626	}
2627	}
2628	}
2629	}
2630
2631	/*
2632	* Return to outer loop.
2633	*/
2634	#if defined(LOG_ENABLED) && defined(DEBUG)
2635	RTLogFlush(NULL);
2636	#endif
2637	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2638	return rc;
2639	}
2640
2641
2642	/**
2643	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2644	*
2645	* This function contains the raw-mode version of the inner
2646	* execution loop (the outer loop being in EMR3ExecuteVM()).
2647	*
2648	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2649	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2650	*
2651	* @param pVM VM handle.
2652	* @param pfFFDone Where to store an indicator telling whether or not
2653	* FFs were done before returning.
2654	*/
2655	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2656	{
2657	int rc = VERR_INTERNAL_ERROR;
2658	PCPUMCTX pCtx = pVM->em.s.pCtx;
2659
2660	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2661	*pfFFDone = false;
2662
2663	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2664
2665	/*
2666	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2667	*/
2668	for (;;)
2669	{
2670	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2671
2672	/*
2673	* Check various preconditions.
2674	*/
2675	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2676
2677	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2678
2679	/*
2680	* Sync page directory.
2681	*/
2682	if (VM_FF_ISPENDING(pVM, (VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)))
2683	{
2684	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2685	if (VBOX_FAILURE(rc))
2686	return rc;
2687
2688	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2689
2690	/* Prefetch pages for EIP and ESP */
2691	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip));
2692	if (rc == VINF_SUCCESS)
2693	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2694	if (rc != VINF_SUCCESS)
2695	{
2696	if (rc != VINF_PGM_SYNC_CR3)
2697	return rc;
2698	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2699	if (VBOX_FAILURE(rc))
2700	return rc;
2701	}
2702
2703	/** @todo maybe prefetch the supervisor stack page as well */
2704	}
2705
2706	#ifdef LOG_ENABLED
2707	uint8_t u8Vector;
2708
2709	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2710	if (rc == VINF_SUCCESS)
2711	{
2712	Log(("Pending hardware interrupt %d\n", u8Vector));
2713	}
2714	/*
2715	* Log important stuff before entering GC.
2716	*/
2717	bool fSingleStep = false;
2718	if ((pCtx->ss & X86_SEL_RPL) == 0 && !fSingleStep)
2719	Log(("HWR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
2720	else if ((pCtx->ss & X86_SEL_RPL) == 3 && !fSingleStep && pCtx->eflags.Bits.u1VM)
2721	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2722	else if ((pCtx->ss & X86_SEL_RPL) == 3 && !fSingleStep)
2723	Log(("HWR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
2724	#endif
2725
2726
2727	/*
2728	* Execute the code.
2729	*/
2730	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2731	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2732	VMMR3Unlock(pVM);
2733	rc = VMMR3HwAccRunGC(pVM);
2734	VMMR3Lock(pVM);
2735	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2736
2737
2738	/*
2739	* Deal with high priority post execution FFs before doing anything else.
2740	*/
2741	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2742	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2743	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2744
2745	/*
2746	* Process the returned status code.
2747	*/
2748	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2749	break;
2750
2751	rc = emR3RawHandleRC(pVM, pCtx, rc);
2752	if (rc != VINF_SUCCESS)
2753	break;
2754
2755	/*
2756	* Check and execute forced actions.
2757	*/
2758	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2759	TMTimerPoll(pVM);
2760	#endif
2761	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2762	{
2763	rc = emR3ForcedActions(pVM, rc);
2764	if ( rc != VINF_SUCCESS
2765	&& rc != VINF_EM_RESCHEDULE_HWACC)
2766	{
2767	*pfFFDone = true;
2768	break;
2769	}
2770	}
2771	}
2772	/*
2773	* Return to outer loop.
2774	*/
2775	#if defined(LOG_ENABLED) && defined(DEBUG)
2776	RTLogFlush(NULL);
2777	#endif
2778	return rc;
2779	}
2780
2781
2782	/**
2783	* Decides whether to execute RAW, HWACC or REM.
2784	*
2785	* @returns new EM state
2786	* @param pVM The VM.
2787	* @param pCtx The CPU context.
2788	*/
2789	inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2790	{
2791	/*
2792	* When forcing raw-mode execution, things are simple.
2793	*/
2794	if (pVM->em.s.fForceRAW)
2795	return EMSTATE_RAW;
2796
2797	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2798	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2799	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2800
2801	X86EFLAGS EFlags = pCtx->eflags;
2802	if (HWACCMIsEnabled(pVM))
2803	{
2804	/* Hardware accelerated raw-mode:
2805	*
2806	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2807	*/
2808	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2809	return EMSTATE_HWACC;
2810
2811	/** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2812	return EMSTATE_REM;
2813	}
2814
2815	/* Standard raw-mode:
2816	*
2817	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2818	* or 32 bits protected mode ring 0 code
2819	*
2820	* The tests are ordered by the likelyhood of being true during normal execution.
2821	*/
2822	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2823	{
2824	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2825	return EMSTATE_REM;
2826	}
2827
2828	#ifndef VBOX_RAW_V86
2829	if (EFlags.u32 & X86_EFL_VM) {
2830	Log2(("raw mode refused: VM_MASK\n"));
2831	return EMSTATE_REM;
2832	}
2833	#endif
2834
2835	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2836	uint32_t u32CR0 = pCtx->cr0;
2837	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2838	{
2839	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2840	return EMSTATE_REM;
2841	}
2842
2843	if (pCtx->cr4 & X86_CR4_PAE)
2844	{
2845	//Log2(("raw mode refused: PAE\n"));
2846	return EMSTATE_REM;
2847	}
2848
2849	unsigned uSS = pCtx->ss;
2850	if ((uSS & X86_SEL_RPL) == 3)
2851	{
2852	if (!EMIsRawRing3Enabled(pVM))
2853	return EMSTATE_REM;
2854
2855	if (!(EFlags.u32 & X86_EFL_IF))
2856	{
2857	#ifdef VBOX_RAW_V86
2858	if(!(EFlags.u32 & X86_EFL_VM))
2859	return EMSTATE_REM;
2860	#else
2861	Log2(("raw mode refused: IF (RawR3)\n"));
2862	return EMSTATE_REM;
2863	#endif
2864	}
2865
2866	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2867	{
2868	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2869	return EMSTATE_REM;
2870	}
2871	}
2872	else
2873	{
2874	if (!EMIsRawRing0Enabled(pVM))
2875	return EMSTATE_REM;
2876
2877	/* Only ring 0 supervisor code. */
2878	if ((uSS & X86_SEL_RPL) != 0)
2879	{
2880	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2881	return EMSTATE_REM;
2882	}
2883
2884	// Let's start with pure 32 bits ring 0 code first
2885	/** @todo What's pure 32-bit mode? flat? */
2886	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2887	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
2888	{
2889	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2890	return EMSTATE_REM;
2891	}
2892
2893	/* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2894	if (!(u32CR0 & X86_CR0_WP))
2895	{
2896	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2897	return EMSTATE_REM;
2898	}
2899
2900	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2901	{
2902	Log2(("raw r0 mode forced: patch code\n"));
2903	return EMSTATE_RAW;
2904	}
2905
2906	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2907	if (!(EFlags.u32 & X86_EFL_IF))
2908	{
2909	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2910	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2911	return EMSTATE_REM;
2912	}
2913	#endif
2914
2915	/** @todo still necessary??? */
2916	if (EFlags.Bits.u2IOPL != 0)
2917	{
2918	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2919	return EMSTATE_REM;
2920	}
2921	}
2922
2923	Assert(PGMPhysIsA20Enabled(pVM));
2924	return EMSTATE_RAW;
2925	}
2926
2927
2928	/**
2929	* Executes all high priority post execution force actions.
2930	*
2931	* @returns rc or a fatal status code.
2932	*
2933	* @param pVM VM handle.
2934	* @param rc The current rc.
2935	*/
2936	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2937	{
2938	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2939	PDMR3CritSectFF(pVM);
2940
2941	if (VM_FF_ISSET(pVM, VM_FF_CSAM_FLUSH_DIRTY_PAGE))
2942	CSAMR3FlushDirtyPages(pVM);
2943
2944	return rc;
2945	}
2946
2947
2948	/**
2949	* Executes all pending forced actions.
2950	*
2951	* Forced actions can cause execution delays and execution
2952	* rescheduling. The first we deal with using action priority, so
2953	* that for instance pending timers aren't scheduled and ran until
2954	* right before execution. The rescheduling we deal with using
2955	* return codes. The same goes for VM termination, only in that case
2956	* we exit everything.
2957	*
2958	* @returns VBox status code of equal or greater importance/severity than rc.
2959	* The most important ones are: VINF_EM_RESCHEDULE,
2960	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2961	*
2962	* @param pVM VM handle.
2963	* @param rc The current rc.
2964	*
2965	*/
2966	static int emR3ForcedActions(PVM pVM, int rc)
2967	{
2968	#ifdef VBOX_STRICT
2969	int rcIrq = VINF_SUCCESS;
2970	#endif
2971	STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2972
2973	#define UPDATE_RC() \
2974	do { \
2975	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2976	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
2977	break; \
2978	if (!rc \|\| rc2 < rc) \
2979	rc = rc2; \
2980	} while (0)
2981
2982	int rc2;
2983
2984	/*
2985	* Post execution chunk first.
2986	*/
2987	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2988	{
2989	/*
2990	* Termination request.
2991	*/
2992	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
2993	{
2994	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
2995	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2996	return VINF_EM_TERMINATE;
2997	}
2998
2999	/*
3000	* Debugger Facility polling.
3001	*/
3002	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3003	{
3004	rc2 = DBGFR3VMMForcedAction(pVM);
3005	UPDATE_RC();
3006	}
3007
3008	/*
3009	* Postponed reset request.
3010	*/
3011	if (VM_FF_ISSET(pVM, VM_FF_RESET))
3012	{
3013	rc2 = VMR3Reset(pVM);
3014	UPDATE_RC();
3015	VM_FF_CLEAR(pVM, VM_FF_RESET);
3016	}
3017
3018	/*
3019	* CSAM page scanning.
3020	*/
3021	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
3022	{
3023	PCPUMCTX pCtx = pVM->em.s.pCtx;
3024
3025	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3026	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3027
3028	CSAMR3CheckCode(pVM, pCtx, pCtx->eip);
3029	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3030	}
3031
3032	/* check that we got them all */
3033	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
3034	}
3035
3036	/*
3037	* Normal priority then.
3038	* (Executed in no particular order.)
3039	*/
3040	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3041	{
3042	/*
3043	* PDM Queues are pending.
3044	*/
3045	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3046	PDMR3QueueFlushAll(pVM);
3047
3048	/*
3049	* PDM DMA transfers are pending.
3050	*/
3051	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3052	PDMR3DmaRun(pVM);
3053
3054	/*
3055	* Requests from other threads.
3056	*/
3057	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3058	{
3059	rc2 = VMR3ReqProcess(pVM);
3060	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3061	{
3062	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3063	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3064	return rc2;
3065	}
3066	UPDATE_RC();
3067	}
3068
3069	/* check that we got them all */
3070	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA)));
3071	}
3072
3073	/*
3074	* Execute polling function ever so often.
3075	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING SOON!
3076	*/
3077	static unsigned cLast = 0;
3078	if (!((++cLast) % 4))
3079	PDMR3Poll(pVM);
3080
3081	/*
3082	* High priority pre execution chunk last.
3083	* (Executed in ascending priority order.)
3084	*/
3085	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3086	{
3087	/*
3088	* Timers before interrupts.
3089	*/
3090	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3091	TMR3TimerQueuesDo(pVM);
3092
3093	/*
3094	* The instruction following an emulated STI should always be executed!
3095	*/
3096	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3097	{
3098	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3099	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3100	{
3101	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3102	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3103	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3104	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3105	*/
3106	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3107	}
3108	if (HWACCMR3IsActive(pVM))
3109	rc2 = VINF_EM_RESCHEDULE_HWACC;
3110	else
3111	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3112
3113	UPDATE_RC();
3114	}
3115
3116	/*
3117	* Interrupts.
3118	*/
3119	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3120	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3121	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3122	&& PATMAreInterruptsEnabled(pVM)
3123	&& !HWACCMR3IsEventPending(pVM))
3124	{
3125	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3126	{
3127	/** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3128	/** @todo this really isn't nice, should properly handle this */
3129	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3130	#ifdef VBOX_STRICT
3131	rcIrq = rc2;
3132	#endif
3133	UPDATE_RC();
3134	}
3135	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3136	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3137	{
3138	rc2 = VINF_EM_RESCHEDULE_REM;
3139	UPDATE_RC();
3140	}
3141	}
3142
3143	/*
3144	* Debugger Facility request.
3145	*/
3146	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3147	{
3148	rc2 = DBGFR3VMMForcedAction(pVM);
3149	UPDATE_RC();
3150	}
3151
3152	/*
3153	* Termination request.
3154	*/
3155	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3156	{
3157	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3158	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3159	return VINF_EM_TERMINATE;
3160	}
3161
3162	#ifdef DEBUG
3163	/*
3164	* Debug, pause the VM.
3165	*/
3166	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3167	{
3168	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3169	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3170	return VINF_EM_SUSPEND;
3171	}
3172
3173	#endif
3174	/* check that we got them all */
3175	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS)));
3176	}
3177
3178	#undef UPDATE_RC
3179	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3180	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3181	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3182	return rc;
3183	}
3184
3185
3186	/**
3187	* Execute VM.
3188	*
3189	* This function is the main loop of the VM. The emulation thread
3190	* calls this function when the VM has been successfully constructed
3191	* and we're ready for executing the VM.
3192	*
3193	* Returning from this function means that the VM is turned off or
3194	* suspended (state already saved) and deconstruction in next in line.
3195	*
3196	* All interaction from other thread are done using forced actions
3197	* and signaling of the wait object.
3198	*
3199	* @returns VBox status code.
3200	* @param pVM The VM to operate on.
3201	*/
3202	EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3203	{
3204	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3205	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3206	VM_ASSERT_EMT(pVM);
3207	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3208
3209	VMMR3Lock(pVM);
3210
3211	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3212	if (rc == 0)
3213	{
3214	/*
3215	* Start the virtual time.
3216	*/
3217	rc = TMVirtualResume(pVM);
3218	Assert(rc == VINF_SUCCESS);
3219	rc = TMCpuTickResume(pVM);
3220	Assert(rc == VINF_SUCCESS);
3221
3222	/*
3223	* The Outer Main Loop.
3224	*/
3225	bool fFFDone = false;
3226	rc = VINF_EM_RESCHEDULE;
3227	pVM->em.s.enmState = EMSTATE_REM;
3228	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3229	for (;;)
3230	{
3231	/*
3232	* Before we can schedule anything (we're here because
3233	* scheduling is required) we must service any pending
3234	* forced actions to avoid any pending action causing
3235	* immidate rescheduling upon entering an inner loop
3236	*
3237	* Do forced actions.
3238	*/
3239	if ( !fFFDone
3240	&& rc != VINF_EM_TERMINATE
3241	&& rc != VINF_EM_OFF
3242	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3243	{
3244	rc = emR3ForcedActions(pVM, rc);
3245	if ( ( rc == VINF_EM_RESCHEDULE_REM
3246	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3247	&& pVM->em.s.fForceRAW)
3248	rc = VINF_EM_RESCHEDULE_RAW;
3249	}
3250	else if (fFFDone)
3251	fFFDone = false;
3252
3253	/*
3254	* Now what to do?
3255	*/
3256	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3257	switch (rc)
3258	{
3259	/*
3260	* Keep doing what we're currently doing.
3261	*/
3262	case VINF_SUCCESS:
3263	break;
3264
3265	/*
3266	* Reschedule - to raw-mode execution.
3267	*/
3268	case VINF_EM_RESCHEDULE_RAW:
3269	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3270	pVM->em.s.enmState = EMSTATE_RAW;
3271	break;
3272
3273	/*
3274	* Reschedule - to hardware accelerated raw-mode execution.
3275	*/
3276	case VINF_EM_RESCHEDULE_HWACC:
3277	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3278	Assert(!pVM->em.s.fForceRAW);
3279	pVM->em.s.enmState = EMSTATE_HWACC;
3280	break;
3281
3282	/*
3283	* Reschedule - to recompiled execution.
3284	*/
3285	case VINF_EM_RESCHEDULE_REM:
3286	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3287	pVM->em.s.enmState = EMSTATE_REM;
3288	break;
3289
3290	/*
3291	* Resume.
3292	*/
3293	case VINF_EM_RESUME:
3294	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3295	/* fall through and get scheduled. */
3296
3297	/*
3298	* Reschedule.
3299	*/
3300	case VINF_EM_RESCHEDULE:
3301	{
3302	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3303	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3304	pVM->em.s.enmState = enmState;
3305	break;
3306	}
3307
3308	/*
3309	* Halted.
3310	*/
3311	case VINF_EM_HALT:
3312	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3313	pVM->em.s.enmState = EMSTATE_HALTED;
3314	break;
3315
3316	/*
3317	* Suspend.
3318	*/
3319	case VINF_EM_SUSPEND:
3320	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3321	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3322	break;
3323
3324	/*
3325	* Reset.
3326	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3327	*/
3328	case VINF_EM_RESET:
3329	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3330	pVM->em.s.enmState = EMSTATE_REM;
3331	break;
3332
3333	/*
3334	* Power Off.
3335	*/
3336	case VINF_EM_OFF:
3337	pVM->em.s.enmState = EMSTATE_TERMINATING;
3338	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3339	TMVirtualPause(pVM);
3340	TMCpuTickPause(pVM);
3341	VMMR3Unlock(pVM);
3342	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3343	return rc;
3344
3345	/*
3346	* Terminate the VM.
3347	*/
3348	case VINF_EM_TERMINATE:
3349	pVM->em.s.enmState = EMSTATE_TERMINATING;
3350	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3351	TMVirtualPause(pVM);
3352	TMCpuTickPause(pVM);
3353	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3354	return rc;
3355
3356	/*
3357	* Guest debug events.
3358	*/
3359	case VINF_EM_DBG_STEPPED:
3360	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3361	case VINF_EM_DBG_STOP:
3362	case VINF_EM_DBG_BREAKPOINT:
3363	case VINF_EM_DBG_STEP:
3364	if (pVM->em.s.enmState == EMSTATE_RAW)
3365	{
3366	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3367	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3368	}
3369	else
3370	{
3371	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3372	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3373	}
3374	break;
3375
3376	/*
3377	* Hypervisor debug events.
3378	*/
3379	case VINF_EM_DBG_HYPER_STEPPED:
3380	case VINF_EM_DBG_HYPER_BREAKPOINT:
3381	case VINF_EM_DBG_HYPER_ASSERTION:
3382	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3383	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3384	break;
3385
3386	/*
3387	* Any error code showing up here other than the ones we
3388	* know and process above are considered to be FATAL.
3389	*
3390	* Unknown warnings and informational status codes are also
3391	* included in this.
3392	*/
3393	default:
3394	if (VBOX_SUCCESS(rc))
3395	{
3396	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3397	rc = VERR_EM_INTERNAL_ERROR;
3398	}
3399	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3400	Log(("EMR3ExecuteVM returns %d\n", rc));
3401	break;
3402	}
3403
3404
3405	/*
3406	* Any waiters can now be woken up
3407	*/
3408	VMMR3Unlock(pVM);
3409	VMMR3Lock(pVM);
3410
3411	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3412	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3413
3414	/*
3415	* Act on the state.
3416	*/
3417	switch (pVM->em.s.enmState)
3418	{
3419	/*
3420	* Execute raw.
3421	*/
3422	case EMSTATE_RAW:
3423	rc = emR3RawExecute(pVM, &fFFDone);
3424	break;
3425
3426	/*
3427	* Execute hardware accelerated raw.
3428	*/
3429	case EMSTATE_HWACC:
3430	rc = emR3HwAccExecute(pVM, &fFFDone);
3431	break;
3432
3433	/*
3434	* Execute recompiled.
3435	*/
3436	case EMSTATE_REM:
3437	#if 0
3438	/* simulate a runtime error */
3439	VMSetRuntimeError (pVM, true, "simulatedError", "pVM=%p", pVM);
3440	#endif
3441	rc = emR3RemExecute(pVM, &fFFDone);
3442	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3443	break;
3444
3445	/*
3446	* hlt - execution halted until interrupt.
3447	*/
3448	case EMSTATE_HALTED:
3449	{
3450	STAM_PROFILE_START(&pVM->em.s.StatHalted, y);
3451	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3452	STAM_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3453	break;
3454	}
3455
3456	/*
3457	* Suspended - return to VM.cpp.
3458	*/
3459	case EMSTATE_SUSPENDED:
3460	TMVirtualPause(pVM);
3461	TMCpuTickPause(pVM);
3462	VMMR3Unlock(pVM);
3463	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3464	return VINF_EM_SUSPEND;
3465
3466	/*
3467	* Debugging in the guest.
3468	*/
3469	case EMSTATE_DEBUG_GUEST_REM:
3470	case EMSTATE_DEBUG_GUEST_RAW:
3471	TMVirtualPause(pVM);
3472	TMCpuTickPause(pVM);
3473	rc = emR3Debug(pVM, rc);
3474	TMVirtualResume(pVM);
3475	TMCpuTickResume(pVM);
3476	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3477	break;
3478
3479	/*
3480	* Debugging in the hypervisor.
3481	*/
3482	case EMSTATE_DEBUG_HYPER:
3483	{
3484	TMVirtualPause(pVM);
3485	TMCpuTickPause(pVM);
3486	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3487
3488	rc = emR3Debug(pVM, rc);
3489	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3490	if (rc != VINF_SUCCESS)
3491	{
3492	/* switch to guru meditation mode */
3493	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3494	VMMR3FatalDump(pVM, rc);
3495	return rc;
3496	}
3497
3498	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3499	TMVirtualResume(pVM);
3500	TMCpuTickResume(pVM);
3501	break;
3502	}
3503
3504	/*
3505	* Guru meditation takes place in the debugger.
3506	*/
3507	case EMSTATE_GURU_MEDITATION:
3508	{
3509	/** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3510	TMVirtualPause(pVM);
3511	TMCpuTickPause(pVM);
3512	VMMR3FatalDump(pVM, rc);
3513	int rc2 = emR3Debug(pVM, rc);
3514	if (rc2 == VERR_DBGF_NOT_ATTACHED)
3515	{
3516	VMMR3Unlock(pVM);
3517	/** @todo change the VM state! */
3518	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3519	return rc;
3520	}
3521	TMVirtualResume(pVM);
3522	TMCpuTickResume(pVM);
3523	rc = rc2;
3524	/** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3525	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3526	break;
3527	}
3528
3529	/*
3530	* The states we don't expect here.
3531	*/
3532	case EMSTATE_NONE:
3533	case EMSTATE_TERMINATING:
3534	default:
3535	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3536	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3537	TMVirtualPause(pVM);
3538	TMCpuTickPause(pVM);
3539	VMMR3Unlock(pVM);
3540	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3541	return VERR_EM_INTERNAL_ERROR;
3542	}
3543	} /* The Outer Main Loop */
3544	}
3545	else
3546	{
3547	/*
3548	* Fatal error.
3549	*/
3550	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3551	TMVirtualPause(pVM);
3552	TMCpuTickPause(pVM);
3553	VMMR3FatalDump(pVM, rc);
3554	emR3Debug(pVM, rc);
3555	VMMR3Unlock(pVM);
3556	/** @todo change the VM state! */
3557	return rc;
3558	}
3559
3560	/* (won't ever get here). */
3561	AssertFailed();
3562	}
3563

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 1073

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