VirtualBox

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 1132

Last change on this file since 1132 was 1091, checked in by vboxsync, 18 years ago

Corrected assertions for v86 mode
PATM & CSAM changes
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 144.6 KB
Line 
1/* $Id: EM.cpp 1091 2007-02-28 08:46:10Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor/Manager.
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22
23/** @page pg_em EM - The Execution Monitor/Manager
24 *
25 * The Execution Monitor/Manager is responsible for running the VM, scheduling
26 * the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27 * the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28 * the VM.
29 *
30 */
31
32/*******************************************************************************
33* Header Files *
34*******************************************************************************/
35#define LOG_GROUP LOG_GROUP_EM
36#include <VBox/em.h>
37#include <VBox/vmm.h>
38#include <VBox/patm.h>
39#include <VBox/csam.h>
40#include <VBox/selm.h>
41#include <VBox/trpm.h>
42#include <VBox/iom.h>
43#include <VBox/dbgf.h>
44#include <VBox/pgm.h>
45#include <VBox/rem.h>
46#include <VBox/tm.h>
47#include <VBox/mm.h>
48#include <VBox/pdm.h>
49#include <VBox/hwaccm.h>
50#include <VBox/patm.h>
51#include "EMInternal.h"
52#include <VBox/vm.h>
53#include <VBox/cpumdis.h>
54#include <VBox/dis.h>
55#include <VBox/disopcode.h>
56#include <VBox/dbgf.h>
57
58#include <VBox/log.h>
59#include <iprt/thread.h>
60#include <iprt/assert.h>
61#include <iprt/asm.h>
62#include <iprt/semaphore.h>
63#include <iprt/string.h>
64#include <iprt/avl.h>
65#include <iprt/stream.h>
66#include <VBox/param.h>
67#include <VBox/err.h>
68
69
70/*******************************************************************************
71* Internal Functions *
72*******************************************************************************/
73static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
74static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
75static int emR3Debug(PVM pVM, int rc);
76static int emR3RemStep(PVM pVM);
77static int emR3RemExecute(PVM pVM, bool *pfFFDone);
78static int emR3RawResumeHyper(PVM pVM);
79static int emR3RawStep(PVM pVM);
80DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
81DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
82static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
83static int emR3RawExecute(PVM pVM, bool *pfFFDone);
84DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
85static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
86static int emR3ForcedActions(PVM pVM, int rc);
87static int emR3RawGuestTrap(PVM pVM);
88
89
90/**
91 * Initializes the EM.
92 *
93 * @returns VBox status code.
94 * @param pVM The VM to operate on.
95 */
96EMR3DECL(int) EMR3Init(PVM pVM)
97{
98 LogFlow(("EMR3Init\n"));
99 /*
100 * Assert alignment and sizes.
101 */
102 AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
103 AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
104 AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
105 ("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
106
107 /*
108 * Init the structure.
109 */
110 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
111 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
112 if (VBOX_FAILURE(rc))
113 pVM->fRawR3Enabled = true;
114 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
115 if (VBOX_FAILURE(rc))
116 pVM->fRawR0Enabled = true;
117 Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
118 pVM->em.s.enmState = EMSTATE_NONE;
119 pVM->em.s.fForceRAW = false;
120
121 rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
122 AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
123 pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
124 AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
125
126 /*
127 * Saved state.
128 */
129 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
130 NULL, emR3Save, NULL,
131 NULL, emR3Load, NULL);
132 if (VBOX_FAILURE(rc))
133 return rc;
134
135 /*
136 * Statistics.
137 */
138#ifdef VBOX_WITH_STATISTICS
139 PEMSTATS pStats;
140 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
141 if (VBOX_FAILURE(rc))
142 return rc;
143 pVM->em.s.pStatsHC = pStats;
144 pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
145
146 STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
147 STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
148
149 STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
150 STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
151
152 STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
153 STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
154 STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
155 STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
156 STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
157 STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
158 STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
159 STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
160 STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
161 STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
162 STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
163 STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
164 STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
165 STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
166 STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
167 STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
168 STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
169 STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
170 STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
171 STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
172 STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
173 STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
174 STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
175 STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
176 STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
177 STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
178 STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
179 STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
180 STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
181 STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
182 STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
183 STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
184 STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
185 //STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
186 STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
187 STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
188 STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
189 STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
190 STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
191 STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
192 STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
193 STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
194 STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
195 STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
196
197 STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
198 STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
199
200 STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
201 STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
202 STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
203 STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
204 STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
205 STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
206 STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
207 STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
208 STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
209 STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
210 STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
211 STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
212 STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
213 STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
214 STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
215 STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
216 STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
217 STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
218 STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
219 STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
220 STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
221 STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
222 STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
223 STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
224 STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
225 STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
226 STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
227 STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
228 STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
229 STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
230 STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
231 STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
232 STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
233 STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
234 STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
235 STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
236 STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
237 //STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
238
239 STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
240 STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
241 STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
242 STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
243 STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
244 STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
245 STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
246 STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
247 STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
248 STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
249 STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
250 STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
251 STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
252 STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
253 STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
254 STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
255 STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
256 STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
257 STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
258 STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
259 STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
260 STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
261
262 STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
263 STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
264 STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
265 STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
266
267 STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
268 STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
269 STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
270 STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
271 STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
272 STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
273 STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
274 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
275 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
276 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
277 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
278 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
279 STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
280 STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
281 STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
282 STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
283 STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
284 STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
285 STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
286 STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
287 STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
288 STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
289 STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
290 STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
291 STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
292 STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
293
294 STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
295 pVM->em.s.pCliStatTree = 0;
296#endif /* VBOX_WITH_STATISTICS */
297
298/* these should be considered for release statistics. */
299 STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
300 STAM_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
301 STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
302 STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
303 STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
304 STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
305 STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
306 STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
307 STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
308 STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
309 STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
310 STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
311 STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
312 STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
313 STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
314 STAM_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
315
316
317 return VINF_SUCCESS;
318}
319
320
321
322/**
323 * Applies relocations to data and code managed by this
324 * component. This function will be called at init and
325 * whenever the VMM need to relocate it self inside the GC.
326 *
327 * @param pVM The VM.
328 */
329EMR3DECL(void) EMR3Relocate(PVM pVM)
330{
331 LogFlow(("EMR3Relocate\n"));
332 if (pVM->em.s.pStatsHC)
333 pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
334}
335
336
337/**
338 * Reset notification.
339 *
340 * @param pVM
341 */
342EMR3DECL(void) EMR3Reset(PVM pVM)
343{
344 LogFlow(("EMR3Reset: \n"));
345 pVM->em.s.fForceRAW = false;
346}
347
348
349/**
350 * Terminates the EM.
351 *
352 * Termination means cleaning up and freeing all resources,
353 * the VM it self is at this point powered off or suspended.
354 *
355 * @returns VBox status code.
356 * @param pVM The VM to operate on.
357 */
358EMR3DECL(int) EMR3Term(PVM pVM)
359{
360 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
361
362 return VINF_SUCCESS;
363}
364
365
366/**
367 * Execute state save operation.
368 *
369 * @returns VBox status code.
370 * @param pVM VM Handle.
371 * @param pSSM SSM operation handle.
372 */
373static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
374{
375 return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
376}
377
378
379/**
380 * Execute state load operation.
381 *
382 * @returns VBox status code.
383 * @param pVM VM Handle.
384 * @param pSSM SSM operation handle.
385 * @param u32Version Data layout version.
386 */
387static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
388{
389 /*
390 * Validate version.
391 */
392 if (u32Version != EM_SAVED_STATE_VERSION)
393 {
394 Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
395 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
396 }
397
398 /*
399 * Load the saved state.
400 */
401 int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
402 if (VBOX_FAILURE(rc))
403 pVM->em.s.fForceRAW = false;
404
405 Assert(pVM->em.s.pCliStatTree == 0);
406 return rc;
407}
408
409
410/**
411 * Enables or disables a set of raw-mode execution modes.
412 *
413 * @returns VINF_SUCCESS on success.
414 * @returns VINF_RESCHEDULE if a rescheduling might be required.
415 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
416 *
417 * @param pVM The VM to operate on.
418 * @param enmMode The execution mode change.
419 * @thread The emulation thread.
420 */
421EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
422{
423 switch (enmMode)
424 {
425 case EMRAW_NONE:
426 pVM->fRawR3Enabled = false;
427 pVM->fRawR0Enabled = false;
428 break;
429 case EMRAW_RING3_ENABLE:
430 pVM->fRawR3Enabled = true;
431 break;
432 case EMRAW_RING3_DISABLE:
433 pVM->fRawR3Enabled = false;
434 break;
435 case EMRAW_RING0_ENABLE:
436 pVM->fRawR0Enabled = true;
437 break;
438 case EMRAW_RING0_DISABLE:
439 pVM->fRawR0Enabled = false;
440 break;
441 default:
442 AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
443 return VERR_INVALID_PARAMETER;
444 }
445 Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
446 pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
447 return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
448}
449
450
451/**
452 * Raise a fatal error.
453 *
454 * Safely terminate the VM with full state report and stuff. This function
455 * will naturally never return.
456 *
457 * @param pVM VM handle.
458 * @param rc VBox status code.
459 */
460EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
461{
462 longjmp(pVM->em.s.u.FatalLongJump, rc);
463 AssertReleaseMsgFailed(("longjmp returned!\n"));
464}
465
466
467/**
468 * Gets the EM state name.
469 *
470 * @returns pointer to read only state name,
471 * @param enmState The state.
472 */
473EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
474{
475 switch (enmState)
476 {
477 case EMSTATE_RAW: return "EMSTATE_RAW";
478 case EMSTATE_HWACC: return "EMSTATE_HWACC";
479 case EMSTATE_REM: return "EMSTATE_REM";
480 case EMSTATE_HALTED: return "EMSTATE_HALTED";
481 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
482 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
483 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
484 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
485 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
486 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
487 default: return "Unknown!";
488 }
489}
490
491
492#ifdef VBOX_WITH_STATISTICS
493/**
494 * Just a braindead function to keep track of cli addresses.
495 * @param pVM VM handle.
496 * @param pInstrGC The EIP of the cli instruction.
497 */
498static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
499{
500 PCLISTAT pRec;
501
502 pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
503 if (!pRec)
504 {
505 /* New cli instruction; insert into the tree. */
506 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
507 Assert(pRec);
508 if (!pRec)
509 return;
510 pRec->Core.Key = (AVLPVKEY)pInstrGC;
511
512 char szCliStatName[32];
513 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
514 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
515
516 bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
517 Assert(fRc); NOREF(fRc);
518 }
519 STAM_COUNTER_INC(&pRec->Counter);
520 STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
521}
522#endif /* VBOX_WITH_STATISTICS */
523
524
525/**
526 * Debug loop.
527 *
528 * @returns VBox status code for EM.
529 * @param pVM VM handle.
530 * @param rc Current EM VBox status code..
531 */
532static int emR3Debug(PVM pVM, int rc)
533{
534 for (;;)
535 {
536 Log(("emR3Debug: rc=%Vrc\n", rc));
537 const int rcLast = rc;
538
539 /*
540 * Debug related RC.
541 */
542 switch (rc)
543 {
544 /*
545 * Single step an instruction.
546 */
547 case VINF_EM_DBG_STEP:
548 if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
549 || pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
550 || pVM->em.s.fForceRAW /* paranoia */)
551 rc = emR3RawStep(pVM);
552 else
553 {
554 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
555 rc = emR3RemStep(pVM);
556 }
557 break;
558
559 /*
560 * Simple events: stepped, breakpoint, stop/assertion.
561 */
562 case VINF_EM_DBG_STEPPED:
563 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
564 break;
565
566 case VINF_EM_DBG_BREAKPOINT:
567 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
568 break;
569
570 case VINF_EM_DBG_STOP:
571 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
572 break;
573
574 case VINF_EM_DBG_HYPER_STEPPED:
575 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
576 break;
577
578 case VINF_EM_DBG_HYPER_BREAKPOINT:
579 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
580 break;
581
582 case VINF_EM_DBG_HYPER_ASSERTION:
583 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
584 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
585 break;
586
587 /*
588 * Guru meditation.
589 */
590 default: /** @todo don't use default for guru, but make special errors code! */
591 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
592 break;
593 }
594
595 /*
596 * Process the result.
597 */
598 do
599 {
600 switch (rc)
601 {
602 /*
603 * Continue the debugging loop.
604 */
605 case VINF_EM_DBG_STEP:
606 case VINF_EM_DBG_STOP:
607 case VINF_EM_DBG_STEPPED:
608 case VINF_EM_DBG_BREAKPOINT:
609 case VINF_EM_DBG_HYPER_STEPPED:
610 case VINF_EM_DBG_HYPER_BREAKPOINT:
611 case VINF_EM_DBG_HYPER_ASSERTION:
612 break;
613
614 /*
615 * Resuming execution (in some form) has to be done here if we got
616 * a hypervisor debug event.
617 */
618 case VINF_SUCCESS:
619 case VINF_EM_RESUME:
620 case VINF_EM_SUSPEND:
621 case VINF_EM_RESCHEDULE:
622 case VINF_EM_RESCHEDULE_RAW:
623 case VINF_EM_RESCHEDULE_REM:
624 case VINF_EM_HALT:
625 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
626 {
627 rc = emR3RawResumeHyper(pVM);
628 if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
629 continue;
630 }
631 if (rc == VINF_SUCCESS)
632 rc = VINF_EM_RESCHEDULE;
633 return rc;
634
635 /*
636 * The debugger isn't attached.
637 * We'll simply turn the thing off since that's the easiest thing to do.
638 */
639 case VERR_DBGF_NOT_ATTACHED:
640 switch (rcLast)
641 {
642 case VINF_EM_DBG_HYPER_ASSERTION:
643 case VINF_EM_DBG_HYPER_STEPPED:
644 case VINF_EM_DBG_HYPER_BREAKPOINT:
645 return rcLast;
646 }
647 return VINF_EM_OFF;
648
649 /*
650 * Status codes terminating the VM in one or another sense.
651 */
652 case VINF_EM_TERMINATE:
653 case VINF_EM_OFF:
654 case VINF_EM_RESET:
655 case VINF_EM_RAW_STALE_SELECTOR:
656 case VINF_EM_RAW_IRET_TRAP:
657 case VERR_TRPM_PANIC:
658 case VERR_TRPM_DONT_PANIC:
659 case VERR_INTERNAL_ERROR:
660 return rc;
661
662 /*
663 * The rest is unexpected, and will keep us here.
664 */
665 default:
666 AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
667 break;
668 }
669 } while (false);
670 } /* debug for ever */
671}
672
673
674/**
675 * Steps recompiled code.
676 *
677 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
678 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
679 *
680 * @param pVM VM handle.
681 */
682static int emR3RemStep(PVM pVM)
683{
684 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
685
686 /*
687 * Switch to REM, step instruction, switch back.
688 */
689 int rc = REMR3State(pVM);
690 if (VBOX_SUCCESS(rc))
691 {
692 rc = REMR3Step(pVM);
693 REMR3StateBack(pVM);
694 }
695 LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
696 return rc;
697}
698
699/**
700 * Executes recompiled code.
701 *
702 * This function contains the recompiler version of the inner
703 * execution loop (the outer loop being in EMR3ExecuteVM()).
704 *
705 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
706 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
707 *
708 * @param pVM VM handle.
709 * @param pfFFDone Where to store an indicator telling wheter or not
710 * FFs were done before returning.
711 *
712 */
713static int emR3RemExecute(PVM pVM, bool *pfFFDone)
714{
715#ifdef LOG_ENABLED
716 PCPUMCTX pCtx = pVM->em.s.pCtx;
717 if (pCtx->eflags.Bits.u1VM)
718 Log(("EMV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
719 else if ((pCtx->ss & X86_SEL_RPL) == 0)
720 Log(("EMR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
721 else if ((pCtx->ss & X86_SEL_RPL) == 3)
722 Log(("EMR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
723#endif
724 STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
725
726#if defined(VBOX_STRICT) && defined(DEBUG_bird)
727 AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
728 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
729 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
730#endif
731
732 /*
733 * Spin till we get a forced action which returns anything but VINF_SUCCESS
734 * or the REM suggests raw-mode execution.
735 */
736 *pfFFDone = false;
737 bool fInREMState = false;
738 int rc = VINF_SUCCESS;
739 for (;;)
740 {
741 /*
742 * Update REM state if not already in sync.
743 */
744 if (!fInREMState)
745 {
746 STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
747 rc = REMR3State(pVM);
748 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
749 if (VBOX_FAILURE(rc))
750 break;
751 fInREMState = true;
752
753 /*
754 * We might have missed the raising of VMREQ, TIMER and some other
755 * imporant FFs while we were busy switching the state. So, check again.
756 */
757 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_TIMER | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_RESET))
758 {
759 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
760 goto l_REMDoForcedActions;
761 }
762 }
763
764
765 /*
766 * Execute REM.
767 */
768 STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
769 rc = REMR3Run(pVM);
770 STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
771
772
773 /*
774 * Deal with high priority post execution FFs before doing anything else.
775 */
776 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
777 rc = emR3HighPriorityPostForcedActions(pVM, rc);
778
779 /*
780 * Process the returned status code.
781 * (Try keep this short! Call functions!)
782 */
783 if (rc != VINF_SUCCESS)
784 {
785 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
786 break;
787 if (rc != VINF_REM_INTERRUPED_FF)
788 {
789 /*
790 * Anything which is not known to us means an internal error
791 * and the termination of the VM!
792 */
793 AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
794 break;
795 }
796 }
797
798
799 /*
800 * Check and execute forced actions.
801 * Sync back the VM state before calling any of these.
802 */
803#ifdef VBOX_HIGH_RES_TIMERS_HACK
804 TMTimerPoll(pVM);
805#endif
806 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_FLUSH_DIRTY_PAGE | VM_FF_CSAM_SCAN_PAGE)))
807 {
808l_REMDoForcedActions:
809 if (fInREMState)
810 {
811 STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
812 REMR3StateBack(pVM);
813 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
814 fInREMState = false;
815 }
816 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
817 rc = emR3ForcedActions(pVM, rc);
818 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
819 if ( rc != VINF_SUCCESS
820 && rc != VINF_EM_RESCHEDULE_REM)
821 {
822 *pfFFDone = true;
823 break;
824 }
825 }
826
827 } /* The Inner Loop, recompiled execution mode version. */
828
829
830 /*
831 * Returning. Sync back the VM state if required.
832 */
833 if (fInREMState)
834 {
835 STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
836 REMR3StateBack(pVM);
837 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
838 }
839
840 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
841 return rc;
842}
843
844
845/**
846 * Resumes executing hypervisor after a debug event.
847 *
848 * This is kind of special since our current guest state is
849 * potentially out of sync.
850 *
851 * @returns VBox status code.
852 * @param pVM The VM handle.
853 */
854static int emR3RawResumeHyper(PVM pVM)
855{
856 int rc;
857 PCPUMCTX pCtx = pVM->em.s.pCtx;
858 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
859 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
860
861 /*
862 * Resume execution.
863 */
864 CPUMRawEnter(pVM, NULL);
865 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_RF);
866 rc = VMMR3ResumeHyper(pVM);
867 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
868 rc = CPUMRawLeave(pVM, NULL, rc);
869 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
870
871 /*
872 * Deal with the return code.
873 */
874 rc = emR3HighPriorityPostForcedActions(pVM, rc);
875 rc = emR3RawHandleRC(pVM, pCtx, rc);
876 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
877 return rc;
878}
879
880
881/**
882 * Steps rawmode.
883 *
884 * @returns VBox status code.
885 * @param pVM The VM handle.
886 */
887static int emR3RawStep(PVM pVM)
888{
889 Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
890 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
891 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
892 int rc;
893 PCPUMCTX pCtx = pVM->em.s.pCtx;
894 bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
895#ifndef DEBUG_sandervl
896 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
897 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
898#endif
899 if (fGuest)
900 {
901 /*
902 * Check vital forced actions, but ignore pending interrupts and timers.
903 */
904 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
905 {
906 rc = emR3RawForcedActions(pVM, pCtx);
907 if (VBOX_FAILURE(rc))
908 return rc;
909 }
910
911 /*
912 * Set flags for single stepping.
913 */
914 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
915 }
916 else
917 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
918
919 /*
920 * Single step.
921 * We do not start time or anything, if anything we should just do a few nanoseconds.
922 */
923 CPUMRawEnter(pVM, NULL);
924 do
925 {
926 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
927 rc = VMMR3ResumeHyper(pVM);
928 else
929 rc = VMMR3RawRunGC(pVM);
930#ifndef DEBUG_sandervl
931 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
932 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
933#endif
934 } while ( rc == VINF_SUCCESS
935 || rc == VINF_EM_RAW_INTERRUPT);
936 rc = CPUMRawLeave(pVM, NULL, rc);
937 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
938
939 /*
940 * Make sure the trap flag is cleared.
941 * (Too bad if the guest is trying to single step too.)
942 */
943 if (fGuest)
944 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
945 else
946 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
947
948 /*
949 * Deal with the return codes.
950 */
951 rc = emR3HighPriorityPostForcedActions(pVM, rc);
952 rc = emR3RawHandleRC(pVM, pCtx, rc);
953 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
954 return rc;
955}
956
957#ifdef DEBUG_sandervl
958void emR3SingleStepExec(PVM pVM, uint32_t cIterations)
959{
960 EMSTATE enmOldState = pVM->em.s.enmState;
961 PCPUMCTX pCtx = pVM->em.s.pCtx;
962
963 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
964
965 Log(("Single step BEGIN:\n"));
966 for(uint32_t i=0;i<cIterations;i++)
967 {
968 DBGFR3PrgStep(pVM);
969 emR3RawStep(pVM);
970 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
971 }
972 Log(("Single step END:\n"));
973 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
974 pVM->em.s.enmState = enmOldState;
975}
976#endif
977
978/**
979 * Executes one (or perhaps a few more) instruction(s).
980 *
981 * @returns VBox status code suitable for EM.
982 *
983 * @param pVM VM handle.
984 * @param rcGC GC return code
985 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
986 * instruction and prefix the log output with this text.
987 */
988#ifdef LOG_ENABLED
989static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
990#else
991static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
992#endif
993{
994 PCPUMCTX pCtx = pVM->em.s.pCtx;
995 int rc;
996
997 /*
998 *
999 * The simple solution is to use the recompiler.
1000 * The better solution is to disassemble the current instruction and
1001 * try handle as many as possible without using REM.
1002 *
1003 */
1004
1005#ifdef LOG_ENABLED
1006 /*
1007 * Disassemble the instruction if requested.
1008 */
1009 if (pszPrefix)
1010 {
1011 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1012 DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1013 }
1014#endif /* LOG_ENABLED */
1015
1016
1017 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) != 1);
1018
1019 /*
1020 * PATM is making life more interesting.
1021 * We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1022 * tell PATM there is a trap in this code and have it take the appropriate actions
1023 * to allow us execute the code in REM.
1024 */
1025 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1026 {
1027 Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
1028
1029 RTGCPTR pNewEip;
1030 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1031 switch (rc)
1032 {
1033 /*
1034 * It's not very useful to emulate a single instruction and then go back to raw
1035 * mode; just execute the whole block until IF is set again.
1036 */
1037 case VINF_SUCCESS:
1038 Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1039 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1040 pCtx->eip = pNewEip;
1041 Assert(pCtx->eip);
1042
1043 if (pCtx->eflags.Bits.u1IF)
1044 {
1045 /*
1046 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1047 */
1048 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1049 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1050 }
1051#if 0 /** @note no noticable change; revisit later when we can emulate iret ourselves. */
1052 else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1053 {
1054 /* special case: iret, that sets IF, detected a pending irq/event */
1055 return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1056 }
1057#endif
1058 return VINF_EM_RESCHEDULE_REM;
1059
1060 /*
1061 * One instruction.
1062 */
1063 case VINF_PATCH_EMULATE_INSTR:
1064 Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1065 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1066 pCtx->eip = pNewEip;
1067 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1068
1069 /*
1070 * The patch was disabled, hand it to the REM.
1071 */
1072 case VERR_PATCH_DISABLED:
1073 Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1074 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1075 pCtx->eip = pNewEip;
1076 if (pCtx->eflags.Bits.u1IF)
1077 {
1078 /*
1079 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1080 */
1081 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1082 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1083 }
1084 return VINF_EM_RESCHEDULE_REM;
1085
1086 /* Force continued patch exection; usually due to write monitored stack. */
1087 case VINF_PATCH_CONTINUE:
1088 return VINF_SUCCESS;
1089
1090 default:
1091 AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1092 return VERR_INTERNAL_ERROR;
1093 }
1094 }
1095
1096#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1097 DISCPUSTATE Cpu;
1098 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1099 if (VBOX_SUCCESS(rc))
1100 {
1101 uint32_t size;
1102
1103 switch (Cpu.pCurInstr->opcode)
1104 {
1105 case OP_MOV:
1106 case OP_AND:
1107 case OP_OR:
1108 case OP_XOR:
1109 case OP_POP:
1110 case OP_INC:
1111 case OP_DEC:
1112 case OP_XCHG:
1113 STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1114 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1115 if (VBOX_SUCCESS(rc))
1116 {
1117 pCtx->eip += Cpu.opsize;
1118 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1119 return rc;
1120 }
1121 if (rc != VERR_EM_INTERPRETER)
1122 AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1123 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1124 break;
1125 }
1126 }
1127#endif
1128 STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1129 rc = REMR3EmulateInstruction(pVM);
1130 STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1131
1132 return rc;
1133}
1134
1135
1136/**
1137 * Executes one (or perhaps a few more) instruction(s).
1138 * This is just a wrapper for discarding pszPrefix in non-logging builds.
1139 *
1140 * @returns VBox status code suitable for EM.
1141 * @param pVM VM handle.
1142 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1143 * instruction and prefix the log output with this text.
1144 * @param rcGC GC return code
1145 */
1146DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1147{
1148#ifdef LOG_ENABLED
1149 return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1150#else
1151 return emR3RawExecuteInstructionWorker(pVM, rcGC);
1152#endif
1153}
1154
1155/**
1156 * Executes one (or perhaps a few more) IO instruction(s).
1157 *
1158 * @returns VBox status code suitable for EM.
1159 * @param pVM VM handle.
1160 */
1161int emR3RawExecuteIOInstruction(PVM pVM)
1162{
1163 int rc;
1164 PCPUMCTX pCtx = pVM->em.s.pCtx;
1165
1166 STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1167
1168 /** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1169 * as io instructions tend to come in packages of more than one
1170 */
1171 DISCPUSTATE Cpu;
1172 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1173 if (VBOX_SUCCESS(rc))
1174 {
1175#ifdef VBOX_WITH_STATISTICS
1176 switch (Cpu.pCurInstr->opcode)
1177 {
1178 case OP_INSB:
1179 case OP_INSWD:
1180 case OP_IN:
1181 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1182 break;
1183
1184 case OP_OUTSB:
1185 case OP_OUTSWD:
1186 case OP_OUT:
1187 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1188 break;
1189 }
1190#endif
1191
1192 if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE)))
1193 {
1194 OP_PARAMVAL ParmVal;
1195 int rc;
1196 switch (Cpu.pCurInstr->opcode)
1197 {
1198 case OP_IN:
1199 {
1200 rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal, PARAM_SOURCE);
1201 if ( VBOX_FAILURE(rc)
1202 || ParmVal.type != PARMTYPE_IMMEDIATE)
1203 break;
1204
1205 if (!(Cpu.param1.flags & (USE_REG_GEN8 | USE_REG_GEN16 | USE_REG_GEN32)))
1206 break;
1207
1208 /* Make sure port access is allowed */
1209 rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1210 if (rc != VINF_SUCCESS)
1211 {
1212 if (rc == VINF_EM_RAW_GUEST_TRAP)
1213 rc = emR3RawGuestTrap(pVM);
1214
1215 return rc;
1216 }
1217
1218 uint32_t u32Value = 0;
1219 switch (Cpu.param1.size)
1220 {
1221 case 1:
1222 Assert(Cpu.param1.base.reg_gen8 == USE_REG_AL);
1223 rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint8_t));
1224 if (VBOX_SUCCESS(rc))
1225 {
1226 pCtx->eax = (pCtx->eax & ~0xFF) | (uint8_t)u32Value;
1227 Log(("EMU: in8 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFF));
1228 pCtx->eip += Cpu.opsize;
1229 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1230 return rc;
1231 }
1232 AssertRC(rc);
1233 break;
1234
1235 case 2:
1236 Assert(Cpu.param1.base.reg_gen16 == USE_REG_AX);
1237 rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint16_t));
1238 if (VBOX_SUCCESS(rc))
1239 {
1240 pCtx->eax = (pCtx->eax & ~0xFFFF) | (uint16_t)u32Value;
1241 Log(("EMU: in16 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFFFF));
1242 pCtx->eip += Cpu.opsize;
1243 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1244 return rc;
1245 }
1246 AssertRC(rc);
1247 break;
1248
1249 case 4:
1250 Assert(Cpu.param1.base.reg_gen32 == USE_REG_EAX);
1251 rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint32_t));
1252 if (VBOX_SUCCESS(rc))
1253 {
1254 pCtx->eax = u32Value;
1255 Log(("EMU: in32 %x, %x\n", ParmVal.val.val16, pCtx->eax));
1256 pCtx->eip += Cpu.opsize;
1257 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1258 return rc;
1259 }
1260 AssertRC(rc);
1261 break;
1262
1263 default:
1264 AssertMsgFailed(("Unexpected port size %d\n", ParmVal.size));
1265 break;
1266 }
1267 break;
1268 }
1269
1270 case OP_OUT:
1271 {
1272 // it really is the destination, but we're interested in the destination value. hence we specify PARAM_SOURCE (bit of a hack)
1273 rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &ParmVal, PARAM_SOURCE);
1274 if ( VBOX_FAILURE(rc)
1275 || ParmVal.type != PARMTYPE_IMMEDIATE)
1276 break;
1277 OP_PARAMVAL ParmVal2;
1278 rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal2, PARAM_SOURCE);
1279 if ( VBOX_FAILURE(rc)
1280 || ParmVal2.type != PARMTYPE_IMMEDIATE)
1281 break;
1282
1283 /* Make sure port access is allowed */
1284 rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1285 if (rc != VINF_SUCCESS)
1286 {
1287 if (rc == VINF_EM_RAW_GUEST_TRAP)
1288 rc = emR3RawGuestTrap(pVM);
1289
1290 return rc;
1291 }
1292
1293 AssertMsg(Cpu.param2.size == ParmVal2.size, ("size %d vs %d\n", Cpu.param2.size, ParmVal2.size));
1294 switch (ParmVal2.size)
1295 {
1296 case 1:
1297 Log(("EMU: out8 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val8));
1298 rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val8, sizeof(ParmVal2.val.val8));
1299 if (VBOX_SUCCESS(rc))
1300 {
1301 pCtx->eip += Cpu.opsize;
1302 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1303 return rc;
1304 }
1305 AssertRC(rc);
1306 break;
1307
1308 case 2:
1309 Log(("EMU: out16 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val16));
1310 rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val16, sizeof(ParmVal2.val.val16));
1311 if (VBOX_SUCCESS(rc))
1312 {
1313 pCtx->eip += Cpu.opsize;
1314 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1315 return rc;
1316 }
1317 AssertRC(rc);
1318 break;
1319
1320 case 4:
1321 Log(("EMU: out32 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val32));
1322 rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val32, sizeof(ParmVal2.val.val32));
1323 if (VBOX_SUCCESS(rc))
1324 {
1325 pCtx->eip += Cpu.opsize;
1326 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1327 return rc;
1328 }
1329 AssertRC(rc);
1330 break;
1331
1332 default:
1333 AssertMsgFailed(("Unexpected port size %d\n", ParmVal2.size));
1334 break;
1335 }
1336 break;
1337 }
1338
1339 default:
1340 break;
1341 }
1342 }//if(!(Cpu.prefix & (PREFIX_REP|PREFIX_REPNE))
1343 else if (Cpu.prefix & PREFIX_REP)
1344 {
1345 switch (Cpu.pCurInstr->opcode)
1346 {
1347 case OP_INSB:
1348 case OP_INSWD:
1349 {
1350 /*
1351 * Do not optimize the destination address decrement case (not worth the effort)
1352 * and likewise for 16 bit address size (would need to use and update only cx/di).
1353 */
1354 if (pCtx->eflags.Bits.u1DF || Cpu.addrmode != CPUMODE_32BIT)
1355 break;
1356 /*
1357 * Get port number and transfer count directly from the registers (no need to bother the
1358 * disassembler). And get the I/O register size from the opcode / prefix.
1359 */
1360 uint32_t uPort = pCtx->edx & 0xffff;
1361 RTGCUINTREG cTransfers = pCtx->ecx;
1362 unsigned cbUnit;
1363 if (Cpu.pCurInstr->opcode == OP_INSB)
1364 cbUnit = 1;
1365 else
1366 cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1367
1368 RTGCPTR GCPtrDst = pCtx->edi;
1369 /* Access verification first; we can't recover from traps inside this instruction, as the port read cannot be repeated. */
1370 rc = PGMVerifyAccess(pVM, GCPtrDst, cTransfers * cbUnit,
1371 X86_PTE_RW | (((pCtx->ss & X86_SEL_RPL) == 3) ? X86_PTE_US : 0));
1372 if (rc != VINF_SUCCESS)
1373 {
1374 Log(("EMU: rep ins%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1375 break;
1376 }
1377
1378 Log(("EMU: rep ins%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1379
1380 /* Make sure port access is allowed */
1381 rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1382 if (rc != VINF_SUCCESS)
1383 {
1384 if (rc == VINF_EM_RAW_GUEST_TRAP)
1385 rc = emR3RawGuestTrap(pVM);
1386
1387 return rc;
1388 }
1389
1390 /*
1391 * If the device supports string transfers, ask it to do as
1392 * much as it wants. The rest is done with single-word transfers.
1393 */
1394 rc = IOMIOPortReadString(pVM, uPort, &GCPtrDst, &cTransfers, cbUnit);
1395 AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1396
1397 while (cTransfers && rc == VINF_SUCCESS)
1398 {
1399 uint32_t u32Value;
1400 rc = IOMIOPortRead(pVM, uPort, &u32Value, cbUnit);
1401 AssertRC(rc);
1402 int rc2 = PGMPhysWriteGCPtrDirty(pVM, GCPtrDst, &u32Value, cbUnit);
1403 AssertRC(rc2);
1404 GCPtrDst += cbUnit;
1405 cTransfers--;
1406 }
1407 pCtx->edi += (pCtx->ecx - cTransfers) * cbUnit;
1408 pCtx->ecx = cTransfers;
1409 if (!cTransfers && VBOX_SUCCESS(rc))
1410 pCtx->eip += Cpu.opsize;
1411 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1412 return rc;
1413 }
1414 case OP_OUTSB:
1415 case OP_OUTSWD:
1416 {
1417 /*
1418 * Do not optimize the source address decrement case (not worth the effort)
1419 * and likewise for 16 bit address size (would need to use and update only cx/si).
1420 */
1421 if (pCtx->eflags.Bits.u1DF || Cpu.addrmode != CPUMODE_32BIT)
1422 break;
1423 /*
1424 * Get port number and transfer count directly from the registers (no need to bother the
1425 * disassembler). And get the I/O register size from the opcode / prefix.
1426 */
1427 uint32_t uPort = pCtx->edx & 0xffff;
1428 RTGCUINTREG cTransfers = pCtx->ecx;
1429 unsigned cbUnit;
1430 if (Cpu.pCurInstr->opcode == OP_OUTSB)
1431 cbUnit = 1;
1432 else
1433 cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1434
1435 RTGCPTR GCPtrSrc = pCtx->esi;
1436 /* Access verification first; we currently can't recover properly from traps inside this instruction */
1437 rc = PGMVerifyAccess(pVM, GCPtrSrc, cTransfers * cbUnit, (((pCtx->ss & X86_SEL_RPL) == 3) ? X86_PTE_US : 0));
1438 if (rc != VINF_SUCCESS)
1439 {
1440 Log(("EMU: rep outs%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1441 break;
1442 }
1443
1444 Log(("EMU: rep outs%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1445
1446 /* Make sure port access is allowed */
1447 rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1448 if (rc != VINF_SUCCESS)
1449 {
1450 if (rc == VINF_EM_RAW_GUEST_TRAP)
1451 rc = emR3RawGuestTrap(pVM);
1452
1453 return rc;
1454 }
1455
1456 /*
1457 * If the device supports string transfers, ask it to do as
1458 * much as it wants. The rest is done with single-word transfers.
1459 */
1460 rc = IOMIOPortWriteString(pVM, uPort, &GCPtrSrc, &cTransfers, cbUnit);
1461 AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1462
1463 while (cTransfers && rc == VINF_SUCCESS)
1464 {
1465 uint32_t u32Value;
1466 rc = PGMPhysReadGCPtr(pVM, &u32Value, GCPtrSrc, cbUnit);
1467 Assert(rc == VINF_SUCCESS);
1468 rc = IOMIOPortWrite(pVM, uPort, u32Value, cbUnit);
1469 AssertRC(rc);
1470 GCPtrSrc += cbUnit;
1471 cTransfers--;
1472 }
1473 pCtx->esi += (pCtx->ecx - cTransfers) * cbUnit;
1474 pCtx->ecx = cTransfers;
1475 if (!cTransfers && VBOX_SUCCESS(rc))
1476 pCtx->eip += Cpu.opsize;
1477 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1478 return rc;
1479 }
1480 }
1481 }//if(Cpu.prefix & PREFIX_REP)
1482 }
1483
1484 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1485 return emR3RawExecuteInstruction(pVM, "IO: ");
1486}
1487
1488
1489/**
1490 * Handle a guest context trap.
1491 *
1492 * @returns VBox status code suitable for EM.
1493 * @param pVM VM handle.
1494 */
1495static int emR3RawGuestTrap(PVM pVM)
1496{
1497 PCPUMCTX pCtx = pVM->em.s.pCtx;
1498
1499 /*
1500 * Get the trap info.
1501 */
1502 uint8_t u8TrapNo;
1503 bool fSoftwareInterrupt;
1504 RTGCUINT uErrorCode;
1505 RTGCUINTPTR uCR2;
1506 int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
1507 if (VBOX_FAILURE(rc))
1508 {
1509 AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1510 return rc;
1511 }
1512
1513 /* Traps can be directly forwarded in hardware accelerated mode. */
1514 if (HWACCMR3IsActive(pVM))
1515 {
1516#ifdef LOGGING_ENABLED
1517 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1518 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1519#endif
1520 return VINF_EM_RESCHEDULE_HWACC;
1521 }
1522
1523 /** Scan kernel code that traps; we might not get another chance. */
1524 if ( (pCtx->ss & X86_SEL_RPL) <= 1
1525 && pCtx->eflags.Bits.u1VM == 0)
1526 {
1527 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1528 CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
1529 }
1530
1531 if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1532 {
1533 DISCPUSTATE cpu;
1534
1535 /* If MONITOR & MWAIT are supported, then interpret them here. */
1536 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1537 if ( VBOX_SUCCESS(rc)
1538 && (cpu.pCurInstr->opcode == OP_MONITOR || cpu.pCurInstr->opcode == OP_MWAIT))
1539 {
1540 uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1541
1542 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1543
1544 if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1545 {
1546 rc = TRPMResetTrap(pVM);
1547 AssertRC(rc);
1548
1549 rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1550 if (VBOX_SUCCESS(rc))
1551 {
1552 pCtx->eip += cpu.opsize;
1553 return rc;
1554 }
1555 return emR3RawExecuteInstruction(pVM, "Monitor: ");
1556 }
1557 }
1558 }
1559 else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1560 {
1561 DISCPUSTATE cpu;
1562
1563 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1564 if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1565 {
1566 /*
1567 * We should really check the TSS for the IO bitmap, but it's not like this
1568 * lazy approach really makes things worse.
1569 */
1570 rc = TRPMResetTrap(pVM);
1571 AssertRC(rc);
1572 return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1573 }
1574 }
1575
1576#ifdef LOG_ENABLED
1577 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1578 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1579
1580 /* Get guest page information. */
1581 uint64_t fFlags = 0;
1582 RTGCPHYS GCPhys = 0;
1583 int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1584 Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1585 pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, fSoftwareInterrupt ? " software" : "", GCPhys, fFlags,
1586 fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1587 fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1588#endif
1589
1590 /*
1591 * #PG has CR2.
1592 * (Because of stuff like above we must set CR2 in a delayed fashion.)
1593 */
1594 if (u8TrapNo == 14 /* #PG */)
1595 pCtx->cr2 = uCR2;
1596
1597 return VINF_EM_RESCHEDULE_REM;
1598}
1599
1600
1601/**
1602 * Handle a ring switch trap.
1603 * Need to do statistics and to install patches. The result is going to REM.
1604 *
1605 * @returns VBox status code suitable for EM.
1606 * @param pVM VM handle.
1607 */
1608int emR3RawRingSwitch(PVM pVM)
1609{
1610 int rc;
1611 DISCPUSTATE Cpu;
1612 PCPUMCTX pCtx = pVM->em.s.pCtx;
1613
1614 /*
1615 * sysenter, syscall & callgate
1616 */
1617 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1618 if (VBOX_SUCCESS(rc))
1619 {
1620 if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1621 {
1622 if (pCtx->SysEnter.cs != 0)
1623 {
1624 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip),
1625 SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1626 if (VBOX_SUCCESS(rc))
1627 {
1628 DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1629 return VINF_EM_RESCHEDULE_RAW;
1630 }
1631 }
1632 }
1633
1634#ifdef VBOX_WITH_STATISTICS
1635 switch (Cpu.pCurInstr->opcode)
1636 {
1637 case OP_SYSENTER:
1638 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1639 break;
1640 case OP_SYSEXIT:
1641 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1642 break;
1643 case OP_SYSCALL:
1644 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1645 break;
1646 case OP_SYSRET:
1647 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1648 break;
1649 }
1650#endif
1651 }
1652 else
1653 AssertRC(rc);
1654
1655 /* go to the REM to emulate a single instruction */
1656 return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1657}
1658
1659/**
1660 * Handle a trap (#PF or #GP) in patch code
1661 *
1662 * @returns VBox status code suitable for EM.
1663 * @param pVM VM handle.
1664 * @param pCtx CPU context
1665 * @param gcret GC return code
1666 */
1667int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1668{
1669 uint8_t u8TrapNo;
1670 int rc;
1671 bool fSoftwareInterrupt;
1672 RTGCUINT uErrorCode;
1673 RTGCUINTPTR uCR2;
1674
1675 Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1676
1677 if (gcret == VINF_PATM_PATCH_INT3)
1678 {
1679 u8TrapNo = 3;
1680 uCR2 = 0;
1681 uErrorCode = 0;
1682 }
1683 else
1684 if (gcret == VINF_PATM_PATCH_TRAP_GP)
1685 {
1686 /* No active trap in this case. Kind of ugly. */
1687 u8TrapNo = X86_XCPT_GP;
1688 uCR2 = 0;
1689 uErrorCode = 0;
1690 }
1691 else
1692 {
1693 rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
1694 if (VBOX_FAILURE(rc))
1695 {
1696 AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1697 return rc;
1698 }
1699 /* Reset the trap as we'll execute the original instruction again. */
1700 TRPMResetTrap(pVM);
1701 }
1702
1703 /*
1704 * Deal with traps inside patch code.
1705 * (This code won't run outside GC.)
1706 */
1707 if (u8TrapNo != 1)
1708 {
1709#ifdef LOG_ENABLED
1710 DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1711 DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1712#endif
1713 Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1714 pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1715
1716 RTGCPTR pNewEip;
1717 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1718 switch (rc)
1719 {
1720 /*
1721 * Execute the faulting instruction.
1722 */
1723 case VINF_SUCCESS:
1724 {
1725 /** @todo execute a whole block */
1726 Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1727 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1728 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1729
1730 pCtx->eip = pNewEip;
1731 AssertRelease(pCtx->eip);
1732
1733 if (pCtx->eflags.Bits.u1IF)
1734 {
1735 /* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1736 * int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1737 */
1738 if ( u8TrapNo == X86_XCPT_GP
1739 && PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1740 {
1741 /** @todo move to PATMR3HandleTrap */
1742 Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1743 PATMR3RemovePatch(pVM, pCtx->eip);
1744 }
1745
1746 /** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1747 /** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1748
1749 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1750 /* Interrupts are enabled; just go back to the original instruction.
1751 return VINF_SUCCESS; */
1752 }
1753 return VINF_EM_RESCHEDULE_REM;
1754 }
1755
1756 /*
1757 * One instruction.
1758 */
1759 case VINF_PATCH_EMULATE_INSTR:
1760 Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1761 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1762 pCtx->eip = pNewEip;
1763 AssertRelease(pCtx->eip);
1764 return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1765
1766 /*
1767 * The patch was disabled, hand it to the REM.
1768 */
1769 case VERR_PATCH_DISABLED:
1770 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1771 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1772 pCtx->eip = pNewEip;
1773 AssertRelease(pCtx->eip);
1774
1775 if (pCtx->eflags.Bits.u1IF)
1776 {
1777 /*
1778 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1779 */
1780 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1781 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1782 }
1783 return VINF_EM_RESCHEDULE_REM;
1784
1785 /* Force continued patch exection; usually due to write monitored stack. */
1786 case VINF_PATCH_CONTINUE:
1787 return VINF_SUCCESS;
1788
1789 /*
1790 * Anything else is *fatal*.
1791 */
1792 default:
1793 AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1794 return VERR_INTERNAL_ERROR;
1795 }
1796 }
1797 return VINF_SUCCESS;
1798}
1799
1800
1801/**
1802 * Handle a privileged instruction.
1803 *
1804 * @returns VBox status code suitable for EM.
1805 * @param pVM VM handle.
1806 */
1807int emR3RawPrivileged(PVM pVM)
1808{
1809 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1810 PCPUMCTX pCtx = pVM->em.s.pCtx;
1811
1812 Assert(!pCtx->eflags.Bits.u1VM);
1813
1814 if (PATMIsEnabled(pVM))
1815 {
1816 /*
1817 * Check if in patch code.
1818 */
1819 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1820 {
1821#ifdef LOG_ENABLED
1822 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1823#endif
1824 AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1825 return VERR_EM_RAW_PATCH_CONFLICT;
1826 }
1827 if ( (pCtx->ss & X86_SEL_RPL) == 0
1828 && !pCtx->eflags.Bits.u1VM
1829 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
1830 {
1831 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip),
1832 SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1833 if (VBOX_SUCCESS(rc))
1834 {
1835#ifdef LOG_ENABLED
1836 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1837#endif
1838 DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1839 return VINF_SUCCESS;
1840 }
1841 }
1842 }
1843
1844#ifdef LOG_ENABLED
1845 if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1846 {
1847 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1848 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1849 }
1850#endif
1851
1852 /*
1853 * Instruction statistics and logging.
1854 */
1855 DISCPUSTATE Cpu;
1856 int rc;
1857
1858 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1859 if (VBOX_SUCCESS(rc))
1860 {
1861#ifdef VBOX_WITH_STATISTICS
1862 PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1863 switch (Cpu.pCurInstr->opcode)
1864 {
1865 case OP_INVLPG:
1866 STAM_COUNTER_INC(&pStats->StatInvlpg);
1867 break;
1868 case OP_IRET:
1869 STAM_COUNTER_INC(&pStats->StatIret);
1870 break;
1871 case OP_CLI:
1872 STAM_COUNTER_INC(&pStats->StatCli);
1873 emR3RecordCli(pVM, pCtx->eip);
1874 break;
1875 case OP_STI:
1876 STAM_COUNTER_INC(&pStats->StatSti);
1877 break;
1878 case OP_INSB:
1879 case OP_INSWD:
1880 case OP_IN:
1881 case OP_OUTSB:
1882 case OP_OUTSWD:
1883 case OP_OUT:
1884 AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1885 break;
1886
1887 case OP_MOV_CR:
1888 if (Cpu.param1.flags & USE_REG_GEN32)
1889 {
1890 //read
1891 Assert(Cpu.param2.flags & USE_REG_CR);
1892 Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1893 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1894 }
1895 else
1896 {
1897 //write
1898 Assert(Cpu.param1.flags & USE_REG_CR);
1899 Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1900 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1901 }
1902 break;
1903
1904 case OP_MOV_DR:
1905 STAM_COUNTER_INC(&pStats->StatMovDRx);
1906 break;
1907 case OP_LLDT:
1908 STAM_COUNTER_INC(&pStats->StatMovLldt);
1909 break;
1910 case OP_LIDT:
1911 STAM_COUNTER_INC(&pStats->StatMovLidt);
1912 break;
1913 case OP_LGDT:
1914 STAM_COUNTER_INC(&pStats->StatMovLgdt);
1915 break;
1916 case OP_SYSENTER:
1917 STAM_COUNTER_INC(&pStats->StatSysEnter);
1918 break;
1919 case OP_SYSEXIT:
1920 STAM_COUNTER_INC(&pStats->StatSysExit);
1921 break;
1922 case OP_SYSCALL:
1923 STAM_COUNTER_INC(&pStats->StatSysCall);
1924 break;
1925 case OP_SYSRET:
1926 STAM_COUNTER_INC(&pStats->StatSysRet);
1927 break;
1928 case OP_HLT:
1929 STAM_COUNTER_INC(&pStats->StatHlt);
1930 break;
1931 default:
1932 STAM_COUNTER_INC(&pStats->StatMisc);
1933 Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1934 break;
1935 }
1936#endif
1937 if ( (pCtx->ss & X86_SEL_RPL) == 0
1938 && SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid))
1939 {
1940 uint32_t size;
1941
1942 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1943 switch (Cpu.pCurInstr->opcode)
1944 {
1945 case OP_CLI:
1946 pCtx->eflags.u32 &= ~X86_EFL_IF;
1947 Assert(Cpu.opsize == 1);
1948 pCtx->eip += Cpu.opsize;
1949 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1950 return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1951
1952 case OP_STI:
1953 pCtx->eflags.u32 |= X86_EFL_IF;
1954 EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
1955 Assert(Cpu.opsize == 1);
1956 pCtx->eip += Cpu.opsize;
1957 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1958 return VINF_SUCCESS;
1959
1960 case OP_HLT:
1961 if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1962 {
1963 PATMTRANSSTATE enmState;
1964 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1965
1966 if (enmState == PATMTRANS_OVERWRITTEN)
1967 {
1968 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1969 Assert(rc == VERR_PATCH_DISABLED);
1970 /* Conflict detected, patch disabled */
1971 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1972
1973 enmState = PATMTRANS_SAFE;
1974 }
1975
1976 /* The translation had better be successful. Otherwise we can't recover. */
1977 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1978 if (enmState != PATMTRANS_OVERWRITTEN)
1979 pCtx->eip = pOrgInstrGC;
1980 }
1981 /* no break; we could just return VINF_EM_HALT here */
1982
1983 case OP_MOV_CR:
1984 case OP_MOV_DR:
1985#ifdef LOG_ENABLED
1986 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1987 {
1988 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1989 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1990 }
1991#endif
1992
1993 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1994 if (VBOX_SUCCESS(rc))
1995 {
1996 pCtx->eip += Cpu.opsize;
1997 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1998
1999 if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2000 && Cpu.param1.flags == USE_REG_CR /* write */
2001 )
2002 {
2003 /* Reschedule is necessary as the execution/paging mode might have changed. */
2004 return VINF_EM_RESCHEDULE;
2005 }
2006 return rc; /* can return VINF_EM_HALT as well. */
2007 }
2008 AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
2009 break; /* fall back to the recompiler */
2010 }
2011 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2012 }
2013 }
2014
2015 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2016 return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
2017
2018 return emR3RawExecuteInstruction(pVM, "PRIV");
2019}
2020
2021
2022/**
2023 * Update the forced rawmode execution modifier.
2024 *
2025 * This function is called when we're returning from the raw-mode loop(s). If we're
2026 * in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2027 * if not in patch code, the flag will be cleared.
2028 *
2029 * We should never interrupt patch code while it's being executed. Cli patches can
2030 * contain big code blocks, but they are always executed with IF=0. Other patches
2031 * replace single instructions and should be atomic.
2032 *
2033 * @returns Updated rc.
2034 *
2035 * @param pVM The VM handle.
2036 * @param pCtx The guest CPU context.
2037 * @param rc The result code.
2038 */
2039DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2040{
2041 if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2042 {
2043 /* ignore reschedule attempts. */
2044 switch (rc)
2045 {
2046 case VINF_EM_RESCHEDULE:
2047 case VINF_EM_RESCHEDULE_REM:
2048 rc = VINF_SUCCESS;
2049 break;
2050 }
2051 pVM->em.s.fForceRAW = true;
2052 }
2053 else
2054 pVM->em.s.fForceRAW = false;
2055 return rc;
2056}
2057
2058
2059/**
2060 * Process a subset of the raw-mode return code.
2061 *
2062 * Since we have to share this with raw-mode single stepping, this inline
2063 * function has been created to avoid code duplication.
2064 *
2065 * @returns VINF_SUCCESS if it's ok to continue raw mode.
2066 * @returns VBox status code to return to the EM main loop.
2067 *
2068 * @param pVM The VM handle
2069 * @param rc The return code.
2070 * @param pCtx The guest cpu context.
2071 */
2072DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2073{
2074 switch (rc)
2075 {
2076 /*
2077 * Common & simple ones.
2078 */
2079 case VINF_SUCCESS:
2080 break;
2081 case VINF_EM_RESCHEDULE_RAW:
2082 case VINF_EM_RESCHEDULE_HWACC:
2083 case VINF_EM_RAW_INTERRUPT:
2084 case VINF_EM_RAW_TO_R3:
2085 case VINF_EM_RAW_TIMER_PENDING:
2086 case VINF_EM_PENDING_REQUEST:
2087 rc = VINF_SUCCESS;
2088 break;
2089
2090 /*
2091 * Privileged instruction.
2092 */
2093 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2094 case VINF_PATM_PATCH_TRAP_GP:
2095 rc = emR3RawPrivileged(pVM);
2096 break;
2097
2098 /*
2099 * Got a trap which needs dispatching.
2100 */
2101 case VINF_EM_RAW_GUEST_TRAP:
2102 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2103 {
2104 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2105 rc = VERR_EM_RAW_PATCH_CONFLICT;
2106 break;
2107 }
2108 uint8_t u8Interrupt;
2109
2110 Assert(TRPMHasTrap(pVM));
2111 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2112
2113 if (TRPMHasTrap(pVM))
2114 {
2115 u8Interrupt = TRPMGetTrapNo(pVM);
2116
2117 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2118 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2119 {
2120 CSAMR3CheckGates(pVM, u8Interrupt, 1);
2121 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2122 /** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2123 }
2124 }
2125 rc = emR3RawGuestTrap(pVM);
2126 break;
2127
2128 /*
2129 * Trap in patch code.
2130 */
2131 case VINF_PATM_PATCH_TRAP_PF:
2132 case VINF_PATM_PATCH_INT3:
2133 rc = emR3PatchTrap(pVM, pCtx, rc);
2134 break;
2135
2136 case VINF_PATM_DUPLICATE_FUNCTION:
2137 Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2138 rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2139 AssertRC(rc);
2140 rc = VINF_SUCCESS;
2141 break;
2142
2143 case VINF_PATM_CHECK_PATCH_PAGE:
2144 rc = PATMR3HandleMonitoredPage(pVM);
2145 AssertRC(rc);
2146 rc = VINF_SUCCESS;
2147 break;
2148
2149 /*
2150 * Patch manager.
2151 */
2152 case VERR_EM_RAW_PATCH_CONFLICT:
2153 AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2154 break;
2155
2156 /*
2157 * Memory mapped I/O access - attempt to patch the instruction
2158 */
2159 case VINF_PATM_HC_MMIO_PATCH_READ:
2160 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip),
2161 PATMFL_MMIO_ACCESS | (SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2162 if (VBOX_FAILURE(rc))
2163 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2164 break;
2165
2166 case VINF_PATM_HC_MMIO_PATCH_WRITE:
2167 AssertFailed(); /* not yet implemented. */
2168 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2169 break;
2170
2171 /*
2172 * Conflict or out of page tables.
2173 *
2174 * VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2175 * do here is to execute the pending forced actions.
2176 */
2177 case VINF_PGM_SYNC_CR3:
2178 AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2179 ("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2180 rc = VINF_SUCCESS;
2181 break;
2182
2183 /*
2184 * Paging mode change.
2185 */
2186 case VINF_PGM_CHANGE_MODE:
2187 rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2188 if (VBOX_SUCCESS(rc))
2189 rc = VINF_EM_RESCHEDULE;
2190 break;
2191
2192 /*
2193 * CSAM wants to perform a task in ring-3. It has set an FF action flag.
2194 */
2195 case VINF_CSAM_PENDING_ACTION:
2196 rc = VINF_SUCCESS;
2197 break;
2198
2199 /*
2200 * Invoked Interrupt gate - must directly (!) go to the recompiler.
2201 */
2202 case VINF_EM_RAW_INTERRUPT_PENDING:
2203 case VINF_EM_RAW_RING_SWITCH_INT:
2204 {
2205 uint8_t u8Interrupt;
2206
2207 Assert(TRPMHasTrap(pVM));
2208 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2209
2210 if (TRPMHasTrap(pVM))
2211 {
2212 u8Interrupt = TRPMGetTrapNo(pVM);
2213
2214 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2215 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2216 {
2217 CSAMR3CheckGates(pVM, u8Interrupt, 1);
2218 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2219 /** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2220 }
2221 }
2222 rc = VINF_EM_RESCHEDULE_REM;
2223 break;
2224 }
2225
2226 /*
2227 * Other ring switch types.
2228 */
2229 case VINF_EM_RAW_RING_SWITCH:
2230 rc = emR3RawRingSwitch(pVM);
2231 break;
2232
2233 /*
2234 * REMGCNotifyInvalidatePage() failed because of overflow.
2235 */
2236 case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2237 Assert((pCtx->ss & X86_SEL_RPL) != 1);
2238 REMR3ReplayInvalidatedPages(pVM);
2239 break;
2240
2241 /*
2242 * I/O Port access - emulate the instruction.
2243 */
2244 case VINF_IOM_HC_IOPORT_READ:
2245 case VINF_IOM_HC_IOPORT_WRITE:
2246 case VINF_IOM_HC_IOPORT_READWRITE:
2247 rc = emR3RawExecuteIOInstruction(pVM);
2248 break;
2249
2250 /*
2251 * Memory mapped I/O access - emulate the instruction.
2252 */
2253 case VINF_IOM_HC_MMIO_READ:
2254 case VINF_IOM_HC_MMIO_WRITE:
2255 case VINF_IOM_HC_MMIO_READ_WRITE:
2256 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2257 break;
2258
2259 /*
2260 * Execute instruction.
2261 */
2262 case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2263 rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2264 break;
2265 case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2266 rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2267 break;
2268 case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2269 rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2270 break;
2271 case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2272 rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2273 break;
2274 case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2275 rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2276 break;
2277
2278 case VINF_EM_RAW_EMULATE_INSTR_HLT:
2279 /** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2280 rc = emR3RawPrivileged(pVM);
2281 break;
2282
2283 case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2284 rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2285 break;
2286
2287 case VINF_EM_RAW_EMULATE_INSTR:
2288 case VINF_PATCH_EMULATE_INSTR:
2289 rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2290 break;
2291
2292 /*
2293 * Stale selector and iret traps => REM.
2294 */
2295 case VINF_EM_RAW_STALE_SELECTOR:
2296 case VINF_EM_RAW_IRET_TRAP:
2297 /* We will not go to the recompiler if EIP points to patch code. */
2298 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2299 {
2300 pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2301 }
2302 LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2303 rc = VINF_EM_RESCHEDULE_REM;
2304 break;
2305
2306 /*
2307 * Up a level.
2308 */
2309 case VINF_EM_TERMINATE:
2310 case VINF_EM_OFF:
2311 case VINF_EM_RESET:
2312 case VINF_EM_SUSPEND:
2313 case VINF_EM_HALT:
2314 case VINF_EM_RESUME:
2315 case VINF_EM_RESCHEDULE:
2316 case VINF_EM_RESCHEDULE_REM:
2317 break;
2318
2319 /*
2320 * Up a level and invoke the debugger.
2321 */
2322 case VINF_EM_DBG_STEPPED:
2323 case VINF_EM_DBG_BREAKPOINT:
2324 case VINF_EM_DBG_STEP:
2325 case VINF_EM_DBG_HYPER_ASSERTION:
2326 case VINF_EM_DBG_HYPER_BREAKPOINT:
2327 case VINF_EM_DBG_HYPER_STEPPED:
2328 case VINF_EM_DBG_STOP:
2329 break;
2330
2331 /*
2332 * Up a level, dump and debug.
2333 */
2334 case VERR_TRPM_DONT_PANIC:
2335 case VERR_TRPM_PANIC:
2336 break;
2337
2338 /*
2339 * Anything which is not known to us means an internal error
2340 * and the termination of the VM!
2341 */
2342 default:
2343 AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2344 break;
2345 }
2346 return rc;
2347}
2348
2349
2350/**
2351 * Process raw-mode specific forced actions.
2352 *
2353 * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2354 *
2355 * @returns VBox status code.
2356 * Only the normal success/failure stuff, no VINF_EM_*.
2357 * @param pVM The VM handle.
2358 * @param pCtx The guest CPUM register context.
2359 */
2360static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2361{
2362 /*
2363 * Note that the order is *vitally* important!
2364 * Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2365 */
2366
2367
2368 /*
2369 * Sync selector tables.
2370 */
2371 if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT))
2372 {
2373 int rc = SELMR3UpdateFromCPUM(pVM);
2374 if (VBOX_FAILURE(rc))
2375 return rc;
2376 }
2377
2378 /*
2379 * Sync IDT.
2380 */
2381 if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2382 {
2383 int rc = TRPMR3SyncIDT(pVM);
2384 if (VBOX_FAILURE(rc))
2385 return rc;
2386 }
2387
2388 /*
2389 * Sync TSS.
2390 */
2391 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2392 {
2393 int rc = SELMR3SyncTSS(pVM);
2394 if (VBOX_FAILURE(rc))
2395 return rc;
2396 }
2397
2398 /*
2399 * Sync page directory.
2400 */
2401 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2402 {
2403 int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2404 if (VBOX_FAILURE(rc))
2405 return rc;
2406
2407 Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT));
2408
2409 /* Prefetch pages for EIP and ESP */
2410 /** @todo This is rather expensive. Should investigate if it really helps at all. */
2411 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip));
2412 if (rc == VINF_SUCCESS)
2413 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2414 if (rc != VINF_SUCCESS)
2415 {
2416 if (rc != VINF_PGM_SYNC_CR3)
2417 return rc;
2418 rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2419 if (VBOX_FAILURE(rc))
2420 return rc;
2421 }
2422 /** @todo maybe prefetch the supervisor stack page as well */
2423 }
2424
2425 return VINF_SUCCESS;
2426}
2427
2428
2429/**
2430 * Executes raw code.
2431 *
2432 * This function contains the raw-mode version of the inner
2433 * execution loop (the outer loop being in EMR3ExecuteVM()).
2434 *
2435 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2436 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2437 *
2438 * @param pVM VM handle.
2439 * @param pfFFDone Where to store an indicator telling whether or not
2440 * FFs were done before returning.
2441 */
2442static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2443{
2444 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2445
2446 int rc = VERR_INTERNAL_ERROR;
2447 PCPUMCTX pCtx = pVM->em.s.pCtx;
2448 LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2449 pVM->em.s.fForceRAW = false;
2450 *pfFFDone = false;
2451
2452
2453 /*
2454 *
2455 * Spin till we get a forced action or raw mode status code resulting in
2456 * in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2457 *
2458 */
2459 for (;;)
2460 {
2461 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2462
2463 /*
2464 * Check various preconditions.
2465 */
2466#ifdef VBOX_STRICT
2467 Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2468 Assert(!(pCtx->cr4 & X86_CR4_PAE));
2469 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) == 3 || (pCtx->ss & X86_SEL_RPL) == 0);
2470 AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2471 || PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2472 ("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2473 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2474 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2475 {
2476 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2477 return VERR_INTERNAL_ERROR;
2478 }
2479#endif /* VBOX_STRICT */
2480
2481 /*
2482 * Process high priority pre-execution raw-mode FFs.
2483 */
2484 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2485 {
2486 rc = emR3RawForcedActions(pVM, pCtx);
2487 if (VBOX_FAILURE(rc))
2488 break;
2489 }
2490
2491 /*
2492 * If we're going to execute ring-0 code, the guest state needs to
2493 * be modified a bit and some of the state components (IF, SS/CS RPL,
2494 * and perhaps EIP) needs to be stored with PATM.
2495 */
2496 rc = CPUMRawEnter(pVM, NULL);
2497 if (rc != VINF_SUCCESS)
2498 {
2499 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2500 break;
2501 }
2502
2503 /*
2504 * Scan code before executing it. Don't bother with user mode or V86 code
2505 */
2506 if ( (pCtx->ss & X86_SEL_RPL) <= 1
2507 && pCtx->eflags.Bits.u1VM == 0
2508 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
2509 {
2510 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2511 CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2512 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2513 }
2514
2515#ifdef LOG_ENABLED
2516 /*
2517 * Log important stuff before entering GC.
2518 */
2519 PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2520 if (pCtx->eflags.Bits.u1VM)
2521 Log(("RV86: %08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2522 else if ((pCtx->ss & X86_SEL_RPL) == 1)
2523 {
2524 bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2525 Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2526 }
2527 else if ((pCtx->ss & X86_SEL_RPL) == 3)
2528 Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2529#endif /* LOG_ENABLED */
2530
2531
2532
2533 /*
2534 * Execute the code.
2535 */
2536 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2537 STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2538 VMMR3Unlock(pVM);
2539 rc = VMMR3RawRunGC(pVM);
2540 VMMR3Lock(pVM);
2541 STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2542 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2543
2544 LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2545 LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2546
2547
2548 /*
2549 * Restore the real CPU state and deal with high priority post
2550 * execution FFs before doing anything else.
2551 */
2552 rc = CPUMRawLeave(pVM, NULL, rc);
2553 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2554 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2555 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2556
2557#ifdef PGM_CACHE_VERY_STRICT
2558 /*
2559 * Page manager cache checks.
2560 */
2561 if ( rc == VINF_EM_RAW_INTERRUPT
2562 || rc == VINF_EM_RAW_GUEST_TRAP
2563 || rc == VINF_IOM_HC_IOPORT_READ
2564 || rc == VINF_IOM_HC_IOPORT_WRITE
2565 || rc == VINF_IOM_HC_IOPORT_READWRITE
2566 //|| rc == VINF_PATM_PATCH_INT3
2567 )
2568 pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2569#endif
2570
2571#ifdef VBOX_STRICT
2572 /*
2573 * Assert TSS consistency & rc vs patch code.
2574 */
2575 if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS | VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2576 && EMIsRawRing0Enabled(pVM))
2577 SELMR3CheckTSS(pVM);
2578 switch (rc)
2579 {
2580 case VINF_SUCCESS:
2581 case VINF_EM_RAW_INTERRUPT:
2582 case VINF_PATM_PATCH_TRAP_PF:
2583 case VINF_PATM_PATCH_TRAP_GP:
2584 case VINF_PATM_PATCH_INT3:
2585 case VINF_PATM_CHECK_PATCH_PAGE:
2586 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2587 case VINF_EM_RAW_GUEST_TRAP:
2588 case VINF_EM_RESCHEDULE_RAW:
2589 break;
2590
2591 default:
2592 if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2593 LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2594 break;
2595 }
2596 /*
2597 * Let's go paranoid!
2598 */
2599 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2600 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2601 {
2602 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2603 return VERR_INTERNAL_ERROR;
2604 }
2605#endif /* VBOX_STRICT */
2606
2607 /*
2608 * Process the returned status code.
2609 */
2610 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2611 {
2612 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2613 break;
2614 }
2615 rc = emR3RawHandleRC(pVM, pCtx, rc);
2616 if (rc != VINF_SUCCESS)
2617 {
2618 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2619 if (rc != VINF_SUCCESS)
2620 {
2621 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2622 break;
2623 }
2624 }
2625
2626 /*
2627 * Check and execute forced actions.
2628 */
2629#ifdef VBOX_HIGH_RES_TIMERS_HACK
2630 TMTimerPoll(pVM);
2631#endif
2632 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2633 if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2634 {
2635 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) != 1);
2636
2637 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2638 rc = emR3ForcedActions(pVM, rc);
2639 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2640 if ( rc != VINF_SUCCESS
2641 && rc != VINF_EM_RESCHEDULE_RAW)
2642 {
2643 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2644 if (rc != VINF_SUCCESS)
2645 {
2646 *pfFFDone = true;
2647 break;
2648 }
2649 }
2650 }
2651 }
2652
2653 /*
2654 * Return to outer loop.
2655 */
2656#if defined(LOG_ENABLED) && defined(DEBUG)
2657 RTLogFlush(NULL);
2658#endif
2659 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2660 return rc;
2661}
2662
2663
2664/**
2665 * Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2666 *
2667 * This function contains the raw-mode version of the inner
2668 * execution loop (the outer loop being in EMR3ExecuteVM()).
2669 *
2670 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2671 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2672 *
2673 * @param pVM VM handle.
2674 * @param pfFFDone Where to store an indicator telling whether or not
2675 * FFs were done before returning.
2676 */
2677static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2678{
2679 int rc = VERR_INTERNAL_ERROR;
2680 PCPUMCTX pCtx = pVM->em.s.pCtx;
2681
2682 LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2683 *pfFFDone = false;
2684
2685 STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2686
2687 /*
2688 * Spin till we get a forced action which returns anything but VINF_SUCCESS.
2689 */
2690 for (;;)
2691 {
2692 STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2693
2694 /*
2695 * Check various preconditions.
2696 */
2697 Assert(!(pCtx->cr4 & X86_CR4_PAE));
2698
2699 VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_TSS));
2700
2701 /*
2702 * Sync page directory.
2703 */
2704 if (VM_FF_ISPENDING(pVM, (VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)))
2705 {
2706 rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2707 if (VBOX_FAILURE(rc))
2708 return rc;
2709
2710 Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT));
2711
2712 /* Prefetch pages for EIP and ESP */
2713 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip));
2714 if (rc == VINF_SUCCESS)
2715 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2716 if (rc != VINF_SUCCESS)
2717 {
2718 if (rc != VINF_PGM_SYNC_CR3)
2719 return rc;
2720 rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2721 if (VBOX_FAILURE(rc))
2722 return rc;
2723 }
2724
2725 /** @todo maybe prefetch the supervisor stack page as well */
2726 }
2727
2728#ifdef LOG_ENABLED
2729 uint8_t u8Vector;
2730
2731 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2732 if (rc == VINF_SUCCESS)
2733 {
2734 Log(("Pending hardware interrupt %d\n", u8Vector));
2735 }
2736 /*
2737 * Log important stuff before entering GC.
2738 */
2739 if (pCtx->eflags.Bits.u1VM)
2740 Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2741 else if ((pCtx->ss & X86_SEL_RPL) == 0)
2742 Log(("HWR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
2743 else if ((pCtx->ss & X86_SEL_RPL) == 3)
2744 Log(("HWR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
2745#endif
2746
2747
2748 /*
2749 * Execute the code.
2750 */
2751 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2752 STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2753 VMMR3Unlock(pVM);
2754 rc = VMMR3HwAccRunGC(pVM);
2755 VMMR3Lock(pVM);
2756 STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2757
2758
2759 /*
2760 * Deal with high priority post execution FFs before doing anything else.
2761 */
2762 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2763 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2764 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2765
2766 /*
2767 * Process the returned status code.
2768 */
2769 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2770 break;
2771
2772 rc = emR3RawHandleRC(pVM, pCtx, rc);
2773 if (rc != VINF_SUCCESS)
2774 break;
2775
2776 /*
2777 * Check and execute forced actions.
2778 */
2779#ifdef VBOX_HIGH_RES_TIMERS_HACK
2780 TMTimerPoll(pVM);
2781#endif
2782 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2783 {
2784 rc = emR3ForcedActions(pVM, rc);
2785 if ( rc != VINF_SUCCESS
2786 && rc != VINF_EM_RESCHEDULE_HWACC)
2787 {
2788 *pfFFDone = true;
2789 break;
2790 }
2791 }
2792 }
2793 /*
2794 * Return to outer loop.
2795 */
2796#if defined(LOG_ENABLED) && defined(DEBUG)
2797 RTLogFlush(NULL);
2798#endif
2799 return rc;
2800}
2801
2802
2803/**
2804 * Decides whether to execute RAW, HWACC or REM.
2805 *
2806 * @returns new EM state
2807 * @param pVM The VM.
2808 * @param pCtx The CPU context.
2809 */
2810inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2811{
2812 /*
2813 * When forcing raw-mode execution, things are simple.
2814 */
2815 if (pVM->em.s.fForceRAW)
2816 return EMSTATE_RAW;
2817
2818 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2819 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2820 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2821
2822 X86EFLAGS EFlags = pCtx->eflags;
2823 if (HWACCMIsEnabled(pVM))
2824 {
2825 /* Hardware accelerated raw-mode:
2826 *
2827 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2828 */
2829 if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2830 return EMSTATE_HWACC;
2831
2832 /** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2833 return EMSTATE_REM;
2834 }
2835
2836 /* Standard raw-mode:
2837 *
2838 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2839 * or 32 bits protected mode ring 0 code
2840 *
2841 * The tests are ordered by the likelyhood of being true during normal execution.
2842 */
2843 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
2844 {
2845 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2846 return EMSTATE_REM;
2847 }
2848
2849#ifndef VBOX_RAW_V86
2850 if (EFlags.u32 & X86_EFL_VM) {
2851 Log2(("raw mode refused: VM_MASK\n"));
2852 return EMSTATE_REM;
2853 }
2854#endif
2855
2856 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2857 uint32_t u32CR0 = pCtx->cr0;
2858 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
2859 {
2860 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2861 return EMSTATE_REM;
2862 }
2863
2864 if (pCtx->cr4 & X86_CR4_PAE)
2865 {
2866 //Log2(("raw mode refused: PAE\n"));
2867 return EMSTATE_REM;
2868 }
2869
2870 unsigned uSS = pCtx->ss;
2871 if ((uSS & X86_SEL_RPL) == 3)
2872 {
2873 if (!EMIsRawRing3Enabled(pVM))
2874 return EMSTATE_REM;
2875
2876 if (!(EFlags.u32 & X86_EFL_IF))
2877 {
2878#ifdef VBOX_RAW_V86
2879 if(!(EFlags.u32 & X86_EFL_VM))
2880 return EMSTATE_REM;
2881#else
2882 Log2(("raw mode refused: IF (RawR3)\n"));
2883 return EMSTATE_REM;
2884#endif
2885 }
2886
2887 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2888 {
2889 Log2(("raw mode refused: CR0.WP + RawR0\n"));
2890 return EMSTATE_REM;
2891 }
2892 }
2893 else
2894 {
2895 if (!EMIsRawRing0Enabled(pVM))
2896 return EMSTATE_REM;
2897
2898 /* Only ring 0 supervisor code. */
2899 if ((uSS & X86_SEL_RPL) != 0)
2900 {
2901 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2902 return EMSTATE_REM;
2903 }
2904
2905 // Let's start with pure 32 bits ring 0 code first
2906 /** @todo What's pure 32-bit mode? flat? */
2907 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2908 || !(pCtx->csHid.Attr.n.u1DefBig))
2909 {
2910 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2911 return EMSTATE_REM;
2912 }
2913
2914 /* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2915 if (!(u32CR0 & X86_CR0_WP))
2916 {
2917 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2918 return EMSTATE_REM;
2919 }
2920
2921 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2922 {
2923 Log2(("raw r0 mode forced: patch code\n"));
2924 return EMSTATE_RAW;
2925 }
2926
2927#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2928 if (!(EFlags.u32 & X86_EFL_IF))
2929 {
2930 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2931 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2932 return EMSTATE_REM;
2933 }
2934#endif
2935
2936 /** @todo still necessary??? */
2937 if (EFlags.Bits.u2IOPL != 0)
2938 {
2939 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2940 return EMSTATE_REM;
2941 }
2942 }
2943
2944 Assert(PGMPhysIsA20Enabled(pVM));
2945 return EMSTATE_RAW;
2946}
2947
2948
2949/**
2950 * Executes all high priority post execution force actions.
2951 *
2952 * @returns rc or a fatal status code.
2953 *
2954 * @param pVM VM handle.
2955 * @param rc The current rc.
2956 */
2957static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2958{
2959 if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2960 PDMR3CritSectFF(pVM);
2961
2962 if (VM_FF_ISSET(pVM, VM_FF_CSAM_FLUSH_DIRTY_PAGE))
2963 CSAMR3FlushDirtyPages(pVM);
2964
2965 return rc;
2966}
2967
2968
2969/**
2970 * Executes all pending forced actions.
2971 *
2972 * Forced actions can cause execution delays and execution
2973 * rescheduling. The first we deal with using action priority, so
2974 * that for instance pending timers aren't scheduled and ran until
2975 * right before execution. The rescheduling we deal with using
2976 * return codes. The same goes for VM termination, only in that case
2977 * we exit everything.
2978 *
2979 * @returns VBox status code of equal or greater importance/severity than rc.
2980 * The most important ones are: VINF_EM_RESCHEDULE,
2981 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2982 *
2983 * @param pVM VM handle.
2984 * @param rc The current rc.
2985 *
2986 */
2987static int emR3ForcedActions(PVM pVM, int rc)
2988{
2989#ifdef VBOX_STRICT
2990 int rcIrq = VINF_SUCCESS;
2991#endif
2992 STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2993
2994#define UPDATE_RC() \
2995 do { \
2996 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2997 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
2998 break; \
2999 if (!rc || rc2 < rc) \
3000 rc = rc2; \
3001 } while (0)
3002
3003 int rc2;
3004
3005 /*
3006 * Post execution chunk first.
3007 */
3008 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
3009 {
3010 /*
3011 * Termination request.
3012 */
3013 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3014 {
3015 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3016 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3017 return VINF_EM_TERMINATE;
3018 }
3019
3020 /*
3021 * Debugger Facility polling.
3022 */
3023 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3024 {
3025 rc2 = DBGFR3VMMForcedAction(pVM);
3026 UPDATE_RC();
3027 }
3028
3029 /*
3030 * Postponed reset request.
3031 */
3032 if (VM_FF_ISSET(pVM, VM_FF_RESET))
3033 {
3034 rc2 = VMR3Reset(pVM);
3035 UPDATE_RC();
3036 VM_FF_CLEAR(pVM, VM_FF_RESET);
3037 }
3038
3039 /*
3040 * CSAM page scanning.
3041 */
3042 if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
3043 {
3044 PCPUMCTX pCtx = pVM->em.s.pCtx;
3045
3046 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3047 Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3048
3049 CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
3050 VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3051 }
3052
3053 /* check that we got them all */
3054 Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_CSAM_SCAN_PAGE)));
3055 }
3056
3057 /*
3058 * Normal priority then.
3059 * (Executed in no particular order.)
3060 */
3061 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3062 {
3063 /*
3064 * PDM Queues are pending.
3065 */
3066 if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3067 PDMR3QueueFlushAll(pVM);
3068
3069 /*
3070 * PDM DMA transfers are pending.
3071 */
3072 if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3073 PDMR3DmaRun(pVM);
3074
3075 /*
3076 * Requests from other threads.
3077 */
3078 if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3079 {
3080 rc2 = VMR3ReqProcess(pVM);
3081 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE)
3082 {
3083 Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3084 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3085 return rc2;
3086 }
3087 UPDATE_RC();
3088 }
3089
3090 /* check that we got them all */
3091 Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA)));
3092 }
3093
3094 /*
3095 * Execute polling function ever so often.
3096 * THIS IS A HACK, IT WILL BE *REPLACED* BY PROPER ASYNC NETWORKING SOON!
3097 */
3098 static unsigned cLast = 0;
3099 if (!((++cLast) % 4))
3100 PDMR3Poll(pVM);
3101
3102 /*
3103 * High priority pre execution chunk last.
3104 * (Executed in ascending priority order.)
3105 */
3106 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3107 {
3108 /*
3109 * Timers before interrupts.
3110 */
3111 if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3112 TMR3TimerQueuesDo(pVM);
3113
3114 /*
3115 * The instruction following an emulated STI should *always* be executed!
3116 */
3117 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3118 {
3119 Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3120 if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3121 {
3122 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3123 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3124 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3125 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3126 */
3127 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3128 }
3129 if (HWACCMR3IsActive(pVM))
3130 rc2 = VINF_EM_RESCHEDULE_HWACC;
3131 else
3132 rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3133
3134 UPDATE_RC();
3135 }
3136
3137 /*
3138 * Interrupts.
3139 */
3140 if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3141 && (!rc || rc >= VINF_EM_RESCHEDULE_RAW)
3142 && !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3143 && PATMAreInterruptsEnabled(pVM)
3144 && !HWACCMR3IsEventPending(pVM))
3145 {
3146 if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
3147 {
3148 /** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3149 /** @todo this really isn't nice, should properly handle this */
3150 rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3151#ifdef VBOX_STRICT
3152 rcIrq = rc2;
3153#endif
3154 UPDATE_RC();
3155 }
3156 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3157 else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3158 {
3159 rc2 = VINF_EM_RESCHEDULE_REM;
3160 UPDATE_RC();
3161 }
3162 }
3163
3164 /*
3165 * Debugger Facility request.
3166 */
3167 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3168 {
3169 rc2 = DBGFR3VMMForcedAction(pVM);
3170 UPDATE_RC();
3171 }
3172
3173 /*
3174 * Termination request.
3175 */
3176 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3177 {
3178 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3179 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3180 return VINF_EM_TERMINATE;
3181 }
3182
3183#ifdef DEBUG
3184 /*
3185 * Debug, pause the VM.
3186 */
3187 if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3188 {
3189 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3190 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3191 return VINF_EM_SUSPEND;
3192 }
3193
3194#endif
3195 /* check that we got them all */
3196 Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER | VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC | VM_FF_DBGF | VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_SELM_SYNC_TSS | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TERMINATE | VM_FF_DEBUG_SUSPEND | VM_FF_INHIBIT_INTERRUPTS)));
3197 }
3198
3199#undef UPDATE_RC
3200 Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3201 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3202 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
3203 return rc;
3204}
3205
3206
3207/**
3208 * Execute VM.
3209 *
3210 * This function is the main loop of the VM. The emulation thread
3211 * calls this function when the VM has been successfully constructed
3212 * and we're ready for executing the VM.
3213 *
3214 * Returning from this function means that the VM is turned off or
3215 * suspended (state already saved) and deconstruction in next in line.
3216 *
3217 * All interaction from other thread are done using forced actions
3218 * and signaling of the wait object.
3219 *
3220 * @returns VBox status code.
3221 * @param pVM The VM to operate on.
3222 */
3223EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3224{
3225 LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3226 pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3227 VM_ASSERT_EMT(pVM);
3228 Assert(pVM->em.s.enmState == EMSTATE_NONE || pVM->em.s.enmState == EMSTATE_SUSPENDED);
3229
3230 VMMR3Lock(pVM);
3231
3232 int rc = setjmp(pVM->em.s.u.FatalLongJump);
3233 if (rc == 0)
3234 {
3235 /*
3236 * Start the virtual time.
3237 */
3238 rc = TMVirtualResume(pVM);
3239 Assert(rc == VINF_SUCCESS);
3240 rc = TMCpuTickResume(pVM);
3241 Assert(rc == VINF_SUCCESS);
3242
3243 /*
3244 * The Outer Main Loop.
3245 */
3246 bool fFFDone = false;
3247 rc = VINF_EM_RESCHEDULE;
3248 pVM->em.s.enmState = EMSTATE_REM;
3249 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3250 for (;;)
3251 {
3252 /*
3253 * Before we can schedule anything (we're here because
3254 * scheduling is required) we must service any pending
3255 * forced actions to avoid any pending action causing
3256 * immidate rescheduling upon entering an inner loop
3257 *
3258 * Do forced actions.
3259 */
3260 if ( !fFFDone
3261 && rc != VINF_EM_TERMINATE
3262 && rc != VINF_EM_OFF
3263 && VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3264 {
3265 rc = emR3ForcedActions(pVM, rc);
3266 if ( ( rc == VINF_EM_RESCHEDULE_REM
3267 || rc == VINF_EM_RESCHEDULE_HWACC)
3268 && pVM->em.s.fForceRAW)
3269 rc = VINF_EM_RESCHEDULE_RAW;
3270 }
3271 else if (fFFDone)
3272 fFFDone = false;
3273
3274 /*
3275 * Now what to do?
3276 */
3277 Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3278 switch (rc)
3279 {
3280 /*
3281 * Keep doing what we're currently doing.
3282 */
3283 case VINF_SUCCESS:
3284 break;
3285
3286 /*
3287 * Reschedule - to raw-mode execution.
3288 */
3289 case VINF_EM_RESCHEDULE_RAW:
3290 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3291 pVM->em.s.enmState = EMSTATE_RAW;
3292 break;
3293
3294 /*
3295 * Reschedule - to hardware accelerated raw-mode execution.
3296 */
3297 case VINF_EM_RESCHEDULE_HWACC:
3298 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3299 Assert(!pVM->em.s.fForceRAW);
3300 pVM->em.s.enmState = EMSTATE_HWACC;
3301 break;
3302
3303 /*
3304 * Reschedule - to recompiled execution.
3305 */
3306 case VINF_EM_RESCHEDULE_REM:
3307 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3308 pVM->em.s.enmState = EMSTATE_REM;
3309 break;
3310
3311 /*
3312 * Resume.
3313 */
3314 case VINF_EM_RESUME:
3315 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3316 /* fall through and get scheduled. */
3317
3318 /*
3319 * Reschedule.
3320 */
3321 case VINF_EM_RESCHEDULE:
3322 {
3323 EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3324 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3325 pVM->em.s.enmState = enmState;
3326 break;
3327 }
3328
3329 /*
3330 * Halted.
3331 */
3332 case VINF_EM_HALT:
3333 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3334 pVM->em.s.enmState = EMSTATE_HALTED;
3335 break;
3336
3337 /*
3338 * Suspend.
3339 */
3340 case VINF_EM_SUSPEND:
3341 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3342 pVM->em.s.enmState = EMSTATE_SUSPENDED;
3343 break;
3344
3345 /*
3346 * Reset.
3347 * We might end up doing a double reset for now, we'll have to clean up the mess later.
3348 */
3349 case VINF_EM_RESET:
3350 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3351 pVM->em.s.enmState = EMSTATE_REM;
3352 break;
3353
3354 /*
3355 * Power Off.
3356 */
3357 case VINF_EM_OFF:
3358 pVM->em.s.enmState = EMSTATE_TERMINATING;
3359 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3360 TMVirtualPause(pVM);
3361 TMCpuTickPause(pVM);
3362 VMMR3Unlock(pVM);
3363 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3364 return rc;
3365
3366 /*
3367 * Terminate the VM.
3368 */
3369 case VINF_EM_TERMINATE:
3370 pVM->em.s.enmState = EMSTATE_TERMINATING;
3371 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3372 TMVirtualPause(pVM);
3373 TMCpuTickPause(pVM);
3374 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3375 return rc;
3376
3377 /*
3378 * Guest debug events.
3379 */
3380 case VINF_EM_DBG_STEPPED:
3381 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3382 case VINF_EM_DBG_STOP:
3383 case VINF_EM_DBG_BREAKPOINT:
3384 case VINF_EM_DBG_STEP:
3385 if (pVM->em.s.enmState == EMSTATE_RAW)
3386 {
3387 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3388 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3389 }
3390 else
3391 {
3392 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3393 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3394 }
3395 break;
3396
3397 /*
3398 * Hypervisor debug events.
3399 */
3400 case VINF_EM_DBG_HYPER_STEPPED:
3401 case VINF_EM_DBG_HYPER_BREAKPOINT:
3402 case VINF_EM_DBG_HYPER_ASSERTION:
3403 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3404 pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3405 break;
3406
3407 /*
3408 * Any error code showing up here other than the ones we
3409 * know and process above are considered to be FATAL.
3410 *
3411 * Unknown warnings and informational status codes are also
3412 * included in this.
3413 */
3414 default:
3415 if (VBOX_SUCCESS(rc))
3416 {
3417 AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3418 rc = VERR_EM_INTERNAL_ERROR;
3419 }
3420 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3421 Log(("EMR3ExecuteVM returns %d\n", rc));
3422 break;
3423 }
3424
3425
3426 /*
3427 * Any waiters can now be woken up
3428 */
3429 VMMR3Unlock(pVM);
3430 VMMR3Lock(pVM);
3431
3432 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3433 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3434
3435 /*
3436 * Act on the state.
3437 */
3438 switch (pVM->em.s.enmState)
3439 {
3440 /*
3441 * Execute raw.
3442 */
3443 case EMSTATE_RAW:
3444 rc = emR3RawExecute(pVM, &fFFDone);
3445 break;
3446
3447 /*
3448 * Execute hardware accelerated raw.
3449 */
3450 case EMSTATE_HWACC:
3451 rc = emR3HwAccExecute(pVM, &fFFDone);
3452 break;
3453
3454 /*
3455 * Execute recompiled.
3456 */
3457 case EMSTATE_REM:
3458#if 0
3459 /* simulate a runtime error */
3460 VMSetRuntimeError (pVM, true, "simulatedError", "pVM=%p", pVM);
3461#endif
3462 rc = emR3RemExecute(pVM, &fFFDone);
3463 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3464 break;
3465
3466 /*
3467 * hlt - execution halted until interrupt.
3468 */
3469 case EMSTATE_HALTED:
3470 {
3471 STAM_PROFILE_START(&pVM->em.s.StatHalted, y);
3472 rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3473 STAM_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3474 break;
3475 }
3476
3477 /*
3478 * Suspended - return to VM.cpp.
3479 */
3480 case EMSTATE_SUSPENDED:
3481 TMVirtualPause(pVM);
3482 TMCpuTickPause(pVM);
3483 VMMR3Unlock(pVM);
3484 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3485 return VINF_EM_SUSPEND;
3486
3487 /*
3488 * Debugging in the guest.
3489 */
3490 case EMSTATE_DEBUG_GUEST_REM:
3491 case EMSTATE_DEBUG_GUEST_RAW:
3492 TMVirtualPause(pVM);
3493 TMCpuTickPause(pVM);
3494 rc = emR3Debug(pVM, rc);
3495 TMVirtualResume(pVM);
3496 TMCpuTickResume(pVM);
3497 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3498 break;
3499
3500 /*
3501 * Debugging in the hypervisor.
3502 */
3503 case EMSTATE_DEBUG_HYPER:
3504 {
3505 TMVirtualPause(pVM);
3506 TMCpuTickPause(pVM);
3507 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3508
3509 rc = emR3Debug(pVM, rc);
3510 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3511 if (rc != VINF_SUCCESS)
3512 {
3513 /* switch to guru meditation mode */
3514 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3515 VMMR3FatalDump(pVM, rc);
3516 return rc;
3517 }
3518
3519 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3520 TMVirtualResume(pVM);
3521 TMCpuTickResume(pVM);
3522 break;
3523 }
3524
3525 /*
3526 * Guru meditation takes place in the debugger.
3527 */
3528 case EMSTATE_GURU_MEDITATION:
3529 {
3530 /** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3531 TMVirtualPause(pVM);
3532 TMCpuTickPause(pVM);
3533 VMMR3FatalDump(pVM, rc);
3534 int rc2 = emR3Debug(pVM, rc);
3535 if (rc2 == VERR_DBGF_NOT_ATTACHED)
3536 {
3537 VMMR3Unlock(pVM);
3538 /** @todo change the VM state! */
3539 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3540 return rc;
3541 }
3542 TMVirtualResume(pVM);
3543 TMCpuTickResume(pVM);
3544 rc = rc2;
3545 /** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3546 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3547 break;
3548 }
3549
3550 /*
3551 * The states we don't expect here.
3552 */
3553 case EMSTATE_NONE:
3554 case EMSTATE_TERMINATING:
3555 default:
3556 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3557 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3558 TMVirtualPause(pVM);
3559 TMCpuTickPause(pVM);
3560 VMMR3Unlock(pVM);
3561 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3562 return VERR_EM_INTERNAL_ERROR;
3563 }
3564 } /* The Outer Main Loop */
3565 }
3566 else
3567 {
3568 /*
3569 * Fatal error.
3570 */
3571 LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3572 TMVirtualPause(pVM);
3573 TMCpuTickPause(pVM);
3574 VMMR3FatalDump(pVM, rc);
3575 emR3Debug(pVM, rc);
3576 VMMR3Unlock(pVM);
3577 /** @todo change the VM state! */
3578 return rc;
3579 }
3580
3581 /* (won't ever get here). */
3582 AssertFailed();
3583}
3584
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