EM.cpp@ 1151

Last change on this file since 1151 was 1148, checked in by vboxsync, 18 years ago
Added emR3SingleStepExecRem
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 145.1 KB

Line
1	/* $Id: EM.cpp 1148 2007-03-02 09:52:17Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor/Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_em EM - The Execution Monitor/Manager
24	*
25	* The Execution Monitor/Manager is responsible for running the VM, scheduling
26	* the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27	* the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28	* the VM.
29	*
30	*/
31
32	/*******************************************************************************
33	* Header Files *
34	*******************************************************************************/
35	#define LOG_GROUP LOG_GROUP_EM
36	#include <VBox/em.h>
37	#include <VBox/vmm.h>
38	#include <VBox/patm.h>
39	#include <VBox/csam.h>
40	#include <VBox/selm.h>
41	#include <VBox/trpm.h>
42	#include <VBox/iom.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/pgm.h>
45	#include <VBox/rem.h>
46	#include <VBox/tm.h>
47	#include <VBox/mm.h>
48	#include <VBox/pdm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/patm.h>
51	#include "EMInternal.h"
52	#include <VBox/vm.h>
53	#include <VBox/cpumdis.h>
54	#include <VBox/dis.h>
55	#include <VBox/disopcode.h>
56	#include <VBox/dbgf.h>
57
58	#include <VBox/log.h>
59	#include <iprt/thread.h>
60	#include <iprt/assert.h>
61	#include <iprt/asm.h>
62	#include <iprt/semaphore.h>
63	#include <iprt/string.h>
64	#include <iprt/avl.h>
65	#include <iprt/stream.h>
66	#include <VBox/param.h>
67	#include <VBox/err.h>
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
74	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
75	static int emR3Debug(PVM pVM, int rc);
76	static int emR3RemStep(PVM pVM);
77	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
78	static int emR3RawResumeHyper(PVM pVM);
79	static int emR3RawStep(PVM pVM);
80	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
81	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
82	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
83	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
84	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
85	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
86	static int emR3ForcedActions(PVM pVM, int rc);
87	static int emR3RawGuestTrap(PVM pVM);
88
89
90	/**
91	* Initializes the EM.
92	*
93	* @returns VBox status code.
94	* @param pVM The VM to operate on.
95	*/
96	EMR3DECL(int) EMR3Init(PVM pVM)
97	{
98	LogFlow(("EMR3Init\n"));
99	/*
100	* Assert alignment and sizes.
101	*/
102	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
103	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
104	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
105	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
106
107	/*
108	* Init the structure.
109	*/
110	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
111	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
112	if (VBOX_FAILURE(rc))
113	pVM->fRawR3Enabled = true;
114	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
115	if (VBOX_FAILURE(rc))
116	pVM->fRawR0Enabled = true;
117	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
118	pVM->em.s.enmState = EMSTATE_NONE;
119	pVM->em.s.fForceRAW = false;
120
121	rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
122	AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
123	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
124	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
125
126	/*
127	* Saved state.
128	*/
129	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
130	NULL, emR3Save, NULL,
131	NULL, emR3Load, NULL);
132	if (VBOX_FAILURE(rc))
133	return rc;
134
135	/*
136	* Statistics.
137	*/
138	#ifdef VBOX_WITH_STATISTICS
139	PEMSTATS pStats;
140	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
141	if (VBOX_FAILURE(rc))
142	return rc;
143	pVM->em.s.pStatsHC = pStats;
144	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
145
146	STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
147	STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
148
149	STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
150	STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
151
152	STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
153	STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
154	STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
155	STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
156	STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
157	STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
158	STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
159	STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
160	STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
161	STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
162	STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
163	STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
164	STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
165	STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
185	//STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
196
197	STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
198	STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
199
200	STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
204	STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
205	STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
206	STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
207	STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
208	STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
237	//STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
238
239	STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
240	STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
241	STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
246	STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
247	STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
248	STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
249	STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
261
262	STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
263	STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
264	STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
265	STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
266
267	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
268	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
269	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
270	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
271	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
272	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
273	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
274	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
275	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
276	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
277	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
278	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
279	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
280	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
281	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
282	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
283	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
284	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
285	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
286	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
287	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
288	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
289	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
290	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
291	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
292	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
293
294	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
295	pVM->em.s.pCliStatTree = 0;
296	#endif /* VBOX_WITH_STATISTICS */
297
298	/* these should be considered for release statistics. */
299	STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
300	STAM_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
301	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
302	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
303	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
304	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
305	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
306	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
307	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
308	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
309	STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
310	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
311	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
312	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
313	STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
314	STAM_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
315
316
317	return VINF_SUCCESS;
318	}
319
320
321
322	/**
323	* Applies relocations to data and code managed by this
324	* component. This function will be called at init and
325	* whenever the VMM need to relocate it self inside the GC.
326	*
327	* @param pVM The VM.
328	*/
329	EMR3DECL(void) EMR3Relocate(PVM pVM)
330	{
331	LogFlow(("EMR3Relocate\n"));
332	if (pVM->em.s.pStatsHC)
333	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
334	}
335
336
337	/**
338	* Reset notification.
339	*
340	* @param pVM
341	*/
342	EMR3DECL(void) EMR3Reset(PVM pVM)
343	{
344	LogFlow(("EMR3Reset: \n"));
345	pVM->em.s.fForceRAW = false;
346	}
347
348
349	/**
350	* Terminates the EM.
351	*
352	* Termination means cleaning up and freeing all resources,
353	* the VM it self is at this point powered off or suspended.
354	*
355	* @returns VBox status code.
356	* @param pVM The VM to operate on.
357	*/
358	EMR3DECL(int) EMR3Term(PVM pVM)
359	{
360	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
361
362	return VINF_SUCCESS;
363	}
364
365
366	/**
367	* Execute state save operation.
368	*
369	* @returns VBox status code.
370	* @param pVM VM Handle.
371	* @param pSSM SSM operation handle.
372	*/
373	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
374	{
375	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
376	}
377
378
379	/**
380	* Execute state load operation.
381	*
382	* @returns VBox status code.
383	* @param pVM VM Handle.
384	* @param pSSM SSM operation handle.
385	* @param u32Version Data layout version.
386	*/
387	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
388	{
389	/*
390	* Validate version.
391	*/
392	if (u32Version != EM_SAVED_STATE_VERSION)
393	{
394	Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
395	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
396	}
397
398	/*
399	* Load the saved state.
400	*/
401	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
402	if (VBOX_FAILURE(rc))
403	pVM->em.s.fForceRAW = false;
404
405	Assert(pVM->em.s.pCliStatTree == 0);
406	return rc;
407	}
408
409
410	/**
411	* Enables or disables a set of raw-mode execution modes.
412	*
413	* @returns VINF_SUCCESS on success.
414	* @returns VINF_RESCHEDULE if a rescheduling might be required.
415	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
416	*
417	* @param pVM The VM to operate on.
418	* @param enmMode The execution mode change.
419	* @thread The emulation thread.
420	*/
421	EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
422	{
423	switch (enmMode)
424	{
425	case EMRAW_NONE:
426	pVM->fRawR3Enabled = false;
427	pVM->fRawR0Enabled = false;
428	break;
429	case EMRAW_RING3_ENABLE:
430	pVM->fRawR3Enabled = true;
431	break;
432	case EMRAW_RING3_DISABLE:
433	pVM->fRawR3Enabled = false;
434	break;
435	case EMRAW_RING0_ENABLE:
436	pVM->fRawR0Enabled = true;
437	break;
438	case EMRAW_RING0_DISABLE:
439	pVM->fRawR0Enabled = false;
440	break;
441	default:
442	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
443	return VERR_INVALID_PARAMETER;
444	}
445	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
446	pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
447	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
448	}
449
450
451	/**
452	* Raise a fatal error.
453	*
454	* Safely terminate the VM with full state report and stuff. This function
455	* will naturally never return.
456	*
457	* @param pVM VM handle.
458	* @param rc VBox status code.
459	*/
460	EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
461	{
462	longjmp(pVM->em.s.u.FatalLongJump, rc);
463	AssertReleaseMsgFailed(("longjmp returned!\n"));
464	}
465
466
467	/**
468	* Gets the EM state name.
469	*
470	* @returns pointer to read only state name,
471	* @param enmState The state.
472	*/
473	EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
474	{
475	switch (enmState)
476	{
477	case EMSTATE_RAW: return "EMSTATE_RAW";
478	case EMSTATE_HWACC: return "EMSTATE_HWACC";
479	case EMSTATE_REM: return "EMSTATE_REM";
480	case EMSTATE_HALTED: return "EMSTATE_HALTED";
481	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
482	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
483	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
484	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
485	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
486	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
487	default: return "Unknown!";
488	}
489	}
490
491
492	#ifdef VBOX_WITH_STATISTICS
493	/**
494	* Just a braindead function to keep track of cli addresses.
495	* @param pVM VM handle.
496	* @param pInstrGC The EIP of the cli instruction.
497	*/
498	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
499	{
500	PCLISTAT pRec;
501
502	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
503	if (!pRec)
504	{
505	/* New cli instruction; insert into the tree. */
506	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
507	Assert(pRec);
508	if (!pRec)
509	return;
510	pRec->Core.Key = (AVLPVKEY)pInstrGC;
511
512	char szCliStatName[32];
513	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
514	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
515
516	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
517	Assert(fRc); NOREF(fRc);
518	}
519	STAM_COUNTER_INC(&pRec->Counter);
520	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
521	}
522	#endif /* VBOX_WITH_STATISTICS */
523
524
525	/**
526	* Debug loop.
527	*
528	* @returns VBox status code for EM.
529	* @param pVM VM handle.
530	* @param rc Current EM VBox status code..
531	*/
532	static int emR3Debug(PVM pVM, int rc)
533	{
534	for (;;)
535	{
536	Log(("emR3Debug: rc=%Vrc\n", rc));
537	const int rcLast = rc;
538
539	/*
540	* Debug related RC.
541	*/
542	switch (rc)
543	{
544	/*
545	* Single step an instruction.
546	*/
547	case VINF_EM_DBG_STEP:
548	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
549	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
550	\|\| pVM->em.s.fForceRAW /* paranoia */)
551	rc = emR3RawStep(pVM);
552	else
553	{
554	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
555	rc = emR3RemStep(pVM);
556	}
557	break;
558
559	/*
560	* Simple events: stepped, breakpoint, stop/assertion.
561	*/
562	case VINF_EM_DBG_STEPPED:
563	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
564	break;
565
566	case VINF_EM_DBG_BREAKPOINT:
567	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
568	break;
569
570	case VINF_EM_DBG_STOP:
571	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
572	break;
573
574	case VINF_EM_DBG_HYPER_STEPPED:
575	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
576	break;
577
578	case VINF_EM_DBG_HYPER_BREAKPOINT:
579	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
580	break;
581
582	case VINF_EM_DBG_HYPER_ASSERTION:
583	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
584	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
585	break;
586
587	/*
588	* Guru meditation.
589	*/
590	default: /** @todo don't use default for guru, but make special errors code! */
591	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
592	break;
593	}
594
595	/*
596	* Process the result.
597	*/
598	do
599	{
600	switch (rc)
601	{
602	/*
603	* Continue the debugging loop.
604	*/
605	case VINF_EM_DBG_STEP:
606	case VINF_EM_DBG_STOP:
607	case VINF_EM_DBG_STEPPED:
608	case VINF_EM_DBG_BREAKPOINT:
609	case VINF_EM_DBG_HYPER_STEPPED:
610	case VINF_EM_DBG_HYPER_BREAKPOINT:
611	case VINF_EM_DBG_HYPER_ASSERTION:
612	break;
613
614	/*
615	* Resuming execution (in some form) has to be done here if we got
616	* a hypervisor debug event.
617	*/
618	case VINF_SUCCESS:
619	case VINF_EM_RESUME:
620	case VINF_EM_SUSPEND:
621	case VINF_EM_RESCHEDULE:
622	case VINF_EM_RESCHEDULE_RAW:
623	case VINF_EM_RESCHEDULE_REM:
624	case VINF_EM_HALT:
625	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
626	{
627	rc = emR3RawResumeHyper(pVM);
628	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
629	continue;
630	}
631	if (rc == VINF_SUCCESS)
632	rc = VINF_EM_RESCHEDULE;
633	return rc;
634
635	/*
636	* The debugger isn't attached.
637	* We'll simply turn the thing off since that's the easiest thing to do.
638	*/
639	case VERR_DBGF_NOT_ATTACHED:
640	switch (rcLast)
641	{
642	case VINF_EM_DBG_HYPER_ASSERTION:
643	case VINF_EM_DBG_HYPER_STEPPED:
644	case VINF_EM_DBG_HYPER_BREAKPOINT:
645	return rcLast;
646	}
647	return VINF_EM_OFF;
648
649	/*
650	* Status codes terminating the VM in one or another sense.
651	*/
652	case VINF_EM_TERMINATE:
653	case VINF_EM_OFF:
654	case VINF_EM_RESET:
655	case VINF_EM_RAW_STALE_SELECTOR:
656	case VINF_EM_RAW_IRET_TRAP:
657	case VERR_TRPM_PANIC:
658	case VERR_TRPM_DONT_PANIC:
659	case VERR_INTERNAL_ERROR:
660	return rc;
661
662	/*
663	* The rest is unexpected, and will keep us here.
664	*/
665	default:
666	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
667	break;
668	}
669	} while (false);
670	} /* debug for ever */
671	}
672
673
674	/**
675	* Steps recompiled code.
676	*
677	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
678	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
679	*
680	* @param pVM VM handle.
681	*/
682	static int emR3RemStep(PVM pVM)
683	{
684	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
685
686	/*
687	* Switch to REM, step instruction, switch back.
688	*/
689	int rc = REMR3State(pVM);
690	if (VBOX_SUCCESS(rc))
691	{
692	rc = REMR3Step(pVM);
693	REMR3StateBack(pVM);
694	}
695	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
696	return rc;
697	}
698
699	/**
700	* Executes recompiled code.
701	*
702	* This function contains the recompiler version of the inner
703	* execution loop (the outer loop being in EMR3ExecuteVM()).
704	*
705	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
706	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
707	*
708	* @param pVM VM handle.
709	* @param pfFFDone Where to store an indicator telling wheter or not
710	* FFs were done before returning.
711	*
712	*/
713	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
714	{
715	#ifdef LOG_ENABLED
716	PCPUMCTX pCtx = pVM->em.s.pCtx;
717	if (pCtx->eflags.Bits.u1VM)
718	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
719	else if ((pCtx->ss & X86_SEL_RPL) == 0)
720	Log(("EMR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
721	else if ((pCtx->ss & X86_SEL_RPL) == 3)
722	Log(("EMR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
723	#endif
724	STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
725
726	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
727	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
728	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
729	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
730	#endif
731
732	/*
733	* Spin till we get a forced action which returns anything but VINF_SUCCESS
734	* or the REM suggests raw-mode execution.
735	*/
736	*pfFFDone = false;
737	bool fInREMState = false;
738	int rc = VINF_SUCCESS;
739	for (;;)
740	{
741	/*
742	* Update REM state if not already in sync.
743	*/
744	if (!fInREMState)
745	{
746	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
747	rc = REMR3State(pVM);
748	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
749	if (VBOX_FAILURE(rc))
750	break;
751	fInREMState = true;
752
753	/*
754	* We might have missed the raising of VMREQ, TIMER and some other
755	* imporant FFs while we were busy switching the state. So, check again.
756	*/
757	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
758	{
759	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
760	goto l_REMDoForcedActions;
761	}
762	}
763
764
765	/*
766	* Execute REM.
767	*/
768	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
769	rc = REMR3Run(pVM);
770	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
771
772
773	/*
774	* Deal with high priority post execution FFs before doing anything else.
775	*/
776	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
777	rc = emR3HighPriorityPostForcedActions(pVM, rc);
778
779	/*
780	* Process the returned status code.
781	* (Try keep this short! Call functions!)
782	*/
783	if (rc != VINF_SUCCESS)
784	{
785	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
786	break;
787	if (rc != VINF_REM_INTERRUPED_FF)
788	{
789	/*
790	* Anything which is not known to us means an internal error
791	* and the termination of the VM!
792	*/
793	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
794	break;
795	}
796	}
797
798
799	/*
800	* Check and execute forced actions.
801	* Sync back the VM state before calling any of these.
802	*/
803	#ifdef VBOX_HIGH_RES_TIMERS_HACK
804	TMTimerPoll(pVM);
805	#endif
806	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_FLUSH_DIRTY_PAGE \| VM_FF_CSAM_SCAN_PAGE)))
807	{
808	l_REMDoForcedActions:
809	if (fInREMState)
810	{
811	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
812	REMR3StateBack(pVM);
813	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
814	fInREMState = false;
815	}
816	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
817	rc = emR3ForcedActions(pVM, rc);
818	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
819	if ( rc != VINF_SUCCESS
820	&& rc != VINF_EM_RESCHEDULE_REM)
821	{
822	*pfFFDone = true;
823	break;
824	}
825	}
826
827	} /* The Inner Loop, recompiled execution mode version. */
828
829
830	/*
831	* Returning. Sync back the VM state if required.
832	*/
833	if (fInREMState)
834	{
835	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
836	REMR3StateBack(pVM);
837	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
838	}
839
840	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
841	return rc;
842	}
843
844
845	/**
846	* Resumes executing hypervisor after a debug event.
847	*
848	* This is kind of special since our current guest state is
849	* potentially out of sync.
850	*
851	* @returns VBox status code.
852	* @param pVM The VM handle.
853	*/
854	static int emR3RawResumeHyper(PVM pVM)
855	{
856	int rc;
857	PCPUMCTX pCtx = pVM->em.s.pCtx;
858	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
859	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
860
861	/*
862	* Resume execution.
863	*/
864	CPUMRawEnter(pVM, NULL);
865	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
866	rc = VMMR3ResumeHyper(pVM);
867	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
868	rc = CPUMRawLeave(pVM, NULL, rc);
869	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
870
871	/*
872	* Deal with the return code.
873	*/
874	rc = emR3HighPriorityPostForcedActions(pVM, rc);
875	rc = emR3RawHandleRC(pVM, pCtx, rc);
876	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
877	return rc;
878	}
879
880
881	/**
882	* Steps rawmode.
883	*
884	* @returns VBox status code.
885	* @param pVM The VM handle.
886	*/
887	static int emR3RawStep(PVM pVM)
888	{
889	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
890	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
891	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
892	int rc;
893	PCPUMCTX pCtx = pVM->em.s.pCtx;
894	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
895	#ifndef DEBUG_sandervl
896	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
897	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
898	#endif
899	if (fGuest)
900	{
901	/*
902	* Check vital forced actions, but ignore pending interrupts and timers.
903	*/
904	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
905	{
906	rc = emR3RawForcedActions(pVM, pCtx);
907	if (VBOX_FAILURE(rc))
908	return rc;
909	}
910
911	/*
912	* Set flags for single stepping.
913	*/
914	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
915	}
916	else
917	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
918
919	/*
920	* Single step.
921	* We do not start time or anything, if anything we should just do a few nanoseconds.
922	*/
923	CPUMRawEnter(pVM, NULL);
924	do
925	{
926	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
927	rc = VMMR3ResumeHyper(pVM);
928	else
929	rc = VMMR3RawRunGC(pVM);
930	#ifndef DEBUG_sandervl
931	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
932	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
933	#endif
934	} while ( rc == VINF_SUCCESS
935	\|\| rc == VINF_EM_RAW_INTERRUPT);
936	rc = CPUMRawLeave(pVM, NULL, rc);
937	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
938
939	/*
940	* Make sure the trap flag is cleared.
941	* (Too bad if the guest is trying to single step too.)
942	*/
943	if (fGuest)
944	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
945	else
946	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
947
948	/*
949	* Deal with the return codes.
950	*/
951	rc = emR3HighPriorityPostForcedActions(pVM, rc);
952	rc = emR3RawHandleRC(pVM, pCtx, rc);
953	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
954	return rc;
955	}
956
957	#ifdef DEBUG_sandervl
958	void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
959	{
960	EMSTATE enmOldState = pVM->em.s.enmState;
961	PCPUMCTX pCtx = pVM->em.s.pCtx;
962
963	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
964
965	Log(("Single step BEGIN:\n"));
966	for(uint32_t i=0;i<cIterations;i++)
967	{
968	DBGFR3PrgStep(pVM);
969	emR3RawStep(pVM);
970	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
971	}
972	Log(("Single step END:\n"));
973	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
974	pVM->em.s.enmState = enmOldState;
975	}
976
977	void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
978	{
979	EMSTATE enmOldState = pVM->em.s.enmState;
980	PCPUMCTX pCtx = pVM->em.s.pCtx;
981
982	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
983
984	Log(("Single step BEGIN:\n"));
985	for(uint32_t i=0;i<cIterations;i++)
986	{
987	DBGFR3PrgStep(pVM);
988	emR3RemStep(pVM);
989	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
990	}
991	Log(("Single step END:\n"));
992	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
993	pVM->em.s.enmState = enmOldState;
994	}
995	#endif
996
997	/**
998	* Executes one (or perhaps a few more) instruction(s).
999	*
1000	* @returns VBox status code suitable for EM.
1001	*
1002	* @param pVM VM handle.
1003	* @param rcGC GC return code
1004	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1005	* instruction and prefix the log output with this text.
1006	*/
1007	#ifdef LOG_ENABLED
1008	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1009	#else
1010	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1011	#endif
1012	{
1013	PCPUMCTX pCtx = pVM->em.s.pCtx;
1014	int rc;
1015
1016	/*
1017	*
1018	* The simple solution is to use the recompiler.
1019	* The better solution is to disassemble the current instruction and
1020	* try handle as many as possible without using REM.
1021	*
1022	*/
1023
1024	#ifdef LOG_ENABLED
1025	/*
1026	* Disassemble the instruction if requested.
1027	*/
1028	if (pszPrefix)
1029	{
1030	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1031	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1032	}
1033	#endif /* LOG_ENABLED */
1034
1035
1036	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
1037
1038	/*
1039	* PATM is making life more interesting.
1040	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1041	* tell PATM there is a trap in this code and have it take the appropriate actions
1042	* to allow us execute the code in REM.
1043	*/
1044	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1045	{
1046	Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
1047
1048	RTGCPTR pNewEip;
1049	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1050	switch (rc)
1051	{
1052	/*
1053	* It's not very useful to emulate a single instruction and then go back to raw
1054	* mode; just execute the whole block until IF is set again.
1055	*/
1056	case VINF_SUCCESS:
1057	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1058	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1059	pCtx->eip = pNewEip;
1060	Assert(pCtx->eip);
1061
1062	if (pCtx->eflags.Bits.u1IF)
1063	{
1064	/*
1065	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1066	*/
1067	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1068	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1069	}
1070	#if 0 /** @note no noticable change; revisit later when we can emulate iret ourselves. */
1071	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1072	{
1073	/* special case: iret, that sets IF, detected a pending irq/event */
1074	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1075	}
1076	#endif
1077	return VINF_EM_RESCHEDULE_REM;
1078
1079	/*
1080	* One instruction.
1081	*/
1082	case VINF_PATCH_EMULATE_INSTR:
1083	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1084	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1085	pCtx->eip = pNewEip;
1086	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1087
1088	/*
1089	* The patch was disabled, hand it to the REM.
1090	*/
1091	case VERR_PATCH_DISABLED:
1092	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1093	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1094	pCtx->eip = pNewEip;
1095	if (pCtx->eflags.Bits.u1IF)
1096	{
1097	/*
1098	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1099	*/
1100	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1101	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1102	}
1103	return VINF_EM_RESCHEDULE_REM;
1104
1105	/* Force continued patch exection; usually due to write monitored stack. */
1106	case VINF_PATCH_CONTINUE:
1107	return VINF_SUCCESS;
1108
1109	default:
1110	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1111	return VERR_INTERNAL_ERROR;
1112	}
1113	}
1114
1115	#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1116	DISCPUSTATE Cpu;
1117	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1118	if (VBOX_SUCCESS(rc))
1119	{
1120	uint32_t size;
1121
1122	switch (Cpu.pCurInstr->opcode)
1123	{
1124	case OP_MOV:
1125	case OP_AND:
1126	case OP_OR:
1127	case OP_XOR:
1128	case OP_POP:
1129	case OP_INC:
1130	case OP_DEC:
1131	case OP_XCHG:
1132	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1133	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1134	if (VBOX_SUCCESS(rc))
1135	{
1136	pCtx->eip += Cpu.opsize;
1137	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1138	return rc;
1139	}
1140	if (rc != VERR_EM_INTERPRETER)
1141	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1142	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1143	break;
1144	}
1145	}
1146	#endif
1147	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1148	rc = REMR3EmulateInstruction(pVM);
1149	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1150
1151	return rc;
1152	}
1153
1154
1155	/**
1156	* Executes one (or perhaps a few more) instruction(s).
1157	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1158	*
1159	* @returns VBox status code suitable for EM.
1160	* @param pVM VM handle.
1161	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1162	* instruction and prefix the log output with this text.
1163	* @param rcGC GC return code
1164	*/
1165	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1166	{
1167	#ifdef LOG_ENABLED
1168	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1169	#else
1170	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1171	#endif
1172	}
1173
1174	/**
1175	* Executes one (or perhaps a few more) IO instruction(s).
1176	*
1177	* @returns VBox status code suitable for EM.
1178	* @param pVM VM handle.
1179	*/
1180	int emR3RawExecuteIOInstruction(PVM pVM)
1181	{
1182	int rc;
1183	PCPUMCTX pCtx = pVM->em.s.pCtx;
1184
1185	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1186
1187	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1188	* as io instructions tend to come in packages of more than one
1189	*/
1190	DISCPUSTATE Cpu;
1191	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1192	if (VBOX_SUCCESS(rc))
1193	{
1194	#ifdef VBOX_WITH_STATISTICS
1195	switch (Cpu.pCurInstr->opcode)
1196	{
1197	case OP_INSB:
1198	case OP_INSWD:
1199	case OP_IN:
1200	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1201	break;
1202
1203	case OP_OUTSB:
1204	case OP_OUTSWD:
1205	case OP_OUT:
1206	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1207	break;
1208	}
1209	#endif
1210
1211	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1212	{
1213	OP_PARAMVAL ParmVal;
1214	int rc;
1215	switch (Cpu.pCurInstr->opcode)
1216	{
1217	case OP_IN:
1218	{
1219	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal, PARAM_SOURCE);
1220	if ( VBOX_FAILURE(rc)
1221	\|\| ParmVal.type != PARMTYPE_IMMEDIATE)
1222	break;
1223
1224	if (!(Cpu.param1.flags & (USE_REG_GEN8 \| USE_REG_GEN16 \| USE_REG_GEN32)))
1225	break;
1226
1227	/* Make sure port access is allowed */
1228	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1229	if (rc != VINF_SUCCESS)
1230	{
1231	if (rc == VINF_EM_RAW_GUEST_TRAP)
1232	rc = emR3RawGuestTrap(pVM);
1233
1234	return rc;
1235	}
1236
1237	uint32_t u32Value = 0;
1238	switch (Cpu.param1.size)
1239	{
1240	case 1:
1241	Assert(Cpu.param1.base.reg_gen8 == USE_REG_AL);
1242	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint8_t));
1243	if (VBOX_SUCCESS(rc))
1244	{
1245	pCtx->eax = (pCtx->eax & ~0xFF) \| (uint8_t)u32Value;
1246	Log(("EMU: in8 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFF));
1247	pCtx->eip += Cpu.opsize;
1248	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1249	return rc;
1250	}
1251	AssertRC(rc);
1252	break;
1253
1254	case 2:
1255	Assert(Cpu.param1.base.reg_gen16 == USE_REG_AX);
1256	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint16_t));
1257	if (VBOX_SUCCESS(rc))
1258	{
1259	pCtx->eax = (pCtx->eax & ~0xFFFF) \| (uint16_t)u32Value;
1260	Log(("EMU: in16 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFFFF));
1261	pCtx->eip += Cpu.opsize;
1262	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1263	return rc;
1264	}
1265	AssertRC(rc);
1266	break;
1267
1268	case 4:
1269	Assert(Cpu.param1.base.reg_gen32 == USE_REG_EAX);
1270	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint32_t));
1271	if (VBOX_SUCCESS(rc))
1272	{
1273	pCtx->eax = u32Value;
1274	Log(("EMU: in32 %x, %x\n", ParmVal.val.val16, pCtx->eax));
1275	pCtx->eip += Cpu.opsize;
1276	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1277	return rc;
1278	}
1279	AssertRC(rc);
1280	break;
1281
1282	default:
1283	AssertMsgFailed(("Unexpected port size %d\n", ParmVal.size));
1284	break;
1285	}
1286	break;
1287	}
1288
1289	case OP_OUT:
1290	{
1291	// it really is the destination, but we're interested in the destination value. hence we specify PARAM_SOURCE (bit of a hack)
1292	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &ParmVal, PARAM_SOURCE);
1293	if ( VBOX_FAILURE(rc)
1294	\|\| ParmVal.type != PARMTYPE_IMMEDIATE)
1295	break;
1296	OP_PARAMVAL ParmVal2;
1297	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal2, PARAM_SOURCE);
1298	if ( VBOX_FAILURE(rc)
1299	\|\| ParmVal2.type != PARMTYPE_IMMEDIATE)
1300	break;
1301
1302	/* Make sure port access is allowed */
1303	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1304	if (rc != VINF_SUCCESS)
1305	{
1306	if (rc == VINF_EM_RAW_GUEST_TRAP)
1307	rc = emR3RawGuestTrap(pVM);
1308
1309	return rc;
1310	}
1311
1312	AssertMsg(Cpu.param2.size == ParmVal2.size, ("size %d vs %d\n", Cpu.param2.size, ParmVal2.size));
1313	switch (ParmVal2.size)
1314	{
1315	case 1:
1316	Log(("EMU: out8 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val8));
1317	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val8, sizeof(ParmVal2.val.val8));
1318	if (VBOX_SUCCESS(rc))
1319	{
1320	pCtx->eip += Cpu.opsize;
1321	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1322	return rc;
1323	}
1324	AssertRC(rc);
1325	break;
1326
1327	case 2:
1328	Log(("EMU: out16 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val16));
1329	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val16, sizeof(ParmVal2.val.val16));
1330	if (VBOX_SUCCESS(rc))
1331	{
1332	pCtx->eip += Cpu.opsize;
1333	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1334	return rc;
1335	}
1336	AssertRC(rc);
1337	break;
1338
1339	case 4:
1340	Log(("EMU: out32 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val32));
1341	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val32, sizeof(ParmVal2.val.val32));
1342	if (VBOX_SUCCESS(rc))
1343	{
1344	pCtx->eip += Cpu.opsize;
1345	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1346	return rc;
1347	}
1348	AssertRC(rc);
1349	break;
1350
1351	default:
1352	AssertMsgFailed(("Unexpected port size %d\n", ParmVal2.size));
1353	break;
1354	}
1355	break;
1356	}
1357
1358	default:
1359	break;
1360	}
1361	}//if(!(Cpu.prefix & (PREFIX_REP\|PREFIX_REPNE))
1362	else if (Cpu.prefix & PREFIX_REP)
1363	{
1364	switch (Cpu.pCurInstr->opcode)
1365	{
1366	case OP_INSB:
1367	case OP_INSWD:
1368	{
1369	/*
1370	* Do not optimize the destination address decrement case (not worth the effort)
1371	* and likewise for 16 bit address size (would need to use and update only cx/di).
1372	*/
1373	if (pCtx->eflags.Bits.u1DF \|\| Cpu.addrmode != CPUMODE_32BIT)
1374	break;
1375	/*
1376	* Get port number and transfer count directly from the registers (no need to bother the
1377	* disassembler). And get the I/O register size from the opcode / prefix.
1378	*/
1379	uint32_t uPort = pCtx->edx & 0xffff;
1380	RTGCUINTREG cTransfers = pCtx->ecx;
1381	unsigned cbUnit;
1382	if (Cpu.pCurInstr->opcode == OP_INSB)
1383	cbUnit = 1;
1384	else
1385	cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1386
1387	RTGCPTR GCPtrDst = pCtx->edi;
1388	/* Access verification first; we can't recover from traps inside this instruction, as the port read cannot be repeated. */
1389	rc = PGMVerifyAccess(pVM, GCPtrDst, cTransfers * cbUnit,
1390	X86_PTE_RW \| (((pCtx->ss & X86_SEL_RPL) == 3) ? X86_PTE_US : 0));
1391	if (rc != VINF_SUCCESS)
1392	{
1393	Log(("EMU: rep ins%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1394	break;
1395	}
1396
1397	Log(("EMU: rep ins%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1398
1399	/* Make sure port access is allowed */
1400	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1401	if (rc != VINF_SUCCESS)
1402	{
1403	if (rc == VINF_EM_RAW_GUEST_TRAP)
1404	rc = emR3RawGuestTrap(pVM);
1405
1406	return rc;
1407	}
1408
1409	/*
1410	* If the device supports string transfers, ask it to do as
1411	* much as it wants. The rest is done with single-word transfers.
1412	*/
1413	rc = IOMIOPortReadString(pVM, uPort, &GCPtrDst, &cTransfers, cbUnit);
1414	AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1415
1416	while (cTransfers && rc == VINF_SUCCESS)
1417	{
1418	uint32_t u32Value;
1419	rc = IOMIOPortRead(pVM, uPort, &u32Value, cbUnit);
1420	AssertRC(rc);
1421	int rc2 = PGMPhysWriteGCPtrDirty(pVM, GCPtrDst, &u32Value, cbUnit);
1422	AssertRC(rc2);
1423	GCPtrDst += cbUnit;
1424	cTransfers--;
1425	}
1426	pCtx->edi += (pCtx->ecx - cTransfers) * cbUnit;
1427	pCtx->ecx = cTransfers;
1428	if (!cTransfers && VBOX_SUCCESS(rc))
1429	pCtx->eip += Cpu.opsize;
1430	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1431	return rc;
1432	}
1433	case OP_OUTSB:
1434	case OP_OUTSWD:
1435	{
1436	/*
1437	* Do not optimize the source address decrement case (not worth the effort)
1438	* and likewise for 16 bit address size (would need to use and update only cx/si).
1439	*/
1440	if (pCtx->eflags.Bits.u1DF \|\| Cpu.addrmode != CPUMODE_32BIT)
1441	break;
1442	/*
1443	* Get port number and transfer count directly from the registers (no need to bother the
1444	* disassembler). And get the I/O register size from the opcode / prefix.
1445	*/
1446	uint32_t uPort = pCtx->edx & 0xffff;
1447	RTGCUINTREG cTransfers = pCtx->ecx;
1448	unsigned cbUnit;
1449	if (Cpu.pCurInstr->opcode == OP_OUTSB)
1450	cbUnit = 1;
1451	else
1452	cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1453
1454	RTGCPTR GCPtrSrc = pCtx->esi;
1455	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1456	rc = PGMVerifyAccess(pVM, GCPtrSrc, cTransfers * cbUnit, (((pCtx->ss & X86_SEL_RPL) == 3) ? X86_PTE_US : 0));
1457	if (rc != VINF_SUCCESS)
1458	{
1459	Log(("EMU: rep outs%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1460	break;
1461	}
1462
1463	Log(("EMU: rep outs%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1464
1465	/* Make sure port access is allowed */
1466	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1467	if (rc != VINF_SUCCESS)
1468	{
1469	if (rc == VINF_EM_RAW_GUEST_TRAP)
1470	rc = emR3RawGuestTrap(pVM);
1471
1472	return rc;
1473	}
1474
1475	/*
1476	* If the device supports string transfers, ask it to do as
1477	* much as it wants. The rest is done with single-word transfers.
1478	*/
1479	rc = IOMIOPortWriteString(pVM, uPort, &GCPtrSrc, &cTransfers, cbUnit);
1480	AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1481
1482	while (cTransfers && rc == VINF_SUCCESS)
1483	{
1484	uint32_t u32Value;
1485	rc = PGMPhysReadGCPtr(pVM, &u32Value, GCPtrSrc, cbUnit);
1486	Assert(rc == VINF_SUCCESS);
1487	rc = IOMIOPortWrite(pVM, uPort, u32Value, cbUnit);
1488	AssertRC(rc);
1489	GCPtrSrc += cbUnit;
1490	cTransfers--;
1491	}
1492	pCtx->esi += (pCtx->ecx - cTransfers) * cbUnit;
1493	pCtx->ecx = cTransfers;
1494	if (!cTransfers && VBOX_SUCCESS(rc))
1495	pCtx->eip += Cpu.opsize;
1496	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1497	return rc;
1498	}
1499	}
1500	}//if(Cpu.prefix & PREFIX_REP)
1501	}
1502
1503	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1504	return emR3RawExecuteInstruction(pVM, "IO: ");
1505	}
1506
1507
1508	/**
1509	* Handle a guest context trap.
1510	*
1511	* @returns VBox status code suitable for EM.
1512	* @param pVM VM handle.
1513	*/
1514	static int emR3RawGuestTrap(PVM pVM)
1515	{
1516	PCPUMCTX pCtx = pVM->em.s.pCtx;
1517
1518	/*
1519	* Get the trap info.
1520	*/
1521	uint8_t u8TrapNo;
1522	bool fSoftwareInterrupt;
1523	RTGCUINT uErrorCode;
1524	RTGCUINTPTR uCR2;
1525	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
1526	if (VBOX_FAILURE(rc))
1527	{
1528	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1529	return rc;
1530	}
1531
1532	/* Traps can be directly forwarded in hardware accelerated mode. */
1533	if (HWACCMR3IsActive(pVM))
1534	{
1535	#ifdef LOGGING_ENABLED
1536	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1537	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1538	#endif
1539	return VINF_EM_RESCHEDULE_HWACC;
1540	}
1541
1542	/** Scan kernel code that traps; we might not get another chance. */
1543	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1544	&& pCtx->eflags.Bits.u1VM == 0)
1545	{
1546	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1547	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
1548	}
1549
1550	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1551	{
1552	DISCPUSTATE cpu;
1553
1554	/* If MONITOR & MWAIT are supported, then interpret them here. */
1555	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1556	if ( VBOX_SUCCESS(rc)
1557	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1558	{
1559	uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1560
1561	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1562
1563	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1564	{
1565	rc = TRPMResetTrap(pVM);
1566	AssertRC(rc);
1567
1568	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1569	if (VBOX_SUCCESS(rc))
1570	{
1571	pCtx->eip += cpu.opsize;
1572	return rc;
1573	}
1574	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1575	}
1576	}
1577	}
1578	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1579	{
1580	DISCPUSTATE cpu;
1581
1582	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1583	if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1584	{
1585	/*
1586	* We should really check the TSS for the IO bitmap, but it's not like this
1587	* lazy approach really makes things worse.
1588	*/
1589	rc = TRPMResetTrap(pVM);
1590	AssertRC(rc);
1591	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1592	}
1593	}
1594
1595	#ifdef LOG_ENABLED
1596	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1597	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1598
1599	/* Get guest page information. */
1600	uint64_t fFlags = 0;
1601	RTGCPHYS GCPhys = 0;
1602	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1603	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1604	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, fSoftwareInterrupt ? " software" : "", GCPhys, fFlags,
1605	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1606	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1607	#endif
1608
1609	/*
1610	* #PG has CR2.
1611	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1612	*/
1613	if (u8TrapNo == 14 /* #PG */)
1614	pCtx->cr2 = uCR2;
1615
1616	return VINF_EM_RESCHEDULE_REM;
1617	}
1618
1619
1620	/**
1621	* Handle a ring switch trap.
1622	* Need to do statistics and to install patches. The result is going to REM.
1623	*
1624	* @returns VBox status code suitable for EM.
1625	* @param pVM VM handle.
1626	*/
1627	int emR3RawRingSwitch(PVM pVM)
1628	{
1629	int rc;
1630	DISCPUSTATE Cpu;
1631	PCPUMCTX pCtx = pVM->em.s.pCtx;
1632
1633	/*
1634	* sysenter, syscall & callgate
1635	*/
1636	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1637	if (VBOX_SUCCESS(rc))
1638	{
1639	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1640	{
1641	if (pCtx->SysEnter.cs != 0)
1642	{
1643	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip),
1644	SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1645	if (VBOX_SUCCESS(rc))
1646	{
1647	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1648	return VINF_EM_RESCHEDULE_RAW;
1649	}
1650	}
1651	}
1652
1653	#ifdef VBOX_WITH_STATISTICS
1654	switch (Cpu.pCurInstr->opcode)
1655	{
1656	case OP_SYSENTER:
1657	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1658	break;
1659	case OP_SYSEXIT:
1660	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1661	break;
1662	case OP_SYSCALL:
1663	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1664	break;
1665	case OP_SYSRET:
1666	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1667	break;
1668	}
1669	#endif
1670	}
1671	else
1672	AssertRC(rc);
1673
1674	/* go to the REM to emulate a single instruction */
1675	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1676	}
1677
1678	/**
1679	* Handle a trap (#PF or #GP) in patch code
1680	*
1681	* @returns VBox status code suitable for EM.
1682	* @param pVM VM handle.
1683	* @param pCtx CPU context
1684	* @param gcret GC return code
1685	*/
1686	int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1687	{
1688	uint8_t u8TrapNo;
1689	int rc;
1690	bool fSoftwareInterrupt;
1691	RTGCUINT uErrorCode;
1692	RTGCUINTPTR uCR2;
1693
1694	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1695
1696	if (gcret == VINF_PATM_PATCH_INT3)
1697	{
1698	u8TrapNo = 3;
1699	uCR2 = 0;
1700	uErrorCode = 0;
1701	}
1702	else
1703	if (gcret == VINF_PATM_PATCH_TRAP_GP)
1704	{
1705	/* No active trap in this case. Kind of ugly. */
1706	u8TrapNo = X86_XCPT_GP;
1707	uCR2 = 0;
1708	uErrorCode = 0;
1709	}
1710	else
1711	{
1712	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
1713	if (VBOX_FAILURE(rc))
1714	{
1715	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1716	return rc;
1717	}
1718	/* Reset the trap as we'll execute the original instruction again. */
1719	TRPMResetTrap(pVM);
1720	}
1721
1722	/*
1723	* Deal with traps inside patch code.
1724	* (This code won't run outside GC.)
1725	*/
1726	if (u8TrapNo != 1)
1727	{
1728	#ifdef LOG_ENABLED
1729	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1730	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1731	#endif
1732	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1733	pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1734
1735	RTGCPTR pNewEip;
1736	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1737	switch (rc)
1738	{
1739	/*
1740	* Execute the faulting instruction.
1741	*/
1742	case VINF_SUCCESS:
1743	{
1744	/** @todo execute a whole block */
1745	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1746	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1747	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1748
1749	pCtx->eip = pNewEip;
1750	AssertRelease(pCtx->eip);
1751
1752	if (pCtx->eflags.Bits.u1IF)
1753	{
1754	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1755	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1756	*/
1757	if ( u8TrapNo == X86_XCPT_GP
1758	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1759	{
1760	/** @todo move to PATMR3HandleTrap */
1761	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1762	PATMR3RemovePatch(pVM, pCtx->eip);
1763	}
1764
1765	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1766	/** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1767
1768	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1769	/* Interrupts are enabled; just go back to the original instruction.
1770	return VINF_SUCCESS; */
1771	}
1772	return VINF_EM_RESCHEDULE_REM;
1773	}
1774
1775	/*
1776	* One instruction.
1777	*/
1778	case VINF_PATCH_EMULATE_INSTR:
1779	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1780	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1781	pCtx->eip = pNewEip;
1782	AssertRelease(pCtx->eip);
1783	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1784
1785	/*
1786	* The patch was disabled, hand it to the REM.
1787	*/
1788	case VERR_PATCH_DISABLED:
1789	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1790	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1791	pCtx->eip = pNewEip;
1792	AssertRelease(pCtx->eip);
1793
1794	if (pCtx->eflags.Bits.u1IF)
1795	{
1796	/*
1797	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1798	*/
1799	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1800	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1801	}
1802	return VINF_EM_RESCHEDULE_REM;
1803
1804	/* Force continued patch exection; usually due to write monitored stack. */
1805	case VINF_PATCH_CONTINUE:
1806	return VINF_SUCCESS;
1807
1808	/*
1809	* Anything else is fatal.
1810	*/
1811	default:
1812	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1813	return VERR_INTERNAL_ERROR;
1814	}
1815	}
1816	return VINF_SUCCESS;
1817	}
1818
1819
1820	/**
1821	* Handle a privileged instruction.
1822	*
1823	* @returns VBox status code suitable for EM.
1824	* @param pVM VM handle.
1825	*/
1826	int emR3RawPrivileged(PVM pVM)
1827	{
1828	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1829	PCPUMCTX pCtx = pVM->em.s.pCtx;
1830
1831	Assert(!pCtx->eflags.Bits.u1VM);
1832
1833	if (PATMIsEnabled(pVM))
1834	{
1835	/*
1836	* Check if in patch code.
1837	*/
1838	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1839	{
1840	#ifdef LOG_ENABLED
1841	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1842	#endif
1843	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1844	return VERR_EM_RAW_PATCH_CONFLICT;
1845	}
1846	if ( (pCtx->ss & X86_SEL_RPL) == 0
1847	&& !pCtx->eflags.Bits.u1VM
1848	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1849	{
1850	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip),
1851	SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1852	if (VBOX_SUCCESS(rc))
1853	{
1854	#ifdef LOG_ENABLED
1855	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1856	#endif
1857	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1858	return VINF_SUCCESS;
1859	}
1860	}
1861	}
1862
1863	#ifdef LOG_ENABLED
1864	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1865	{
1866	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1867	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1868	}
1869	#endif
1870
1871	/*
1872	* Instruction statistics and logging.
1873	*/
1874	DISCPUSTATE Cpu;
1875	int rc;
1876
1877	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1878	if (VBOX_SUCCESS(rc))
1879	{
1880	#ifdef VBOX_WITH_STATISTICS
1881	PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1882	switch (Cpu.pCurInstr->opcode)
1883	{
1884	case OP_INVLPG:
1885	STAM_COUNTER_INC(&pStats->StatInvlpg);
1886	break;
1887	case OP_IRET:
1888	STAM_COUNTER_INC(&pStats->StatIret);
1889	break;
1890	case OP_CLI:
1891	STAM_COUNTER_INC(&pStats->StatCli);
1892	emR3RecordCli(pVM, pCtx->eip);
1893	break;
1894	case OP_STI:
1895	STAM_COUNTER_INC(&pStats->StatSti);
1896	break;
1897	case OP_INSB:
1898	case OP_INSWD:
1899	case OP_IN:
1900	case OP_OUTSB:
1901	case OP_OUTSWD:
1902	case OP_OUT:
1903	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1904	break;
1905
1906	case OP_MOV_CR:
1907	if (Cpu.param1.flags & USE_REG_GEN32)
1908	{
1909	//read
1910	Assert(Cpu.param2.flags & USE_REG_CR);
1911	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1912	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1913	}
1914	else
1915	{
1916	//write
1917	Assert(Cpu.param1.flags & USE_REG_CR);
1918	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1919	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1920	}
1921	break;
1922
1923	case OP_MOV_DR:
1924	STAM_COUNTER_INC(&pStats->StatMovDRx);
1925	break;
1926	case OP_LLDT:
1927	STAM_COUNTER_INC(&pStats->StatMovLldt);
1928	break;
1929	case OP_LIDT:
1930	STAM_COUNTER_INC(&pStats->StatMovLidt);
1931	break;
1932	case OP_LGDT:
1933	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1934	break;
1935	case OP_SYSENTER:
1936	STAM_COUNTER_INC(&pStats->StatSysEnter);
1937	break;
1938	case OP_SYSEXIT:
1939	STAM_COUNTER_INC(&pStats->StatSysExit);
1940	break;
1941	case OP_SYSCALL:
1942	STAM_COUNTER_INC(&pStats->StatSysCall);
1943	break;
1944	case OP_SYSRET:
1945	STAM_COUNTER_INC(&pStats->StatSysRet);
1946	break;
1947	case OP_HLT:
1948	STAM_COUNTER_INC(&pStats->StatHlt);
1949	break;
1950	default:
1951	STAM_COUNTER_INC(&pStats->StatMisc);
1952	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1953	break;
1954	}
1955	#endif
1956	if ( (pCtx->ss & X86_SEL_RPL) == 0
1957	&& SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid))
1958	{
1959	uint32_t size;
1960
1961	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1962	switch (Cpu.pCurInstr->opcode)
1963	{
1964	case OP_CLI:
1965	pCtx->eflags.u32 &= ~X86_EFL_IF;
1966	Assert(Cpu.opsize == 1);
1967	pCtx->eip += Cpu.opsize;
1968	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1969	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1970
1971	case OP_STI:
1972	pCtx->eflags.u32 \|= X86_EFL_IF;
1973	EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
1974	Assert(Cpu.opsize == 1);
1975	pCtx->eip += Cpu.opsize;
1976	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1977	return VINF_SUCCESS;
1978
1979	case OP_HLT:
1980	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1981	{
1982	PATMTRANSSTATE enmState;
1983	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1984
1985	if (enmState == PATMTRANS_OVERWRITTEN)
1986	{
1987	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1988	Assert(rc == VERR_PATCH_DISABLED);
1989	/* Conflict detected, patch disabled */
1990	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1991
1992	enmState = PATMTRANS_SAFE;
1993	}
1994
1995	/* The translation had better be successful. Otherwise we can't recover. */
1996	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1997	if (enmState != PATMTRANS_OVERWRITTEN)
1998	pCtx->eip = pOrgInstrGC;
1999	}
2000	/* no break; we could just return VINF_EM_HALT here */
2001
2002	case OP_MOV_CR:
2003	case OP_MOV_DR:
2004	#ifdef LOG_ENABLED
2005	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2006	{
2007	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2008	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2009	}
2010	#endif
2011
2012	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2013	if (VBOX_SUCCESS(rc))
2014	{
2015	pCtx->eip += Cpu.opsize;
2016	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2017
2018	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2019	&& Cpu.param1.flags == USE_REG_CR /* write */
2020	)
2021	{
2022	/* Reschedule is necessary as the execution/paging mode might have changed. */
2023	return VINF_EM_RESCHEDULE;
2024	}
2025	return rc; /* can return VINF_EM_HALT as well. */
2026	}
2027	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
2028	break; /* fall back to the recompiler */
2029	}
2030	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2031	}
2032	}
2033
2034	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2035	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
2036
2037	return emR3RawExecuteInstruction(pVM, "PRIV");
2038	}
2039
2040
2041	/**
2042	* Update the forced rawmode execution modifier.
2043	*
2044	* This function is called when we're returning from the raw-mode loop(s). If we're
2045	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2046	* if not in patch code, the flag will be cleared.
2047	*
2048	* We should never interrupt patch code while it's being executed. Cli patches can
2049	* contain big code blocks, but they are always executed with IF=0. Other patches
2050	* replace single instructions and should be atomic.
2051	*
2052	* @returns Updated rc.
2053	*
2054	* @param pVM The VM handle.
2055	* @param pCtx The guest CPU context.
2056	* @param rc The result code.
2057	*/
2058	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2059	{
2060	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2061	{
2062	/* ignore reschedule attempts. */
2063	switch (rc)
2064	{
2065	case VINF_EM_RESCHEDULE:
2066	case VINF_EM_RESCHEDULE_REM:
2067	rc = VINF_SUCCESS;
2068	break;
2069	}
2070	pVM->em.s.fForceRAW = true;
2071	}
2072	else
2073	pVM->em.s.fForceRAW = false;
2074	return rc;
2075	}
2076
2077
2078	/**
2079	* Process a subset of the raw-mode return code.
2080	*
2081	* Since we have to share this with raw-mode single stepping, this inline
2082	* function has been created to avoid code duplication.
2083	*
2084	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2085	* @returns VBox status code to return to the EM main loop.
2086	*
2087	* @param pVM The VM handle
2088	* @param rc The return code.
2089	* @param pCtx The guest cpu context.
2090	*/
2091	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2092	{
2093	switch (rc)
2094	{
2095	/*
2096	* Common & simple ones.
2097	*/
2098	case VINF_SUCCESS:
2099	break;
2100	case VINF_EM_RESCHEDULE_RAW:
2101	case VINF_EM_RESCHEDULE_HWACC:
2102	case VINF_EM_RAW_INTERRUPT:
2103	case VINF_EM_RAW_TO_R3:
2104	case VINF_EM_RAW_TIMER_PENDING:
2105	case VINF_EM_PENDING_REQUEST:
2106	rc = VINF_SUCCESS;
2107	break;
2108
2109	/*
2110	* Privileged instruction.
2111	*/
2112	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2113	case VINF_PATM_PATCH_TRAP_GP:
2114	rc = emR3RawPrivileged(pVM);
2115	break;
2116
2117	/*
2118	* Got a trap which needs dispatching.
2119	*/
2120	case VINF_EM_RAW_GUEST_TRAP:
2121	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2122	{
2123	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2124	rc = VERR_EM_RAW_PATCH_CONFLICT;
2125	break;
2126	}
2127	uint8_t u8Interrupt;
2128
2129	Assert(TRPMHasTrap(pVM));
2130	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2131
2132	if (TRPMHasTrap(pVM))
2133	{
2134	u8Interrupt = TRPMGetTrapNo(pVM);
2135
2136	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2137	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2138	{
2139	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2140	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2141	/** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2142	}
2143	}
2144	rc = emR3RawGuestTrap(pVM);
2145	break;
2146
2147	/*
2148	* Trap in patch code.
2149	*/
2150	case VINF_PATM_PATCH_TRAP_PF:
2151	case VINF_PATM_PATCH_INT3:
2152	rc = emR3PatchTrap(pVM, pCtx, rc);
2153	break;
2154
2155	case VINF_PATM_DUPLICATE_FUNCTION:
2156	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2157	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2158	AssertRC(rc);
2159	rc = VINF_SUCCESS;
2160	break;
2161
2162	case VINF_PATM_CHECK_PATCH_PAGE:
2163	rc = PATMR3HandleMonitoredPage(pVM);
2164	AssertRC(rc);
2165	rc = VINF_SUCCESS;
2166	break;
2167
2168	/*
2169	* Patch manager.
2170	*/
2171	case VERR_EM_RAW_PATCH_CONFLICT:
2172	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2173	break;
2174
2175	/*
2176	* Memory mapped I/O access - attempt to patch the instruction
2177	*/
2178	case VINF_PATM_HC_MMIO_PATCH_READ:
2179	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip),
2180	PATMFL_MMIO_ACCESS \| (SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2181	if (VBOX_FAILURE(rc))
2182	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2183	break;
2184
2185	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2186	AssertFailed(); /* not yet implemented. */
2187	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2188	break;
2189
2190	/*
2191	* Conflict or out of page tables.
2192	*
2193	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2194	* do here is to execute the pending forced actions.
2195	*/
2196	case VINF_PGM_SYNC_CR3:
2197	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2198	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2199	rc = VINF_SUCCESS;
2200	break;
2201
2202	/*
2203	* Paging mode change.
2204	*/
2205	case VINF_PGM_CHANGE_MODE:
2206	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2207	if (VBOX_SUCCESS(rc))
2208	rc = VINF_EM_RESCHEDULE;
2209	break;
2210
2211	/*
2212	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2213	*/
2214	case VINF_CSAM_PENDING_ACTION:
2215	rc = VINF_SUCCESS;
2216	break;
2217
2218	/*
2219	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2220	*/
2221	case VINF_EM_RAW_INTERRUPT_PENDING:
2222	case VINF_EM_RAW_RING_SWITCH_INT:
2223	{
2224	uint8_t u8Interrupt;
2225
2226	Assert(TRPMHasTrap(pVM));
2227	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2228
2229	if (TRPMHasTrap(pVM))
2230	{
2231	u8Interrupt = TRPMGetTrapNo(pVM);
2232
2233	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2234	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2235	{
2236	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2237	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2238	/** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2239	}
2240	}
2241	rc = VINF_EM_RESCHEDULE_REM;
2242	break;
2243	}
2244
2245	/*
2246	* Other ring switch types.
2247	*/
2248	case VINF_EM_RAW_RING_SWITCH:
2249	rc = emR3RawRingSwitch(pVM);
2250	break;
2251
2252	/*
2253	* REMGCNotifyInvalidatePage() failed because of overflow.
2254	*/
2255	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2256	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2257	REMR3ReplayInvalidatedPages(pVM);
2258	break;
2259
2260	/*
2261	* I/O Port access - emulate the instruction.
2262	*/
2263	case VINF_IOM_HC_IOPORT_READ:
2264	case VINF_IOM_HC_IOPORT_WRITE:
2265	case VINF_IOM_HC_IOPORT_READWRITE:
2266	rc = emR3RawExecuteIOInstruction(pVM);
2267	break;
2268
2269	/*
2270	* Memory mapped I/O access - emulate the instruction.
2271	*/
2272	case VINF_IOM_HC_MMIO_READ:
2273	case VINF_IOM_HC_MMIO_WRITE:
2274	case VINF_IOM_HC_MMIO_READ_WRITE:
2275	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2276	break;
2277
2278	/*
2279	* Execute instruction.
2280	*/
2281	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2282	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2283	break;
2284	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2285	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2286	break;
2287	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2288	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2289	break;
2290	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2291	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2292	break;
2293	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2294	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2295	break;
2296
2297	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2298	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2299	rc = emR3RawPrivileged(pVM);
2300	break;
2301
2302	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2303	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2304	break;
2305
2306	case VINF_EM_RAW_EMULATE_INSTR:
2307	case VINF_PATCH_EMULATE_INSTR:
2308	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2309	break;
2310
2311	/*
2312	* Stale selector and iret traps => REM.
2313	*/
2314	case VINF_EM_RAW_STALE_SELECTOR:
2315	case VINF_EM_RAW_IRET_TRAP:
2316	/* We will not go to the recompiler if EIP points to patch code. */
2317	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2318	{
2319	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2320	}
2321	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2322	rc = VINF_EM_RESCHEDULE_REM;
2323	break;
2324
2325	/*
2326	* Up a level.
2327	*/
2328	case VINF_EM_TERMINATE:
2329	case VINF_EM_OFF:
2330	case VINF_EM_RESET:
2331	case VINF_EM_SUSPEND:
2332	case VINF_EM_HALT:
2333	case VINF_EM_RESUME:
2334	case VINF_EM_RESCHEDULE:
2335	case VINF_EM_RESCHEDULE_REM:
2336	break;
2337
2338	/*
2339	* Up a level and invoke the debugger.
2340	*/
2341	case VINF_EM_DBG_STEPPED:
2342	case VINF_EM_DBG_BREAKPOINT:
2343	case VINF_EM_DBG_STEP:
2344	case VINF_EM_DBG_HYPER_ASSERTION:
2345	case VINF_EM_DBG_HYPER_BREAKPOINT:
2346	case VINF_EM_DBG_HYPER_STEPPED:
2347	case VINF_EM_DBG_STOP:
2348	break;
2349
2350	/*
2351	* Up a level, dump and debug.
2352	*/
2353	case VERR_TRPM_DONT_PANIC:
2354	case VERR_TRPM_PANIC:
2355	break;
2356
2357	/*
2358	* Anything which is not known to us means an internal error
2359	* and the termination of the VM!
2360	*/
2361	default:
2362	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2363	break;
2364	}
2365	return rc;
2366	}
2367
2368
2369	/**
2370	* Process raw-mode specific forced actions.
2371	*
2372	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2373	*
2374	* @returns VBox status code.
2375	* Only the normal success/failure stuff, no VINF_EM_*.
2376	* @param pVM The VM handle.
2377	* @param pCtx The guest CPUM register context.
2378	*/
2379	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2380	{
2381	/*
2382	* Note that the order is vitally important!
2383	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2384	*/
2385
2386
2387	/*
2388	* Sync selector tables.
2389	*/
2390	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2391	{
2392	int rc = SELMR3UpdateFromCPUM(pVM);
2393	if (VBOX_FAILURE(rc))
2394	return rc;
2395	}
2396
2397	/*
2398	* Sync IDT.
2399	*/
2400	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2401	{
2402	int rc = TRPMR3SyncIDT(pVM);
2403	if (VBOX_FAILURE(rc))
2404	return rc;
2405	}
2406
2407	/*
2408	* Sync TSS.
2409	*/
2410	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2411	{
2412	int rc = SELMR3SyncTSS(pVM);
2413	if (VBOX_FAILURE(rc))
2414	return rc;
2415	}
2416
2417	/*
2418	* Sync page directory.
2419	*/
2420	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2421	{
2422	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2423	if (VBOX_FAILURE(rc))
2424	return rc;
2425
2426	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2427
2428	/* Prefetch pages for EIP and ESP */
2429	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2430	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip));
2431	if (rc == VINF_SUCCESS)
2432	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2433	if (rc != VINF_SUCCESS)
2434	{
2435	if (rc != VINF_PGM_SYNC_CR3)
2436	return rc;
2437	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2438	if (VBOX_FAILURE(rc))
2439	return rc;
2440	}
2441	/** @todo maybe prefetch the supervisor stack page as well */
2442	}
2443
2444	return VINF_SUCCESS;
2445	}
2446
2447
2448	/**
2449	* Executes raw code.
2450	*
2451	* This function contains the raw-mode version of the inner
2452	* execution loop (the outer loop being in EMR3ExecuteVM()).
2453	*
2454	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2455	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2456	*
2457	* @param pVM VM handle.
2458	* @param pfFFDone Where to store an indicator telling whether or not
2459	* FFs were done before returning.
2460	*/
2461	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2462	{
2463	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2464
2465	int rc = VERR_INTERNAL_ERROR;
2466	PCPUMCTX pCtx = pVM->em.s.pCtx;
2467	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2468	pVM->em.s.fForceRAW = false;
2469	*pfFFDone = false;
2470
2471
2472	/*
2473	*
2474	* Spin till we get a forced action or raw mode status code resulting in
2475	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2476	*
2477	*/
2478	for (;;)
2479	{
2480	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2481
2482	/*
2483	* Check various preconditions.
2484	*/
2485	#ifdef VBOX_STRICT
2486	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2487	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2488	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2489	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2490	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2491	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2492	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2493	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2494	{
2495	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2496	return VERR_INTERNAL_ERROR;
2497	}
2498	#endif /* VBOX_STRICT */
2499
2500	/*
2501	* Process high priority pre-execution raw-mode FFs.
2502	*/
2503	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2504	{
2505	rc = emR3RawForcedActions(pVM, pCtx);
2506	if (VBOX_FAILURE(rc))
2507	break;
2508	}
2509
2510	/*
2511	* If we're going to execute ring-0 code, the guest state needs to
2512	* be modified a bit and some of the state components (IF, SS/CS RPL,
2513	* and perhaps EIP) needs to be stored with PATM.
2514	*/
2515	rc = CPUMRawEnter(pVM, NULL);
2516	if (rc != VINF_SUCCESS)
2517	{
2518	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2519	break;
2520	}
2521
2522	/*
2523	* Scan code before executing it. Don't bother with user mode or V86 code
2524	*/
2525	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2526	&& pCtx->eflags.Bits.u1VM == 0
2527	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2528	{
2529	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2530	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2531	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2532	}
2533
2534	#ifdef LOG_ENABLED
2535	/*
2536	* Log important stuff before entering GC.
2537	*/
2538	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2539	if (pCtx->eflags.Bits.u1VM)
2540	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2541	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2542	{
2543	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2544	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2545	}
2546	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2547	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2548	#endif /* LOG_ENABLED */
2549
2550
2551
2552	/*
2553	* Execute the code.
2554	*/
2555	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2556	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2557	VMMR3Unlock(pVM);
2558	rc = VMMR3RawRunGC(pVM);
2559	VMMR3Lock(pVM);
2560	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2561	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2562
2563	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2564	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2565
2566
2567	/*
2568	* Restore the real CPU state and deal with high priority post
2569	* execution FFs before doing anything else.
2570	*/
2571	rc = CPUMRawLeave(pVM, NULL, rc);
2572	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2573	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2574	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2575
2576	#ifdef PGM_CACHE_VERY_STRICT
2577	/*
2578	* Page manager cache checks.
2579	*/
2580	if ( rc == VINF_EM_RAW_INTERRUPT
2581	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2582	\|\| rc == VINF_IOM_HC_IOPORT_READ
2583	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2584	\|\| rc == VINF_IOM_HC_IOPORT_READWRITE
2585	//\|\| rc == VINF_PATM_PATCH_INT3
2586	)
2587	pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2588	#endif
2589
2590	#ifdef VBOX_STRICT
2591	/*
2592	* Assert TSS consistency & rc vs patch code.
2593	*/
2594	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2595	&& EMIsRawRing0Enabled(pVM))
2596	SELMR3CheckTSS(pVM);
2597	switch (rc)
2598	{
2599	case VINF_SUCCESS:
2600	case VINF_EM_RAW_INTERRUPT:
2601	case VINF_PATM_PATCH_TRAP_PF:
2602	case VINF_PATM_PATCH_TRAP_GP:
2603	case VINF_PATM_PATCH_INT3:
2604	case VINF_PATM_CHECK_PATCH_PAGE:
2605	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2606	case VINF_EM_RAW_GUEST_TRAP:
2607	case VINF_EM_RESCHEDULE_RAW:
2608	break;
2609
2610	default:
2611	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2612	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2613	break;
2614	}
2615	/*
2616	* Let's go paranoid!
2617	*/
2618	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2619	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2620	{
2621	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2622	return VERR_INTERNAL_ERROR;
2623	}
2624	#endif /* VBOX_STRICT */
2625
2626	/*
2627	* Process the returned status code.
2628	*/
2629	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2630	{
2631	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2632	break;
2633	}
2634	rc = emR3RawHandleRC(pVM, pCtx, rc);
2635	if (rc != VINF_SUCCESS)
2636	{
2637	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2638	if (rc != VINF_SUCCESS)
2639	{
2640	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2641	break;
2642	}
2643	}
2644
2645	/*
2646	* Check and execute forced actions.
2647	*/
2648	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2649	TMTimerPoll(pVM);
2650	#endif
2651	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2652	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2653	{
2654	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2655
2656	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2657	rc = emR3ForcedActions(pVM, rc);
2658	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2659	if ( rc != VINF_SUCCESS
2660	&& rc != VINF_EM_RESCHEDULE_RAW)
2661	{
2662	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2663	if (rc != VINF_SUCCESS)
2664	{
2665	*pfFFDone = true;
2666	break;
2667	}
2668	}
2669	}
2670	}
2671
2672	/*
2673	* Return to outer loop.
2674	*/
2675	#if defined(LOG_ENABLED) && defined(DEBUG)
2676	RTLogFlush(NULL);
2677	#endif
2678	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2679	return rc;
2680	}
2681
2682
2683	/**
2684	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2685	*
2686	* This function contains the raw-mode version of the inner
2687	* execution loop (the outer loop being in EMR3ExecuteVM()).
2688	*
2689	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2690	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2691	*
2692	* @param pVM VM handle.
2693	* @param pfFFDone Where to store an indicator telling whether or not
2694	* FFs were done before returning.
2695	*/
2696	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2697	{
2698	int rc = VERR_INTERNAL_ERROR;
2699	PCPUMCTX pCtx = pVM->em.s.pCtx;
2700
2701	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2702	*pfFFDone = false;
2703
2704	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2705
2706	/*
2707	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2708	*/
2709	for (;;)
2710	{
2711	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2712
2713	/*
2714	* Check various preconditions.
2715	*/
2716	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2717
2718	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2719
2720	/*
2721	* Sync page directory.
2722	*/
2723	if (VM_FF_ISPENDING(pVM, (VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)))
2724	{
2725	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2726	if (VBOX_FAILURE(rc))
2727	return rc;
2728
2729	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2730
2731	/* Prefetch pages for EIP and ESP */
2732	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip));
2733	if (rc == VINF_SUCCESS)
2734	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2735	if (rc != VINF_SUCCESS)
2736	{
2737	if (rc != VINF_PGM_SYNC_CR3)
2738	return rc;
2739	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2740	if (VBOX_FAILURE(rc))
2741	return rc;
2742	}
2743
2744	/** @todo maybe prefetch the supervisor stack page as well */
2745	}
2746
2747	#ifdef LOG_ENABLED
2748	uint8_t u8Vector;
2749
2750	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2751	if (rc == VINF_SUCCESS)
2752	{
2753	Log(("Pending hardware interrupt %d\n", u8Vector));
2754	}
2755	/*
2756	* Log important stuff before entering GC.
2757	*/
2758	if (pCtx->eflags.Bits.u1VM)
2759	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2760	else if ((pCtx->ss & X86_SEL_RPL) == 0)
2761	Log(("HWR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
2762	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2763	Log(("HWR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
2764	#endif
2765
2766
2767	/*
2768	* Execute the code.
2769	*/
2770	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2771	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2772	VMMR3Unlock(pVM);
2773	rc = VMMR3HwAccRunGC(pVM);
2774	VMMR3Lock(pVM);
2775	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2776
2777
2778	/*
2779	* Deal with high priority post execution FFs before doing anything else.
2780	*/
2781	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2782	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2783	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2784
2785	/*
2786	* Process the returned status code.
2787	*/
2788	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2789	break;
2790
2791	rc = emR3RawHandleRC(pVM, pCtx, rc);
2792	if (rc != VINF_SUCCESS)
2793	break;
2794
2795	/*
2796	* Check and execute forced actions.
2797	*/
2798	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2799	TMTimerPoll(pVM);
2800	#endif
2801	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2802	{
2803	rc = emR3ForcedActions(pVM, rc);
2804	if ( rc != VINF_SUCCESS
2805	&& rc != VINF_EM_RESCHEDULE_HWACC)
2806	{
2807	*pfFFDone = true;
2808	break;
2809	}
2810	}
2811	}
2812	/*
2813	* Return to outer loop.
2814	*/
2815	#if defined(LOG_ENABLED) && defined(DEBUG)
2816	RTLogFlush(NULL);
2817	#endif
2818	return rc;
2819	}
2820
2821
2822	/**
2823	* Decides whether to execute RAW, HWACC or REM.
2824	*
2825	* @returns new EM state
2826	* @param pVM The VM.
2827	* @param pCtx The CPU context.
2828	*/
2829	inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2830	{
2831	/*
2832	* When forcing raw-mode execution, things are simple.
2833	*/
2834	if (pVM->em.s.fForceRAW)
2835	return EMSTATE_RAW;
2836
2837	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2838	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2839	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2840
2841	X86EFLAGS EFlags = pCtx->eflags;
2842	if (HWACCMIsEnabled(pVM))
2843	{
2844	/* Hardware accelerated raw-mode:
2845	*
2846	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2847	*/
2848	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2849	return EMSTATE_HWACC;
2850
2851	/** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2852	return EMSTATE_REM;
2853	}
2854
2855	/* Standard raw-mode:
2856	*
2857	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2858	* or 32 bits protected mode ring 0 code
2859	*
2860	* The tests are ordered by the likelyhood of being true during normal execution.
2861	*/
2862	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2863	{
2864	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2865	return EMSTATE_REM;
2866	}
2867
2868	#ifndef VBOX_RAW_V86
2869	if (EFlags.u32 & X86_EFL_VM) {
2870	Log2(("raw mode refused: VM_MASK\n"));
2871	return EMSTATE_REM;
2872	}
2873	#endif
2874
2875	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2876	uint32_t u32CR0 = pCtx->cr0;
2877	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2878	{
2879	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2880	return EMSTATE_REM;
2881	}
2882
2883	if (pCtx->cr4 & X86_CR4_PAE)
2884	{
2885	//Log2(("raw mode refused: PAE\n"));
2886	return EMSTATE_REM;
2887	}
2888
2889	unsigned uSS = pCtx->ss;
2890	if ((uSS & X86_SEL_RPL) == 3)
2891	{
2892	if (!EMIsRawRing3Enabled(pVM))
2893	return EMSTATE_REM;
2894
2895	if (!(EFlags.u32 & X86_EFL_IF))
2896	{
2897	#ifdef VBOX_RAW_V86
2898	if(!(EFlags.u32 & X86_EFL_VM))
2899	return EMSTATE_REM;
2900	#else
2901	Log2(("raw mode refused: IF (RawR3)\n"));
2902	return EMSTATE_REM;
2903	#endif
2904	}
2905
2906	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2907	{
2908	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2909	return EMSTATE_REM;
2910	}
2911	}
2912	else
2913	{
2914	if (!EMIsRawRing0Enabled(pVM))
2915	return EMSTATE_REM;
2916
2917	/* Only ring 0 supervisor code. */
2918	if ((uSS & X86_SEL_RPL) != 0)
2919	{
2920	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2921	return EMSTATE_REM;
2922	}
2923
2924	// Let's start with pure 32 bits ring 0 code first
2925	/** @todo What's pure 32-bit mode? flat? */
2926	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2927	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
2928	{
2929	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2930	return EMSTATE_REM;
2931	}
2932
2933	/* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2934	if (!(u32CR0 & X86_CR0_WP))
2935	{
2936	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2937	return EMSTATE_REM;
2938	}
2939
2940	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2941	{
2942	Log2(("raw r0 mode forced: patch code\n"));
2943	return EMSTATE_RAW;
2944	}
2945
2946	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2947	if (!(EFlags.u32 & X86_EFL_IF))
2948	{
2949	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2950	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2951	return EMSTATE_REM;
2952	}
2953	#endif
2954
2955	/** @todo still necessary??? */
2956	if (EFlags.Bits.u2IOPL != 0)
2957	{
2958	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2959	return EMSTATE_REM;
2960	}
2961	}
2962
2963	Assert(PGMPhysIsA20Enabled(pVM));
2964	return EMSTATE_RAW;
2965	}
2966
2967
2968	/**
2969	* Executes all high priority post execution force actions.
2970	*
2971	* @returns rc or a fatal status code.
2972	*
2973	* @param pVM VM handle.
2974	* @param rc The current rc.
2975	*/
2976	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2977	{
2978	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2979	PDMR3CritSectFF(pVM);
2980
2981	if (VM_FF_ISSET(pVM, VM_FF_CSAM_FLUSH_DIRTY_PAGE))
2982	CSAMR3FlushDirtyPages(pVM);
2983
2984	return rc;
2985	}
2986
2987
2988	/**
2989	* Executes all pending forced actions.
2990	*
2991	* Forced actions can cause execution delays and execution
2992	* rescheduling. The first we deal with using action priority, so
2993	* that for instance pending timers aren't scheduled and ran until
2994	* right before execution. The rescheduling we deal with using
2995	* return codes. The same goes for VM termination, only in that case
2996	* we exit everything.
2997	*
2998	* @returns VBox status code of equal or greater importance/severity than rc.
2999	* The most important ones are: VINF_EM_RESCHEDULE,
3000	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3001	*
3002	* @param pVM VM handle.
3003	* @param rc The current rc.
3004	*
3005	*/
3006	static int emR3ForcedActions(PVM pVM, int rc)
3007	{
3008	#ifdef VBOX_STRICT
3009	int rcIrq = VINF_SUCCESS;
3010	#endif
3011	STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
3012
3013	#define UPDATE_RC() \
3014	do { \
3015	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
3016	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
3017	break; \
3018	if (!rc \|\| rc2 < rc) \
3019	rc = rc2; \
3020	} while (0)
3021
3022	int rc2;
3023
3024	/*
3025	* Post execution chunk first.
3026	*/
3027	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
3028	{
3029	/*
3030	* Termination request.
3031	*/
3032	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3033	{
3034	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3035	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3036	return VINF_EM_TERMINATE;
3037	}
3038
3039	/*
3040	* Debugger Facility polling.
3041	*/
3042	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3043	{
3044	rc2 = DBGFR3VMMForcedAction(pVM);
3045	UPDATE_RC();
3046	}
3047
3048	/*
3049	* Postponed reset request.
3050	*/
3051	if (VM_FF_ISSET(pVM, VM_FF_RESET))
3052	{
3053	rc2 = VMR3Reset(pVM);
3054	UPDATE_RC();
3055	VM_FF_CLEAR(pVM, VM_FF_RESET);
3056	}
3057
3058	/*
3059	* CSAM page scanning.
3060	*/
3061	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
3062	{
3063	PCPUMCTX pCtx = pVM->em.s.pCtx;
3064
3065	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3066	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3067
3068	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
3069	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3070	}
3071
3072	/* check that we got them all */
3073	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
3074	}
3075
3076	/*
3077	* Normal priority then.
3078	* (Executed in no particular order.)
3079	*/
3080	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3081	{
3082	/*
3083	* PDM Queues are pending.
3084	*/
3085	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3086	PDMR3QueueFlushAll(pVM);
3087
3088	/*
3089	* PDM DMA transfers are pending.
3090	*/
3091	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3092	PDMR3DmaRun(pVM);
3093
3094	/*
3095	* Requests from other threads.
3096	*/
3097	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3098	{
3099	rc2 = VMR3ReqProcess(pVM);
3100	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3101	{
3102	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3103	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3104	return rc2;
3105	}
3106	UPDATE_RC();
3107	}
3108
3109	/* check that we got them all */
3110	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA)));
3111	}
3112
3113	/*
3114	* Execute polling function ever so often.
3115	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING SOON!
3116	*/
3117	static unsigned cLast = 0;
3118	if (!((++cLast) % 4))
3119	PDMR3Poll(pVM);
3120
3121	/*
3122	* High priority pre execution chunk last.
3123	* (Executed in ascending priority order.)
3124	*/
3125	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3126	{
3127	/*
3128	* Timers before interrupts.
3129	*/
3130	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3131	TMR3TimerQueuesDo(pVM);
3132
3133	/*
3134	* The instruction following an emulated STI should always be executed!
3135	*/
3136	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3137	{
3138	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3139	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3140	{
3141	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3142	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3143	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3144	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3145	*/
3146	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3147	}
3148	if (HWACCMR3IsActive(pVM))
3149	rc2 = VINF_EM_RESCHEDULE_HWACC;
3150	else
3151	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3152
3153	UPDATE_RC();
3154	}
3155
3156	/*
3157	* Interrupts.
3158	*/
3159	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3160	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3161	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3162	&& PATMAreInterruptsEnabled(pVM)
3163	&& !HWACCMR3IsEventPending(pVM))
3164	{
3165	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3166	{
3167	/** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3168	/** @todo this really isn't nice, should properly handle this */
3169	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3170	#ifdef VBOX_STRICT
3171	rcIrq = rc2;
3172	#endif
3173	UPDATE_RC();
3174	}
3175	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3176	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3177	{
3178	rc2 = VINF_EM_RESCHEDULE_REM;
3179	UPDATE_RC();
3180	}
3181	}
3182
3183	/*
3184	* Debugger Facility request.
3185	*/
3186	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3187	{
3188	rc2 = DBGFR3VMMForcedAction(pVM);
3189	UPDATE_RC();
3190	}
3191
3192	/*
3193	* Termination request.
3194	*/
3195	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3196	{
3197	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3198	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3199	return VINF_EM_TERMINATE;
3200	}
3201
3202	#ifdef DEBUG
3203	/*
3204	* Debug, pause the VM.
3205	*/
3206	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3207	{
3208	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3209	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3210	return VINF_EM_SUSPEND;
3211	}
3212
3213	#endif
3214	/* check that we got them all */
3215	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS)));
3216	}
3217
3218	#undef UPDATE_RC
3219	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3220	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3221	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3222	return rc;
3223	}
3224
3225
3226	/**
3227	* Execute VM.
3228	*
3229	* This function is the main loop of the VM. The emulation thread
3230	* calls this function when the VM has been successfully constructed
3231	* and we're ready for executing the VM.
3232	*
3233	* Returning from this function means that the VM is turned off or
3234	* suspended (state already saved) and deconstruction in next in line.
3235	*
3236	* All interaction from other thread are done using forced actions
3237	* and signaling of the wait object.
3238	*
3239	* @returns VBox status code.
3240	* @param pVM The VM to operate on.
3241	*/
3242	EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3243	{
3244	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3245	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3246	VM_ASSERT_EMT(pVM);
3247	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3248
3249	VMMR3Lock(pVM);
3250
3251	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3252	if (rc == 0)
3253	{
3254	/*
3255	* Start the virtual time.
3256	*/
3257	rc = TMVirtualResume(pVM);
3258	Assert(rc == VINF_SUCCESS);
3259	rc = TMCpuTickResume(pVM);
3260	Assert(rc == VINF_SUCCESS);
3261
3262	/*
3263	* The Outer Main Loop.
3264	*/
3265	bool fFFDone = false;
3266	rc = VINF_EM_RESCHEDULE;
3267	pVM->em.s.enmState = EMSTATE_REM;
3268	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3269	for (;;)
3270	{
3271	/*
3272	* Before we can schedule anything (we're here because
3273	* scheduling is required) we must service any pending
3274	* forced actions to avoid any pending action causing
3275	* immidate rescheduling upon entering an inner loop
3276	*
3277	* Do forced actions.
3278	*/
3279	if ( !fFFDone
3280	&& rc != VINF_EM_TERMINATE
3281	&& rc != VINF_EM_OFF
3282	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3283	{
3284	rc = emR3ForcedActions(pVM, rc);
3285	if ( ( rc == VINF_EM_RESCHEDULE_REM
3286	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3287	&& pVM->em.s.fForceRAW)
3288	rc = VINF_EM_RESCHEDULE_RAW;
3289	}
3290	else if (fFFDone)
3291	fFFDone = false;
3292
3293	/*
3294	* Now what to do?
3295	*/
3296	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3297	switch (rc)
3298	{
3299	/*
3300	* Keep doing what we're currently doing.
3301	*/
3302	case VINF_SUCCESS:
3303	break;
3304
3305	/*
3306	* Reschedule - to raw-mode execution.
3307	*/
3308	case VINF_EM_RESCHEDULE_RAW:
3309	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3310	pVM->em.s.enmState = EMSTATE_RAW;
3311	break;
3312
3313	/*
3314	* Reschedule - to hardware accelerated raw-mode execution.
3315	*/
3316	case VINF_EM_RESCHEDULE_HWACC:
3317	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3318	Assert(!pVM->em.s.fForceRAW);
3319	pVM->em.s.enmState = EMSTATE_HWACC;
3320	break;
3321
3322	/*
3323	* Reschedule - to recompiled execution.
3324	*/
3325	case VINF_EM_RESCHEDULE_REM:
3326	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3327	pVM->em.s.enmState = EMSTATE_REM;
3328	break;
3329
3330	/*
3331	* Resume.
3332	*/
3333	case VINF_EM_RESUME:
3334	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3335	/* fall through and get scheduled. */
3336
3337	/*
3338	* Reschedule.
3339	*/
3340	case VINF_EM_RESCHEDULE:
3341	{
3342	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3343	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3344	pVM->em.s.enmState = enmState;
3345	break;
3346	}
3347
3348	/*
3349	* Halted.
3350	*/
3351	case VINF_EM_HALT:
3352	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3353	pVM->em.s.enmState = EMSTATE_HALTED;
3354	break;
3355
3356	/*
3357	* Suspend.
3358	*/
3359	case VINF_EM_SUSPEND:
3360	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3361	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3362	break;
3363
3364	/*
3365	* Reset.
3366	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3367	*/
3368	case VINF_EM_RESET:
3369	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3370	pVM->em.s.enmState = EMSTATE_REM;
3371	break;
3372
3373	/*
3374	* Power Off.
3375	*/
3376	case VINF_EM_OFF:
3377	pVM->em.s.enmState = EMSTATE_TERMINATING;
3378	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3379	TMVirtualPause(pVM);
3380	TMCpuTickPause(pVM);
3381	VMMR3Unlock(pVM);
3382	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3383	return rc;
3384
3385	/*
3386	* Terminate the VM.
3387	*/
3388	case VINF_EM_TERMINATE:
3389	pVM->em.s.enmState = EMSTATE_TERMINATING;
3390	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3391	TMVirtualPause(pVM);
3392	TMCpuTickPause(pVM);
3393	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3394	return rc;
3395
3396	/*
3397	* Guest debug events.
3398	*/
3399	case VINF_EM_DBG_STEPPED:
3400	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3401	case VINF_EM_DBG_STOP:
3402	case VINF_EM_DBG_BREAKPOINT:
3403	case VINF_EM_DBG_STEP:
3404	if (pVM->em.s.enmState == EMSTATE_RAW)
3405	{
3406	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3407	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3408	}
3409	else
3410	{
3411	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3412	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3413	}
3414	break;
3415
3416	/*
3417	* Hypervisor debug events.
3418	*/
3419	case VINF_EM_DBG_HYPER_STEPPED:
3420	case VINF_EM_DBG_HYPER_BREAKPOINT:
3421	case VINF_EM_DBG_HYPER_ASSERTION:
3422	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3423	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3424	break;
3425
3426	/*
3427	* Any error code showing up here other than the ones we
3428	* know and process above are considered to be FATAL.
3429	*
3430	* Unknown warnings and informational status codes are also
3431	* included in this.
3432	*/
3433	default:
3434	if (VBOX_SUCCESS(rc))
3435	{
3436	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3437	rc = VERR_EM_INTERNAL_ERROR;
3438	}
3439	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3440	Log(("EMR3ExecuteVM returns %d\n", rc));
3441	break;
3442	}
3443
3444
3445	/*
3446	* Any waiters can now be woken up
3447	*/
3448	VMMR3Unlock(pVM);
3449	VMMR3Lock(pVM);
3450
3451	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3452	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3453
3454	/*
3455	* Act on the state.
3456	*/
3457	switch (pVM->em.s.enmState)
3458	{
3459	/*
3460	* Execute raw.
3461	*/
3462	case EMSTATE_RAW:
3463	rc = emR3RawExecute(pVM, &fFFDone);
3464	break;
3465
3466	/*
3467	* Execute hardware accelerated raw.
3468	*/
3469	case EMSTATE_HWACC:
3470	rc = emR3HwAccExecute(pVM, &fFFDone);
3471	break;
3472
3473	/*
3474	* Execute recompiled.
3475	*/
3476	case EMSTATE_REM:
3477	#if 0
3478	/* simulate a runtime error */
3479	VMSetRuntimeError (pVM, true, "simulatedError", "pVM=%p", pVM);
3480	#endif
3481	rc = emR3RemExecute(pVM, &fFFDone);
3482	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3483	break;
3484
3485	/*
3486	* hlt - execution halted until interrupt.
3487	*/
3488	case EMSTATE_HALTED:
3489	{
3490	STAM_PROFILE_START(&pVM->em.s.StatHalted, y);
3491	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3492	STAM_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3493	break;
3494	}
3495
3496	/*
3497	* Suspended - return to VM.cpp.
3498	*/
3499	case EMSTATE_SUSPENDED:
3500	TMVirtualPause(pVM);
3501	TMCpuTickPause(pVM);
3502	VMMR3Unlock(pVM);
3503	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3504	return VINF_EM_SUSPEND;
3505
3506	/*
3507	* Debugging in the guest.
3508	*/
3509	case EMSTATE_DEBUG_GUEST_REM:
3510	case EMSTATE_DEBUG_GUEST_RAW:
3511	TMVirtualPause(pVM);
3512	TMCpuTickPause(pVM);
3513	rc = emR3Debug(pVM, rc);
3514	TMVirtualResume(pVM);
3515	TMCpuTickResume(pVM);
3516	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3517	break;
3518
3519	/*
3520	* Debugging in the hypervisor.
3521	*/
3522	case EMSTATE_DEBUG_HYPER:
3523	{
3524	TMVirtualPause(pVM);
3525	TMCpuTickPause(pVM);
3526	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3527
3528	rc = emR3Debug(pVM, rc);
3529	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3530	if (rc != VINF_SUCCESS)
3531	{
3532	/* switch to guru meditation mode */
3533	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3534	VMMR3FatalDump(pVM, rc);
3535	return rc;
3536	}
3537
3538	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3539	TMVirtualResume(pVM);
3540	TMCpuTickResume(pVM);
3541	break;
3542	}
3543
3544	/*
3545	* Guru meditation takes place in the debugger.
3546	*/
3547	case EMSTATE_GURU_MEDITATION:
3548	{
3549	/** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3550	TMVirtualPause(pVM);
3551	TMCpuTickPause(pVM);
3552	VMMR3FatalDump(pVM, rc);
3553	int rc2 = emR3Debug(pVM, rc);
3554	if (rc2 == VERR_DBGF_NOT_ATTACHED)
3555	{
3556	VMMR3Unlock(pVM);
3557	/** @todo change the VM state! */
3558	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3559	return rc;
3560	}
3561	TMVirtualResume(pVM);
3562	TMCpuTickResume(pVM);
3563	rc = rc2;
3564	/** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3565	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3566	break;
3567	}
3568
3569	/*
3570	* The states we don't expect here.
3571	*/
3572	case EMSTATE_NONE:
3573	case EMSTATE_TERMINATING:
3574	default:
3575	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3576	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3577	TMVirtualPause(pVM);
3578	TMCpuTickPause(pVM);
3579	VMMR3Unlock(pVM);
3580	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3581	return VERR_EM_INTERNAL_ERROR;
3582	}
3583	} /* The Outer Main Loop */
3584	}
3585	else
3586	{
3587	/*
3588	* Fatal error.
3589	*/
3590	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3591	TMVirtualPause(pVM);
3592	TMCpuTickPause(pVM);
3593	VMMR3FatalDump(pVM, rc);
3594	emR3Debug(pVM, rc);
3595	VMMR3Unlock(pVM);
3596	/** @todo change the VM state! */
3597	return rc;
3598	}
3599
3600	/* (won't ever get here). */
3601	AssertFailed();
3602	}
3603

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 1151

Download in other formats: