VirtualBox

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 11964

Last change on this file since 11964 was 11792, checked in by vboxsync, 16 years ago

Assert when the SSM version doesn't match.

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1/* $Id: EM.cpp 11792 2008-08-29 08:51:20Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor/Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/** @page pg_em EM - The Execution Monitor/Manager
24 *
25 * The Execution Monitor/Manager is responsible for running the VM, scheduling
26 * the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27 * the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28 * the VM.
29 *
30 */
31
32/*******************************************************************************
33* Header Files *
34*******************************************************************************/
35#define LOG_GROUP LOG_GROUP_EM
36#include <VBox/em.h>
37#include <VBox/vmm.h>
38#include <VBox/patm.h>
39#include <VBox/csam.h>
40#include <VBox/selm.h>
41#include <VBox/trpm.h>
42#include <VBox/iom.h>
43#include <VBox/dbgf.h>
44#include <VBox/pgm.h>
45#include <VBox/rem.h>
46#include <VBox/tm.h>
47#include <VBox/mm.h>
48#include <VBox/ssm.h>
49#include <VBox/pdmapi.h>
50#include <VBox/pdmcritsect.h>
51#include <VBox/pdmqueue.h>
52#include <VBox/hwaccm.h>
53#include <VBox/patm.h>
54#include "EMInternal.h"
55#include <VBox/vm.h>
56#include <VBox/cpumdis.h>
57#include <VBox/dis.h>
58#include <VBox/disopcode.h>
59#include <VBox/dbgf.h>
60
61#include <VBox/log.h>
62#include <iprt/thread.h>
63#include <iprt/assert.h>
64#include <iprt/asm.h>
65#include <iprt/semaphore.h>
66#include <iprt/string.h>
67#include <iprt/avl.h>
68#include <iprt/stream.h>
69#include <VBox/param.h>
70#include <VBox/err.h>
71
72
73/*******************************************************************************
74* Internal Functions *
75*******************************************************************************/
76static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
77static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
78static int emR3Debug(PVM pVM, int rc);
79static int emR3RemStep(PVM pVM);
80static int emR3RemExecute(PVM pVM, bool *pfFFDone);
81static int emR3RawResumeHyper(PVM pVM);
82static int emR3RawStep(PVM pVM);
83DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
84DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
85static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
86static int emR3RawExecute(PVM pVM, bool *pfFFDone);
87DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
88static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
89static int emR3ForcedActions(PVM pVM, int rc);
90static int emR3RawGuestTrap(PVM pVM);
91
92
93/**
94 * Initializes the EM.
95 *
96 * @returns VBox status code.
97 * @param pVM The VM to operate on.
98 */
99EMR3DECL(int) EMR3Init(PVM pVM)
100{
101 LogFlow(("EMR3Init\n"));
102 /*
103 * Assert alignment and sizes.
104 */
105 AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
106 AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
107 AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
108 ("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
109
110 /*
111 * Init the structure.
112 */
113 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
114 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
115 if (VBOX_FAILURE(rc))
116 pVM->fRawR3Enabled = true;
117 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
118 if (VBOX_FAILURE(rc))
119 pVM->fRawR0Enabled = true;
120 Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
121 pVM->em.s.enmState = EMSTATE_NONE;
122 pVM->em.s.fForceRAW = false;
123
124 rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
125 AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
126 pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
127 AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
128
129 /*
130 * Saved state.
131 */
132 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
133 NULL, emR3Save, NULL,
134 NULL, emR3Load, NULL);
135 if (VBOX_FAILURE(rc))
136 return rc;
137
138 /*
139 * Statistics.
140 */
141#ifdef VBOX_WITH_STATISTICS
142 PEMSTATS pStats;
143 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
144 if (VBOX_FAILURE(rc))
145 return rc;
146 pVM->em.s.pStatsHC = pStats;
147 pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
148
149 STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
150 STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
151
152 STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
153 STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
154
155 STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
156 STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
157 STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
158 STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
159 STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
160 STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
161 STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
162 STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
163 STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
164 STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
165 STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
166 STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
167 STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
168 STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
169 STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
170 STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
171 STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
172 STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
173 STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
174 STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
175 STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
176 STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
177 STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
178 STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
179 STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
180 STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
181 STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
182 STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
183 STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
184 STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
185 STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
186 STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
187 STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
188 STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
189 STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
190 STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
191 STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
192 STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
193 STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
194 STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
195 STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
196 STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
197 STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
198 STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
199 STAM_REG_USED(pVM, &pStats->StatGCBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
200 STAM_REG_USED(pVM, &pStats->StatHCBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
201 STAM_REG_USED(pVM, &pStats->StatGCBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
202 STAM_REG_USED(pVM, &pStats->StatHCBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
203 STAM_REG_USED(pVM, &pStats->StatGCBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
204 STAM_REG_USED(pVM, &pStats->StatHCBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
205 STAM_REG_USED(pVM, &pStats->StatGCCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
206 STAM_REG_USED(pVM, &pStats->StatHCCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
207 STAM_REG_USED(pVM, &pStats->StatGCCmpXchg8b, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
208 STAM_REG_USED(pVM, &pStats->StatHCCmpXchg8b, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
209 STAM_REG_USED(pVM, &pStats->StatGCXAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
210 STAM_REG_USED(pVM, &pStats->StatHCXAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
211 STAM_REG_USED(pVM, &pStats->StatHCRdmsr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
212 STAM_REG_USED(pVM, &pStats->StatGCRdmsr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
213 STAM_REG_USED(pVM, &pStats->StatHCWrmsr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
214 STAM_REG_USED(pVM, &pStats->StatGCWrmsr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
215 STAM_REG_USED(pVM, &pStats->StatHCStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
216 STAM_REG_USED(pVM, &pStats->StatGCStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
217
218 STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
219 STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
220
221 STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
222 STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
223 STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
224 STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
225 STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
226 STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
227 STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
228 STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
229 STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
230 STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
231 STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
232 STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
233 STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
234 STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
235 STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
236 STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
237 STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
238 STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
239 STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
240 STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
241 STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
242 STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
243 STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
244 STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
245 STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
246 STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
247 STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
248 STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
249 STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
250 STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
251 STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
252 STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
253 STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
254 STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
255 STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
256 STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
257 STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
258 STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
259 STAM_REG_USED(pVM, &pStats->StatGCFailedRdmsr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
260 STAM_REG_USED(pVM, &pStats->StatHCFailedRdmsr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
261 STAM_REG_USED(pVM, &pStats->StatGCFailedWrmsr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
262 STAM_REG_USED(pVM, &pStats->StatHCFailedWrmsr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
263
264 STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
265 STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
266 STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
267 STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
268 STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
269 STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
270 STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
271 STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
272 STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
273 STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
274 STAM_REG_USED(pVM, &pStats->StatGCFailedBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
275 STAM_REG_USED(pVM, &pStats->StatHCFailedBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
276 STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
277 STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
278 STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
279 STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
280 STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
281 STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
282 STAM_REG_USED(pVM, &pStats->StatGCFailedXAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
283 STAM_REG_USED(pVM, &pStats->StatHCFailedXAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
284 STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
285 STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
286 STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
287 STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
288 STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
289 STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
290 STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
291 STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
292
293 STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
294 STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
295 STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
296 STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
297
298 STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
299 STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
300 STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
301 STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
302 STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
303 STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
304 STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
305 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
306 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
307 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
308 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
309 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
310 STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
311 STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
312 STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
313 STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
314 STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
315 STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
316 STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
317 STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
318 STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
319 STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
320 STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
321 STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
322 STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
323 STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
324
325 STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
326 pVM->em.s.pCliStatTree = 0;
327#endif /* VBOX_WITH_STATISTICS */
328
329/* these should be considered for release statistics. */
330 STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
331 STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
332 STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
333 STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
334 STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
335 STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
336 STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
337 STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
338 STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
339 STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
340 STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
341 STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
342 STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
343 STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
344 STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
345 STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
346
347
348 return VINF_SUCCESS;
349}
350
351
352
353/**
354 * Applies relocations to data and code managed by this
355 * component. This function will be called at init and
356 * whenever the VMM need to relocate it self inside the GC.
357 *
358 * @param pVM The VM.
359 */
360EMR3DECL(void) EMR3Relocate(PVM pVM)
361{
362 LogFlow(("EMR3Relocate\n"));
363 if (pVM->em.s.pStatsHC)
364 pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
365}
366
367
368/**
369 * Reset notification.
370 *
371 * @param pVM
372 */
373EMR3DECL(void) EMR3Reset(PVM pVM)
374{
375 LogFlow(("EMR3Reset: \n"));
376 pVM->em.s.fForceRAW = false;
377}
378
379
380/**
381 * Terminates the EM.
382 *
383 * Termination means cleaning up and freeing all resources,
384 * the VM it self is at this point powered off or suspended.
385 *
386 * @returns VBox status code.
387 * @param pVM The VM to operate on.
388 */
389EMR3DECL(int) EMR3Term(PVM pVM)
390{
391 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
392
393 return VINF_SUCCESS;
394}
395
396
397/**
398 * Execute state save operation.
399 *
400 * @returns VBox status code.
401 * @param pVM VM Handle.
402 * @param pSSM SSM operation handle.
403 */
404static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
405{
406 return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
407}
408
409
410/**
411 * Execute state load operation.
412 *
413 * @returns VBox status code.
414 * @param pVM VM Handle.
415 * @param pSSM SSM operation handle.
416 * @param u32Version Data layout version.
417 */
418static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
419{
420 /*
421 * Validate version.
422 */
423 if (u32Version != EM_SAVED_STATE_VERSION)
424 {
425 AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
426 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
427 }
428
429 /*
430 * Load the saved state.
431 */
432 int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
433 if (VBOX_FAILURE(rc))
434 pVM->em.s.fForceRAW = false;
435
436 Assert(pVM->em.s.pCliStatTree == 0);
437 return rc;
438}
439
440
441/**
442 * Enables or disables a set of raw-mode execution modes.
443 *
444 * @returns VINF_SUCCESS on success.
445 * @returns VINF_RESCHEDULE if a rescheduling might be required.
446 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
447 *
448 * @param pVM The VM to operate on.
449 * @param enmMode The execution mode change.
450 * @thread The emulation thread.
451 */
452EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
453{
454 switch (enmMode)
455 {
456 case EMRAW_NONE:
457 pVM->fRawR3Enabled = false;
458 pVM->fRawR0Enabled = false;
459 break;
460 case EMRAW_RING3_ENABLE:
461 pVM->fRawR3Enabled = true;
462 break;
463 case EMRAW_RING3_DISABLE:
464 pVM->fRawR3Enabled = false;
465 break;
466 case EMRAW_RING0_ENABLE:
467 pVM->fRawR0Enabled = true;
468 break;
469 case EMRAW_RING0_DISABLE:
470 pVM->fRawR0Enabled = false;
471 break;
472 default:
473 AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
474 return VERR_INVALID_PARAMETER;
475 }
476 Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
477 pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
478 return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
479}
480
481
482/**
483 * Raise a fatal error.
484 *
485 * Safely terminate the VM with full state report and stuff. This function
486 * will naturally never return.
487 *
488 * @param pVM VM handle.
489 * @param rc VBox status code.
490 */
491EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
492{
493 longjmp(pVM->em.s.u.FatalLongJump, rc);
494 AssertReleaseMsgFailed(("longjmp returned!\n"));
495}
496
497
498/**
499 * Gets the EM state name.
500 *
501 * @returns pointer to read only state name,
502 * @param enmState The state.
503 */
504EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
505{
506 switch (enmState)
507 {
508 case EMSTATE_NONE: return "EMSTATE_NONE";
509 case EMSTATE_RAW: return "EMSTATE_RAW";
510 case EMSTATE_HWACC: return "EMSTATE_HWACC";
511 case EMSTATE_REM: return "EMSTATE_REM";
512 case EMSTATE_HALTED: return "EMSTATE_HALTED";
513 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
514 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
515 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
516 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
517 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
518 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
519 default: return "Unknown!";
520 }
521}
522
523
524#ifdef VBOX_WITH_STATISTICS
525/**
526 * Just a braindead function to keep track of cli addresses.
527 * @param pVM VM handle.
528 * @param pInstrGC The EIP of the cli instruction.
529 */
530static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
531{
532 PCLISTAT pRec;
533
534 pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
535 if (!pRec)
536 {
537 /* New cli instruction; insert into the tree. */
538 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
539 Assert(pRec);
540 if (!pRec)
541 return;
542 pRec->Core.Key = (AVLPVKEY)pInstrGC;
543
544 char szCliStatName[32];
545 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
546 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
547
548 bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
549 Assert(fRc); NOREF(fRc);
550 }
551 STAM_COUNTER_INC(&pRec->Counter);
552 STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
553}
554#endif /* VBOX_WITH_STATISTICS */
555
556
557/**
558 * Debug loop.
559 *
560 * @returns VBox status code for EM.
561 * @param pVM VM handle.
562 * @param rc Current EM VBox status code..
563 */
564static int emR3Debug(PVM pVM, int rc)
565{
566 for (;;)
567 {
568 Log(("emR3Debug: rc=%Vrc\n", rc));
569 const int rcLast = rc;
570
571 /*
572 * Debug related RC.
573 */
574 switch (rc)
575 {
576 /*
577 * Single step an instruction.
578 */
579 case VINF_EM_DBG_STEP:
580 if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
581 || pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
582 || pVM->em.s.fForceRAW /* paranoia */)
583 rc = emR3RawStep(pVM);
584 else
585 {
586 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
587 rc = emR3RemStep(pVM);
588 }
589 break;
590
591 /*
592 * Simple events: stepped, breakpoint, stop/assertion.
593 */
594 case VINF_EM_DBG_STEPPED:
595 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
596 break;
597
598 case VINF_EM_DBG_BREAKPOINT:
599 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
600 break;
601
602 case VINF_EM_DBG_STOP:
603 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
604 break;
605
606 case VINF_EM_DBG_HYPER_STEPPED:
607 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
608 break;
609
610 case VINF_EM_DBG_HYPER_BREAKPOINT:
611 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
612 break;
613
614 case VINF_EM_DBG_HYPER_ASSERTION:
615 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
616 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
617 break;
618
619 /*
620 * Guru meditation.
621 */
622 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
623 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
624 break;
625
626 default: /** @todo don't use default for guru, but make special errors code! */
627 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
628 break;
629 }
630
631 /*
632 * Process the result.
633 */
634 do
635 {
636 switch (rc)
637 {
638 /*
639 * Continue the debugging loop.
640 */
641 case VINF_EM_DBG_STEP:
642 case VINF_EM_DBG_STOP:
643 case VINF_EM_DBG_STEPPED:
644 case VINF_EM_DBG_BREAKPOINT:
645 case VINF_EM_DBG_HYPER_STEPPED:
646 case VINF_EM_DBG_HYPER_BREAKPOINT:
647 case VINF_EM_DBG_HYPER_ASSERTION:
648 break;
649
650 /*
651 * Resuming execution (in some form) has to be done here if we got
652 * a hypervisor debug event.
653 */
654 case VINF_SUCCESS:
655 case VINF_EM_RESUME:
656 case VINF_EM_SUSPEND:
657 case VINF_EM_RESCHEDULE:
658 case VINF_EM_RESCHEDULE_RAW:
659 case VINF_EM_RESCHEDULE_REM:
660 case VINF_EM_HALT:
661 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
662 {
663 rc = emR3RawResumeHyper(pVM);
664 if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
665 continue;
666 }
667 if (rc == VINF_SUCCESS)
668 rc = VINF_EM_RESCHEDULE;
669 return rc;
670
671 /*
672 * The debugger isn't attached.
673 * We'll simply turn the thing off since that's the easiest thing to do.
674 */
675 case VERR_DBGF_NOT_ATTACHED:
676 switch (rcLast)
677 {
678 case VINF_EM_DBG_HYPER_ASSERTION:
679 case VINF_EM_DBG_HYPER_STEPPED:
680 case VINF_EM_DBG_HYPER_BREAKPOINT:
681 return rcLast;
682 }
683 return VINF_EM_OFF;
684
685 /*
686 * Status codes terminating the VM in one or another sense.
687 */
688 case VINF_EM_TERMINATE:
689 case VINF_EM_OFF:
690 case VINF_EM_RESET:
691 case VINF_EM_RAW_STALE_SELECTOR:
692 case VINF_EM_RAW_IRET_TRAP:
693 case VERR_TRPM_PANIC:
694 case VERR_TRPM_DONT_PANIC:
695 case VERR_INTERNAL_ERROR:
696 return rc;
697
698 /*
699 * The rest is unexpected, and will keep us here.
700 */
701 default:
702 AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
703 break;
704 }
705 } while (false);
706 } /* debug for ever */
707}
708
709
710/**
711 * Steps recompiled code.
712 *
713 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
714 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
715 *
716 * @param pVM VM handle.
717 */
718static int emR3RemStep(PVM pVM)
719{
720 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
721
722 /*
723 * Switch to REM, step instruction, switch back.
724 */
725 int rc = REMR3State(pVM);
726 if (VBOX_SUCCESS(rc))
727 {
728 rc = REMR3Step(pVM);
729 REMR3StateBack(pVM);
730 }
731 LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
732 return rc;
733}
734
735/**
736 * Executes recompiled code.
737 *
738 * This function contains the recompiler version of the inner
739 * execution loop (the outer loop being in EMR3ExecuteVM()).
740 *
741 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
742 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
743 *
744 * @param pVM VM handle.
745 * @param pfFFDone Where to store an indicator telling wheter or not
746 * FFs were done before returning.
747 *
748 */
749static int emR3RemExecute(PVM pVM, bool *pfFFDone)
750{
751#ifdef LOG_ENABLED
752 PCPUMCTX pCtx = pVM->em.s.pCtx;
753 uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
754
755 if (pCtx->eflags.Bits.u1VM)
756 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
757 else
758 Log(("EMR%d: %08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
759#endif
760 STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
761
762#if defined(VBOX_STRICT) && defined(DEBUG_bird)
763 AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
764 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
765 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
766#endif
767
768 /*
769 * Spin till we get a forced action which returns anything but VINF_SUCCESS
770 * or the REM suggests raw-mode execution.
771 */
772 *pfFFDone = false;
773 bool fInREMState = false;
774 int rc = VINF_SUCCESS;
775 for (;;)
776 {
777 /*
778 * Update REM state if not already in sync.
779 */
780 if (!fInREMState)
781 {
782 STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
783 rc = REMR3State(pVM);
784 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
785 if (VBOX_FAILURE(rc))
786 break;
787 fInREMState = true;
788
789 /*
790 * We might have missed the raising of VMREQ, TIMER and some other
791 * imporant FFs while we were busy switching the state. So, check again.
792 */
793 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_TIMER | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_RESET))
794 {
795 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
796 goto l_REMDoForcedActions;
797 }
798 }
799
800
801 /*
802 * Execute REM.
803 */
804 STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
805 rc = REMR3Run(pVM);
806 STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
807
808
809 /*
810 * Deal with high priority post execution FFs before doing anything else.
811 */
812 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
813 rc = emR3HighPriorityPostForcedActions(pVM, rc);
814
815 /*
816 * Process the returned status code.
817 * (Try keep this short! Call functions!)
818 */
819 if (rc != VINF_SUCCESS)
820 {
821 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
822 break;
823 if (rc != VINF_REM_INTERRUPED_FF)
824 {
825 /*
826 * Anything which is not known to us means an internal error
827 * and the termination of the VM!
828 */
829 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Vra\n", rc));
830 break;
831 }
832 }
833
834
835 /*
836 * Check and execute forced actions.
837 * Sync back the VM state before calling any of these.
838 */
839#ifdef VBOX_HIGH_RES_TIMERS_HACK
840 TMTimerPoll(pVM);
841#endif
842 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION | VM_FF_CSAM_SCAN_PAGE)))
843 {
844l_REMDoForcedActions:
845 if (fInREMState)
846 {
847 STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
848 REMR3StateBack(pVM);
849 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
850 fInREMState = false;
851 }
852 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
853 rc = emR3ForcedActions(pVM, rc);
854 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
855 if ( rc != VINF_SUCCESS
856 && rc != VINF_EM_RESCHEDULE_REM)
857 {
858 *pfFFDone = true;
859 break;
860 }
861 }
862
863 } /* The Inner Loop, recompiled execution mode version. */
864
865
866 /*
867 * Returning. Sync back the VM state if required.
868 */
869 if (fInREMState)
870 {
871 STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
872 REMR3StateBack(pVM);
873 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
874 }
875
876 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
877 return rc;
878}
879
880
881/**
882 * Resumes executing hypervisor after a debug event.
883 *
884 * This is kind of special since our current guest state is
885 * potentially out of sync.
886 *
887 * @returns VBox status code.
888 * @param pVM The VM handle.
889 */
890static int emR3RawResumeHyper(PVM pVM)
891{
892 int rc;
893 PCPUMCTX pCtx = pVM->em.s.pCtx;
894 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
895 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
896
897 /*
898 * Resume execution.
899 */
900 CPUMRawEnter(pVM, NULL);
901 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_RF);
902 rc = VMMR3ResumeHyper(pVM);
903 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
904 rc = CPUMRawLeave(pVM, NULL, rc);
905 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
906
907 /*
908 * Deal with the return code.
909 */
910 rc = emR3HighPriorityPostForcedActions(pVM, rc);
911 rc = emR3RawHandleRC(pVM, pCtx, rc);
912 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
913 return rc;
914}
915
916
917/**
918 * Steps rawmode.
919 *
920 * @returns VBox status code.
921 * @param pVM The VM handle.
922 */
923static int emR3RawStep(PVM pVM)
924{
925 Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
926 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
927 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
928 int rc;
929 PCPUMCTX pCtx = pVM->em.s.pCtx;
930 bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
931#ifndef DEBUG_sandervl
932 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
933 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
934#endif
935 if (fGuest)
936 {
937 /*
938 * Check vital forced actions, but ignore pending interrupts and timers.
939 */
940 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
941 {
942 rc = emR3RawForcedActions(pVM, pCtx);
943 if (VBOX_FAILURE(rc))
944 return rc;
945 }
946
947 /*
948 * Set flags for single stepping.
949 */
950 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
951 }
952 else
953 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
954
955 /*
956 * Single step.
957 * We do not start time or anything, if anything we should just do a few nanoseconds.
958 */
959 CPUMRawEnter(pVM, NULL);
960 do
961 {
962 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
963 rc = VMMR3ResumeHyper(pVM);
964 else
965 rc = VMMR3RawRunGC(pVM);
966#ifndef DEBUG_sandervl
967 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
968 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
969#endif
970 } while ( rc == VINF_SUCCESS
971 || rc == VINF_EM_RAW_INTERRUPT);
972 rc = CPUMRawLeave(pVM, NULL, rc);
973 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
974
975 /*
976 * Make sure the trap flag is cleared.
977 * (Too bad if the guest is trying to single step too.)
978 */
979 if (fGuest)
980 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
981 else
982 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
983
984 /*
985 * Deal with the return codes.
986 */
987 rc = emR3HighPriorityPostForcedActions(pVM, rc);
988 rc = emR3RawHandleRC(pVM, pCtx, rc);
989 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
990 return rc;
991}
992
993
994#ifdef DEBUG
995
996/**
997 * Steps hardware accelerated mode.
998 *
999 * @returns VBox status code.
1000 * @param pVM The VM handle.
1001 */
1002static int emR3HwAccStep(PVM pVM)
1003{
1004 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1005
1006 int rc;
1007 PCPUMCTX pCtx = pVM->em.s.pCtx;
1008 VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_TSS));
1009
1010 /*
1011 * Check vital forced actions, but ignore pending interrupts and timers.
1012 */
1013 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1014 {
1015 rc = emR3RawForcedActions(pVM, pCtx);
1016 if (VBOX_FAILURE(rc))
1017 return rc;
1018 }
1019 /*
1020 * Set flags for single stepping.
1021 */
1022 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
1023
1024 /*
1025 * Single step.
1026 * We do not start time or anything, if anything we should just do a few nanoseconds.
1027 */
1028 do
1029 {
1030 rc = VMMR3HwAccRunGC(pVM);
1031 } while ( rc == VINF_SUCCESS
1032 || rc == VINF_EM_RAW_INTERRUPT);
1033 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1034
1035 /*
1036 * Make sure the trap flag is cleared.
1037 * (Too bad if the guest is trying to single step too.)
1038 */
1039 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1040
1041 /*
1042 * Deal with the return codes.
1043 */
1044 rc = emR3HighPriorityPostForcedActions(pVM, rc);
1045 rc = emR3RawHandleRC(pVM, pCtx, rc);
1046 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1047 return rc;
1048}
1049
1050
1051void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1052{
1053 EMSTATE enmOldState = pVM->em.s.enmState;
1054
1055 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1056
1057 Log(("Single step BEGIN:\n"));
1058 for(uint32_t i=0;i<cIterations;i++)
1059 {
1060 DBGFR3PrgStep(pVM);
1061 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1062 emR3RawStep(pVM);
1063 }
1064 Log(("Single step END:\n"));
1065 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1066 pVM->em.s.enmState = enmOldState;
1067}
1068
1069
1070void emR3SingleStepExecHwAcc(PVM pVM, uint32_t cIterations)
1071{
1072 EMSTATE enmOldState = pVM->em.s.enmState;
1073
1074 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1075
1076 Log(("Single step BEGIN:\n"));
1077 for(uint32_t i=0;i<cIterations;i++)
1078 {
1079 DBGFR3PrgStep(pVM);
1080 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1081 emR3HwAccStep(pVM);
1082 }
1083 Log(("Single step END:\n"));
1084 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1085 pVM->em.s.enmState = enmOldState;
1086}
1087
1088
1089void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1090{
1091 EMSTATE enmOldState = pVM->em.s.enmState;
1092
1093 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1094
1095 Log(("Single step BEGIN:\n"));
1096 for(uint32_t i=0;i<cIterations;i++)
1097 {
1098 DBGFR3PrgStep(pVM);
1099 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1100 emR3RemStep(pVM);
1101 }
1102 Log(("Single step END:\n"));
1103 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1104 pVM->em.s.enmState = enmOldState;
1105}
1106
1107#endif /* DEBUG */
1108
1109
1110/**
1111 * Executes one (or perhaps a few more) instruction(s).
1112 *
1113 * @returns VBox status code suitable for EM.
1114 *
1115 * @param pVM VM handle.
1116 * @param rcGC GC return code
1117 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1118 * instruction and prefix the log output with this text.
1119 */
1120#ifdef LOG_ENABLED
1121static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1122#else
1123static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1124#endif
1125{
1126 PCPUMCTX pCtx = pVM->em.s.pCtx;
1127 int rc;
1128
1129 /*
1130 *
1131 * The simple solution is to use the recompiler.
1132 * The better solution is to disassemble the current instruction and
1133 * try handle as many as possible without using REM.
1134 *
1135 */
1136
1137#ifdef LOG_ENABLED
1138 /*
1139 * Disassemble the instruction if requested.
1140 */
1141 if (pszPrefix)
1142 {
1143 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1144 DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1145 }
1146#endif /* LOG_ENABLED */
1147
1148 /*
1149 * PATM is making life more interesting.
1150 * We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1151 * tell PATM there is a trap in this code and have it take the appropriate actions
1152 * to allow us execute the code in REM.
1153 */
1154 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1155 {
1156 Log(("emR3RawExecuteInstruction: In patch block. eip=%VRv\n", pCtx->eip));
1157
1158 RTGCPTR pNewEip;
1159 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1160 switch (rc)
1161 {
1162 /*
1163 * It's not very useful to emulate a single instruction and then go back to raw
1164 * mode; just execute the whole block until IF is set again.
1165 */
1166 case VINF_SUCCESS:
1167 Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1168 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1169 pCtx->eip = pNewEip;
1170 Assert(pCtx->eip);
1171
1172 if (pCtx->eflags.Bits.u1IF)
1173 {
1174 /*
1175 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1176 */
1177 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1178 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1179 }
1180 else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1181 {
1182 /* special case: iret, that sets IF, detected a pending irq/event */
1183 return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1184 }
1185 return VINF_EM_RESCHEDULE_REM;
1186
1187 /*
1188 * One instruction.
1189 */
1190 case VINF_PATCH_EMULATE_INSTR:
1191 Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1192 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1193 pCtx->eip = pNewEip;
1194 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1195
1196 /*
1197 * The patch was disabled, hand it to the REM.
1198 */
1199 case VERR_PATCH_DISABLED:
1200 Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1201 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1202 pCtx->eip = pNewEip;
1203 if (pCtx->eflags.Bits.u1IF)
1204 {
1205 /*
1206 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1207 */
1208 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1209 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1210 }
1211 return VINF_EM_RESCHEDULE_REM;
1212
1213 /* Force continued patch exection; usually due to write monitored stack. */
1214 case VINF_PATCH_CONTINUE:
1215 return VINF_SUCCESS;
1216
1217 default:
1218 AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1219 return VERR_INTERNAL_ERROR;
1220 }
1221 }
1222
1223#if 0
1224 /* Try our own instruction emulator before falling back to the recompiler. */
1225 DISCPUSTATE Cpu;
1226 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1227 if (VBOX_SUCCESS(rc))
1228 {
1229 uint32_t size;
1230
1231 switch (Cpu.pCurInstr->opcode)
1232 {
1233 /* @todo we can do more now */
1234 case OP_MOV:
1235 case OP_AND:
1236 case OP_OR:
1237 case OP_XOR:
1238 case OP_POP:
1239 case OP_INC:
1240 case OP_DEC:
1241 case OP_XCHG:
1242 STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1243 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1244 if (VBOX_SUCCESS(rc))
1245 {
1246 pCtx->rip += Cpu.opsize;
1247 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1248 return rc;
1249 }
1250 if (rc != VERR_EM_INTERPRETER)
1251 AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1252 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1253 break;
1254 }
1255 }
1256#endif
1257 STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1258 rc = REMR3EmulateInstruction(pVM);
1259 STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1260
1261 return rc;
1262}
1263
1264
1265/**
1266 * Executes one (or perhaps a few more) instruction(s).
1267 * This is just a wrapper for discarding pszPrefix in non-logging builds.
1268 *
1269 * @returns VBox status code suitable for EM.
1270 * @param pVM VM handle.
1271 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1272 * instruction and prefix the log output with this text.
1273 * @param rcGC GC return code
1274 */
1275DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1276{
1277#ifdef LOG_ENABLED
1278 return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1279#else
1280 return emR3RawExecuteInstructionWorker(pVM, rcGC);
1281#endif
1282}
1283
1284/**
1285 * Executes one (or perhaps a few more) IO instruction(s).
1286 *
1287 * @returns VBox status code suitable for EM.
1288 * @param pVM VM handle.
1289 */
1290int emR3RawExecuteIOInstruction(PVM pVM)
1291{
1292 int rc;
1293 PCPUMCTX pCtx = pVM->em.s.pCtx;
1294
1295 STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1296
1297 /** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1298 * as io instructions tend to come in packages of more than one
1299 */
1300 DISCPUSTATE Cpu;
1301 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "IO EMU");
1302 if (VBOX_SUCCESS(rc))
1303 {
1304 rc = VINF_EM_RAW_EMULATE_INSTR;
1305
1306 if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE)))
1307 {
1308 switch (Cpu.pCurInstr->opcode)
1309 {
1310 case OP_IN:
1311 {
1312 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1313 rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1314 break;
1315 }
1316
1317 case OP_OUT:
1318 {
1319 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1320 rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1321 break;
1322 }
1323 }
1324 }
1325 else if (Cpu.prefix & PREFIX_REP)
1326 {
1327 switch (Cpu.pCurInstr->opcode)
1328 {
1329 case OP_INSB:
1330 case OP_INSWD:
1331 {
1332 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1333 rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1334 break;
1335 }
1336
1337 case OP_OUTSB:
1338 case OP_OUTSWD:
1339 {
1340 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1341 rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1342 break;
1343 }
1344 }
1345 }
1346
1347 /*
1348 * Handled the I/O return codes.
1349 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1350 */
1351 if (IOM_SUCCESS(rc))
1352 {
1353 pCtx->rip += Cpu.opsize;
1354 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1355 return rc;
1356 }
1357
1358 if (rc == VINF_EM_RAW_GUEST_TRAP)
1359 {
1360 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1361 rc = emR3RawGuestTrap(pVM);
1362 return rc;
1363 }
1364 AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1365
1366 if (VBOX_FAILURE(rc))
1367 {
1368 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1369 return rc;
1370 }
1371 AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RESCHEDULE_REM, ("rc=%Vrc\n", rc));
1372 }
1373 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1374 return emR3RawExecuteInstruction(pVM, "IO: ");
1375}
1376
1377
1378/**
1379 * Handle a guest context trap.
1380 *
1381 * @returns VBox status code suitable for EM.
1382 * @param pVM VM handle.
1383 */
1384static int emR3RawGuestTrap(PVM pVM)
1385{
1386 PCPUMCTX pCtx = pVM->em.s.pCtx;
1387
1388 /*
1389 * Get the trap info.
1390 */
1391 uint8_t u8TrapNo;
1392 TRPMEVENT enmType;;
1393 RTGCUINT uErrorCode;
1394 RTGCUINTPTR uCR2;
1395 int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1396 if (VBOX_FAILURE(rc))
1397 {
1398 AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1399 return rc;
1400 }
1401
1402 /* Traps can be directly forwarded in hardware accelerated mode. */
1403 if (HWACCMR3IsActive(pVM))
1404 {
1405#ifdef LOGGING_ENABLED
1406 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1407 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1408#endif
1409 return VINF_EM_RESCHEDULE_HWACC;
1410 }
1411
1412 /** Scan kernel code that traps; we might not get another chance. */
1413 if ( (pCtx->ss & X86_SEL_RPL) <= 1
1414 && !pCtx->eflags.Bits.u1VM)
1415 {
1416 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1417 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1418 }
1419
1420 if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1421 {
1422 DISCPUSTATE cpu;
1423
1424 /* If MONITOR & MWAIT are supported, then interpret them here. */
1425 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1426 if ( VBOX_SUCCESS(rc)
1427 && (cpu.pCurInstr->opcode == OP_MONITOR || cpu.pCurInstr->opcode == OP_MWAIT))
1428 {
1429 uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1430
1431 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1432
1433 if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1434 {
1435 rc = TRPMResetTrap(pVM);
1436 AssertRC(rc);
1437
1438 rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1439 if (VBOX_SUCCESS(rc))
1440 {
1441 pCtx->rip += cpu.opsize;
1442 return rc;
1443 }
1444 return emR3RawExecuteInstruction(pVM, "Monitor: ");
1445 }
1446 }
1447 }
1448 else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1449 {
1450 DISCPUSTATE cpu;
1451
1452 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1453 if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1454 {
1455 /*
1456 * We should really check the TSS for the IO bitmap, but it's not like this
1457 * lazy approach really makes things worse.
1458 */
1459 rc = TRPMResetTrap(pVM);
1460 AssertRC(rc);
1461 return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1462 }
1463 }
1464
1465#ifdef LOG_ENABLED
1466 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1467 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1468
1469 /* Get guest page information. */
1470 uint64_t fFlags = 0;
1471 RTGCPHYS GCPhys = 0;
1472 int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1473 Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1474 pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1475 fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1476 fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1477#endif
1478
1479 /*
1480 * #PG has CR2.
1481 * (Because of stuff like above we must set CR2 in a delayed fashion.)
1482 */
1483 if (u8TrapNo == 14 /* #PG */)
1484 pCtx->cr2 = uCR2;
1485
1486 return VINF_EM_RESCHEDULE_REM;
1487}
1488
1489
1490/**
1491 * Handle a ring switch trap.
1492 * Need to do statistics and to install patches. The result is going to REM.
1493 *
1494 * @returns VBox status code suitable for EM.
1495 * @param pVM VM handle.
1496 */
1497int emR3RawRingSwitch(PVM pVM)
1498{
1499 int rc;
1500 DISCPUSTATE Cpu;
1501 PCPUMCTX pCtx = pVM->em.s.pCtx;
1502
1503 /*
1504 * sysenter, syscall & callgate
1505 */
1506 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1507 if (VBOX_SUCCESS(rc))
1508 {
1509 if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1510 {
1511 if (pCtx->SysEnter.cs != 0)
1512 {
1513 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1514 (SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1515 if (VBOX_SUCCESS(rc))
1516 {
1517 DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1518 return VINF_EM_RESCHEDULE_RAW;
1519 }
1520 }
1521 }
1522
1523#ifdef VBOX_WITH_STATISTICS
1524 switch (Cpu.pCurInstr->opcode)
1525 {
1526 case OP_SYSENTER:
1527 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1528 break;
1529 case OP_SYSEXIT:
1530 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1531 break;
1532 case OP_SYSCALL:
1533 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1534 break;
1535 case OP_SYSRET:
1536 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1537 break;
1538 }
1539#endif
1540 }
1541 else
1542 AssertRC(rc);
1543
1544 /* go to the REM to emulate a single instruction */
1545 return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1546}
1547
1548/**
1549 * Handle a trap (#PF or #GP) in patch code
1550 *
1551 * @returns VBox status code suitable for EM.
1552 * @param pVM VM handle.
1553 * @param pCtx CPU context
1554 * @param gcret GC return code
1555 */
1556int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1557{
1558 uint8_t u8TrapNo;
1559 int rc;
1560 TRPMEVENT enmType;
1561 RTGCUINT uErrorCode;
1562 RTGCUINTPTR uCR2;
1563
1564 Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1565
1566 if (gcret == VINF_PATM_PATCH_INT3)
1567 {
1568 u8TrapNo = 3;
1569 uCR2 = 0;
1570 uErrorCode = 0;
1571 }
1572 else
1573 if (gcret == VINF_PATM_PATCH_TRAP_GP)
1574 {
1575 /* No active trap in this case. Kind of ugly. */
1576 u8TrapNo = X86_XCPT_GP;
1577 uCR2 = 0;
1578 uErrorCode = 0;
1579 }
1580 else
1581 {
1582 rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1583 if (VBOX_FAILURE(rc))
1584 {
1585 AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1586 return rc;
1587 }
1588 /* Reset the trap as we'll execute the original instruction again. */
1589 TRPMResetTrap(pVM);
1590 }
1591
1592 /*
1593 * Deal with traps inside patch code.
1594 * (This code won't run outside GC.)
1595 */
1596 if (u8TrapNo != 1)
1597 {
1598#ifdef LOG_ENABLED
1599 DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1600 DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1601
1602 DISCPUSTATE Cpu;
1603 int rc;
1604
1605 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1606 if ( VBOX_SUCCESS(rc)
1607 && Cpu.pCurInstr->opcode == OP_IRET)
1608 {
1609 uint32_t eip, selCS, uEFlags;
1610
1611 /* Iret crashes are bad as we have already changed the flags on the stack */
1612 rc = PGMPhysReadGCPtr(pVM, &eip, pCtx->esp, 4);
1613 rc |= PGMPhysReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1614 rc |= PGMPhysReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1615 if (rc == VINF_SUCCESS)
1616 {
1617 if ( (uEFlags & X86_EFL_VM)
1618 || (selCS & X86_SEL_RPL) == 3)
1619 {
1620 uint32_t selSS, esp;
1621
1622 rc |= PGMPhysReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1623 rc |= PGMPhysReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1624
1625 if (uEFlags & X86_EFL_VM)
1626 {
1627 uint32_t selDS, selES, selFS, selGS;
1628 rc = PGMPhysReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1629 rc |= PGMPhysReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1630 rc |= PGMPhysReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1631 rc |= PGMPhysReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1632 if (rc == VINF_SUCCESS)
1633 {
1634 Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1635 Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1636 }
1637 }
1638 else
1639 Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1640 }
1641 else
1642 Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1643 }
1644 }
1645#endif
1646 Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1647 pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1648
1649 RTGCPTR pNewEip;
1650 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1651 switch (rc)
1652 {
1653 /*
1654 * Execute the faulting instruction.
1655 */
1656 case VINF_SUCCESS:
1657 {
1658 /** @todo execute a whole block */
1659 Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1660 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1661 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1662
1663 pCtx->eip = pNewEip;
1664 AssertRelease(pCtx->eip);
1665
1666 if (pCtx->eflags.Bits.u1IF)
1667 {
1668 /* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1669 * int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1670 */
1671 if ( u8TrapNo == X86_XCPT_GP
1672 && PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1673 {
1674 /** @todo move to PATMR3HandleTrap */
1675 Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1676 PATMR3RemovePatch(pVM, pCtx->eip);
1677 }
1678
1679 /** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1680 /** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1681
1682 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1683 /* Interrupts are enabled; just go back to the original instruction.
1684 return VINF_SUCCESS; */
1685 }
1686 return VINF_EM_RESCHEDULE_REM;
1687 }
1688
1689 /*
1690 * One instruction.
1691 */
1692 case VINF_PATCH_EMULATE_INSTR:
1693 Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1694 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1695 pCtx->eip = pNewEip;
1696 AssertRelease(pCtx->eip);
1697 return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1698
1699 /*
1700 * The patch was disabled, hand it to the REM.
1701 */
1702 case VERR_PATCH_DISABLED:
1703 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1704 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1705 pCtx->eip = pNewEip;
1706 AssertRelease(pCtx->eip);
1707
1708 if (pCtx->eflags.Bits.u1IF)
1709 {
1710 /*
1711 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1712 */
1713 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1714 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1715 }
1716 return VINF_EM_RESCHEDULE_REM;
1717
1718 /* Force continued patch exection; usually due to write monitored stack. */
1719 case VINF_PATCH_CONTINUE:
1720 return VINF_SUCCESS;
1721
1722 /*
1723 * Anything else is *fatal*.
1724 */
1725 default:
1726 AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1727 return VERR_INTERNAL_ERROR;
1728 }
1729 }
1730 return VINF_SUCCESS;
1731}
1732
1733
1734/**
1735 * Handle a privileged instruction.
1736 *
1737 * @returns VBox status code suitable for EM.
1738 * @param pVM VM handle.
1739 */
1740int emR3RawPrivileged(PVM pVM)
1741{
1742 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1743 PCPUMCTX pCtx = pVM->em.s.pCtx;
1744
1745 Assert(!pCtx->eflags.Bits.u1VM);
1746
1747 if (PATMIsEnabled(pVM))
1748 {
1749 /*
1750 * Check if in patch code.
1751 */
1752 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1753 {
1754#ifdef LOG_ENABLED
1755 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1756#endif
1757 AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1758 return VERR_EM_RAW_PATCH_CONFLICT;
1759 }
1760 if ( (pCtx->ss & X86_SEL_RPL) == 0
1761 && !pCtx->eflags.Bits.u1VM
1762 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
1763 {
1764 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1765 (SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1766 if (VBOX_SUCCESS(rc))
1767 {
1768#ifdef LOG_ENABLED
1769 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1770#endif
1771 DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1772 return VINF_SUCCESS;
1773 }
1774 }
1775 }
1776
1777#ifdef LOG_ENABLED
1778 if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1779 {
1780 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1781 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1782 }
1783#endif
1784
1785 /*
1786 * Instruction statistics and logging.
1787 */
1788 DISCPUSTATE Cpu;
1789 int rc;
1790
1791 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1792 if (VBOX_SUCCESS(rc))
1793 {
1794#ifdef VBOX_WITH_STATISTICS
1795 PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1796 switch (Cpu.pCurInstr->opcode)
1797 {
1798 case OP_INVLPG:
1799 STAM_COUNTER_INC(&pStats->StatInvlpg);
1800 break;
1801 case OP_IRET:
1802 STAM_COUNTER_INC(&pStats->StatIret);
1803 break;
1804 case OP_CLI:
1805 STAM_COUNTER_INC(&pStats->StatCli);
1806 emR3RecordCli(pVM, pCtx->rip);
1807 break;
1808 case OP_STI:
1809 STAM_COUNTER_INC(&pStats->StatSti);
1810 break;
1811 case OP_INSB:
1812 case OP_INSWD:
1813 case OP_IN:
1814 case OP_OUTSB:
1815 case OP_OUTSWD:
1816 case OP_OUT:
1817 AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1818 break;
1819
1820 case OP_MOV_CR:
1821 if (Cpu.param1.flags & USE_REG_GEN32)
1822 {
1823 //read
1824 Assert(Cpu.param2.flags & USE_REG_CR);
1825 Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1826 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1827 }
1828 else
1829 {
1830 //write
1831 Assert(Cpu.param1.flags & USE_REG_CR);
1832 Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1833 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1834 }
1835 break;
1836
1837 case OP_MOV_DR:
1838 STAM_COUNTER_INC(&pStats->StatMovDRx);
1839 break;
1840 case OP_LLDT:
1841 STAM_COUNTER_INC(&pStats->StatMovLldt);
1842 break;
1843 case OP_LIDT:
1844 STAM_COUNTER_INC(&pStats->StatMovLidt);
1845 break;
1846 case OP_LGDT:
1847 STAM_COUNTER_INC(&pStats->StatMovLgdt);
1848 break;
1849 case OP_SYSENTER:
1850 STAM_COUNTER_INC(&pStats->StatSysEnter);
1851 break;
1852 case OP_SYSEXIT:
1853 STAM_COUNTER_INC(&pStats->StatSysExit);
1854 break;
1855 case OP_SYSCALL:
1856 STAM_COUNTER_INC(&pStats->StatSysCall);
1857 break;
1858 case OP_SYSRET:
1859 STAM_COUNTER_INC(&pStats->StatSysRet);
1860 break;
1861 case OP_HLT:
1862 STAM_COUNTER_INC(&pStats->StatHlt);
1863 break;
1864 default:
1865 STAM_COUNTER_INC(&pStats->StatMisc);
1866 Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1867 break;
1868 }
1869#endif
1870 if ( (pCtx->ss & X86_SEL_RPL) == 0
1871 && !pCtx->eflags.Bits.u1VM
1872 && SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
1873 {
1874 uint32_t size;
1875
1876 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1877 switch (Cpu.pCurInstr->opcode)
1878 {
1879 case OP_CLI:
1880 pCtx->eflags.u32 &= ~X86_EFL_IF;
1881 Assert(Cpu.opsize == 1);
1882 pCtx->rip += Cpu.opsize;
1883 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1884 return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1885
1886 case OP_STI:
1887 pCtx->eflags.u32 |= X86_EFL_IF;
1888 EMSetInhibitInterruptsPC(pVM, pCtx->rip + Cpu.opsize);
1889 Assert(Cpu.opsize == 1);
1890 pCtx->rip += Cpu.opsize;
1891 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1892 return VINF_SUCCESS;
1893
1894 case OP_HLT:
1895 if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1896 {
1897 PATMTRANSSTATE enmState;
1898 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1899
1900 if (enmState == PATMTRANS_OVERWRITTEN)
1901 {
1902 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1903 Assert(rc == VERR_PATCH_DISABLED);
1904 /* Conflict detected, patch disabled */
1905 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1906
1907 enmState = PATMTRANS_SAFE;
1908 }
1909
1910 /* The translation had better be successful. Otherwise we can't recover. */
1911 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1912 if (enmState != PATMTRANS_OVERWRITTEN)
1913 pCtx->eip = pOrgInstrGC;
1914 }
1915 /* no break; we could just return VINF_EM_HALT here */
1916
1917 case OP_MOV_CR:
1918 case OP_MOV_DR:
1919#ifdef LOG_ENABLED
1920 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1921 {
1922 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1923 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1924 }
1925#endif
1926
1927 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1928 if (VBOX_SUCCESS(rc))
1929 {
1930 pCtx->rip += Cpu.opsize;
1931 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1932
1933 if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1934 && Cpu.param1.flags == USE_REG_CR /* write */
1935 )
1936 {
1937 /* Reschedule is necessary as the execution/paging mode might have changed. */
1938 return VINF_EM_RESCHEDULE;
1939 }
1940 return rc; /* can return VINF_EM_HALT as well. */
1941 }
1942 AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1943 break; /* fall back to the recompiler */
1944 }
1945 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1946 }
1947 }
1948
1949 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1950 return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1951
1952 return emR3RawExecuteInstruction(pVM, "PRIV");
1953}
1954
1955
1956/**
1957 * Update the forced rawmode execution modifier.
1958 *
1959 * This function is called when we're returning from the raw-mode loop(s). If we're
1960 * in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1961 * if not in patch code, the flag will be cleared.
1962 *
1963 * We should never interrupt patch code while it's being executed. Cli patches can
1964 * contain big code blocks, but they are always executed with IF=0. Other patches
1965 * replace single instructions and should be atomic.
1966 *
1967 * @returns Updated rc.
1968 *
1969 * @param pVM The VM handle.
1970 * @param pCtx The guest CPU context.
1971 * @param rc The result code.
1972 */
1973DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
1974{
1975 if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1976 {
1977 /* ignore reschedule attempts. */
1978 switch (rc)
1979 {
1980 case VINF_EM_RESCHEDULE:
1981 case VINF_EM_RESCHEDULE_REM:
1982 rc = VINF_SUCCESS;
1983 break;
1984 }
1985 pVM->em.s.fForceRAW = true;
1986 }
1987 else
1988 pVM->em.s.fForceRAW = false;
1989 return rc;
1990}
1991
1992
1993/**
1994 * Process a subset of the raw-mode return code.
1995 *
1996 * Since we have to share this with raw-mode single stepping, this inline
1997 * function has been created to avoid code duplication.
1998 *
1999 * @returns VINF_SUCCESS if it's ok to continue raw mode.
2000 * @returns VBox status code to return to the EM main loop.
2001 *
2002 * @param pVM The VM handle
2003 * @param rc The return code.
2004 * @param pCtx The guest cpu context.
2005 */
2006DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2007{
2008 switch (rc)
2009 {
2010 /*
2011 * Common & simple ones.
2012 */
2013 case VINF_SUCCESS:
2014 break;
2015 case VINF_EM_RESCHEDULE_RAW:
2016 case VINF_EM_RESCHEDULE_HWACC:
2017 case VINF_EM_RAW_INTERRUPT:
2018 case VINF_EM_RAW_TO_R3:
2019 case VINF_EM_RAW_TIMER_PENDING:
2020 case VINF_EM_PENDING_REQUEST:
2021 rc = VINF_SUCCESS;
2022 break;
2023
2024 /*
2025 * Privileged instruction.
2026 */
2027 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2028 case VINF_PATM_PATCH_TRAP_GP:
2029 rc = emR3RawPrivileged(pVM);
2030 break;
2031
2032 /*
2033 * Got a trap which needs dispatching.
2034 */
2035 case VINF_EM_RAW_GUEST_TRAP:
2036 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2037 {
2038 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2039 rc = VERR_EM_RAW_PATCH_CONFLICT;
2040 break;
2041 }
2042
2043 Assert(TRPMHasTrap(pVM));
2044 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2045
2046 if (TRPMHasTrap(pVM))
2047 {
2048 uint8_t u8Interrupt;
2049 RTGCUINT uErrorCode;
2050 TRPMERRORCODE enmError = TRPM_TRAP_NO_ERRORCODE;
2051
2052 rc = TRPMQueryTrapAll(pVM, &u8Interrupt, NULL, &uErrorCode, NULL);
2053 AssertRC(rc);
2054
2055 if (uErrorCode != ~0U)
2056 enmError = TRPM_TRAP_HAS_ERRORCODE;
2057
2058 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2059 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2060 {
2061 CSAMR3CheckGates(pVM, u8Interrupt, 1);
2062 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2063
2064 /** If it was successful, then we could go back to raw mode. */
2065 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER)
2066 {
2067 /* Must check pending forced actions as our IDT or GDT might be out of sync */
2068 EMR3CheckRawForcedActions(pVM);
2069
2070 rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8Interrupt, uErrorCode, enmError, TRPM_TRAP, -1);
2071 if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
2072 {
2073 TRPMResetTrap(pVM);
2074 return VINF_EM_RESCHEDULE_RAW;
2075 }
2076 }
2077 }
2078 }
2079 rc = emR3RawGuestTrap(pVM);
2080 break;
2081
2082 /*
2083 * Trap in patch code.
2084 */
2085 case VINF_PATM_PATCH_TRAP_PF:
2086 case VINF_PATM_PATCH_INT3:
2087 rc = emR3PatchTrap(pVM, pCtx, rc);
2088 break;
2089
2090 case VINF_PATM_DUPLICATE_FUNCTION:
2091 Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2092 rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2093 AssertRC(rc);
2094 rc = VINF_SUCCESS;
2095 break;
2096
2097 case VINF_PATM_CHECK_PATCH_PAGE:
2098 rc = PATMR3HandleMonitoredPage(pVM);
2099 AssertRC(rc);
2100 rc = VINF_SUCCESS;
2101 break;
2102
2103 /*
2104 * Patch manager.
2105 */
2106 case VERR_EM_RAW_PATCH_CONFLICT:
2107 AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2108 break;
2109
2110 /*
2111 * Memory mapped I/O access - attempt to patch the instruction
2112 */
2113 case VINF_PATM_HC_MMIO_PATCH_READ:
2114 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2115 PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2116 if (VBOX_FAILURE(rc))
2117 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2118 break;
2119
2120 case VINF_PATM_HC_MMIO_PATCH_WRITE:
2121 AssertFailed(); /* not yet implemented. */
2122 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2123 break;
2124
2125 /*
2126 * Conflict or out of page tables.
2127 *
2128 * VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2129 * do here is to execute the pending forced actions.
2130 */
2131 case VINF_PGM_SYNC_CR3:
2132 AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2133 ("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2134 rc = VINF_SUCCESS;
2135 break;
2136
2137 /*
2138 * Paging mode change.
2139 */
2140 case VINF_PGM_CHANGE_MODE:
2141 rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2142 if (VBOX_SUCCESS(rc))
2143 rc = VINF_EM_RESCHEDULE;
2144 break;
2145
2146 /*
2147 * CSAM wants to perform a task in ring-3. It has set an FF action flag.
2148 */
2149 case VINF_CSAM_PENDING_ACTION:
2150 rc = VINF_SUCCESS;
2151 break;
2152
2153 /*
2154 * Invoked Interrupt gate - must directly (!) go to the recompiler.
2155 */
2156 case VINF_EM_RAW_INTERRUPT_PENDING:
2157 case VINF_EM_RAW_RING_SWITCH_INT:
2158 {
2159 uint8_t u8Interrupt;
2160
2161 Assert(TRPMHasTrap(pVM));
2162 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2163
2164 if (TRPMHasTrap(pVM))
2165 {
2166 u8Interrupt = TRPMGetTrapNo(pVM);
2167
2168 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2169 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2170 {
2171 CSAMR3CheckGates(pVM, u8Interrupt, 1);
2172 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2173 /** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2174 }
2175 }
2176 rc = VINF_EM_RESCHEDULE_REM;
2177 break;
2178 }
2179
2180 /*
2181 * Other ring switch types.
2182 */
2183 case VINF_EM_RAW_RING_SWITCH:
2184 rc = emR3RawRingSwitch(pVM);
2185 break;
2186
2187 /*
2188 * REMGCNotifyInvalidatePage() failed because of overflow.
2189 */
2190 case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2191 Assert((pCtx->ss & X86_SEL_RPL) != 1);
2192 REMR3ReplayInvalidatedPages(pVM);
2193 rc = VINF_SUCCESS;
2194 break;
2195
2196 /*
2197 * I/O Port access - emulate the instruction.
2198 */
2199 case VINF_IOM_HC_IOPORT_READ:
2200 case VINF_IOM_HC_IOPORT_WRITE:
2201 rc = emR3RawExecuteIOInstruction(pVM);
2202 break;
2203
2204 /*
2205 * Memory mapped I/O access - emulate the instruction.
2206 */
2207 case VINF_IOM_HC_MMIO_READ:
2208 case VINF_IOM_HC_MMIO_WRITE:
2209 case VINF_IOM_HC_MMIO_READ_WRITE:
2210 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2211 break;
2212
2213 /*
2214 * Execute instruction.
2215 */
2216 case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2217 rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2218 break;
2219 case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2220 rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2221 break;
2222 case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2223 rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2224 break;
2225 case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2226 rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2227 break;
2228 case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2229 rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2230 break;
2231
2232 case VINF_EM_RAW_EMULATE_INSTR_HLT:
2233 /** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2234 rc = emR3RawPrivileged(pVM);
2235 break;
2236
2237 case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2238 rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2239 break;
2240
2241 case VINF_EM_RAW_EMULATE_INSTR:
2242 case VINF_PATCH_EMULATE_INSTR:
2243 rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2244 break;
2245
2246 /*
2247 * Stale selector and iret traps => REM.
2248 */
2249 case VINF_EM_RAW_STALE_SELECTOR:
2250 case VINF_EM_RAW_IRET_TRAP:
2251 /* We will not go to the recompiler if EIP points to patch code. */
2252 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2253 {
2254 pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2255 }
2256 LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2257 rc = VINF_EM_RESCHEDULE_REM;
2258 break;
2259
2260 /*
2261 * Up a level.
2262 */
2263 case VINF_EM_TERMINATE:
2264 case VINF_EM_OFF:
2265 case VINF_EM_RESET:
2266 case VINF_EM_SUSPEND:
2267 case VINF_EM_HALT:
2268 case VINF_EM_RESUME:
2269 case VINF_EM_RESCHEDULE:
2270 case VINF_EM_RESCHEDULE_REM:
2271 break;
2272
2273 /*
2274 * Up a level and invoke the debugger.
2275 */
2276 case VINF_EM_DBG_STEPPED:
2277 case VINF_EM_DBG_BREAKPOINT:
2278 case VINF_EM_DBG_STEP:
2279 case VINF_EM_DBG_HYPER_ASSERTION:
2280 case VINF_EM_DBG_HYPER_BREAKPOINT:
2281 case VINF_EM_DBG_HYPER_STEPPED:
2282 case VINF_EM_DBG_STOP:
2283 break;
2284
2285 /*
2286 * Up a level, dump and debug.
2287 */
2288 case VERR_TRPM_DONT_PANIC:
2289 case VERR_TRPM_PANIC:
2290 break;
2291
2292 /*
2293 * Anything which is not known to us means an internal error
2294 * and the termination of the VM!
2295 */
2296 default:
2297 AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2298 break;
2299 }
2300 return rc;
2301}
2302
2303/**
2304 * Check for pending raw actions
2305 *
2306 * @returns VBox status code.
2307 * @param pVM The VM to operate on.
2308 */
2309EMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2310{
2311 return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2312}
2313
2314
2315/**
2316 * Process raw-mode specific forced actions.
2317 *
2318 * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2319 *
2320 * @returns VBox status code.
2321 * Only the normal success/failure stuff, no VINF_EM_*.
2322 * @param pVM The VM handle.
2323 * @param pCtx The guest CPUM register context.
2324 */
2325static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2326{
2327 /*
2328 * Note that the order is *vitally* important!
2329 * Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2330 */
2331
2332
2333 /*
2334 * Sync selector tables.
2335 */
2336 if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT))
2337 {
2338 int rc = SELMR3UpdateFromCPUM(pVM);
2339 if (VBOX_FAILURE(rc))
2340 return rc;
2341 }
2342
2343 /*
2344 * Sync IDT.
2345 */
2346 if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2347 {
2348 int rc = TRPMR3SyncIDT(pVM);
2349 if (VBOX_FAILURE(rc))
2350 return rc;
2351 }
2352
2353 /*
2354 * Sync TSS.
2355 */
2356 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2357 {
2358 int rc = SELMR3SyncTSS(pVM);
2359 if (VBOX_FAILURE(rc))
2360 return rc;
2361 }
2362
2363 /*
2364 * Sync page directory.
2365 */
2366 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2367 {
2368 int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2369 if (VBOX_FAILURE(rc))
2370 return rc;
2371
2372 Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT));
2373
2374 /* Prefetch pages for EIP and ESP */
2375 /** @todo This is rather expensive. Should investigate if it really helps at all. */
2376 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2377 if (rc == VINF_SUCCESS)
2378 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2379 if (rc != VINF_SUCCESS)
2380 {
2381 if (rc != VINF_PGM_SYNC_CR3)
2382 return rc;
2383 rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2384 if (VBOX_FAILURE(rc))
2385 return rc;
2386 }
2387 /** @todo maybe prefetch the supervisor stack page as well */
2388 }
2389
2390 /*
2391 * Allocate handy pages (just in case the above actions have consumed some pages).
2392 */
2393 if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
2394 {
2395 int rc = PGMR3PhysAllocateHandyPages(pVM);
2396 if (VBOX_FAILURE(rc))
2397 return rc;
2398 }
2399
2400 return VINF_SUCCESS;
2401}
2402
2403
2404/**
2405 * Executes raw code.
2406 *
2407 * This function contains the raw-mode version of the inner
2408 * execution loop (the outer loop being in EMR3ExecuteVM()).
2409 *
2410 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2411 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2412 *
2413 * @param pVM VM handle.
2414 * @param pfFFDone Where to store an indicator telling whether or not
2415 * FFs were done before returning.
2416 */
2417static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2418{
2419 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2420
2421 int rc = VERR_INTERNAL_ERROR;
2422 PCPUMCTX pCtx = pVM->em.s.pCtx;
2423 LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2424 pVM->em.s.fForceRAW = false;
2425 *pfFFDone = false;
2426
2427
2428 /*
2429 *
2430 * Spin till we get a forced action or raw mode status code resulting in
2431 * in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2432 *
2433 */
2434 for (;;)
2435 {
2436 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2437
2438 /*
2439 * Check various preconditions.
2440 */
2441#ifdef VBOX_STRICT
2442 Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2443 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) == 3 || (pCtx->ss & X86_SEL_RPL) == 0);
2444 AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2445 || PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2446 ("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2447 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2448 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2449 {
2450 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2451 return VERR_INTERNAL_ERROR;
2452 }
2453#endif /* VBOX_STRICT */
2454
2455 /*
2456 * Process high priority pre-execution raw-mode FFs.
2457 */
2458 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2459 {
2460 rc = emR3RawForcedActions(pVM, pCtx);
2461 if (VBOX_FAILURE(rc))
2462 break;
2463 }
2464
2465 /*
2466 * If we're going to execute ring-0 code, the guest state needs to
2467 * be modified a bit and some of the state components (IF, SS/CS RPL,
2468 * and perhaps EIP) needs to be stored with PATM.
2469 */
2470 rc = CPUMRawEnter(pVM, NULL);
2471 if (rc != VINF_SUCCESS)
2472 {
2473 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2474 break;
2475 }
2476
2477 /*
2478 * Scan code before executing it. Don't bother with user mode or V86 code
2479 */
2480 if ( (pCtx->ss & X86_SEL_RPL) <= 1
2481 && !pCtx->eflags.Bits.u1VM
2482 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
2483 {
2484 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2485 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2486 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2487 }
2488
2489#ifdef LOG_ENABLED
2490 /*
2491 * Log important stuff before entering GC.
2492 */
2493 PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2494 if (pCtx->eflags.Bits.u1VM)
2495 Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2496 else if ((pCtx->ss & X86_SEL_RPL) == 1)
2497 {
2498 bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2499 Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2500 }
2501 else if ((pCtx->ss & X86_SEL_RPL) == 3)
2502 Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2503#endif /* LOG_ENABLED */
2504
2505
2506
2507 /*
2508 * Execute the code.
2509 */
2510 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2511 STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2512 VMMR3Unlock(pVM);
2513 rc = VMMR3RawRunGC(pVM);
2514 VMMR3Lock(pVM);
2515 STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2516 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2517
2518 LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2519 LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2520
2521 /*
2522 * Restore the real CPU state and deal with high priority post
2523 * execution FFs before doing anything else.
2524 */
2525 rc = CPUMRawLeave(pVM, NULL, rc);
2526 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2527 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2528 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2529
2530#ifdef VBOX_STRICT
2531 /*
2532 * Assert TSS consistency & rc vs patch code.
2533 */
2534 if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS | VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2535 && EMIsRawRing0Enabled(pVM))
2536 SELMR3CheckTSS(pVM);
2537 switch (rc)
2538 {
2539 case VINF_SUCCESS:
2540 case VINF_EM_RAW_INTERRUPT:
2541 case VINF_PATM_PATCH_TRAP_PF:
2542 case VINF_PATM_PATCH_TRAP_GP:
2543 case VINF_PATM_PATCH_INT3:
2544 case VINF_PATM_CHECK_PATCH_PAGE:
2545 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2546 case VINF_EM_RAW_GUEST_TRAP:
2547 case VINF_EM_RESCHEDULE_RAW:
2548 break;
2549
2550 default:
2551 if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2552 LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VRv for reason %Vrc\n", (RTRCPTR)CPUMGetGuestEIP(pVM), rc));
2553 break;
2554 }
2555 /*
2556 * Let's go paranoid!
2557 */
2558 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2559 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2560 {
2561 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2562 return VERR_INTERNAL_ERROR;
2563 }
2564#endif /* VBOX_STRICT */
2565
2566 /*
2567 * Process the returned status code.
2568 */
2569 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2570 {
2571 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2572 break;
2573 }
2574 rc = emR3RawHandleRC(pVM, pCtx, rc);
2575 if (rc != VINF_SUCCESS)
2576 {
2577 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2578 if (rc != VINF_SUCCESS)
2579 {
2580 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2581 break;
2582 }
2583 }
2584
2585 /*
2586 * Check and execute forced actions.
2587 */
2588#ifdef VBOX_HIGH_RES_TIMERS_HACK
2589 TMTimerPoll(pVM);
2590#endif
2591 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2592 if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2593 {
2594 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) != 1);
2595
2596 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2597 rc = emR3ForcedActions(pVM, rc);
2598 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2599 if ( rc != VINF_SUCCESS
2600 && rc != VINF_EM_RESCHEDULE_RAW)
2601 {
2602 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2603 if (rc != VINF_SUCCESS)
2604 {
2605 *pfFFDone = true;
2606 break;
2607 }
2608 }
2609 }
2610 }
2611
2612 /*
2613 * Return to outer loop.
2614 */
2615#if defined(LOG_ENABLED) && defined(DEBUG)
2616 RTLogFlush(NULL);
2617#endif
2618 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2619 return rc;
2620}
2621
2622
2623/**
2624 * Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2625 *
2626 * This function contains the raw-mode version of the inner
2627 * execution loop (the outer loop being in EMR3ExecuteVM()).
2628 *
2629 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2630 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2631 *
2632 * @param pVM VM handle.
2633 * @param pfFFDone Where to store an indicator telling whether or not
2634 * FFs were done before returning.
2635 */
2636static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2637{
2638 int rc = VERR_INTERNAL_ERROR;
2639 PCPUMCTX pCtx = pVM->em.s.pCtx;
2640
2641 LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%VGv)\n", pCtx->cs, pCtx->rip));
2642 *pfFFDone = false;
2643
2644 STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2645
2646 /*
2647 * Spin till we get a forced action which returns anything but VINF_SUCCESS.
2648 */
2649 for (;;)
2650 {
2651 STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2652
2653 /*
2654 * Check various preconditions.
2655 */
2656 VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_TSS));
2657
2658 /*
2659 * Process high priority pre-execution raw-mode FFs.
2660 */
2661 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2662 {
2663 rc = emR3RawForcedActions(pVM, pCtx);
2664 if (VBOX_FAILURE(rc))
2665 break;
2666 }
2667
2668#ifdef LOG_ENABLED
2669 uint8_t u8Vector;
2670
2671 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2672 if (rc == VINF_SUCCESS)
2673 {
2674 Log(("Pending hardware interrupt=0x%x ) cs:eip=%04X:%VGv\n", u8Vector, pCtx->cs, pCtx->rip));
2675 }
2676 /*
2677 * Log important stuff before entering GC.
2678 */
2679 uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2680
2681 if (pCtx->eflags.Bits.u1VM)
2682 Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2683 else
2684 if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
2685 Log(("HWR%d: %04X:%VGv ESP=%VGv IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2686 else
2687 Log(("HWR%d: %04X:%08X ESP=%08X IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2688#endif
2689
2690 /*
2691 * Execute the code.
2692 */
2693 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2694 STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2695 VMMR3Unlock(pVM);
2696 rc = VMMR3HwAccRunGC(pVM);
2697 VMMR3Lock(pVM);
2698 STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2699
2700 /*
2701 * Deal with high priority post execution FFs before doing anything else.
2702 */
2703 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2704 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2705 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2706
2707 /*
2708 * Process the returned status code.
2709 */
2710 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2711 break;
2712
2713 rc = emR3RawHandleRC(pVM, pCtx, rc);
2714 if (rc != VINF_SUCCESS)
2715 break;
2716
2717 /*
2718 * Check and execute forced actions.
2719 */
2720#ifdef VBOX_HIGH_RES_TIMERS_HACK
2721 TMTimerPoll(pVM);
2722#endif
2723 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2724 {
2725 rc = emR3ForcedActions(pVM, rc);
2726 if ( rc != VINF_SUCCESS
2727 && rc != VINF_EM_RESCHEDULE_HWACC)
2728 {
2729 *pfFFDone = true;
2730 break;
2731 }
2732 }
2733 }
2734 /*
2735 * Return to outer loop.
2736 */
2737#if defined(LOG_ENABLED) && defined(DEBUG)
2738 RTLogFlush(NULL);
2739#endif
2740 return rc;
2741}
2742
2743
2744/**
2745 * Decides whether to execute RAW, HWACC or REM.
2746 *
2747 * @returns new EM state
2748 * @param pVM The VM.
2749 * @param pCtx The CPU context.
2750 */
2751inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2752{
2753 /*
2754 * When forcing raw-mode execution, things are simple.
2755 */
2756 if (pVM->em.s.fForceRAW)
2757 return EMSTATE_RAW;
2758
2759 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2760 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2761 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2762
2763 X86EFLAGS EFlags = pCtx->eflags;
2764 if (HWACCMIsEnabled(pVM))
2765 {
2766 /* Hardware accelerated raw-mode:
2767 *
2768 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2769 */
2770 if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2771 return EMSTATE_HWACC;
2772
2773 /** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2774 return EMSTATE_REM;
2775 }
2776
2777 /* Standard raw-mode:
2778 *
2779 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2780 * or 32 bits protected mode ring 0 code
2781 *
2782 * The tests are ordered by the likelyhood of being true during normal execution.
2783 */
2784 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
2785 {
2786 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2787 return EMSTATE_REM;
2788 }
2789
2790#ifndef VBOX_RAW_V86
2791 if (EFlags.u32 & X86_EFL_VM) {
2792 Log2(("raw mode refused: VM_MASK\n"));
2793 return EMSTATE_REM;
2794 }
2795#endif
2796
2797 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2798 uint32_t u32CR0 = pCtx->cr0;
2799 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
2800 {
2801 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2802 return EMSTATE_REM;
2803 }
2804
2805 if (pCtx->cr4 & X86_CR4_PAE)
2806 {
2807 uint32_t u32Dummy, u32Features;
2808
2809 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2810 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
2811 return EMSTATE_REM;
2812 }
2813
2814 unsigned uSS = pCtx->ss;
2815 if ( pCtx->eflags.Bits.u1VM
2816 || (uSS & X86_SEL_RPL) == 3)
2817 {
2818 if (!EMIsRawRing3Enabled(pVM))
2819 return EMSTATE_REM;
2820
2821 if (!(EFlags.u32 & X86_EFL_IF))
2822 {
2823 Log2(("raw mode refused: IF (RawR3)\n"));
2824 return EMSTATE_REM;
2825 }
2826
2827 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2828 {
2829 Log2(("raw mode refused: CR0.WP + RawR0\n"));
2830 return EMSTATE_REM;
2831 }
2832 }
2833 else
2834 {
2835 if (!EMIsRawRing0Enabled(pVM))
2836 return EMSTATE_REM;
2837
2838 /* Only ring 0 supervisor code. */
2839 if ((uSS & X86_SEL_RPL) != 0)
2840 {
2841 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2842 return EMSTATE_REM;
2843 }
2844
2845 // Let's start with pure 32 bits ring 0 code first
2846 /** @todo What's pure 32-bit mode? flat? */
2847 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2848 || !(pCtx->csHid.Attr.n.u1DefBig))
2849 {
2850 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2851 return EMSTATE_REM;
2852 }
2853
2854 /* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2855 if (!(u32CR0 & X86_CR0_WP))
2856 {
2857 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2858 return EMSTATE_REM;
2859 }
2860
2861 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2862 {
2863 Log2(("raw r0 mode forced: patch code\n"));
2864 return EMSTATE_RAW;
2865 }
2866
2867#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2868 if (!(EFlags.u32 & X86_EFL_IF))
2869 {
2870 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2871 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2872 return EMSTATE_REM;
2873 }
2874#endif
2875
2876 /** @todo still necessary??? */
2877 if (EFlags.Bits.u2IOPL != 0)
2878 {
2879 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2880 return EMSTATE_REM;
2881 }
2882 }
2883
2884 Assert(PGMPhysIsA20Enabled(pVM));
2885 return EMSTATE_RAW;
2886}
2887
2888
2889/**
2890 * Executes all high priority post execution force actions.
2891 *
2892 * @returns rc or a fatal status code.
2893 *
2894 * @param pVM VM handle.
2895 * @param rc The current rc.
2896 */
2897static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2898{
2899 if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2900 PDMR3CritSectFF(pVM);
2901
2902 if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
2903 CSAMR3DoPendingAction(pVM);
2904
2905 return rc;
2906}
2907
2908
2909/**
2910 * Executes all pending forced actions.
2911 *
2912 * Forced actions can cause execution delays and execution
2913 * rescheduling. The first we deal with using action priority, so
2914 * that for instance pending timers aren't scheduled and ran until
2915 * right before execution. The rescheduling we deal with using
2916 * return codes. The same goes for VM termination, only in that case
2917 * we exit everything.
2918 *
2919 * @returns VBox status code of equal or greater importance/severity than rc.
2920 * The most important ones are: VINF_EM_RESCHEDULE,
2921 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2922 *
2923 * @param pVM VM handle.
2924 * @param rc The current rc.
2925 *
2926 */
2927static int emR3ForcedActions(PVM pVM, int rc)
2928{
2929#ifdef VBOX_STRICT
2930 int rcIrq = VINF_SUCCESS;
2931#endif
2932 STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2933
2934#define UPDATE_RC() \
2935 do { \
2936 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2937 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
2938 break; \
2939 if (!rc || rc2 < rc) \
2940 rc = rc2; \
2941 } while (0)
2942
2943 int rc2;
2944
2945 /*
2946 * Post execution chunk first.
2947 */
2948 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2949 {
2950 /*
2951 * Termination request.
2952 */
2953 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
2954 {
2955 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
2956 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2957 return VINF_EM_TERMINATE;
2958 }
2959
2960 /*
2961 * Debugger Facility polling.
2962 */
2963 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
2964 {
2965 rc2 = DBGFR3VMMForcedAction(pVM);
2966 UPDATE_RC();
2967 }
2968
2969 /*
2970 * Postponed reset request.
2971 */
2972 if (VM_FF_ISSET(pVM, VM_FF_RESET))
2973 {
2974 rc2 = VMR3Reset(pVM);
2975 UPDATE_RC();
2976 VM_FF_CLEAR(pVM, VM_FF_RESET);
2977 }
2978
2979 /*
2980 * CSAM page scanning.
2981 */
2982 if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
2983 {
2984 PCPUMCTX pCtx = pVM->em.s.pCtx;
2985
2986 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
2987 Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
2988
2989 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2990 VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
2991 }
2992
2993 /* check that we got them all */
2994 Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_CSAM_SCAN_PAGE)));
2995 }
2996
2997 /*
2998 * Normal priority then.
2999 * (Executed in no particular order.)
3000 */
3001 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3002 {
3003 /*
3004 * PDM Queues are pending.
3005 */
3006 if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3007 PDMR3QueueFlushAll(pVM);
3008
3009 /*
3010 * PDM DMA transfers are pending.
3011 */
3012 if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3013 PDMR3DmaRun(pVM);
3014
3015 /*
3016 * Requests from other threads.
3017 */
3018 if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3019 {
3020 rc2 = VMR3ReqProcessU(pVM->pUVM);
3021 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE)
3022 {
3023 Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3024 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3025 return rc2;
3026 }
3027 UPDATE_RC();
3028 }
3029
3030 /* Replay the handler notification changes. */
3031 if (VM_FF_ISSET(pVM, VM_FF_REM_HANDLER_NOTIFY))
3032 REMR3ReplayHandlerNotifications(pVM);
3033
3034 /* check that we got them all */
3035 Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY)));
3036 }
3037
3038 /*
3039 * Execute polling function ever so often.
3040 * THIS IS A HACK, IT WILL BE *REPLACED* BY PROPER ASYNC NETWORKING SOON!
3041 */
3042 static unsigned cLast = 0;
3043 if (!((++cLast) % 4))
3044 PDMR3Poll(pVM);
3045
3046 /*
3047 * High priority pre execution chunk last.
3048 * (Executed in ascending priority order.)
3049 */
3050 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3051 {
3052 /*
3053 * Timers before interrupts.
3054 */
3055 if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3056 TMR3TimerQueuesDo(pVM);
3057
3058 /*
3059 * The instruction following an emulated STI should *always* be executed!
3060 */
3061 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3062 {
3063 Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", (RTGCPTR)CPUMGetGuestRIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3064 if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3065 {
3066 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3067 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3068 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3069 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3070 */
3071 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3072 }
3073 if (HWACCMR3IsActive(pVM))
3074 rc2 = VINF_EM_RESCHEDULE_HWACC;
3075 else
3076 rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3077
3078 UPDATE_RC();
3079 }
3080
3081 /*
3082 * Interrupts.
3083 */
3084 if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3085 && (!rc || rc >= VINF_EM_RESCHEDULE_RAW)
3086 && !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3087 && PATMAreInterruptsEnabled(pVM)
3088 && !HWACCMR3IsEventPending(pVM))
3089 {
3090 if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
3091 {
3092 /** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3093 /** @todo this really isn't nice, should properly handle this */
3094 rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3095#ifdef VBOX_STRICT
3096 rcIrq = rc2;
3097#endif
3098 UPDATE_RC();
3099 }
3100 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3101 else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3102 {
3103 rc2 = VINF_EM_RESCHEDULE_REM;
3104 UPDATE_RC();
3105 }
3106 }
3107
3108 /*
3109 * Allocate handy pages.
3110 */
3111 if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
3112 {
3113 rc2 = PGMR3PhysAllocateHandyPages(pVM);
3114 UPDATE_RC();
3115 }
3116
3117 /*
3118 * Debugger Facility request.
3119 */
3120 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3121 {
3122 rc2 = DBGFR3VMMForcedAction(pVM);
3123 UPDATE_RC();
3124 }
3125
3126 /*
3127 * Termination request.
3128 */
3129 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3130 {
3131 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3132 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3133 return VINF_EM_TERMINATE;
3134 }
3135
3136#ifdef DEBUG
3137 /*
3138 * Debug, pause the VM.
3139 */
3140 if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3141 {
3142 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3143 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3144 return VINF_EM_SUSPEND;
3145 }
3146
3147#endif
3148 /* check that we got them all */
3149 Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER | VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC | VM_FF_DBGF | VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_SELM_SYNC_TSS | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TERMINATE | VM_FF_DEBUG_SUSPEND | VM_FF_INHIBIT_INTERRUPTS | VM_FF_PGM_NEED_HANDY_PAGES)));
3150 }
3151
3152#undef UPDATE_RC
3153 Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3154 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3155 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
3156 return rc;
3157}
3158
3159
3160/**
3161 * Execute VM.
3162 *
3163 * This function is the main loop of the VM. The emulation thread
3164 * calls this function when the VM has been successfully constructed
3165 * and we're ready for executing the VM.
3166 *
3167 * Returning from this function means that the VM is turned off or
3168 * suspended (state already saved) and deconstruction in next in line.
3169 *
3170 * All interaction from other thread are done using forced actions
3171 * and signaling of the wait object.
3172 *
3173 * @returns VBox status code.
3174 * @param pVM The VM to operate on.
3175 */
3176EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3177{
3178 LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3179 pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3180 VM_ASSERT_EMT(pVM);
3181 Assert(pVM->em.s.enmState == EMSTATE_NONE || pVM->em.s.enmState == EMSTATE_SUSPENDED);
3182
3183 VMMR3Lock(pVM);
3184
3185 int rc = setjmp(pVM->em.s.u.FatalLongJump);
3186 if (rc == 0)
3187 {
3188 /*
3189 * Start the virtual time.
3190 */
3191 rc = TMVirtualResume(pVM);
3192 Assert(rc == VINF_SUCCESS);
3193 rc = TMCpuTickResume(pVM);
3194 Assert(rc == VINF_SUCCESS);
3195
3196 /*
3197 * The Outer Main Loop.
3198 */
3199 bool fFFDone = false;
3200 rc = VINF_EM_RESCHEDULE;
3201 pVM->em.s.enmState = EMSTATE_REM;
3202 STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3203 for (;;)
3204 {
3205 /*
3206 * Before we can schedule anything (we're here because
3207 * scheduling is required) we must service any pending
3208 * forced actions to avoid any pending action causing
3209 * immidate rescheduling upon entering an inner loop
3210 *
3211 * Do forced actions.
3212 */
3213 if ( !fFFDone
3214 && rc != VINF_EM_TERMINATE
3215 && rc != VINF_EM_OFF
3216 && VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3217 {
3218 rc = emR3ForcedActions(pVM, rc);
3219 if ( ( rc == VINF_EM_RESCHEDULE_REM
3220 || rc == VINF_EM_RESCHEDULE_HWACC)
3221 && pVM->em.s.fForceRAW)
3222 rc = VINF_EM_RESCHEDULE_RAW;
3223 }
3224 else if (fFFDone)
3225 fFFDone = false;
3226
3227 /*
3228 * Now what to do?
3229 */
3230 Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3231 switch (rc)
3232 {
3233 /*
3234 * Keep doing what we're currently doing.
3235 */
3236 case VINF_SUCCESS:
3237 break;
3238
3239 /*
3240 * Reschedule - to raw-mode execution.
3241 */
3242 case VINF_EM_RESCHEDULE_RAW:
3243 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3244 pVM->em.s.enmState = EMSTATE_RAW;
3245 break;
3246
3247 /*
3248 * Reschedule - to hardware accelerated raw-mode execution.
3249 */
3250 case VINF_EM_RESCHEDULE_HWACC:
3251 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3252 Assert(!pVM->em.s.fForceRAW);
3253 pVM->em.s.enmState = EMSTATE_HWACC;
3254 break;
3255
3256 /*
3257 * Reschedule - to recompiled execution.
3258 */
3259 case VINF_EM_RESCHEDULE_REM:
3260 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3261 pVM->em.s.enmState = EMSTATE_REM;
3262 break;
3263
3264 /*
3265 * Resume.
3266 */
3267 case VINF_EM_RESUME:
3268 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3269 /* fall through and get scheduled. */
3270
3271 /*
3272 * Reschedule.
3273 */
3274 case VINF_EM_RESCHEDULE:
3275 {
3276 EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3277 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3278 pVM->em.s.enmState = enmState;
3279 break;
3280 }
3281
3282 /*
3283 * Halted.
3284 */
3285 case VINF_EM_HALT:
3286 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3287 pVM->em.s.enmState = EMSTATE_HALTED;
3288 break;
3289
3290 /*
3291 * Suspend.
3292 */
3293 case VINF_EM_SUSPEND:
3294 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3295 pVM->em.s.enmState = EMSTATE_SUSPENDED;
3296 break;
3297
3298 /*
3299 * Reset.
3300 * We might end up doing a double reset for now, we'll have to clean up the mess later.
3301 */
3302 case VINF_EM_RESET:
3303 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3304 pVM->em.s.enmState = EMSTATE_REM;
3305 break;
3306
3307 /*
3308 * Power Off.
3309 */
3310 case VINF_EM_OFF:
3311 pVM->em.s.enmState = EMSTATE_TERMINATING;
3312 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3313 TMVirtualPause(pVM);
3314 TMCpuTickPause(pVM);
3315 VMMR3Unlock(pVM);
3316 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3317 return rc;
3318
3319 /*
3320 * Terminate the VM.
3321 */
3322 case VINF_EM_TERMINATE:
3323 pVM->em.s.enmState = EMSTATE_TERMINATING;
3324 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3325 TMVirtualPause(pVM);
3326 TMCpuTickPause(pVM);
3327 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3328 return rc;
3329
3330 /*
3331 * Guest debug events.
3332 */
3333 case VINF_EM_DBG_STEPPED:
3334 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3335 case VINF_EM_DBG_STOP:
3336 case VINF_EM_DBG_BREAKPOINT:
3337 case VINF_EM_DBG_STEP:
3338 if (pVM->em.s.enmState == EMSTATE_RAW)
3339 {
3340 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3341 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3342 }
3343 else
3344 {
3345 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3346 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3347 }
3348 break;
3349
3350 /*
3351 * Hypervisor debug events.
3352 */
3353 case VINF_EM_DBG_HYPER_STEPPED:
3354 case VINF_EM_DBG_HYPER_BREAKPOINT:
3355 case VINF_EM_DBG_HYPER_ASSERTION:
3356 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3357 pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3358 break;
3359
3360 /*
3361 * Any error code showing up here other than the ones we
3362 * know and process above are considered to be FATAL.
3363 *
3364 * Unknown warnings and informational status codes are also
3365 * included in this.
3366 */
3367 default:
3368 if (VBOX_SUCCESS(rc))
3369 {
3370 AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3371 rc = VERR_EM_INTERNAL_ERROR;
3372 }
3373 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3374 Log(("EMR3ExecuteVM returns %d\n", rc));
3375 break;
3376 }
3377
3378
3379 /*
3380 * Any waiters can now be woken up
3381 */
3382 VMMR3Unlock(pVM);
3383 VMMR3Lock(pVM);
3384
3385 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3386 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3387
3388 /*
3389 * Act on the state.
3390 */
3391 switch (pVM->em.s.enmState)
3392 {
3393 /*
3394 * Execute raw.
3395 */
3396 case EMSTATE_RAW:
3397 rc = emR3RawExecute(pVM, &fFFDone);
3398 break;
3399
3400 /*
3401 * Execute hardware accelerated raw.
3402 */
3403 case EMSTATE_HWACC:
3404 rc = emR3HwAccExecute(pVM, &fFFDone);
3405 break;
3406
3407 /*
3408 * Execute recompiled.
3409 */
3410 case EMSTATE_REM:
3411 rc = emR3RemExecute(pVM, &fFFDone);
3412 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3413 break;
3414
3415 /*
3416 * hlt - execution halted until interrupt.
3417 */
3418 case EMSTATE_HALTED:
3419 {
3420 STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3421 rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3422 STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3423 break;
3424 }
3425
3426 /*
3427 * Suspended - return to VM.cpp.
3428 */
3429 case EMSTATE_SUSPENDED:
3430 TMVirtualPause(pVM);
3431 TMCpuTickPause(pVM);
3432 VMMR3Unlock(pVM);
3433 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3434 return VINF_EM_SUSPEND;
3435
3436 /*
3437 * Debugging in the guest.
3438 */
3439 case EMSTATE_DEBUG_GUEST_REM:
3440 case EMSTATE_DEBUG_GUEST_RAW:
3441 TMVirtualPause(pVM);
3442 TMCpuTickPause(pVM);
3443 rc = emR3Debug(pVM, rc);
3444 TMVirtualResume(pVM);
3445 TMCpuTickResume(pVM);
3446 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3447 break;
3448
3449 /*
3450 * Debugging in the hypervisor.
3451 */
3452 case EMSTATE_DEBUG_HYPER:
3453 {
3454 TMVirtualPause(pVM);
3455 TMCpuTickPause(pVM);
3456 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3457
3458 rc = emR3Debug(pVM, rc);
3459 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3460 if (rc != VINF_SUCCESS)
3461 {
3462 /* switch to guru meditation mode */
3463 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3464 VMMR3FatalDump(pVM, rc);
3465 return rc;
3466 }
3467
3468 STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3469 TMVirtualResume(pVM);
3470 TMCpuTickResume(pVM);
3471 break;
3472 }
3473
3474 /*
3475 * Guru meditation takes place in the debugger.
3476 */
3477 case EMSTATE_GURU_MEDITATION:
3478 {
3479 TMVirtualPause(pVM);
3480 TMCpuTickPause(pVM);
3481 VMMR3FatalDump(pVM, rc);
3482 emR3Debug(pVM, rc);
3483 VMMR3Unlock(pVM);
3484 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3485 return rc;
3486 }
3487
3488 /*
3489 * The states we don't expect here.
3490 */
3491 case EMSTATE_NONE:
3492 case EMSTATE_TERMINATING:
3493 default:
3494 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3495 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3496 TMVirtualPause(pVM);
3497 TMCpuTickPause(pVM);
3498 VMMR3Unlock(pVM);
3499 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3500 return VERR_EM_INTERNAL_ERROR;
3501 }
3502 } /* The Outer Main Loop */
3503 }
3504 else
3505 {
3506 /*
3507 * Fatal error.
3508 */
3509 LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3510 TMVirtualPause(pVM);
3511 TMCpuTickPause(pVM);
3512 VMMR3FatalDump(pVM, rc);
3513 emR3Debug(pVM, rc);
3514 VMMR3Unlock(pVM);
3515 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3516 /** @todo change the VM state! */
3517 return rc;
3518 }
3519
3520 /* (won't ever get here). */
3521 AssertFailed();
3522}
3523
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