EM.cpp@ 13089

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1	/* $Id: EM.cpp 13005 2008-10-06 12:35:21Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_em EM - The Execution Monitor / Manager
23	*
24	* The Execution Monitor/Manager is responsible for running the VM, scheduling
25	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26	* Interpreted), and keeping the CPU states in sync. The function
27	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29	* emR3RemExecute).
30	*
31	* The interpreted execution is only used to avoid switching between
32	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33	* The interpretation is thus implemented as part of EM.
34	*
35	* @see grp_em
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_EM
42	#include <VBox/em.h>
43	#include <VBox/vmm.h>
44	#include <VBox/patm.h>
45	#include <VBox/csam.h>
46	#include <VBox/selm.h>
47	#include <VBox/trpm.h>
48	#include <VBox/iom.h>
49	#include <VBox/dbgf.h>
50	#include <VBox/pgm.h>
51	#include <VBox/rem.h>
52	#include <VBox/tm.h>
53	#include <VBox/mm.h>
54	#include <VBox/ssm.h>
55	#include <VBox/pdmapi.h>
56	#include <VBox/pdmcritsect.h>
57	#include <VBox/pdmqueue.h>
58	#include <VBox/hwaccm.h>
59	#include <VBox/patm.h>
60	#include "EMInternal.h"
61	#include <VBox/vm.h>
62	#include <VBox/cpumdis.h>
63	#include <VBox/dis.h>
64	#include <VBox/disopcode.h>
65	#include <VBox/dbgf.h>
66
67	#include <VBox/log.h>
68	#include <iprt/thread.h>
69	#include <iprt/assert.h>
70	#include <iprt/asm.h>
71	#include <iprt/semaphore.h>
72	#include <iprt/string.h>
73	#include <iprt/avl.h>
74	#include <iprt/stream.h>
75	#include <VBox/param.h>
76	#include <VBox/err.h>
77
78
79	/*******************************************************************************
80	* Internal Functions *
81	*******************************************************************************/
82	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
83	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
84	static int emR3Debug(PVM pVM, int rc);
85	static int emR3RemStep(PVM pVM);
86	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
87	static int emR3RawResumeHyper(PVM pVM);
88	static int emR3RawStep(PVM pVM);
89	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
90	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
91	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
92	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
93	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
94	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
95	static int emR3ForcedActions(PVM pVM, int rc);
96	static int emR3RawGuestTrap(PVM pVM);
97
98
99	/**
100	* Initializes the EM.
101	*
102	* @returns VBox status code.
103	* @param pVM The VM to operate on.
104	*/
105	VMMR3DECL(int) EMR3Init(PVM pVM)
106	{
107	LogFlow(("EMR3Init\n"));
108	/*
109	* Assert alignment and sizes.
110	*/
111	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
112	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
113	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
114	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
115
116	/*
117	* Init the structure.
118	*/
119	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
120	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
121	if (VBOX_FAILURE(rc))
122	pVM->fRawR3Enabled = true;
123	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
124	if (VBOX_FAILURE(rc))
125	pVM->fRawR0Enabled = true;
126	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
127	pVM->em.s.enmState = EMSTATE_NONE;
128	pVM->em.s.fForceRAW = false;
129
130	rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
131	AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
132	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
133	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
134
135	/*
136	* Saved state.
137	*/
138	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
139	NULL, emR3Save, NULL,
140	NULL, emR3Load, NULL);
141	if (VBOX_FAILURE(rc))
142	return rc;
143
144	/*
145	* Statistics.
146	*/
147	#ifdef VBOX_WITH_STATISTICS
148	PEMSTATS pStats;
149	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
150	if (VBOX_FAILURE(rc))
151	return rc;
152	pVM->em.s.pStatsR3 = pStats;
153	pVM->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
154	pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
155
156	STAM_REG(pVM, &pStats->StatRZEmulate, STAMTYPE_PROFILE, "/EM/RZ/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
157	STAM_REG(pVM, &pStats->StatR3Emulate, STAMTYPE_PROFILE, "/EM/R3/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
158
159	STAM_REG(pVM, &pStats->StatRZInterpretSucceeded, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
160	STAM_REG(pVM, &pStats->StatR3InterpretSucceeded, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
161
162	STAM_REG_USED(pVM, &pStats->StatRZAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
163	STAM_REG_USED(pVM, &pStats->StatR3And, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
164	STAM_REG_USED(pVM, &pStats->StatRZAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
165	STAM_REG_USED(pVM, &pStats->StatR3Add, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatRZAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatR3Adc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatRZSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatR3Sub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatRZCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatR3CpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatRZDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatR3Dec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatRZHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatR3Hlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatRZInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatR3Inc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatRZInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatR3InvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatRZIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatR3Iret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatRZLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatR3LLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatRZLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatR3LIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatRZLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatR3LGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatRZMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatR3Mov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatRZMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatR3MovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatRZMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatR3MovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatRZOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatR3Or, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
196	STAM_REG_USED(pVM, &pStats->StatRZPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
197	STAM_REG_USED(pVM, &pStats->StatR3Pop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatRZRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatR3Rdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatRZSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatR3Sti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatRZXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatR3Xchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
204	STAM_REG_USED(pVM, &pStats->StatRZXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
205	STAM_REG_USED(pVM, &pStats->StatR3Xor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
206	STAM_REG_USED(pVM, &pStats->StatRZMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
207	STAM_REG_USED(pVM, &pStats->StatR3Monitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
208	STAM_REG_USED(pVM, &pStats->StatRZMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatR3MWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatRZBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatR3Btr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatRZBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatR3Bts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatRZBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatR3Btc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatRZCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatR3CmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatRZCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatR3CmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatRZXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatR3XAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatR3Rdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatRZRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatR3Wrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatRZWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatR3StosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatRZStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
228
229	STAM_REG(pVM, &pStats->StatRZInterpretFailed, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
230	STAM_REG(pVM, &pStats->StatR3InterpretFailed, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
231
232	STAM_REG_USED(pVM, &pStats->StatRZFailedAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatR3FailedAnd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatRZFailedCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatR3FailedCpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatRZFailedDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
237	STAM_REG_USED(pVM, &pStats->StatR3FailedDec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
238	STAM_REG_USED(pVM, &pStats->StatRZFailedHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
239	STAM_REG_USED(pVM, &pStats->StatR3FailedHlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatRZFailedInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatR3FailedInc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatRZFailedInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatR3FailedInvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatRZFailedIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatR3FailedIret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
246	STAM_REG_USED(pVM, &pStats->StatRZFailedLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
247	STAM_REG_USED(pVM, &pStats->StatR3FailedLLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
248	STAM_REG_USED(pVM, &pStats->StatRZFailedLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
249	STAM_REG_USED(pVM, &pStats->StatR3FailedLIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatRZFailedLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatR3FailedLGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatRZFailedMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatR3FailedMov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatRZFailedMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatR3FailedMovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatRZFailedMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatR3FailedMovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatRZFailedOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatR3FailedOr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatRZFailedPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
261	STAM_REG_USED(pVM, &pStats->StatR3FailedPop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
262	STAM_REG_USED(pVM, &pStats->StatRZFailedSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
263	STAM_REG_USED(pVM, &pStats->StatR3FailedSti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
264	STAM_REG_USED(pVM, &pStats->StatRZFailedXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
265	STAM_REG_USED(pVM, &pStats->StatR3FailedXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
266	STAM_REG_USED(pVM, &pStats->StatRZFailedXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
267	STAM_REG_USED(pVM, &pStats->StatR3FailedXor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
268	STAM_REG_USED(pVM, &pStats->StatRZFailedMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
269	STAM_REG_USED(pVM, &pStats->StatR3FailedMonitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
270	STAM_REG_USED(pVM, &pStats->StatRZFailedMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
271	STAM_REG_USED(pVM, &pStats->StatR3FailedMWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
272	STAM_REG_USED(pVM, &pStats->StatRZFailedRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
273	STAM_REG_USED(pVM, &pStats->StatR3FailedRdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
274	STAM_REG_USED(pVM, &pStats->StatRZFailedRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
275	STAM_REG_USED(pVM, &pStats->StatR3FailedRdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
276	STAM_REG_USED(pVM, &pStats->StatRZFailedWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
277	STAM_REG_USED(pVM, &pStats->StatR3FailedWrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
278
279	STAM_REG_USED(pVM, &pStats->StatRZFailedMisc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
280	STAM_REG_USED(pVM, &pStats->StatR3FailedMisc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
281	STAM_REG_USED(pVM, &pStats->StatRZFailedAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
282	STAM_REG_USED(pVM, &pStats->StatR3FailedAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
283	STAM_REG_USED(pVM, &pStats->StatRZFailedAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
284	STAM_REG_USED(pVM, &pStats->StatR3FailedAdc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
285	STAM_REG_USED(pVM, &pStats->StatRZFailedBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
286	STAM_REG_USED(pVM, &pStats->StatR3FailedBtr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
287	STAM_REG_USED(pVM, &pStats->StatRZFailedBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
288	STAM_REG_USED(pVM, &pStats->StatR3FailedBts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
289	STAM_REG_USED(pVM, &pStats->StatRZFailedBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
290	STAM_REG_USED(pVM, &pStats->StatR3FailedBtc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
291	STAM_REG_USED(pVM, &pStats->StatRZFailedCli, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
292	STAM_REG_USED(pVM, &pStats->StatR3FailedCli, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
293	STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
294	STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
295	STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
296	STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
297	STAM_REG_USED(pVM, &pStats->StatRZFailedXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
298	STAM_REG_USED(pVM, &pStats->StatR3FailedXAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
299	STAM_REG_USED(pVM, &pStats->StatRZFailedMovNTPS, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
300	STAM_REG_USED(pVM, &pStats->StatR3FailedMovNTPS, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
301	STAM_REG_USED(pVM, &pStats->StatRZFailedStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
302	STAM_REG_USED(pVM, &pStats->StatR3FailedStosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
303	STAM_REG_USED(pVM, &pStats->StatRZFailedSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
304	STAM_REG_USED(pVM, &pStats->StatR3FailedSub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
305	STAM_REG_USED(pVM, &pStats->StatRZFailedWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
306	STAM_REG_USED(pVM, &pStats->StatR3FailedWbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
307
308	STAM_REG_USED(pVM, &pStats->StatRZFailedUserMode, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
309	STAM_REG_USED(pVM, &pStats->StatR3FailedUserMode, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
310	STAM_REG_USED(pVM, &pStats->StatRZFailedPrefix, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
311	STAM_REG_USED(pVM, &pStats->StatR3FailedPrefix, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
312
313	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
314	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
315	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/R3/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
316	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
317	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
318	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
319	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
320	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
321	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
322	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
323	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
324	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
325	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
326	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
327	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
328	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
329	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
330	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/R3/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
331	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
332	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
333	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
334	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
335	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
336	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
337	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
338	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
339
340	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
341	pVM->em.s.pCliStatTree = 0;
342	#endif /* VBOX_WITH_STATISTICS */
343
344	/* these should be considered for release statistics. */
345	STAM_REL_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
346	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
347	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
348	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
349
350	STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
351	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
352	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
353	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
354	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
355	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
356	STAM_REL_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
357	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
358	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
359	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
360	STAM_REL_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
361	STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
362
363
364	return VINF_SUCCESS;
365	}
366
367
368	/**
369	* Applies relocations to data and code managed by this
370	* component. This function will be called at init and
371	* whenever the VMM need to relocate it self inside the GC.
372	*
373	* @param pVM The VM.
374	*/
375	VMMR3DECL(void) EMR3Relocate(PVM pVM)
376	{
377	LogFlow(("EMR3Relocate\n"));
378	if (pVM->em.s.pStatsR3)
379	pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVM->em.s.pStatsR3);
380	}
381
382
383	/**
384	* Reset notification.
385	*
386	* @param pVM
387	*/
388	VMMR3DECL(void) EMR3Reset(PVM pVM)
389	{
390	LogFlow(("EMR3Reset: \n"));
391	pVM->em.s.fForceRAW = false;
392	}
393
394
395	/**
396	* Terminates the EM.
397	*
398	* Termination means cleaning up and freeing all resources,
399	* the VM it self is at this point powered off or suspended.
400	*
401	* @returns VBox status code.
402	* @param pVM The VM to operate on.
403	*/
404	VMMR3DECL(int) EMR3Term(PVM pVM)
405	{
406	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
407
408	return VINF_SUCCESS;
409	}
410
411
412	/**
413	* Execute state save operation.
414	*
415	* @returns VBox status code.
416	* @param pVM VM Handle.
417	* @param pSSM SSM operation handle.
418	*/
419	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
420	{
421	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
422	}
423
424
425	/**
426	* Execute state load operation.
427	*
428	* @returns VBox status code.
429	* @param pVM VM Handle.
430	* @param pSSM SSM operation handle.
431	* @param u32Version Data layout version.
432	*/
433	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
434	{
435	/*
436	* Validate version.
437	*/
438	if (u32Version != EM_SAVED_STATE_VERSION)
439	{
440	AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
441	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
442	}
443
444	/*
445	* Load the saved state.
446	*/
447	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
448	if (VBOX_FAILURE(rc))
449	pVM->em.s.fForceRAW = false;
450
451	Assert(!pVM->em.s.pCliStatTree);
452	return rc;
453	}
454
455
456	/**
457	* Enables or disables a set of raw-mode execution modes.
458	*
459	* @returns VINF_SUCCESS on success.
460	* @returns VINF_RESCHEDULE if a rescheduling might be required.
461	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
462	*
463	* @param pVM The VM to operate on.
464	* @param enmMode The execution mode change.
465	* @thread The emulation thread.
466	*/
467	VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
468	{
469	switch (enmMode)
470	{
471	case EMRAW_NONE:
472	pVM->fRawR3Enabled = false;
473	pVM->fRawR0Enabled = false;
474	break;
475	case EMRAW_RING3_ENABLE:
476	pVM->fRawR3Enabled = true;
477	break;
478	case EMRAW_RING3_DISABLE:
479	pVM->fRawR3Enabled = false;
480	break;
481	case EMRAW_RING0_ENABLE:
482	pVM->fRawR0Enabled = true;
483	break;
484	case EMRAW_RING0_DISABLE:
485	pVM->fRawR0Enabled = false;
486	break;
487	default:
488	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
489	return VERR_INVALID_PARAMETER;
490	}
491	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
492	pVM->fRawR3Enabled, pVM->fRawR0Enabled));
493	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
494	}
495
496
497	/**
498	* Raise a fatal error.
499	*
500	* Safely terminate the VM with full state report and stuff. This function
501	* will naturally never return.
502	*
503	* @param pVM VM handle.
504	* @param rc VBox status code.
505	*/
506	VMMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
507	{
508	longjmp(pVM->em.s.u.FatalLongJump, rc);
509	AssertReleaseMsgFailed(("longjmp returned!\n"));
510	}
511
512
513	/**
514	* Gets the EM state name.
515	*
516	* @returns pointer to read only state name,
517	* @param enmState The state.
518	*/
519	VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
520	{
521	switch (enmState)
522	{
523	case EMSTATE_NONE: return "EMSTATE_NONE";
524	case EMSTATE_RAW: return "EMSTATE_RAW";
525	case EMSTATE_HWACC: return "EMSTATE_HWACC";
526	case EMSTATE_REM: return "EMSTATE_REM";
527	case EMSTATE_HALTED: return "EMSTATE_HALTED";
528	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
529	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
530	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
531	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
532	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
533	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
534	default: return "Unknown!";
535	}
536	}
537
538
539	#ifdef VBOX_WITH_STATISTICS
540	/**
541	* Just a braindead function to keep track of cli addresses.
542	* @param pVM VM handle.
543	* @param pInstrGC The EIP of the cli instruction.
544	*/
545	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
546	{
547	PCLISTAT pRec;
548
549	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
550	if (!pRec)
551	{
552	/* New cli instruction; insert into the tree. */
553	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
554	Assert(pRec);
555	if (!pRec)
556	return;
557	pRec->Core.Key = (AVLPVKEY)pInstrGC;
558
559	char szCliStatName[32];
560	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
561	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
562
563	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
564	Assert(fRc); NOREF(fRc);
565	}
566	STAM_COUNTER_INC(&pRec->Counter);
567	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
568	}
569	#endif /* VBOX_WITH_STATISTICS */
570
571
572	/**
573	* Debug loop.
574	*
575	* @returns VBox status code for EM.
576	* @param pVM VM handle.
577	* @param rc Current EM VBox status code..
578	*/
579	static int emR3Debug(PVM pVM, int rc)
580	{
581	for (;;)
582	{
583	Log(("emR3Debug: rc=%Vrc\n", rc));
584	const int rcLast = rc;
585
586	/*
587	* Debug related RC.
588	*/
589	switch (rc)
590	{
591	/*
592	* Single step an instruction.
593	*/
594	case VINF_EM_DBG_STEP:
595	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
596	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
597	\|\| pVM->em.s.fForceRAW /* paranoia */)
598	rc = emR3RawStep(pVM);
599	else
600	{
601	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
602	rc = emR3RemStep(pVM);
603	}
604	break;
605
606	/*
607	* Simple events: stepped, breakpoint, stop/assertion.
608	*/
609	case VINF_EM_DBG_STEPPED:
610	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
611	break;
612
613	case VINF_EM_DBG_BREAKPOINT:
614	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
615	break;
616
617	case VINF_EM_DBG_STOP:
618	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
619	break;
620
621	case VINF_EM_DBG_HYPER_STEPPED:
622	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
623	break;
624
625	case VINF_EM_DBG_HYPER_BREAKPOINT:
626	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
627	break;
628
629	case VINF_EM_DBG_HYPER_ASSERTION:
630	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
631	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
632	break;
633
634	/*
635	* Guru meditation.
636	*/
637	case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
638	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
639	break;
640
641	default: /** @todo don't use default for guru, but make special errors code! */
642	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
643	break;
644	}
645
646	/*
647	* Process the result.
648	*/
649	do
650	{
651	switch (rc)
652	{
653	/*
654	* Continue the debugging loop.
655	*/
656	case VINF_EM_DBG_STEP:
657	case VINF_EM_DBG_STOP:
658	case VINF_EM_DBG_STEPPED:
659	case VINF_EM_DBG_BREAKPOINT:
660	case VINF_EM_DBG_HYPER_STEPPED:
661	case VINF_EM_DBG_HYPER_BREAKPOINT:
662	case VINF_EM_DBG_HYPER_ASSERTION:
663	break;
664
665	/*
666	* Resuming execution (in some form) has to be done here if we got
667	* a hypervisor debug event.
668	*/
669	case VINF_SUCCESS:
670	case VINF_EM_RESUME:
671	case VINF_EM_SUSPEND:
672	case VINF_EM_RESCHEDULE:
673	case VINF_EM_RESCHEDULE_RAW:
674	case VINF_EM_RESCHEDULE_REM:
675	case VINF_EM_HALT:
676	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
677	{
678	rc = emR3RawResumeHyper(pVM);
679	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
680	continue;
681	}
682	if (rc == VINF_SUCCESS)
683	rc = VINF_EM_RESCHEDULE;
684	return rc;
685
686	/*
687	* The debugger isn't attached.
688	* We'll simply turn the thing off since that's the easiest thing to do.
689	*/
690	case VERR_DBGF_NOT_ATTACHED:
691	switch (rcLast)
692	{
693	case VINF_EM_DBG_HYPER_ASSERTION:
694	case VINF_EM_DBG_HYPER_STEPPED:
695	case VINF_EM_DBG_HYPER_BREAKPOINT:
696	return rcLast;
697	}
698	return VINF_EM_OFF;
699
700	/*
701	* Status codes terminating the VM in one or another sense.
702	*/
703	case VINF_EM_TERMINATE:
704	case VINF_EM_OFF:
705	case VINF_EM_RESET:
706	case VINF_EM_RAW_STALE_SELECTOR:
707	case VINF_EM_RAW_IRET_TRAP:
708	case VERR_TRPM_PANIC:
709	case VERR_TRPM_DONT_PANIC:
710	case VERR_INTERNAL_ERROR:
711	return rc;
712
713	/*
714	* The rest is unexpected, and will keep us here.
715	*/
716	default:
717	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
718	break;
719	}
720	} while (false);
721	} /* debug for ever */
722	}
723
724
725	/**
726	* Steps recompiled code.
727	*
728	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
729	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
730	*
731	* @param pVM VM handle.
732	*/
733	static int emR3RemStep(PVM pVM)
734	{
735	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
736
737	/*
738	* Switch to REM, step instruction, switch back.
739	*/
740	int rc = REMR3State(pVM, pVM->em.s.fREMFlushTBs);
741	if (VBOX_SUCCESS(rc))
742	{
743	rc = REMR3Step(pVM);
744	REMR3StateBack(pVM);
745	pVM->em.s.fREMFlushTBs = false;
746	}
747	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
748	return rc;
749	}
750
751
752	/**
753	* Executes recompiled code.
754	*
755	* This function contains the recompiler version of the inner
756	* execution loop (the outer loop being in EMR3ExecuteVM()).
757	*
758	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
759	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
760	*
761	* @param pVM VM handle.
762	* @param pfFFDone Where to store an indicator telling wheter or not
763	* FFs were done before returning.
764	*
765	*/
766	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
767	{
768	#ifdef LOG_ENABLED
769	PCPUMCTX pCtx = pVM->em.s.pCtx;
770	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
771
772	if (pCtx->eflags.Bits.u1VM)
773	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
774	else
775	Log(("EMR%d: %08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
776	#endif
777	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
778
779	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
780	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
781	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
782	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
783	#endif
784
785	/*
786	* Spin till we get a forced action which returns anything but VINF_SUCCESS
787	* or the REM suggests raw-mode execution.
788	*/
789	*pfFFDone = false;
790	bool fInREMState = false;
791	int rc = VINF_SUCCESS;
792	for (;;)
793	{
794	/*
795	* Update REM state if not already in sync.
796	*/
797	if (!fInREMState)
798	{
799	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
800	rc = REMR3State(pVM, pVM->em.s.fREMFlushTBs);
801	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
802	if (VBOX_FAILURE(rc))
803	break;
804	fInREMState = true;
805	pVM->em.s.fREMFlushTBs = false;
806
807	/*
808	* We might have missed the raising of VMREQ, TIMER and some other
809	* imporant FFs while we were busy switching the state. So, check again.
810	*/
811	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
812	{
813	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
814	goto l_REMDoForcedActions;
815	}
816	}
817
818
819	/*
820	* Execute REM.
821	*/
822	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
823	rc = REMR3Run(pVM);
824	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
825
826
827	/*
828	* Deal with high priority post execution FFs before doing anything else.
829	*/
830	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
831	rc = emR3HighPriorityPostForcedActions(pVM, rc);
832
833	/*
834	* Process the returned status code.
835	* (Try keep this short! Call functions!)
836	*/
837	if (rc != VINF_SUCCESS)
838	{
839	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
840	break;
841	if (rc != VINF_REM_INTERRUPED_FF)
842	{
843	/*
844	* Anything which is not known to us means an internal error
845	* and the termination of the VM!
846	*/
847	AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Vra\n", rc));
848	break;
849	}
850	}
851
852
853	/*
854	* Check and execute forced actions.
855	* Sync back the VM state before calling any of these.
856	*/
857	#ifdef VBOX_HIGH_RES_TIMERS_HACK
858	TMTimerPoll(pVM);
859	#endif
860	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
861	{
862	l_REMDoForcedActions:
863	if (fInREMState)
864	{
865	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
866	REMR3StateBack(pVM);
867	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
868	fInREMState = false;
869	}
870	STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
871	rc = emR3ForcedActions(pVM, rc);
872	STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
873	if ( rc != VINF_SUCCESS
874	&& rc != VINF_EM_RESCHEDULE_REM)
875	{
876	*pfFFDone = true;
877	break;
878	}
879	}
880
881	} /* The Inner Loop, recompiled execution mode version. */
882
883
884	/*
885	* Returning. Sync back the VM state if required.
886	*/
887	if (fInREMState)
888	{
889	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
890	REMR3StateBack(pVM);
891	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
892	}
893
894	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
895	return rc;
896	}
897
898
899	/**
900	* Resumes executing hypervisor after a debug event.
901	*
902	* This is kind of special since our current guest state is
903	* potentially out of sync.
904	*
905	* @returns VBox status code.
906	* @param pVM The VM handle.
907	*/
908	static int emR3RawResumeHyper(PVM pVM)
909	{
910	int rc;
911	PCPUMCTX pCtx = pVM->em.s.pCtx;
912	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
913	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
914
915	/*
916	* Resume execution.
917	*/
918	CPUMRawEnter(pVM, NULL);
919	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
920	rc = VMMR3ResumeHyper(pVM);
921	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
922	rc = CPUMRawLeave(pVM, NULL, rc);
923	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
924
925	/*
926	* Deal with the return code.
927	*/
928	rc = emR3HighPriorityPostForcedActions(pVM, rc);
929	rc = emR3RawHandleRC(pVM, pCtx, rc);
930	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
931	return rc;
932	}
933
934
935	/**
936	* Steps rawmode.
937	*
938	* @returns VBox status code.
939	* @param pVM The VM handle.
940	*/
941	static int emR3RawStep(PVM pVM)
942	{
943	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
944	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
945	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
946	int rc;
947	PCPUMCTX pCtx = pVM->em.s.pCtx;
948	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
949	#ifndef DEBUG_sandervl
950	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
951	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
952	#endif
953	if (fGuest)
954	{
955	/*
956	* Check vital forced actions, but ignore pending interrupts and timers.
957	*/
958	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
959	{
960	rc = emR3RawForcedActions(pVM, pCtx);
961	if (VBOX_FAILURE(rc))
962	return rc;
963	}
964
965	/*
966	* Set flags for single stepping.
967	*/
968	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
969	}
970	else
971	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
972
973	/*
974	* Single step.
975	* We do not start time or anything, if anything we should just do a few nanoseconds.
976	*/
977	CPUMRawEnter(pVM, NULL);
978	do
979	{
980	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
981	rc = VMMR3ResumeHyper(pVM);
982	else
983	rc = VMMR3RawRunGC(pVM);
984	#ifndef DEBUG_sandervl
985	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
986	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
987	#endif
988	} while ( rc == VINF_SUCCESS
989	\|\| rc == VINF_EM_RAW_INTERRUPT);
990	rc = CPUMRawLeave(pVM, NULL, rc);
991	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
992
993	/*
994	* Make sure the trap flag is cleared.
995	* (Too bad if the guest is trying to single step too.)
996	*/
997	if (fGuest)
998	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
999	else
1000	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
1001
1002	/*
1003	* Deal with the return codes.
1004	*/
1005	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1006	rc = emR3RawHandleRC(pVM, pCtx, rc);
1007	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1008	return rc;
1009	}
1010
1011
1012	#ifdef DEBUG
1013
1014	/**
1015	* Steps hardware accelerated mode.
1016	*
1017	* @returns VBox status code.
1018	* @param pVM The VM handle.
1019	*/
1020	static int emR3HwAccStep(PVM pVM)
1021	{
1022	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1023
1024	int rc;
1025	PCPUMCTX pCtx = pVM->em.s.pCtx;
1026	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
1027
1028	/*
1029	* Check vital forced actions, but ignore pending interrupts and timers.
1030	*/
1031	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1032	{
1033	rc = emR3RawForcedActions(pVM, pCtx);
1034	if (VBOX_FAILURE(rc))
1035	return rc;
1036	}
1037	/*
1038	* Set flags for single stepping.
1039	*/
1040	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1041
1042	/*
1043	* Single step.
1044	* We do not start time or anything, if anything we should just do a few nanoseconds.
1045	*/
1046	do
1047	{
1048	rc = VMMR3HwAccRunGC(pVM);
1049	} while ( rc == VINF_SUCCESS
1050	\|\| rc == VINF_EM_RAW_INTERRUPT);
1051	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1052
1053	/*
1054	* Make sure the trap flag is cleared.
1055	* (Too bad if the guest is trying to single step too.)
1056	*/
1057	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1058
1059	/*
1060	* Deal with the return codes.
1061	*/
1062	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1063	rc = emR3RawHandleRC(pVM, pCtx, rc);
1064	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1065	return rc;
1066	}
1067
1068
1069	void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1070	{
1071	EMSTATE enmOldState = pVM->em.s.enmState;
1072
1073	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1074
1075	Log(("Single step BEGIN:\n"));
1076	for (uint32_t i = 0; i < cIterations; i++)
1077	{
1078	DBGFR3PrgStep(pVM);
1079	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1080	emR3RawStep(pVM);
1081	}
1082	Log(("Single step END:\n"));
1083	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1084	pVM->em.s.enmState = enmOldState;
1085	}
1086
1087
1088	void emR3SingleStepExecHwAcc(PVM pVM, uint32_t cIterations)
1089	{
1090	EMSTATE enmOldState = pVM->em.s.enmState;
1091
1092	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1093
1094	Log(("Single step BEGIN:\n"));
1095	for (uint32_t i = 0; i < cIterations; i++)
1096	{
1097	DBGFR3PrgStep(pVM);
1098	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1099	emR3HwAccStep(pVM);
1100	}
1101	Log(("Single step END:\n"));
1102	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1103	pVM->em.s.enmState = enmOldState;
1104	}
1105
1106
1107	void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1108	{
1109	EMSTATE enmOldState = pVM->em.s.enmState;
1110
1111	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1112
1113	Log(("Single step BEGIN:\n"));
1114	for (uint32_t i = 0; i < cIterations; i++)
1115	{
1116	DBGFR3PrgStep(pVM);
1117	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1118	emR3RemStep(pVM);
1119	}
1120	Log(("Single step END:\n"));
1121	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1122	pVM->em.s.enmState = enmOldState;
1123	}
1124
1125	#endif /* DEBUG */
1126
1127
1128	/**
1129	* Executes one (or perhaps a few more) instruction(s).
1130	*
1131	* @returns VBox status code suitable for EM.
1132	*
1133	* @param pVM VM handle.
1134	* @param rcGC GC return code
1135	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1136	* instruction and prefix the log output with this text.
1137	*/
1138	#ifdef LOG_ENABLED
1139	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1140	#else
1141	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1142	#endif
1143	{
1144	PCPUMCTX pCtx = pVM->em.s.pCtx;
1145	int rc;
1146
1147	/*
1148	*
1149	* The simple solution is to use the recompiler.
1150	* The better solution is to disassemble the current instruction and
1151	* try handle as many as possible without using REM.
1152	*
1153	*/
1154
1155	#ifdef LOG_ENABLED
1156	/*
1157	* Disassemble the instruction if requested.
1158	*/
1159	if (pszPrefix)
1160	{
1161	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1162	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1163	}
1164	#endif /* LOG_ENABLED */
1165
1166	/*
1167	* PATM is making life more interesting.
1168	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1169	* tell PATM there is a trap in this code and have it take the appropriate actions
1170	* to allow us execute the code in REM.
1171	*/
1172	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1173	{
1174	Log(("emR3RawExecuteInstruction: In patch block. eip=%VRv\n", pCtx->eip));
1175
1176	RTGCPTR pNewEip;
1177	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1178	switch (rc)
1179	{
1180	/*
1181	* It's not very useful to emulate a single instruction and then go back to raw
1182	* mode; just execute the whole block until IF is set again.
1183	*/
1184	case VINF_SUCCESS:
1185	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1186	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1187	pCtx->eip = pNewEip;
1188	Assert(pCtx->eip);
1189
1190	if (pCtx->eflags.Bits.u1IF)
1191	{
1192	/*
1193	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1194	*/
1195	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1196	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1197	}
1198	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1199	{
1200	/* special case: iret, that sets IF, detected a pending irq/event */
1201	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1202	}
1203	return VINF_EM_RESCHEDULE_REM;
1204
1205	/*
1206	* One instruction.
1207	*/
1208	case VINF_PATCH_EMULATE_INSTR:
1209	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1210	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1211	pCtx->eip = pNewEip;
1212	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1213
1214	/*
1215	* The patch was disabled, hand it to the REM.
1216	*/
1217	case VERR_PATCH_DISABLED:
1218	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1219	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1220	pCtx->eip = pNewEip;
1221	if (pCtx->eflags.Bits.u1IF)
1222	{
1223	/*
1224	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1225	*/
1226	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1227	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1228	}
1229	return VINF_EM_RESCHEDULE_REM;
1230
1231	/* Force continued patch exection; usually due to write monitored stack. */
1232	case VINF_PATCH_CONTINUE:
1233	return VINF_SUCCESS;
1234
1235	default:
1236	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1237	return VERR_INTERNAL_ERROR;
1238	}
1239	}
1240
1241	#if 0
1242	/* Try our own instruction emulator before falling back to the recompiler. */
1243	DISCPUSTATE Cpu;
1244	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1245	if (VBOX_SUCCESS(rc))
1246	{
1247	uint32_t size;
1248
1249	switch (Cpu.pCurInstr->opcode)
1250	{
1251	/* @todo we can do more now */
1252	case OP_MOV:
1253	case OP_AND:
1254	case OP_OR:
1255	case OP_XOR:
1256	case OP_POP:
1257	case OP_INC:
1258	case OP_DEC:
1259	case OP_XCHG:
1260	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1261	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1262	if (VBOX_SUCCESS(rc))
1263	{
1264	pCtx->rip += Cpu.opsize;
1265	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1266	return rc;
1267	}
1268	if (rc != VERR_EM_INTERPRETER)
1269	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1270	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1271	break;
1272	}
1273	}
1274	#endif /* 0 */
1275	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1276	rc = REMR3EmulateInstruction(pVM);
1277	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1278
1279	return rc;
1280	}
1281
1282
1283	/**
1284	* Executes one (or perhaps a few more) instruction(s).
1285	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1286	*
1287	* @returns VBox status code suitable for EM.
1288	* @param pVM VM handle.
1289	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1290	* instruction and prefix the log output with this text.
1291	* @param rcGC GC return code
1292	*/
1293	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1294	{
1295	#ifdef LOG_ENABLED
1296	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1297	#else
1298	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1299	#endif
1300	}
1301
1302	/**
1303	* Executes one (or perhaps a few more) IO instruction(s).
1304	*
1305	* @returns VBox status code suitable for EM.
1306	* @param pVM VM handle.
1307	*/
1308	int emR3RawExecuteIOInstruction(PVM pVM)
1309	{
1310	int rc;
1311	PCPUMCTX pCtx = pVM->em.s.pCtx;
1312
1313	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1314
1315	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1316	* as io instructions tend to come in packages of more than one
1317	*/
1318	DISCPUSTATE Cpu;
1319	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "IO EMU");
1320	if (VBOX_SUCCESS(rc))
1321	{
1322	rc = VINF_EM_RAW_EMULATE_INSTR;
1323
1324	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1325	{
1326	switch (Cpu.pCurInstr->opcode)
1327	{
1328	case OP_IN:
1329	{
1330	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1331	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1332	break;
1333	}
1334
1335	case OP_OUT:
1336	{
1337	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1338	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1339	break;
1340	}
1341	}
1342	}
1343	else if (Cpu.prefix & PREFIX_REP)
1344	{
1345	switch (Cpu.pCurInstr->opcode)
1346	{
1347	case OP_INSB:
1348	case OP_INSWD:
1349	{
1350	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1351	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1352	break;
1353	}
1354
1355	case OP_OUTSB:
1356	case OP_OUTSWD:
1357	{
1358	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1359	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1360	break;
1361	}
1362	}
1363	}
1364
1365	/*
1366	* Handled the I/O return codes.
1367	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1368	*/
1369	if (IOM_SUCCESS(rc))
1370	{
1371	pCtx->rip += Cpu.opsize;
1372	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1373	return rc;
1374	}
1375
1376	if (rc == VINF_EM_RAW_GUEST_TRAP)
1377	{
1378	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1379	rc = emR3RawGuestTrap(pVM);
1380	return rc;
1381	}
1382	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1383
1384	if (VBOX_FAILURE(rc))
1385	{
1386	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1387	return rc;
1388	}
1389	AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc=%Vrc\n", rc));
1390	}
1391	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1392	return emR3RawExecuteInstruction(pVM, "IO: ");
1393	}
1394
1395
1396	/**
1397	* Handle a guest context trap.
1398	*
1399	* @returns VBox status code suitable for EM.
1400	* @param pVM VM handle.
1401	*/
1402	static int emR3RawGuestTrap(PVM pVM)
1403	{
1404	PCPUMCTX pCtx = pVM->em.s.pCtx;
1405
1406	/*
1407	* Get the trap info.
1408	*/
1409	uint8_t u8TrapNo;
1410	TRPMEVENT enmType;
1411	RTGCUINT uErrorCode;
1412	RTGCUINTPTR uCR2;
1413	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1414	if (VBOX_FAILURE(rc))
1415	{
1416	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1417	return rc;
1418	}
1419
1420	/* Traps can be directly forwarded in hardware accelerated mode. */
1421	if (HWACCMR3IsActive(pVM))
1422	{
1423	#ifdef LOGGING_ENABLED
1424	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1425	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1426	#endif
1427	return VINF_EM_RESCHEDULE_HWACC;
1428	}
1429
1430	/** Scan kernel code that traps; we might not get another chance. */
1431	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1432	&& !pCtx->eflags.Bits.u1VM)
1433	{
1434	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1435	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1436	}
1437
1438	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1439	{
1440	DISCPUSTATE cpu;
1441
1442	/* If MONITOR & MWAIT are supported, then interpret them here. */
1443	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1444	if ( VBOX_SUCCESS(rc)
1445	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1446	{
1447	uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1448
1449	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1450
1451	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1452	{
1453	rc = TRPMResetTrap(pVM);
1454	AssertRC(rc);
1455
1456	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1457	if (VBOX_SUCCESS(rc))
1458	{
1459	pCtx->rip += cpu.opsize;
1460	return rc;
1461	}
1462	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1463	}
1464	}
1465	}
1466	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1467	{
1468	DISCPUSTATE cpu;
1469
1470	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1471	if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1472	{
1473	/*
1474	* We should really check the TSS for the IO bitmap, but it's not like this
1475	* lazy approach really makes things worse.
1476	*/
1477	rc = TRPMResetTrap(pVM);
1478	AssertRC(rc);
1479	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1480	}
1481	}
1482
1483	#ifdef LOG_ENABLED
1484	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1485	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1486
1487	/* Get guest page information. */
1488	uint64_t fFlags = 0;
1489	RTGCPHYS GCPhys = 0;
1490	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1491	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1492	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1493	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1494	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1495	#endif
1496
1497	/*
1498	* #PG has CR2.
1499	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1500	*/
1501	if (u8TrapNo == 14 /* #PG */)
1502	pCtx->cr2 = uCR2;
1503
1504	return VINF_EM_RESCHEDULE_REM;
1505	}
1506
1507
1508	/**
1509	* Handle a ring switch trap.
1510	* Need to do statistics and to install patches. The result is going to REM.
1511	*
1512	* @returns VBox status code suitable for EM.
1513	* @param pVM VM handle.
1514	*/
1515	int emR3RawRingSwitch(PVM pVM)
1516	{
1517	int rc;
1518	DISCPUSTATE Cpu;
1519	PCPUMCTX pCtx = pVM->em.s.pCtx;
1520
1521	/*
1522	* sysenter, syscall & callgate
1523	*/
1524	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1525	if (VBOX_SUCCESS(rc))
1526	{
1527	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1528	{
1529	if (pCtx->SysEnter.cs != 0)
1530	{
1531	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1532	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1533	if (VBOX_SUCCESS(rc))
1534	{
1535	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1536	return VINF_EM_RESCHEDULE_RAW;
1537	}
1538	}
1539	}
1540
1541	#ifdef VBOX_WITH_STATISTICS
1542	switch (Cpu.pCurInstr->opcode)
1543	{
1544	case OP_SYSENTER:
1545	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysEnter);
1546	break;
1547	case OP_SYSEXIT:
1548	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysExit);
1549	break;
1550	case OP_SYSCALL:
1551	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysCall);
1552	break;
1553	case OP_SYSRET:
1554	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysRet);
1555	break;
1556	}
1557	#endif
1558	}
1559	else
1560	AssertRC(rc);
1561
1562	/* go to the REM to emulate a single instruction */
1563	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1564	}
1565
1566	/**
1567	* Handle a trap (\#PF or \#GP) in patch code
1568	*
1569	* @returns VBox status code suitable for EM.
1570	* @param pVM VM handle.
1571	* @param pCtx CPU context
1572	* @param gcret GC return code
1573	*/
1574	int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1575	{
1576	uint8_t u8TrapNo;
1577	int rc;
1578	TRPMEVENT enmType;
1579	RTGCUINT uErrorCode;
1580	RTGCUINTPTR uCR2;
1581
1582	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1583
1584	if (gcret == VINF_PATM_PATCH_INT3)
1585	{
1586	u8TrapNo = 3;
1587	uCR2 = 0;
1588	uErrorCode = 0;
1589	}
1590	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
1591	{
1592	/* No active trap in this case. Kind of ugly. */
1593	u8TrapNo = X86_XCPT_GP;
1594	uCR2 = 0;
1595	uErrorCode = 0;
1596	}
1597	else
1598	{
1599	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1600	if (VBOX_FAILURE(rc))
1601	{
1602	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1603	return rc;
1604	}
1605	/* Reset the trap as we'll execute the original instruction again. */
1606	TRPMResetTrap(pVM);
1607	}
1608
1609	/*
1610	* Deal with traps inside patch code.
1611	* (This code won't run outside GC.)
1612	*/
1613	if (u8TrapNo != 1)
1614	{
1615	#ifdef LOG_ENABLED
1616	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1617	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1618
1619	DISCPUSTATE Cpu;
1620	int rc;
1621
1622	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1623	if ( VBOX_SUCCESS(rc)
1624	&& Cpu.pCurInstr->opcode == OP_IRET)
1625	{
1626	uint32_t eip, selCS, uEFlags;
1627
1628	/* Iret crashes are bad as we have already changed the flags on the stack */
1629	rc = PGMPhysReadGCPtr(pVM, &eip, pCtx->esp, 4);
1630	rc \|= PGMPhysReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1631	rc \|= PGMPhysReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1632	if (rc == VINF_SUCCESS)
1633	{
1634	if ( (uEFlags & X86_EFL_VM)
1635	\|\| (selCS & X86_SEL_RPL) == 3)
1636	{
1637	uint32_t selSS, esp;
1638
1639	rc \|= PGMPhysReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1640	rc \|= PGMPhysReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1641
1642	if (uEFlags & X86_EFL_VM)
1643	{
1644	uint32_t selDS, selES, selFS, selGS;
1645	rc = PGMPhysReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1646	rc \|= PGMPhysReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1647	rc \|= PGMPhysReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1648	rc \|= PGMPhysReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1649	if (rc == VINF_SUCCESS)
1650	{
1651	Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1652	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1653	}
1654	}
1655	else
1656	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1657	}
1658	else
1659	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1660	}
1661	}
1662	#endif /* LOG_ENABLED */
1663	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1664	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1665
1666	RTGCPTR pNewEip;
1667	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1668	switch (rc)
1669	{
1670	/*
1671	* Execute the faulting instruction.
1672	*/
1673	case VINF_SUCCESS:
1674	{
1675	/** @todo execute a whole block */
1676	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1677	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1678	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1679
1680	pCtx->eip = pNewEip;
1681	AssertRelease(pCtx->eip);
1682
1683	if (pCtx->eflags.Bits.u1IF)
1684	{
1685	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1686	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1687	*/
1688	if ( u8TrapNo == X86_XCPT_GP
1689	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1690	{
1691	/** @todo move to PATMR3HandleTrap */
1692	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1693	PATMR3RemovePatch(pVM, pCtx->eip);
1694	}
1695
1696	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1697	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
1698
1699	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1700	/* Interrupts are enabled; just go back to the original instruction.
1701	return VINF_SUCCESS; */
1702	}
1703	return VINF_EM_RESCHEDULE_REM;
1704	}
1705
1706	/*
1707	* One instruction.
1708	*/
1709	case VINF_PATCH_EMULATE_INSTR:
1710	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1711	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1712	pCtx->eip = pNewEip;
1713	AssertRelease(pCtx->eip);
1714	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1715
1716	/*
1717	* The patch was disabled, hand it to the REM.
1718	*/
1719	case VERR_PATCH_DISABLED:
1720	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1721	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1722	pCtx->eip = pNewEip;
1723	AssertRelease(pCtx->eip);
1724
1725	if (pCtx->eflags.Bits.u1IF)
1726	{
1727	/*
1728	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1729	*/
1730	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1731	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1732	}
1733	return VINF_EM_RESCHEDULE_REM;
1734
1735	/* Force continued patch exection; usually due to write monitored stack. */
1736	case VINF_PATCH_CONTINUE:
1737	return VINF_SUCCESS;
1738
1739	/*
1740	* Anything else is fatal.
1741	*/
1742	default:
1743	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1744	return VERR_INTERNAL_ERROR;
1745	}
1746	}
1747	return VINF_SUCCESS;
1748	}
1749
1750
1751	/**
1752	* Handle a privileged instruction.
1753	*
1754	* @returns VBox status code suitable for EM.
1755	* @param pVM VM handle.
1756	*/
1757	int emR3RawPrivileged(PVM pVM)
1758	{
1759	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1760	PCPUMCTX pCtx = pVM->em.s.pCtx;
1761
1762	Assert(!pCtx->eflags.Bits.u1VM);
1763
1764	if (PATMIsEnabled(pVM))
1765	{
1766	/*
1767	* Check if in patch code.
1768	*/
1769	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1770	{
1771	#ifdef LOG_ENABLED
1772	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1773	#endif
1774	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1775	return VERR_EM_RAW_PATCH_CONFLICT;
1776	}
1777	if ( (pCtx->ss & X86_SEL_RPL) == 0
1778	&& !pCtx->eflags.Bits.u1VM
1779	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1780	{
1781	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1782	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1783	if (VBOX_SUCCESS(rc))
1784	{
1785	#ifdef LOG_ENABLED
1786	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1787	#endif
1788	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1789	return VINF_SUCCESS;
1790	}
1791	}
1792	}
1793
1794	#ifdef LOG_ENABLED
1795	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1796	{
1797	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1798	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1799	}
1800	#endif
1801
1802	/*
1803	* Instruction statistics and logging.
1804	*/
1805	DISCPUSTATE Cpu;
1806	int rc;
1807
1808	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1809	if (VBOX_SUCCESS(rc))
1810	{
1811	#ifdef VBOX_WITH_STATISTICS
1812	PEMSTATS pStats = pVM->em.s.CTX_SUFF(pStats);
1813	switch (Cpu.pCurInstr->opcode)
1814	{
1815	case OP_INVLPG:
1816	STAM_COUNTER_INC(&pStats->StatInvlpg);
1817	break;
1818	case OP_IRET:
1819	STAM_COUNTER_INC(&pStats->StatIret);
1820	break;
1821	case OP_CLI:
1822	STAM_COUNTER_INC(&pStats->StatCli);
1823	emR3RecordCli(pVM, pCtx->rip);
1824	break;
1825	case OP_STI:
1826	STAM_COUNTER_INC(&pStats->StatSti);
1827	break;
1828	case OP_INSB:
1829	case OP_INSWD:
1830	case OP_IN:
1831	case OP_OUTSB:
1832	case OP_OUTSWD:
1833	case OP_OUT:
1834	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1835	break;
1836
1837	case OP_MOV_CR:
1838	if (Cpu.param1.flags & USE_REG_GEN32)
1839	{
1840	//read
1841	Assert(Cpu.param2.flags & USE_REG_CR);
1842	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1843	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1844	}
1845	else
1846	{
1847	//write
1848	Assert(Cpu.param1.flags & USE_REG_CR);
1849	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1850	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1851	}
1852	break;
1853
1854	case OP_MOV_DR:
1855	STAM_COUNTER_INC(&pStats->StatMovDRx);
1856	break;
1857	case OP_LLDT:
1858	STAM_COUNTER_INC(&pStats->StatMovLldt);
1859	break;
1860	case OP_LIDT:
1861	STAM_COUNTER_INC(&pStats->StatMovLidt);
1862	break;
1863	case OP_LGDT:
1864	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1865	break;
1866	case OP_SYSENTER:
1867	STAM_COUNTER_INC(&pStats->StatSysEnter);
1868	break;
1869	case OP_SYSEXIT:
1870	STAM_COUNTER_INC(&pStats->StatSysExit);
1871	break;
1872	case OP_SYSCALL:
1873	STAM_COUNTER_INC(&pStats->StatSysCall);
1874	break;
1875	case OP_SYSRET:
1876	STAM_COUNTER_INC(&pStats->StatSysRet);
1877	break;
1878	case OP_HLT:
1879	STAM_COUNTER_INC(&pStats->StatHlt);
1880	break;
1881	default:
1882	STAM_COUNTER_INC(&pStats->StatMisc);
1883	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1884	break;
1885	}
1886	#endif /* VBOX_WITH_STATISTICS */
1887	if ( (pCtx->ss & X86_SEL_RPL) == 0
1888	&& !pCtx->eflags.Bits.u1VM
1889	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
1890	{
1891	uint32_t size;
1892
1893	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1894	switch (Cpu.pCurInstr->opcode)
1895	{
1896	case OP_CLI:
1897	pCtx->eflags.u32 &= ~X86_EFL_IF;
1898	Assert(Cpu.opsize == 1);
1899	pCtx->rip += Cpu.opsize;
1900	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1901	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1902
1903	case OP_STI:
1904	pCtx->eflags.u32 \|= X86_EFL_IF;
1905	EMSetInhibitInterruptsPC(pVM, pCtx->rip + Cpu.opsize);
1906	Assert(Cpu.opsize == 1);
1907	pCtx->rip += Cpu.opsize;
1908	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1909	return VINF_SUCCESS;
1910
1911	case OP_HLT:
1912	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1913	{
1914	PATMTRANSSTATE enmState;
1915	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1916
1917	if (enmState == PATMTRANS_OVERWRITTEN)
1918	{
1919	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1920	Assert(rc == VERR_PATCH_DISABLED);
1921	/* Conflict detected, patch disabled */
1922	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1923
1924	enmState = PATMTRANS_SAFE;
1925	}
1926
1927	/* The translation had better be successful. Otherwise we can't recover. */
1928	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1929	if (enmState != PATMTRANS_OVERWRITTEN)
1930	pCtx->eip = pOrgInstrGC;
1931	}
1932	/* no break; we could just return VINF_EM_HALT here */
1933
1934	case OP_MOV_CR:
1935	case OP_MOV_DR:
1936	#ifdef LOG_ENABLED
1937	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1938	{
1939	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1940	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1941	}
1942	#endif
1943
1944	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1945	if (VBOX_SUCCESS(rc))
1946	{
1947	pCtx->rip += Cpu.opsize;
1948	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1949
1950	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1951	&& Cpu.param1.flags == USE_REG_CR /* write */
1952	)
1953	{
1954	/* Deal with CR0 updates inside patch code that force
1955	* us to go to the recompiler.
1956	*/
1957	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1958	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1959	{
1960	PATMTRANSSTATE enmState;
1961	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1962
1963	Assert(pCtx->eflags.Bits.u1IF == 0);
1964	Log(("Force recompiler switch due to cr0 (%VGp) update\n", pCtx->cr0));
1965	if (enmState == PATMTRANS_OVERWRITTEN)
1966	{
1967	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1968	Assert(rc == VERR_PATCH_DISABLED);
1969	/* Conflict detected, patch disabled */
1970	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->rip));
1971	enmState = PATMTRANS_SAFE;
1972	}
1973	/* The translation had better be successful. Otherwise we can't recover. */
1974	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->rip));
1975	if (enmState != PATMTRANS_OVERWRITTEN)
1976	pCtx->rip = pOrgInstrGC;
1977	}
1978
1979	/* Reschedule is necessary as the execution/paging mode might have changed. */
1980	return VINF_EM_RESCHEDULE;
1981	}
1982	return rc; /* can return VINF_EM_HALT as well. */
1983	}
1984	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1985	break; /* fall back to the recompiler */
1986	}
1987	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1988	}
1989	}
1990
1991	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1992	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1993
1994	return emR3RawExecuteInstruction(pVM, "PRIV");
1995	}
1996
1997
1998	/**
1999	* Update the forced rawmode execution modifier.
2000	*
2001	* This function is called when we're returning from the raw-mode loop(s). If we're
2002	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2003	* if not in patch code, the flag will be cleared.
2004	*
2005	* We should never interrupt patch code while it's being executed. Cli patches can
2006	* contain big code blocks, but they are always executed with IF=0. Other patches
2007	* replace single instructions and should be atomic.
2008	*
2009	* @returns Updated rc.
2010	*
2011	* @param pVM The VM handle.
2012	* @param pCtx The guest CPU context.
2013	* @param rc The result code.
2014	*/
2015	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2016	{
2017	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2018	{
2019	/* ignore reschedule attempts. */
2020	switch (rc)
2021	{
2022	case VINF_EM_RESCHEDULE:
2023	case VINF_EM_RESCHEDULE_REM:
2024	rc = VINF_SUCCESS;
2025	break;
2026	}
2027	pVM->em.s.fForceRAW = true;
2028	}
2029	else
2030	pVM->em.s.fForceRAW = false;
2031	return rc;
2032	}
2033
2034
2035	/**
2036	* Process a subset of the raw-mode return code.
2037	*
2038	* Since we have to share this with raw-mode single stepping, this inline
2039	* function has been created to avoid code duplication.
2040	*
2041	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2042	* @returns VBox status code to return to the EM main loop.
2043	*
2044	* @param pVM The VM handle
2045	* @param rc The return code.
2046	* @param pCtx The guest cpu context.
2047	*/
2048	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2049	{
2050	switch (rc)
2051	{
2052	/*
2053	* Common & simple ones.
2054	*/
2055	case VINF_SUCCESS:
2056	break;
2057	case VINF_EM_RESCHEDULE_RAW:
2058	case VINF_EM_RESCHEDULE_HWACC:
2059	case VINF_EM_RAW_INTERRUPT:
2060	case VINF_EM_RAW_TO_R3:
2061	case VINF_EM_RAW_TIMER_PENDING:
2062	case VINF_EM_PENDING_REQUEST:
2063	rc = VINF_SUCCESS;
2064	break;
2065
2066	/*
2067	* Privileged instruction.
2068	*/
2069	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2070	case VINF_PATM_PATCH_TRAP_GP:
2071	rc = emR3RawPrivileged(pVM);
2072	break;
2073
2074	/*
2075	* Got a trap which needs dispatching.
2076	*/
2077	case VINF_EM_RAW_GUEST_TRAP:
2078	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2079	{
2080	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2081	rc = VERR_EM_RAW_PATCH_CONFLICT;
2082	break;
2083	}
2084
2085	Assert(TRPMHasTrap(pVM));
2086	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2087
2088	if (TRPMHasTrap(pVM))
2089	{
2090	uint8_t u8Interrupt;
2091	RTGCUINT uErrorCode;
2092	TRPMERRORCODE enmError = TRPM_TRAP_NO_ERRORCODE;
2093
2094	rc = TRPMQueryTrapAll(pVM, &u8Interrupt, NULL, &uErrorCode, NULL);
2095	AssertRC(rc);
2096
2097	if (uErrorCode != ~0U)
2098	enmError = TRPM_TRAP_HAS_ERRORCODE;
2099
2100	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2101	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2102	{
2103	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2104	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2105
2106	/** If it was successful, then we could go back to raw mode. */
2107	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER)
2108	{
2109	/* Must check pending forced actions as our IDT or GDT might be out of sync */
2110	EMR3CheckRawForcedActions(pVM);
2111
2112	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8Interrupt, uErrorCode, enmError, TRPM_TRAP, -1);
2113	if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
2114	{
2115	TRPMResetTrap(pVM);
2116	return VINF_EM_RESCHEDULE_RAW;
2117	}
2118	}
2119	}
2120	}
2121	rc = emR3RawGuestTrap(pVM);
2122	break;
2123
2124	/*
2125	* Trap in patch code.
2126	*/
2127	case VINF_PATM_PATCH_TRAP_PF:
2128	case VINF_PATM_PATCH_INT3:
2129	rc = emR3PatchTrap(pVM, pCtx, rc);
2130	break;
2131
2132	case VINF_PATM_DUPLICATE_FUNCTION:
2133	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2134	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2135	AssertRC(rc);
2136	rc = VINF_SUCCESS;
2137	break;
2138
2139	case VINF_PATM_CHECK_PATCH_PAGE:
2140	rc = PATMR3HandleMonitoredPage(pVM);
2141	AssertRC(rc);
2142	rc = VINF_SUCCESS;
2143	break;
2144
2145	/*
2146	* Patch manager.
2147	*/
2148	case VERR_EM_RAW_PATCH_CONFLICT:
2149	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2150	break;
2151
2152	/*
2153	* Memory mapped I/O access - attempt to patch the instruction
2154	*/
2155	case VINF_PATM_HC_MMIO_PATCH_READ:
2156	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2157	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2158	if (VBOX_FAILURE(rc))
2159	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2160	break;
2161
2162	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2163	AssertFailed(); /* not yet implemented. */
2164	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2165	break;
2166
2167	/*
2168	* Conflict or out of page tables.
2169	*
2170	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2171	* do here is to execute the pending forced actions.
2172	*/
2173	case VINF_PGM_SYNC_CR3:
2174	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2175	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2176	rc = VINF_SUCCESS;
2177	break;
2178
2179	/*
2180	* Paging mode change.
2181	*/
2182	case VINF_PGM_CHANGE_MODE:
2183	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2184	if (VBOX_SUCCESS(rc))
2185	rc = VINF_EM_RESCHEDULE;
2186	break;
2187
2188	/*
2189	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2190	*/
2191	case VINF_CSAM_PENDING_ACTION:
2192	rc = VINF_SUCCESS;
2193	break;
2194
2195	/*
2196	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2197	*/
2198	case VINF_EM_RAW_INTERRUPT_PENDING:
2199	case VINF_EM_RAW_RING_SWITCH_INT:
2200	{
2201	uint8_t u8Interrupt;
2202
2203	Assert(TRPMHasTrap(pVM));
2204	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2205
2206	if (TRPMHasTrap(pVM))
2207	{
2208	u8Interrupt = TRPMGetTrapNo(pVM);
2209
2210	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2211	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2212	{
2213	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2214	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2215	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2216	}
2217	}
2218	rc = VINF_EM_RESCHEDULE_REM;
2219	break;
2220	}
2221
2222	/*
2223	* Other ring switch types.
2224	*/
2225	case VINF_EM_RAW_RING_SWITCH:
2226	rc = emR3RawRingSwitch(pVM);
2227	break;
2228
2229	/*
2230	* REMGCNotifyInvalidatePage() failed because of overflow.
2231	*/
2232	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2233	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2234	REMR3ReplayInvalidatedPages(pVM);
2235	rc = VINF_SUCCESS;
2236	break;
2237
2238	/*
2239	* I/O Port access - emulate the instruction.
2240	*/
2241	case VINF_IOM_HC_IOPORT_READ:
2242	case VINF_IOM_HC_IOPORT_WRITE:
2243	rc = emR3RawExecuteIOInstruction(pVM);
2244	break;
2245
2246	/*
2247	* Memory mapped I/O access - emulate the instruction.
2248	*/
2249	case VINF_IOM_HC_MMIO_READ:
2250	case VINF_IOM_HC_MMIO_WRITE:
2251	case VINF_IOM_HC_MMIO_READ_WRITE:
2252	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2253	break;
2254
2255	/*
2256	* Execute instruction.
2257	*/
2258	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2259	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2260	break;
2261	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2262	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2263	break;
2264	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2265	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2266	break;
2267	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2268	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2269	break;
2270	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2271	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2272	break;
2273
2274	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2275	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2276	rc = emR3RawPrivileged(pVM);
2277	break;
2278
2279	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2280	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2281	break;
2282
2283	case VINF_EM_RAW_EMULATE_INSTR:
2284	case VINF_PATCH_EMULATE_INSTR:
2285	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2286	break;
2287
2288	/*
2289	* Stale selector and iret traps => REM.
2290	*/
2291	case VINF_EM_RAW_STALE_SELECTOR:
2292	case VINF_EM_RAW_IRET_TRAP:
2293	/* We will not go to the recompiler if EIP points to patch code. */
2294	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2295	{
2296	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2297	}
2298	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2299	rc = VINF_EM_RESCHEDULE_REM;
2300	break;
2301
2302	/*
2303	* Up a level.
2304	*/
2305	case VINF_EM_TERMINATE:
2306	case VINF_EM_OFF:
2307	case VINF_EM_RESET:
2308	case VINF_EM_SUSPEND:
2309	case VINF_EM_HALT:
2310	case VINF_EM_RESUME:
2311	case VINF_EM_RESCHEDULE:
2312	case VINF_EM_RESCHEDULE_REM:
2313	break;
2314
2315	/*
2316	* Up a level and invoke the debugger.
2317	*/
2318	case VINF_EM_DBG_STEPPED:
2319	case VINF_EM_DBG_BREAKPOINT:
2320	case VINF_EM_DBG_STEP:
2321	case VINF_EM_DBG_HYPER_ASSERTION:
2322	case VINF_EM_DBG_HYPER_BREAKPOINT:
2323	case VINF_EM_DBG_HYPER_STEPPED:
2324	case VINF_EM_DBG_STOP:
2325	break;
2326
2327	/*
2328	* Up a level, dump and debug.
2329	*/
2330	case VERR_TRPM_DONT_PANIC:
2331	case VERR_TRPM_PANIC:
2332	break;
2333
2334	case VERR_VMX_INVALID_VMCS_FIELD:
2335	case VERR_VMX_INVALID_VMCS_PTR:
2336	case VERR_VMX_INVALID_VMXON_PTR:
2337	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2338	case VERR_VMX_UNEXPECTED_EXCEPTION:
2339	case VERR_VMX_UNEXPECTED_EXIT_CODE:
2340	case VERR_VMX_INVALID_GUEST_STATE:
2341	HWACCMR3CheckError(pVM, rc);
2342	break;
2343	/*
2344	* Anything which is not known to us means an internal error
2345	* and the termination of the VM!
2346	*/
2347	default:
2348	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2349	break;
2350	}
2351	return rc;
2352	}
2353
2354
2355	/**
2356	* Check for pending raw actions
2357	*
2358	* @returns VBox status code.
2359	* @param pVM The VM to operate on.
2360	*/
2361	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2362	{
2363	return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2364	}
2365
2366
2367	/**
2368	* Process raw-mode specific forced actions.
2369	*
2370	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2371	*
2372	* @returns VBox status code.
2373	* Only the normal success/failure stuff, no VINF_EM_*.
2374	* @param pVM The VM handle.
2375	* @param pCtx The guest CPUM register context.
2376	*/
2377	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2378	{
2379	/*
2380	* Note that the order is vitally important!
2381	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2382	*/
2383
2384
2385	/*
2386	* Sync selector tables.
2387	*/
2388	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2389	{
2390	int rc = SELMR3UpdateFromCPUM(pVM);
2391	if (VBOX_FAILURE(rc))
2392	return rc;
2393	}
2394
2395	/*
2396	* Sync IDT.
2397	*/
2398	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2399	{
2400	int rc = TRPMR3SyncIDT(pVM);
2401	if (VBOX_FAILURE(rc))
2402	return rc;
2403	}
2404
2405	/*
2406	* Sync TSS.
2407	*/
2408	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2409	{
2410	int rc = SELMR3SyncTSS(pVM);
2411	if (VBOX_FAILURE(rc))
2412	return rc;
2413	}
2414
2415	/*
2416	* Sync page directory.
2417	*/
2418	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2419	{
2420	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2421	if (VBOX_FAILURE(rc))
2422	return rc;
2423
2424	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2425
2426	/* Prefetch pages for EIP and ESP */
2427	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2428	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2429	if (rc == VINF_SUCCESS)
2430	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2431	if (rc != VINF_SUCCESS)
2432	{
2433	if (rc != VINF_PGM_SYNC_CR3)
2434	return rc;
2435	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2436	if (VBOX_FAILURE(rc))
2437	return rc;
2438	}
2439	/** @todo maybe prefetch the supervisor stack page as well */
2440	}
2441
2442	/*
2443	* Allocate handy pages (just in case the above actions have consumed some pages).
2444	*/
2445	if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
2446	{
2447	int rc = PGMR3PhysAllocateHandyPages(pVM);
2448	if (VBOX_FAILURE(rc))
2449	return rc;
2450	}
2451
2452	return VINF_SUCCESS;
2453	}
2454
2455
2456	/**
2457	* Executes raw code.
2458	*
2459	* This function contains the raw-mode version of the inner
2460	* execution loop (the outer loop being in EMR3ExecuteVM()).
2461	*
2462	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2463	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2464	*
2465	* @param pVM VM handle.
2466	* @param pfFFDone Where to store an indicator telling whether or not
2467	* FFs were done before returning.
2468	*/
2469	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2470	{
2471	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2472
2473	int rc = VERR_INTERNAL_ERROR;
2474	PCPUMCTX pCtx = pVM->em.s.pCtx;
2475	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2476	pVM->em.s.fForceRAW = false;
2477	*pfFFDone = false;
2478
2479
2480	/*
2481	*
2482	* Spin till we get a forced action or raw mode status code resulting in
2483	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2484	*
2485	*/
2486	for (;;)
2487	{
2488	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2489
2490	/*
2491	* Check various preconditions.
2492	*/
2493	#ifdef VBOX_STRICT
2494	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2495	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2496	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2497	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2498	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2499	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2500	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2501	{
2502	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2503	return VERR_INTERNAL_ERROR;
2504	}
2505	#endif /* VBOX_STRICT */
2506
2507	/*
2508	* Process high priority pre-execution raw-mode FFs.
2509	*/
2510	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2511	{
2512	rc = emR3RawForcedActions(pVM, pCtx);
2513	if (VBOX_FAILURE(rc))
2514	break;
2515	}
2516
2517	/*
2518	* If we're going to execute ring-0 code, the guest state needs to
2519	* be modified a bit and some of the state components (IF, SS/CS RPL,
2520	* and perhaps EIP) needs to be stored with PATM.
2521	*/
2522	rc = CPUMRawEnter(pVM, NULL);
2523	if (rc != VINF_SUCCESS)
2524	{
2525	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2526	break;
2527	}
2528
2529	/*
2530	* Scan code before executing it. Don't bother with user mode or V86 code
2531	*/
2532	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2533	&& !pCtx->eflags.Bits.u1VM
2534	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2535	{
2536	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2537	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2538	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2539	}
2540
2541	#ifdef LOG_ENABLED
2542	/*
2543	* Log important stuff before entering GC.
2544	*/
2545	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2546	if (pCtx->eflags.Bits.u1VM)
2547	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2548	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2549	{
2550	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2551	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2552	}
2553	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2554	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2555	#endif /* LOG_ENABLED */
2556
2557
2558
2559	/*
2560	* Execute the code.
2561	*/
2562	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2563	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2564	VMMR3Unlock(pVM);
2565	rc = VMMR3RawRunGC(pVM);
2566	VMMR3Lock(pVM);
2567	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2568	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2569
2570	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2571	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2572
2573
2574
2575	/*
2576	* Restore the real CPU state and deal with high priority post
2577	* execution FFs before doing anything else.
2578	*/
2579	rc = CPUMRawLeave(pVM, NULL, rc);
2580	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2581	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2582	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2583
2584	#ifdef VBOX_STRICT
2585	/*
2586	* Assert TSS consistency & rc vs patch code.
2587	*/
2588	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2589	&& EMIsRawRing0Enabled(pVM))
2590	SELMR3CheckTSS(pVM);
2591	switch (rc)
2592	{
2593	case VINF_SUCCESS:
2594	case VINF_EM_RAW_INTERRUPT:
2595	case VINF_PATM_PATCH_TRAP_PF:
2596	case VINF_PATM_PATCH_TRAP_GP:
2597	case VINF_PATM_PATCH_INT3:
2598	case VINF_PATM_CHECK_PATCH_PAGE:
2599	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2600	case VINF_EM_RAW_GUEST_TRAP:
2601	case VINF_EM_RESCHEDULE_RAW:
2602	break;
2603
2604	default:
2605	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2606	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VRv for reason %Vrc\n", (RTRCPTR)CPUMGetGuestEIP(pVM), rc));
2607	break;
2608	}
2609	/*
2610	* Let's go paranoid!
2611	*/
2612	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2613	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2614	{
2615	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2616	return VERR_INTERNAL_ERROR;
2617	}
2618	#endif /* VBOX_STRICT */
2619
2620	/*
2621	* Process the returned status code.
2622	*/
2623	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2624	{
2625	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2626	break;
2627	}
2628	rc = emR3RawHandleRC(pVM, pCtx, rc);
2629	if (rc != VINF_SUCCESS)
2630	{
2631	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2632	if (rc != VINF_SUCCESS)
2633	{
2634	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2635	break;
2636	}
2637	}
2638
2639	/*
2640	* Check and execute forced actions.
2641	*/
2642	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2643	TMTimerPoll(pVM);
2644	#endif
2645	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2646	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2647	{
2648	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2649
2650	STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2651	rc = emR3ForcedActions(pVM, rc);
2652	STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2653	if ( rc != VINF_SUCCESS
2654	&& rc != VINF_EM_RESCHEDULE_RAW)
2655	{
2656	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2657	if (rc != VINF_SUCCESS)
2658	{
2659	*pfFFDone = true;
2660	break;
2661	}
2662	}
2663	}
2664	}
2665
2666	/*
2667	* Return to outer loop.
2668	*/
2669	#if defined(LOG_ENABLED) && defined(DEBUG)
2670	RTLogFlush(NULL);
2671	#endif
2672	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2673	return rc;
2674	}
2675
2676
2677	/**
2678	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2679	*
2680	* This function contains the raw-mode version of the inner
2681	* execution loop (the outer loop being in EMR3ExecuteVM()).
2682	*
2683	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2684	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2685	*
2686	* @param pVM VM handle.
2687	* @param pfFFDone Where to store an indicator telling whether or not
2688	* FFs were done before returning.
2689	*/
2690	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2691	{
2692	int rc = VERR_INTERNAL_ERROR;
2693	PCPUMCTX pCtx = pVM->em.s.pCtx;
2694
2695	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%VGv)\n", pCtx->cs, pCtx->rip));
2696	*pfFFDone = false;
2697
2698	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2699
2700	/*
2701	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2702	*/
2703	for (;;)
2704	{
2705	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2706
2707	/*
2708	* Check various preconditions.
2709	*/
2710	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2711
2712	/*
2713	* Process high priority pre-execution raw-mode FFs.
2714	*/
2715	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2716	{
2717	rc = emR3RawForcedActions(pVM, pCtx);
2718	if (VBOX_FAILURE(rc))
2719	break;
2720	}
2721
2722	#ifdef LOG_ENABLED
2723	/*
2724	* Log important stuff before entering GC.
2725	*/
2726	if (TRPMHasTrap(pVM))
2727	Log(("Pending hardware interrupt=0x%x cs:eip=%04X:%VGv\n", TRPMGetTrapNo(pVM), pCtx->cs, pCtx->rip));
2728
2729	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2730	if (pCtx->eflags.Bits.u1VM)
2731	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2732	else if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
2733	Log(("HWR%d: %04X:%VGv ESP=%VGv IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2734	else
2735	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2736	#endif /* LOG_ENABLED */
2737
2738	/*
2739	* Execute the code.
2740	*/
2741	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2742	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2743	VMMR3Unlock(pVM);
2744	rc = VMMR3HwAccRunGC(pVM);
2745	VMMR3Lock(pVM);
2746	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2747
2748	/*
2749	* Deal with high priority post execution FFs before doing anything else.
2750	*/
2751	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2752	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2753	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2754
2755	/*
2756	* Process the returned status code.
2757	*/
2758	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2759	break;
2760
2761	rc = emR3RawHandleRC(pVM, pCtx, rc);
2762	if (rc != VINF_SUCCESS)
2763	break;
2764
2765	/*
2766	* Check and execute forced actions.
2767	*/
2768	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2769	TMTimerPoll(pVM);
2770	#endif
2771	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2772	{
2773	rc = emR3ForcedActions(pVM, rc);
2774	if ( rc != VINF_SUCCESS
2775	&& rc != VINF_EM_RESCHEDULE_HWACC)
2776	{
2777	*pfFFDone = true;
2778	break;
2779	}
2780	}
2781	}
2782	/*
2783	* Return to outer loop.
2784	*/
2785	#if defined(LOG_ENABLED) && defined(DEBUG)
2786	RTLogFlush(NULL);
2787	#endif
2788	return rc;
2789	}
2790
2791
2792	/**
2793	* Decides whether to execute RAW, HWACC or REM.
2794	*
2795	* @returns new EM state
2796	* @param pVM The VM.
2797	* @param pCtx The CPU context.
2798	*/
2799	DECLINLINE(EMSTATE) emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2800	{
2801	/*
2802	* When forcing raw-mode execution, things are simple.
2803	*/
2804	if (pVM->em.s.fForceRAW)
2805	return EMSTATE_RAW;
2806
2807	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2808	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2809	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2810
2811	X86EFLAGS EFlags = pCtx->eflags;
2812	if (HWACCMIsEnabled(pVM))
2813	{
2814	/* Hardware accelerated raw-mode:
2815	*
2816	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2817	*/
2818	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2819	return EMSTATE_HWACC;
2820
2821	/* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
2822	* off monitoring features essential for raw mode! */
2823	return EMSTATE_REM;
2824	}
2825
2826	/*
2827	* Standard raw-mode:
2828	*
2829	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2830	* or 32 bits protected mode ring 0 code
2831	*
2832	* The tests are ordered by the likelyhood of being true during normal execution.
2833	*/
2834	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2835	{
2836	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2837	return EMSTATE_REM;
2838	}
2839
2840	#ifndef VBOX_RAW_V86
2841	if (EFlags.u32 & X86_EFL_VM) {
2842	Log2(("raw mode refused: VM_MASK\n"));
2843	return EMSTATE_REM;
2844	}
2845	#endif
2846
2847	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2848	uint32_t u32CR0 = pCtx->cr0;
2849	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2850	{
2851	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2852	return EMSTATE_REM;
2853	}
2854
2855	if (pCtx->cr4 & X86_CR4_PAE)
2856	{
2857	uint32_t u32Dummy, u32Features;
2858
2859	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2860	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
2861	return EMSTATE_REM;
2862	}
2863
2864	unsigned uSS = pCtx->ss;
2865	if ( pCtx->eflags.Bits.u1VM
2866	\|\| (uSS & X86_SEL_RPL) == 3)
2867	{
2868	if (!EMIsRawRing3Enabled(pVM))
2869	return EMSTATE_REM;
2870
2871	if (!(EFlags.u32 & X86_EFL_IF))
2872	{
2873	Log2(("raw mode refused: IF (RawR3)\n"));
2874	return EMSTATE_REM;
2875	}
2876
2877	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2878	{
2879	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2880	return EMSTATE_REM;
2881	}
2882	}
2883	else
2884	{
2885	if (!EMIsRawRing0Enabled(pVM))
2886	return EMSTATE_REM;
2887
2888	/* Only ring 0 supervisor code. */
2889	if ((uSS & X86_SEL_RPL) != 0)
2890	{
2891	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2892	return EMSTATE_REM;
2893	}
2894
2895	// Let's start with pure 32 bits ring 0 code first
2896	/** @todo What's pure 32-bit mode? flat? */
2897	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2898	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
2899	{
2900	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2901	return EMSTATE_REM;
2902	}
2903
2904	/* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2905	if (!(u32CR0 & X86_CR0_WP))
2906	{
2907	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2908	return EMSTATE_REM;
2909	}
2910
2911	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2912	{
2913	Log2(("raw r0 mode forced: patch code\n"));
2914	return EMSTATE_RAW;
2915	}
2916
2917	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2918	if (!(EFlags.u32 & X86_EFL_IF))
2919	{
2920	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2921	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2922	return EMSTATE_REM;
2923	}
2924	#endif
2925
2926	/** @todo still necessary??? */
2927	if (EFlags.Bits.u2IOPL != 0)
2928	{
2929	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2930	return EMSTATE_REM;
2931	}
2932	}
2933
2934	Assert(PGMPhysIsA20Enabled(pVM));
2935	return EMSTATE_RAW;
2936	}
2937
2938
2939	/**
2940	* Executes all high priority post execution force actions.
2941	*
2942	* @returns rc or a fatal status code.
2943	*
2944	* @param pVM VM handle.
2945	* @param rc The current rc.
2946	*/
2947	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2948	{
2949	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2950	PDMR3CritSectFF(pVM);
2951
2952	if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
2953	CSAMR3DoPendingAction(pVM);
2954
2955	return rc;
2956	}
2957
2958
2959	/**
2960	* Executes all pending forced actions.
2961	*
2962	* Forced actions can cause execution delays and execution
2963	* rescheduling. The first we deal with using action priority, so
2964	* that for instance pending timers aren't scheduled and ran until
2965	* right before execution. The rescheduling we deal with using
2966	* return codes. The same goes for VM termination, only in that case
2967	* we exit everything.
2968	*
2969	* @returns VBox status code of equal or greater importance/severity than rc.
2970	* The most important ones are: VINF_EM_RESCHEDULE,
2971	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2972	*
2973	* @param pVM VM handle.
2974	* @param rc The current rc.
2975	*
2976	*/
2977	static int emR3ForcedActions(PVM pVM, int rc)
2978	{
2979	STAM_REL_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2980	#ifdef VBOX_STRICT
2981	int rcIrq = VINF_SUCCESS;
2982	#endif
2983	int rc2;
2984	#define UPDATE_RC() \
2985	do { \
2986	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2987	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
2988	break; \
2989	if (!rc \|\| rc2 < rc) \
2990	rc = rc2; \
2991	} while (0)
2992
2993	/*
2994	* Post execution chunk first.
2995	*/
2996	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2997	{
2998	/*
2999	* Termination request.
3000	*/
3001	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3002	{
3003	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3004	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3005	return VINF_EM_TERMINATE;
3006	}
3007
3008	/*
3009	* Debugger Facility polling.
3010	*/
3011	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3012	{
3013	rc2 = DBGFR3VMMForcedAction(pVM);
3014	UPDATE_RC();
3015	}
3016
3017	/*
3018	* Postponed reset request.
3019	*/
3020	if (VM_FF_ISSET(pVM, VM_FF_RESET))
3021	{
3022	rc2 = VMR3Reset(pVM);
3023	UPDATE_RC();
3024	VM_FF_CLEAR(pVM, VM_FF_RESET);
3025	}
3026
3027	/*
3028	* CSAM page scanning.
3029	*/
3030	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
3031	{
3032	PCPUMCTX pCtx = pVM->em.s.pCtx;
3033
3034	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3035	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3036
3037	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3038	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3039	}
3040
3041	/* check that we got them all */
3042	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
3043	}
3044
3045	/*
3046	* Normal priority then.
3047	* (Executed in no particular order.)
3048	*/
3049	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3050	{
3051	/*
3052	* PDM Queues are pending.
3053	*/
3054	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3055	PDMR3QueueFlushAll(pVM);
3056
3057	/*
3058	* PDM DMA transfers are pending.
3059	*/
3060	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3061	PDMR3DmaRun(pVM);
3062
3063	/*
3064	* Requests from other threads.
3065	*/
3066	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3067	{
3068	rc2 = VMR3ReqProcessU(pVM->pUVM);
3069	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3070	{
3071	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3072	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3073	return rc2;
3074	}
3075	UPDATE_RC();
3076	}
3077
3078	/* Replay the handler notification changes. */
3079	if (VM_FF_ISSET(pVM, VM_FF_REM_HANDLER_NOTIFY))
3080	REMR3ReplayHandlerNotifications(pVM);
3081
3082	/* check that we got them all */
3083	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY)));
3084	}
3085
3086	/*
3087	* Execute polling function ever so often.
3088	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING "SOON"!
3089	*/
3090	static unsigned cLast = 0;
3091	if (!((++cLast) % 4))
3092	PDMR3Poll(pVM);
3093
3094	/*
3095	* High priority pre execution chunk last.
3096	* (Executed in ascending priority order.)
3097	*/
3098	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3099	{
3100	/*
3101	* Timers before interrupts.
3102	*/
3103	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3104	TMR3TimerQueuesDo(pVM);
3105
3106	/*
3107	* The instruction following an emulated STI should always be executed!
3108	*/
3109	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3110	{
3111	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", (RTGCPTR)CPUMGetGuestRIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3112	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3113	{
3114	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3115	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3116	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3117	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3118	*/
3119	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3120	}
3121	if (HWACCMR3IsActive(pVM))
3122	rc2 = VINF_EM_RESCHEDULE_HWACC;
3123	else
3124	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3125
3126	UPDATE_RC();
3127	}
3128
3129	/*
3130	* Interrupts.
3131	*/
3132	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3133	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3134	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3135	&& PATMAreInterruptsEnabled(pVM)
3136	&& !HWACCMR3IsEventPending(pVM))
3137	{
3138	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3139	{
3140	/* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3141	/** @todo this really isn't nice, should properly handle this */
3142	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3143	#ifdef VBOX_STRICT
3144	rcIrq = rc2;
3145	#endif
3146	UPDATE_RC();
3147	}
3148	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3149	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3150	{
3151	rc2 = VINF_EM_RESCHEDULE_REM;
3152	UPDATE_RC();
3153	}
3154	}
3155
3156	/*
3157	* Allocate handy pages.
3158	*/
3159	if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
3160	{
3161	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3162	UPDATE_RC();
3163	}
3164
3165	/*
3166	* Debugger Facility request.
3167	*/
3168	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3169	{
3170	rc2 = DBGFR3VMMForcedAction(pVM);
3171	UPDATE_RC();
3172	}
3173
3174	/*
3175	* Termination request.
3176	*/
3177	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3178	{
3179	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3180	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3181	return VINF_EM_TERMINATE;
3182	}
3183
3184	#ifdef DEBUG
3185	/*
3186	* Debug, pause the VM.
3187	*/
3188	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3189	{
3190	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3191	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3192	return VINF_EM_SUSPEND;
3193	}
3194
3195	#endif
3196	/* check that we got them all */
3197	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS \| VM_FF_PGM_NEED_HANDY_PAGES)));
3198	}
3199
3200	#undef UPDATE_RC
3201	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3202	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3203	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3204	return rc;
3205	}
3206
3207
3208	/**
3209	* Execute VM.
3210	*
3211	* This function is the main loop of the VM. The emulation thread
3212	* calls this function when the VM has been successfully constructed
3213	* and we're ready for executing the VM.
3214	*
3215	* Returning from this function means that the VM is turned off or
3216	* suspended (state already saved) and deconstruction in next in line.
3217	*
3218	* All interaction from other thread are done using forced actions
3219	* and signaling of the wait object.
3220	*
3221	* @returns VBox status code.
3222	* @param pVM The VM to operate on.
3223	*/
3224	VMMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3225	{
3226	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3227	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3228	VM_ASSERT_EMT(pVM);
3229	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3230
3231	VMMR3Lock(pVM);
3232
3233	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3234	if (rc == 0)
3235	{
3236	/*
3237	* Start the virtual time.
3238	*/
3239	rc = TMVirtualResume(pVM);
3240	Assert(rc == VINF_SUCCESS);
3241	rc = TMCpuTickResume(pVM);
3242	Assert(rc == VINF_SUCCESS);
3243
3244	/*
3245	* The Outer Main Loop.
3246	*/
3247	bool fFFDone = false;
3248	rc = VINF_EM_RESCHEDULE;
3249	pVM->em.s.enmState = EMSTATE_REM;
3250	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3251	for (;;)
3252	{
3253	/*
3254	* Before we can schedule anything (we're here because
3255	* scheduling is required) we must service any pending
3256	* forced actions to avoid any pending action causing
3257	* immediate rescheduling upon entering an inner loop
3258	*
3259	* Do forced actions.
3260	*/
3261	if ( !fFFDone
3262	&& rc != VINF_EM_TERMINATE
3263	&& rc != VINF_EM_OFF
3264	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3265	{
3266	rc = emR3ForcedActions(pVM, rc);
3267	if ( ( rc == VINF_EM_RESCHEDULE_REM
3268	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3269	&& pVM->em.s.fForceRAW)
3270	rc = VINF_EM_RESCHEDULE_RAW;
3271	}
3272	else if (fFFDone)
3273	fFFDone = false;
3274
3275	/*
3276	* Now what to do?
3277	*/
3278	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3279	switch (rc)
3280	{
3281	/*
3282	* Keep doing what we're currently doing.
3283	*/
3284	case VINF_SUCCESS:
3285	break;
3286
3287	/*
3288	* Reschedule - to raw-mode execution.
3289	*/
3290	case VINF_EM_RESCHEDULE_RAW:
3291	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3292	pVM->em.s.enmState = EMSTATE_RAW;
3293	break;
3294
3295	/*
3296	* Reschedule - to hardware accelerated raw-mode execution.
3297	*/
3298	case VINF_EM_RESCHEDULE_HWACC:
3299	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3300	Assert(!pVM->em.s.fForceRAW);
3301	pVM->em.s.enmState = EMSTATE_HWACC;
3302	break;
3303
3304	/*
3305	* Reschedule - to recompiled execution.
3306	*/
3307	case VINF_EM_RESCHEDULE_REM:
3308	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3309	pVM->em.s.enmState = EMSTATE_REM;
3310	break;
3311
3312	/*
3313	* Resume.
3314	*/
3315	case VINF_EM_RESUME:
3316	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3317	/* fall through and get scheduled. */
3318
3319	/*
3320	* Reschedule.
3321	*/
3322	case VINF_EM_RESCHEDULE:
3323	{
3324	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3325	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3326	pVM->em.s.enmState = enmState;
3327	break;
3328	}
3329
3330	/*
3331	* Halted.
3332	*/
3333	case VINF_EM_HALT:
3334	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3335	pVM->em.s.enmState = EMSTATE_HALTED;
3336	break;
3337
3338	/*
3339	* Suspend.
3340	*/
3341	case VINF_EM_SUSPEND:
3342	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3343	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3344	break;
3345
3346	/*
3347	* Reset.
3348	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3349	*/
3350	case VINF_EM_RESET:
3351	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3352	pVM->em.s.enmState = EMSTATE_REM;
3353	break;
3354
3355	/*
3356	* Power Off.
3357	*/
3358	case VINF_EM_OFF:
3359	pVM->em.s.enmState = EMSTATE_TERMINATING;
3360	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3361	TMVirtualPause(pVM);
3362	TMCpuTickPause(pVM);
3363	VMMR3Unlock(pVM);
3364	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3365	return rc;
3366
3367	/*
3368	* Terminate the VM.
3369	*/
3370	case VINF_EM_TERMINATE:
3371	pVM->em.s.enmState = EMSTATE_TERMINATING;
3372	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3373	TMVirtualPause(pVM);
3374	TMCpuTickPause(pVM);
3375	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3376	return rc;
3377
3378	/*
3379	* Guest debug events.
3380	*/
3381	case VINF_EM_DBG_STEPPED:
3382	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3383	case VINF_EM_DBG_STOP:
3384	case VINF_EM_DBG_BREAKPOINT:
3385	case VINF_EM_DBG_STEP:
3386	if (pVM->em.s.enmState == EMSTATE_RAW)
3387	{
3388	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3389	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3390	}
3391	else
3392	{
3393	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3394	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3395	}
3396	break;
3397
3398	/*
3399	* Hypervisor debug events.
3400	*/
3401	case VINF_EM_DBG_HYPER_STEPPED:
3402	case VINF_EM_DBG_HYPER_BREAKPOINT:
3403	case VINF_EM_DBG_HYPER_ASSERTION:
3404	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3405	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3406	break;
3407
3408	/*
3409	* Any error code showing up here other than the ones we
3410	* know and process above are considered to be FATAL.
3411	*
3412	* Unknown warnings and informational status codes are also
3413	* included in this.
3414	*/
3415	default:
3416	if (VBOX_SUCCESS(rc))
3417	{
3418	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3419	rc = VERR_EM_INTERNAL_ERROR;
3420	}
3421	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3422	Log(("EMR3ExecuteVM returns %d\n", rc));
3423	break;
3424	}
3425
3426
3427	/*
3428	* Any waiters can now be woken up
3429	*/
3430	VMMR3Unlock(pVM);
3431	VMMR3Lock(pVM);
3432
3433	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3434	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3435
3436	/*
3437	* Act on the state.
3438	*/
3439	switch (pVM->em.s.enmState)
3440	{
3441	/*
3442	* Execute raw.
3443	*/
3444	case EMSTATE_RAW:
3445	rc = emR3RawExecute(pVM, &fFFDone);
3446	break;
3447
3448	/*
3449	* Execute hardware accelerated raw.
3450	*/
3451	case EMSTATE_HWACC:
3452	rc = emR3HwAccExecute(pVM, &fFFDone);
3453	break;
3454
3455	/*
3456	* Execute recompiled.
3457	*/
3458	case EMSTATE_REM:
3459	rc = emR3RemExecute(pVM, &fFFDone);
3460	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3461	break;
3462
3463	/*
3464	* hlt - execution halted until interrupt.
3465	*/
3466	case EMSTATE_HALTED:
3467	{
3468	STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3469	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3470	STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3471	break;
3472	}
3473
3474	/*
3475	* Suspended - return to VM.cpp.
3476	*/
3477	case EMSTATE_SUSPENDED:
3478	TMVirtualPause(pVM);
3479	TMCpuTickPause(pVM);
3480	VMMR3Unlock(pVM);
3481	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3482	return VINF_EM_SUSPEND;
3483
3484	/*
3485	* Debugging in the guest.
3486	*/
3487	case EMSTATE_DEBUG_GUEST_REM:
3488	case EMSTATE_DEBUG_GUEST_RAW:
3489	TMVirtualPause(pVM);
3490	TMCpuTickPause(pVM);
3491	rc = emR3Debug(pVM, rc);
3492	TMVirtualResume(pVM);
3493	TMCpuTickResume(pVM);
3494	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3495	break;
3496
3497	/*
3498	* Debugging in the hypervisor.
3499	*/
3500	case EMSTATE_DEBUG_HYPER:
3501	{
3502	TMVirtualPause(pVM);
3503	TMCpuTickPause(pVM);
3504	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3505
3506	rc = emR3Debug(pVM, rc);
3507	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3508	if (rc != VINF_SUCCESS)
3509	{
3510	/* switch to guru meditation mode */
3511	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3512	VMMR3FatalDump(pVM, rc);
3513	return rc;
3514	}
3515
3516	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3517	TMVirtualResume(pVM);
3518	TMCpuTickResume(pVM);
3519	break;
3520	}
3521
3522	/*
3523	* Guru meditation takes place in the debugger.
3524	*/
3525	case EMSTATE_GURU_MEDITATION:
3526	{
3527	TMVirtualPause(pVM);
3528	TMCpuTickPause(pVM);
3529	VMMR3FatalDump(pVM, rc);
3530	emR3Debug(pVM, rc);
3531	VMMR3Unlock(pVM);
3532	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3533	return rc;
3534	}
3535
3536	/*
3537	* The states we don't expect here.
3538	*/
3539	case EMSTATE_NONE:
3540	case EMSTATE_TERMINATING:
3541	default:
3542	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3543	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3544	TMVirtualPause(pVM);
3545	TMCpuTickPause(pVM);
3546	VMMR3Unlock(pVM);
3547	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3548	return VERR_EM_INTERNAL_ERROR;
3549	}
3550	} /* The Outer Main Loop */
3551	}
3552	else
3553	{
3554	/*
3555	* Fatal error.
3556	*/
3557	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3558	TMVirtualPause(pVM);
3559	TMCpuTickPause(pVM);
3560	VMMR3FatalDump(pVM, rc);
3561	emR3Debug(pVM, rc);
3562	VMMR3Unlock(pVM);
3563	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3564	/** @todo change the VM state! */
3565	return rc;
3566	}
3567
3568	/* (won't ever get here). */
3569	AssertFailed();
3570	}
3571

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 13089

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