VirtualBox

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 15852

Last change on this file since 15852 was 15609, checked in by vboxsync, 16 years ago

HWACCM/EM: Sketeched out some scheduling notification from EM to let HWACCM know when to resync the guest state - disabled for the time being.

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File size: 153.4 KB
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1/* $Id: EM.cpp 15609 2008-12-16 22:00:21Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_em EM - The Execution Monitor / Manager
23 *
24 * The Execution Monitor/Manager is responsible for running the VM, scheduling
25 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26 * Interpreted), and keeping the CPU states in sync. The function
27 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28 * modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29 * emR3RemExecute).
30 *
31 * The interpreted execution is only used to avoid switching between
32 * raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33 * The interpretation is thus implemented as part of EM.
34 *
35 * @see grp_em
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_EM
42#include <VBox/em.h>
43#include <VBox/vmm.h>
44#ifdef VBOX_WITH_VMI
45# include <VBox/parav.h>
46#endif
47#include <VBox/patm.h>
48#include <VBox/csam.h>
49#include <VBox/selm.h>
50#include <VBox/trpm.h>
51#include <VBox/iom.h>
52#include <VBox/dbgf.h>
53#include <VBox/pgm.h>
54#include <VBox/rem.h>
55#include <VBox/tm.h>
56#include <VBox/mm.h>
57#include <VBox/ssm.h>
58#include <VBox/pdmapi.h>
59#include <VBox/pdmcritsect.h>
60#include <VBox/pdmqueue.h>
61#include <VBox/hwaccm.h>
62#include <VBox/patm.h>
63#include "EMInternal.h"
64#include <VBox/vm.h>
65#include <VBox/cpumdis.h>
66#include <VBox/dis.h>
67#include <VBox/disopcode.h>
68#include <VBox/dbgf.h>
69
70#include <VBox/log.h>
71#include <iprt/thread.h>
72#include <iprt/assert.h>
73#include <iprt/asm.h>
74#include <iprt/semaphore.h>
75#include <iprt/string.h>
76#include <iprt/avl.h>
77#include <iprt/stream.h>
78#include <VBox/param.h>
79#include <VBox/err.h>
80
81
82/*******************************************************************************
83* Defined Constants And Macros *
84*******************************************************************************/
85#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
86#define EM_NOTIFY_HWACCM
87#endif
88
89
90/*******************************************************************************
91* Internal Functions *
92*******************************************************************************/
93static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
94static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
95static int emR3Debug(PVM pVM, int rc);
96static int emR3RemStep(PVM pVM);
97static int emR3RemExecute(PVM pVM, bool *pfFFDone);
98static int emR3RawResumeHyper(PVM pVM);
99static int emR3RawStep(PVM pVM);
100DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
101DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
102static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
103static int emR3RawExecute(PVM pVM, bool *pfFFDone);
104DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
105static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
106static int emR3ForcedActions(PVM pVM, int rc);
107static int emR3RawGuestTrap(PVM pVM);
108static int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret);
109static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations);
110static EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx);
111
112/**
113 * Initializes the EM.
114 *
115 * @returns VBox status code.
116 * @param pVM The VM to operate on.
117 */
118VMMR3DECL(int) EMR3Init(PVM pVM)
119{
120 LogFlow(("EMR3Init\n"));
121 /*
122 * Assert alignment and sizes.
123 */
124 AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
125 AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
126 AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
127 ("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
128
129 /*
130 * Init the structure.
131 */
132 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
133 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
134 if (RT_FAILURE(rc))
135 pVM->fRawR3Enabled = true;
136 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
137 if (RT_FAILURE(rc))
138 pVM->fRawR0Enabled = true;
139 Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
140 pVM->em.s.enmState = EMSTATE_NONE;
141 pVM->em.s.fForceRAW = false;
142
143 pVM->em.s.pCtx = CPUMQueryGuestCtxPtr(pVM);
144 pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
145 AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
146
147 /*
148 * Saved state.
149 */
150 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
151 NULL, emR3Save, NULL,
152 NULL, emR3Load, NULL);
153 if (RT_FAILURE(rc))
154 return rc;
155
156 /*
157 * Statistics.
158 */
159#ifdef VBOX_WITH_STATISTICS
160 PEMSTATS pStats;
161 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
162 if (RT_FAILURE(rc))
163 return rc;
164 pVM->em.s.pStatsR3 = pStats;
165 pVM->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
166 pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
167
168 STAM_REG(pVM, &pStats->StatRZEmulate, STAMTYPE_PROFILE, "/EM/RZ/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
169 STAM_REG(pVM, &pStats->StatR3Emulate, STAMTYPE_PROFILE, "/EM/R3/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
170
171 STAM_REG(pVM, &pStats->StatRZInterpretSucceeded, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
172 STAM_REG(pVM, &pStats->StatR3InterpretSucceeded, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
173
174 STAM_REG_USED(pVM, &pStats->StatRZAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
175 STAM_REG_USED(pVM, &pStats->StatR3And, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
176 STAM_REG_USED(pVM, &pStats->StatRZAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
177 STAM_REG_USED(pVM, &pStats->StatR3Add, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
178 STAM_REG_USED(pVM, &pStats->StatRZAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
179 STAM_REG_USED(pVM, &pStats->StatR3Adc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
180 STAM_REG_USED(pVM, &pStats->StatRZSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
181 STAM_REG_USED(pVM, &pStats->StatR3Sub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
182 STAM_REG_USED(pVM, &pStats->StatRZCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
183 STAM_REG_USED(pVM, &pStats->StatR3CpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
184 STAM_REG_USED(pVM, &pStats->StatRZDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
185 STAM_REG_USED(pVM, &pStats->StatR3Dec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
186 STAM_REG_USED(pVM, &pStats->StatRZHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
187 STAM_REG_USED(pVM, &pStats->StatR3Hlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
188 STAM_REG_USED(pVM, &pStats->StatRZInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
189 STAM_REG_USED(pVM, &pStats->StatR3Inc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
190 STAM_REG_USED(pVM, &pStats->StatRZInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
191 STAM_REG_USED(pVM, &pStats->StatR3InvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
192 STAM_REG_USED(pVM, &pStats->StatRZIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
193 STAM_REG_USED(pVM, &pStats->StatR3Iret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
194 STAM_REG_USED(pVM, &pStats->StatRZLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
195 STAM_REG_USED(pVM, &pStats->StatR3LLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
196 STAM_REG_USED(pVM, &pStats->StatRZLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
197 STAM_REG_USED(pVM, &pStats->StatR3LIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
198 STAM_REG_USED(pVM, &pStats->StatRZLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
199 STAM_REG_USED(pVM, &pStats->StatR3LGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
200 STAM_REG_USED(pVM, &pStats->StatRZMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
201 STAM_REG_USED(pVM, &pStats->StatR3Mov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
202 STAM_REG_USED(pVM, &pStats->StatRZMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
203 STAM_REG_USED(pVM, &pStats->StatR3MovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
204 STAM_REG_USED(pVM, &pStats->StatRZMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
205 STAM_REG_USED(pVM, &pStats->StatR3MovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
206 STAM_REG_USED(pVM, &pStats->StatRZOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
207 STAM_REG_USED(pVM, &pStats->StatR3Or, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
208 STAM_REG_USED(pVM, &pStats->StatRZPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
209 STAM_REG_USED(pVM, &pStats->StatR3Pop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
210 STAM_REG_USED(pVM, &pStats->StatRZRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
211 STAM_REG_USED(pVM, &pStats->StatR3Rdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
212 STAM_REG_USED(pVM, &pStats->StatRZSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
213 STAM_REG_USED(pVM, &pStats->StatR3Sti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
214 STAM_REG_USED(pVM, &pStats->StatRZXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
215 STAM_REG_USED(pVM, &pStats->StatR3Xchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
216 STAM_REG_USED(pVM, &pStats->StatRZXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
217 STAM_REG_USED(pVM, &pStats->StatR3Xor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
218 STAM_REG_USED(pVM, &pStats->StatRZMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
219 STAM_REG_USED(pVM, &pStats->StatR3Monitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
220 STAM_REG_USED(pVM, &pStats->StatRZMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
221 STAM_REG_USED(pVM, &pStats->StatR3MWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
222 STAM_REG_USED(pVM, &pStats->StatRZBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
223 STAM_REG_USED(pVM, &pStats->StatR3Btr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
224 STAM_REG_USED(pVM, &pStats->StatRZBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
225 STAM_REG_USED(pVM, &pStats->StatR3Bts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
226 STAM_REG_USED(pVM, &pStats->StatRZBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
227 STAM_REG_USED(pVM, &pStats->StatR3Btc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
228 STAM_REG_USED(pVM, &pStats->StatRZCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
229 STAM_REG_USED(pVM, &pStats->StatR3CmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
230 STAM_REG_USED(pVM, &pStats->StatRZCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
231 STAM_REG_USED(pVM, &pStats->StatR3CmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
232 STAM_REG_USED(pVM, &pStats->StatRZXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
233 STAM_REG_USED(pVM, &pStats->StatR3XAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
234 STAM_REG_USED(pVM, &pStats->StatR3Rdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
235 STAM_REG_USED(pVM, &pStats->StatRZRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
236 STAM_REG_USED(pVM, &pStats->StatR3Wrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
237 STAM_REG_USED(pVM, &pStats->StatRZWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
238 STAM_REG_USED(pVM, &pStats->StatR3StosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
239 STAM_REG_USED(pVM, &pStats->StatRZStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
240 STAM_REG_USED(pVM, &pStats->StatRZWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
241 STAM_REG_USED(pVM, &pStats->StatR3WbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
242 STAM_REG_USED(pVM, &pStats->StatRZLmsw, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was successfully interpreted.");
243 STAM_REG_USED(pVM, &pStats->StatR3Lmsw, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was successfully interpreted.");
244
245 STAM_REG(pVM, &pStats->StatRZInterpretFailed, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
246 STAM_REG(pVM, &pStats->StatR3InterpretFailed, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
247
248 STAM_REG_USED(pVM, &pStats->StatRZFailedAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
249 STAM_REG_USED(pVM, &pStats->StatR3FailedAnd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
250 STAM_REG_USED(pVM, &pStats->StatRZFailedCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
251 STAM_REG_USED(pVM, &pStats->StatR3FailedCpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
252 STAM_REG_USED(pVM, &pStats->StatRZFailedDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
253 STAM_REG_USED(pVM, &pStats->StatR3FailedDec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
254 STAM_REG_USED(pVM, &pStats->StatRZFailedHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
255 STAM_REG_USED(pVM, &pStats->StatR3FailedHlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
256 STAM_REG_USED(pVM, &pStats->StatRZFailedInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
257 STAM_REG_USED(pVM, &pStats->StatR3FailedInc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
258 STAM_REG_USED(pVM, &pStats->StatRZFailedInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
259 STAM_REG_USED(pVM, &pStats->StatR3FailedInvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
260 STAM_REG_USED(pVM, &pStats->StatRZFailedIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
261 STAM_REG_USED(pVM, &pStats->StatR3FailedIret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
262 STAM_REG_USED(pVM, &pStats->StatRZFailedLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
263 STAM_REG_USED(pVM, &pStats->StatR3FailedLLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
264 STAM_REG_USED(pVM, &pStats->StatRZFailedLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
265 STAM_REG_USED(pVM, &pStats->StatR3FailedLIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
266 STAM_REG_USED(pVM, &pStats->StatRZFailedLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
267 STAM_REG_USED(pVM, &pStats->StatR3FailedLGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
268 STAM_REG_USED(pVM, &pStats->StatRZFailedMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
269 STAM_REG_USED(pVM, &pStats->StatR3FailedMov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
270 STAM_REG_USED(pVM, &pStats->StatRZFailedMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
271 STAM_REG_USED(pVM, &pStats->StatR3FailedMovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
272 STAM_REG_USED(pVM, &pStats->StatRZFailedMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
273 STAM_REG_USED(pVM, &pStats->StatR3FailedMovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
274 STAM_REG_USED(pVM, &pStats->StatRZFailedOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
275 STAM_REG_USED(pVM, &pStats->StatR3FailedOr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
276 STAM_REG_USED(pVM, &pStats->StatRZFailedPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
277 STAM_REG_USED(pVM, &pStats->StatR3FailedPop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
278 STAM_REG_USED(pVM, &pStats->StatRZFailedSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
279 STAM_REG_USED(pVM, &pStats->StatR3FailedSti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
280 STAM_REG_USED(pVM, &pStats->StatRZFailedXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
281 STAM_REG_USED(pVM, &pStats->StatR3FailedXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
282 STAM_REG_USED(pVM, &pStats->StatRZFailedXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
283 STAM_REG_USED(pVM, &pStats->StatR3FailedXor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
284 STAM_REG_USED(pVM, &pStats->StatRZFailedMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
285 STAM_REG_USED(pVM, &pStats->StatR3FailedMonitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
286 STAM_REG_USED(pVM, &pStats->StatRZFailedMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
287 STAM_REG_USED(pVM, &pStats->StatR3FailedMWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
288 STAM_REG_USED(pVM, &pStats->StatRZFailedRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
289 STAM_REG_USED(pVM, &pStats->StatR3FailedRdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
290 STAM_REG_USED(pVM, &pStats->StatRZFailedRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
291 STAM_REG_USED(pVM, &pStats->StatR3FailedRdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
292 STAM_REG_USED(pVM, &pStats->StatRZFailedWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
293 STAM_REG_USED(pVM, &pStats->StatR3FailedWrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
294 STAM_REG_USED(pVM, &pStats->StatRZFailedLmsw, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was not interpreted.");
295 STAM_REG_USED(pVM, &pStats->StatR3FailedLmsw, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was not interpreted.");
296
297 STAM_REG_USED(pVM, &pStats->StatRZFailedMisc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
298 STAM_REG_USED(pVM, &pStats->StatR3FailedMisc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
299 STAM_REG_USED(pVM, &pStats->StatRZFailedAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
300 STAM_REG_USED(pVM, &pStats->StatR3FailedAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
301 STAM_REG_USED(pVM, &pStats->StatRZFailedAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
302 STAM_REG_USED(pVM, &pStats->StatR3FailedAdc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
303 STAM_REG_USED(pVM, &pStats->StatRZFailedBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
304 STAM_REG_USED(pVM, &pStats->StatR3FailedBtr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
305 STAM_REG_USED(pVM, &pStats->StatRZFailedBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
306 STAM_REG_USED(pVM, &pStats->StatR3FailedBts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
307 STAM_REG_USED(pVM, &pStats->StatRZFailedBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
308 STAM_REG_USED(pVM, &pStats->StatR3FailedBtc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
309 STAM_REG_USED(pVM, &pStats->StatRZFailedCli, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
310 STAM_REG_USED(pVM, &pStats->StatR3FailedCli, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
311 STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
312 STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
313 STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
314 STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
315 STAM_REG_USED(pVM, &pStats->StatRZFailedXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
316 STAM_REG_USED(pVM, &pStats->StatR3FailedXAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
317 STAM_REG_USED(pVM, &pStats->StatRZFailedMovNTPS, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
318 STAM_REG_USED(pVM, &pStats->StatR3FailedMovNTPS, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
319 STAM_REG_USED(pVM, &pStats->StatRZFailedStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
320 STAM_REG_USED(pVM, &pStats->StatR3FailedStosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
321 STAM_REG_USED(pVM, &pStats->StatRZFailedSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
322 STAM_REG_USED(pVM, &pStats->StatR3FailedSub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
323 STAM_REG_USED(pVM, &pStats->StatRZFailedWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
324 STAM_REG_USED(pVM, &pStats->StatR3FailedWbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
325
326 STAM_REG_USED(pVM, &pStats->StatRZFailedUserMode, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
327 STAM_REG_USED(pVM, &pStats->StatR3FailedUserMode, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
328 STAM_REG_USED(pVM, &pStats->StatRZFailedPrefix, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
329 STAM_REG_USED(pVM, &pStats->StatR3FailedPrefix, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
330
331 STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
332 STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
333 STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/R3/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
334 STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
335 STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
336 STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
337 STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
338 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
339 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
340 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
341 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
342 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
343 STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
344 STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
345 STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
346 STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
347 STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
348 STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/R3/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
349 STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
350 STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
351 STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
352 STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
353 STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
354 STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
355 STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
356 STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
357
358 STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
359 pVM->em.s.pCliStatTree = 0;
360#endif /* VBOX_WITH_STATISTICS */
361
362 /* these should be considered for release statistics. */
363 STAM_REL_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
364 STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
365 STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
366 STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
367
368 STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
369 STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
370 STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
371 STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
372 STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
373 STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
374 STAM_REL_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
375 STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
376 STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
377 STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
378 STAM_REL_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
379 STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
380
381
382 return VINF_SUCCESS;
383}
384
385
386/**
387 * Initializes the per-VCPU EM.
388 *
389 * @returns VBox status code.
390 * @param pVM The VM to operate on.
391 */
392VMMR3DECL(int) EMR3InitCPU(PVM pVM)
393{
394 LogFlow(("EMR3InitCPU\n"));
395 return VINF_SUCCESS;
396}
397
398
399/**
400 * Applies relocations to data and code managed by this
401 * component. This function will be called at init and
402 * whenever the VMM need to relocate it self inside the GC.
403 *
404 * @param pVM The VM.
405 */
406VMMR3DECL(void) EMR3Relocate(PVM pVM)
407{
408 LogFlow(("EMR3Relocate\n"));
409 if (pVM->em.s.pStatsR3)
410 pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVM->em.s.pStatsR3);
411}
412
413
414/**
415 * Reset notification.
416 *
417 * @param pVM
418 */
419VMMR3DECL(void) EMR3Reset(PVM pVM)
420{
421 LogFlow(("EMR3Reset: \n"));
422 pVM->em.s.fForceRAW = false;
423}
424
425
426/**
427 * Terminates the EM.
428 *
429 * Termination means cleaning up and freeing all resources,
430 * the VM it self is at this point powered off or suspended.
431 *
432 * @returns VBox status code.
433 * @param pVM The VM to operate on.
434 */
435VMMR3DECL(int) EMR3Term(PVM pVM)
436{
437 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
438
439 return VINF_SUCCESS;
440}
441
442/**
443 * Terminates the per-VCPU EM.
444 *
445 * Termination means cleaning up and freeing all resources,
446 * the VM it self is at this point powered off or suspended.
447 *
448 * @returns VBox status code.
449 * @param pVM The VM to operate on.
450 */
451VMMR3DECL(int) EMR3TermCPU(PVM pVM)
452{
453 return 0;
454}
455
456/**
457 * Execute state save operation.
458 *
459 * @returns VBox status code.
460 * @param pVM VM Handle.
461 * @param pSSM SSM operation handle.
462 */
463static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
464{
465 return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
466}
467
468
469/**
470 * Execute state load operation.
471 *
472 * @returns VBox status code.
473 * @param pVM VM Handle.
474 * @param pSSM SSM operation handle.
475 * @param u32Version Data layout version.
476 */
477static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
478{
479 /*
480 * Validate version.
481 */
482 if (u32Version != EM_SAVED_STATE_VERSION)
483 {
484 AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
485 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
486 }
487
488 /*
489 * Load the saved state.
490 */
491 int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
492 if (RT_FAILURE(rc))
493 pVM->em.s.fForceRAW = false;
494
495 Assert(!pVM->em.s.pCliStatTree);
496 return rc;
497}
498
499
500/**
501 * Enables or disables a set of raw-mode execution modes.
502 *
503 * @returns VINF_SUCCESS on success.
504 * @returns VINF_RESCHEDULE if a rescheduling might be required.
505 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
506 *
507 * @param pVM The VM to operate on.
508 * @param enmMode The execution mode change.
509 * @thread The emulation thread.
510 */
511VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
512{
513 switch (enmMode)
514 {
515 case EMRAW_NONE:
516 pVM->fRawR3Enabled = false;
517 pVM->fRawR0Enabled = false;
518 break;
519 case EMRAW_RING3_ENABLE:
520 pVM->fRawR3Enabled = true;
521 break;
522 case EMRAW_RING3_DISABLE:
523 pVM->fRawR3Enabled = false;
524 break;
525 case EMRAW_RING0_ENABLE:
526 pVM->fRawR0Enabled = true;
527 break;
528 case EMRAW_RING0_DISABLE:
529 pVM->fRawR0Enabled = false;
530 break;
531 default:
532 AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
533 return VERR_INVALID_PARAMETER;
534 }
535 Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
536 pVM->fRawR3Enabled, pVM->fRawR0Enabled));
537 return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
538}
539
540
541/**
542 * Raise a fatal error.
543 *
544 * Safely terminate the VM with full state report and stuff. This function
545 * will naturally never return.
546 *
547 * @param pVM VM handle.
548 * @param rc VBox status code.
549 */
550VMMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
551{
552 longjmp(pVM->em.s.u.FatalLongJump, rc);
553 AssertReleaseMsgFailed(("longjmp returned!\n"));
554}
555
556
557/**
558 * Gets the EM state name.
559 *
560 * @returns pointer to read only state name,
561 * @param enmState The state.
562 */
563VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
564{
565 switch (enmState)
566 {
567 case EMSTATE_NONE: return "EMSTATE_NONE";
568 case EMSTATE_RAW: return "EMSTATE_RAW";
569 case EMSTATE_HWACC: return "EMSTATE_HWACC";
570 case EMSTATE_REM: return "EMSTATE_REM";
571 case EMSTATE_PARAV: return "EMSTATE_PARAV";
572 case EMSTATE_HALTED: return "EMSTATE_HALTED";
573 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
574 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
575 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
576 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
577 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
578 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
579 default: return "Unknown!";
580 }
581}
582
583
584#ifdef VBOX_WITH_STATISTICS
585/**
586 * Just a braindead function to keep track of cli addresses.
587 * @param pVM VM handle.
588 * @param GCPtrInstr The EIP of the cli instruction.
589 */
590static void emR3RecordCli(PVM pVM, RTGCPTR GCPtrInstr)
591{
592 PCLISTAT pRec;
593
594 pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)GCPtrInstr);
595 if (!pRec)
596 {
597 /* New cli instruction; insert into the tree. */
598 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
599 Assert(pRec);
600 if (!pRec)
601 return;
602 pRec->Core.Key = (AVLPVKEY)GCPtrInstr;
603
604 char szCliStatName[32];
605 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
606 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
607
608 bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
609 Assert(fRc); NOREF(fRc);
610 }
611 STAM_COUNTER_INC(&pRec->Counter);
612 STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
613}
614#endif /* VBOX_WITH_STATISTICS */
615
616
617/**
618 * Debug loop.
619 *
620 * @returns VBox status code for EM.
621 * @param pVM VM handle.
622 * @param rc Current EM VBox status code..
623 */
624static int emR3Debug(PVM pVM, int rc)
625{
626 for (;;)
627 {
628 Log(("emR3Debug: rc=%Rrc\n", rc));
629 const int rcLast = rc;
630
631 /*
632 * Debug related RC.
633 */
634 switch (rc)
635 {
636 /*
637 * Single step an instruction.
638 */
639 case VINF_EM_DBG_STEP:
640 if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
641 || pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
642 || pVM->em.s.fForceRAW /* paranoia */)
643 rc = emR3RawStep(pVM);
644 else
645 {
646 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
647 rc = emR3RemStep(pVM);
648 }
649 break;
650
651 /*
652 * Simple events: stepped, breakpoint, stop/assertion.
653 */
654 case VINF_EM_DBG_STEPPED:
655 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
656 break;
657
658 case VINF_EM_DBG_BREAKPOINT:
659 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
660 break;
661
662 case VINF_EM_DBG_STOP:
663 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
664 break;
665
666 case VINF_EM_DBG_HYPER_STEPPED:
667 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
668 break;
669
670 case VINF_EM_DBG_HYPER_BREAKPOINT:
671 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
672 break;
673
674 case VINF_EM_DBG_HYPER_ASSERTION:
675 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
676 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
677 break;
678
679 /*
680 * Guru meditation.
681 */
682 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
683 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
684 break;
685 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
686 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
687 break;
688
689 default: /** @todo don't use default for guru, but make special errors code! */
690 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
691 break;
692 }
693
694 /*
695 * Process the result.
696 */
697 do
698 {
699 switch (rc)
700 {
701 /*
702 * Continue the debugging loop.
703 */
704 case VINF_EM_DBG_STEP:
705 case VINF_EM_DBG_STOP:
706 case VINF_EM_DBG_STEPPED:
707 case VINF_EM_DBG_BREAKPOINT:
708 case VINF_EM_DBG_HYPER_STEPPED:
709 case VINF_EM_DBG_HYPER_BREAKPOINT:
710 case VINF_EM_DBG_HYPER_ASSERTION:
711 break;
712
713 /*
714 * Resuming execution (in some form) has to be done here if we got
715 * a hypervisor debug event.
716 */
717 case VINF_SUCCESS:
718 case VINF_EM_RESUME:
719 case VINF_EM_SUSPEND:
720 case VINF_EM_RESCHEDULE:
721 case VINF_EM_RESCHEDULE_RAW:
722 case VINF_EM_RESCHEDULE_REM:
723 case VINF_EM_HALT:
724 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
725 {
726 rc = emR3RawResumeHyper(pVM);
727 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
728 continue;
729 }
730 if (rc == VINF_SUCCESS)
731 rc = VINF_EM_RESCHEDULE;
732 return rc;
733
734 /*
735 * The debugger isn't attached.
736 * We'll simply turn the thing off since that's the easiest thing to do.
737 */
738 case VERR_DBGF_NOT_ATTACHED:
739 switch (rcLast)
740 {
741 case VINF_EM_DBG_HYPER_STEPPED:
742 case VINF_EM_DBG_HYPER_BREAKPOINT:
743 case VINF_EM_DBG_HYPER_ASSERTION:
744 case VERR_TRPM_PANIC:
745 case VERR_TRPM_DONT_PANIC:
746 case VERR_VMM_RING0_ASSERTION:
747 return rcLast;
748 }
749 return VINF_EM_OFF;
750
751 /*
752 * Status codes terminating the VM in one or another sense.
753 */
754 case VINF_EM_TERMINATE:
755 case VINF_EM_OFF:
756 case VINF_EM_RESET:
757 case VINF_EM_RAW_STALE_SELECTOR:
758 case VINF_EM_RAW_IRET_TRAP:
759 case VERR_TRPM_PANIC:
760 case VERR_TRPM_DONT_PANIC:
761 case VERR_VMM_RING0_ASSERTION:
762 case VERR_INTERNAL_ERROR:
763 return rc;
764
765 /*
766 * The rest is unexpected, and will keep us here.
767 */
768 default:
769 AssertMsgFailed(("Unxpected rc %Rrc!\n", rc));
770 break;
771 }
772 } while (false);
773 } /* debug for ever */
774}
775
776
777/**
778 * Steps recompiled code.
779 *
780 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
781 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
782 *
783 * @param pVM VM handle.
784 */
785static int emR3RemStep(PVM pVM)
786{
787 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
788
789 /*
790 * Switch to REM, step instruction, switch back.
791 */
792 int rc = REMR3State(pVM);
793 if (RT_SUCCESS(rc))
794 {
795 rc = REMR3Step(pVM);
796 REMR3StateBack(pVM);
797 }
798 LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
799 return rc;
800}
801
802
803/**
804 * Executes recompiled code.
805 *
806 * This function contains the recompiler version of the inner
807 * execution loop (the outer loop being in EMR3ExecuteVM()).
808 *
809 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
810 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
811 *
812 * @param pVM VM handle.
813 * @param pfFFDone Where to store an indicator telling wheter or not
814 * FFs were done before returning.
815 *
816 */
817static int emR3RemExecute(PVM pVM, bool *pfFFDone)
818{
819#ifdef LOG_ENABLED
820 PCPUMCTX pCtx = pVM->em.s.pCtx;
821 uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
822
823 if (pCtx->eflags.Bits.u1VM)
824 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
825 else
826 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
827#endif
828 STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
829
830#if defined(VBOX_STRICT) && defined(DEBUG_bird)
831 AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
832 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
833 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
834#endif
835
836 /*
837 * Spin till we get a forced action which returns anything but VINF_SUCCESS
838 * or the REM suggests raw-mode execution.
839 */
840 *pfFFDone = false;
841 bool fInREMState = false;
842 int rc = VINF_SUCCESS;
843 for (;;)
844 {
845 /*
846 * Update REM state if not already in sync.
847 */
848 if (!fInREMState)
849 {
850 STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
851 rc = REMR3State(pVM);
852 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
853 if (RT_FAILURE(rc))
854 break;
855 fInREMState = true;
856
857 /*
858 * We might have missed the raising of VMREQ, TIMER and some other
859 * imporant FFs while we were busy switching the state. So, check again.
860 */
861 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_TIMER | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_RESET))
862 {
863 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
864 goto l_REMDoForcedActions;
865 }
866 }
867
868
869 /*
870 * Execute REM.
871 */
872 STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
873 rc = REMR3Run(pVM);
874 STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
875
876
877 /*
878 * Deal with high priority post execution FFs before doing anything else.
879 */
880 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
881 rc = emR3HighPriorityPostForcedActions(pVM, rc);
882
883 /*
884 * Process the returned status code.
885 * (Try keep this short! Call functions!)
886 */
887 if (rc != VINF_SUCCESS)
888 {
889 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
890 break;
891 if (rc != VINF_REM_INTERRUPED_FF)
892 {
893 /*
894 * Anything which is not known to us means an internal error
895 * and the termination of the VM!
896 */
897 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
898 break;
899 }
900 }
901
902
903 /*
904 * Check and execute forced actions.
905 * Sync back the VM state before calling any of these.
906 */
907#ifdef VBOX_HIGH_RES_TIMERS_HACK
908 TMTimerPoll(pVM);
909#endif
910 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION | VM_FF_CSAM_SCAN_PAGE)))
911 {
912l_REMDoForcedActions:
913 if (fInREMState)
914 {
915 STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
916 REMR3StateBack(pVM);
917 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
918 fInREMState = false;
919 }
920 STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
921 rc = emR3ForcedActions(pVM, rc);
922 STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
923 if ( rc != VINF_SUCCESS
924 && rc != VINF_EM_RESCHEDULE_REM)
925 {
926 *pfFFDone = true;
927 break;
928 }
929 }
930
931 } /* The Inner Loop, recompiled execution mode version. */
932
933
934 /*
935 * Returning. Sync back the VM state if required.
936 */
937 if (fInREMState)
938 {
939 STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
940 REMR3StateBack(pVM);
941 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
942 }
943
944 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
945 return rc;
946}
947
948
949/**
950 * Resumes executing hypervisor after a debug event.
951 *
952 * This is kind of special since our current guest state is
953 * potentially out of sync.
954 *
955 * @returns VBox status code.
956 * @param pVM The VM handle.
957 */
958static int emR3RawResumeHyper(PVM pVM)
959{
960 int rc;
961 PCPUMCTX pCtx = pVM->em.s.pCtx;
962 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
963 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
964
965 /*
966 * Resume execution.
967 */
968 CPUMRawEnter(pVM, NULL);
969 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_RF);
970 rc = VMMR3ResumeHyper(pVM);
971 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
972 rc = CPUMRawLeave(pVM, NULL, rc);
973 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
974
975 /*
976 * Deal with the return code.
977 */
978 rc = emR3HighPriorityPostForcedActions(pVM, rc);
979 rc = emR3RawHandleRC(pVM, pCtx, rc);
980 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
981 return rc;
982}
983
984
985/**
986 * Steps rawmode.
987 *
988 * @returns VBox status code.
989 * @param pVM The VM handle.
990 */
991static int emR3RawStep(PVM pVM)
992{
993 Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
994 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
995 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
996 int rc;
997 PCPUMCTX pCtx = pVM->em.s.pCtx;
998 bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
999#ifndef DEBUG_sandervl
1000 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
1001 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
1002#endif
1003 if (fGuest)
1004 {
1005 /*
1006 * Check vital forced actions, but ignore pending interrupts and timers.
1007 */
1008 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1009 {
1010 rc = emR3RawForcedActions(pVM, pCtx);
1011 if (RT_FAILURE(rc))
1012 return rc;
1013 }
1014
1015 /*
1016 * Set flags for single stepping.
1017 */
1018 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
1019 }
1020 else
1021 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
1022
1023 /*
1024 * Single step.
1025 * We do not start time or anything, if anything we should just do a few nanoseconds.
1026 */
1027 CPUMRawEnter(pVM, NULL);
1028 do
1029 {
1030 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
1031 rc = VMMR3ResumeHyper(pVM);
1032 else
1033 rc = VMMR3RawRunGC(pVM);
1034#ifndef DEBUG_sandervl
1035 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
1036 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
1037#endif
1038 } while ( rc == VINF_SUCCESS
1039 || rc == VINF_EM_RAW_INTERRUPT);
1040 rc = CPUMRawLeave(pVM, NULL, rc);
1041 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1042
1043 /*
1044 * Make sure the trap flag is cleared.
1045 * (Too bad if the guest is trying to single step too.)
1046 */
1047 if (fGuest)
1048 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1049 else
1050 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
1051
1052 /*
1053 * Deal with the return codes.
1054 */
1055 rc = emR3HighPriorityPostForcedActions(pVM, rc);
1056 rc = emR3RawHandleRC(pVM, pCtx, rc);
1057 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1058 return rc;
1059}
1060
1061
1062#ifdef DEBUG
1063
1064/**
1065 * Steps hardware accelerated mode.
1066 *
1067 * @returns VBox status code.
1068 * @param pVM The VM handle.
1069 * @param idCpu VMCPU id.
1070 */
1071static int emR3HwAccStep(PVM pVM, RTCPUID idCpu)
1072{
1073 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1074
1075 int rc;
1076 PCPUMCTX pCtx = pVM->em.s.pCtx;
1077 VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_TSS));
1078
1079 /*
1080 * Check vital forced actions, but ignore pending interrupts and timers.
1081 */
1082 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1083 {
1084 rc = emR3RawForcedActions(pVM, pCtx);
1085 if (RT_FAILURE(rc))
1086 return rc;
1087 }
1088 /*
1089 * Set flags for single stepping.
1090 */
1091 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
1092
1093 /*
1094 * Single step.
1095 * We do not start time or anything, if anything we should just do a few nanoseconds.
1096 */
1097 do
1098 {
1099 rc = VMMR3HwAccRunGC(pVM, idCpu);
1100 } while ( rc == VINF_SUCCESS
1101 || rc == VINF_EM_RAW_INTERRUPT);
1102 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1103
1104 /*
1105 * Make sure the trap flag is cleared.
1106 * (Too bad if the guest is trying to single step too.)
1107 */
1108 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1109
1110 /*
1111 * Deal with the return codes.
1112 */
1113 rc = emR3HighPriorityPostForcedActions(pVM, rc);
1114 rc = emR3RawHandleRC(pVM, pCtx, rc);
1115 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1116 return rc;
1117}
1118
1119
1120void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1121{
1122 EMSTATE enmOldState = pVM->em.s.enmState;
1123
1124 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1125
1126 Log(("Single step BEGIN:\n"));
1127 for (uint32_t i = 0; i < cIterations; i++)
1128 {
1129 DBGFR3PrgStep(pVM);
1130 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1131 emR3RawStep(pVM);
1132 }
1133 Log(("Single step END:\n"));
1134 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1135 pVM->em.s.enmState = enmOldState;
1136}
1137
1138
1139static int emR3SingleStepExecHwAcc(PVM pVM, RTCPUID idCpu, uint32_t cIterations)
1140{
1141 EMSTATE enmOldState = pVM->em.s.enmState;
1142
1143 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1144
1145 Log(("Single step BEGIN:\n"));
1146 for (uint32_t i = 0; i < cIterations; i++)
1147 {
1148 DBGFR3PrgStep(pVM);
1149 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1150 emR3HwAccStep(pVM, idCpu);
1151 if (!HWACCMR3CanExecuteGuest(pVM, pVM->em.s.pCtx))
1152 break;
1153 }
1154 Log(("Single step END:\n"));
1155 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1156 pVM->em.s.enmState = enmOldState;
1157 return VINF_EM_RESCHEDULE_REM;
1158}
1159
1160
1161static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1162{
1163 EMSTATE enmOldState = pVM->em.s.enmState;
1164
1165 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1166
1167 Log(("Single step BEGIN:\n"));
1168 for (uint32_t i = 0; i < cIterations; i++)
1169 {
1170 DBGFR3PrgStep(pVM);
1171 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1172 emR3RemStep(pVM);
1173 if (emR3Reschedule(pVM, pVM->em.s.pCtx) != EMSTATE_REM)
1174 break;
1175 }
1176 Log(("Single step END:\n"));
1177 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1178 pVM->em.s.enmState = enmOldState;
1179 return VINF_EM_RESCHEDULE;
1180}
1181
1182#endif /* DEBUG */
1183
1184
1185/**
1186 * Executes one (or perhaps a few more) instruction(s).
1187 *
1188 * @returns VBox status code suitable for EM.
1189 *
1190 * @param pVM VM handle.
1191 * @param rcGC GC return code
1192 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1193 * instruction and prefix the log output with this text.
1194 */
1195#ifdef LOG_ENABLED
1196static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1197#else
1198static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1199#endif
1200{
1201 PCPUMCTX pCtx = pVM->em.s.pCtx;
1202 int rc;
1203
1204 /*
1205 *
1206 * The simple solution is to use the recompiler.
1207 * The better solution is to disassemble the current instruction and
1208 * try handle as many as possible without using REM.
1209 *
1210 */
1211
1212#ifdef LOG_ENABLED
1213 /*
1214 * Disassemble the instruction if requested.
1215 */
1216 if (pszPrefix)
1217 {
1218 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1219 DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1220 }
1221#endif /* LOG_ENABLED */
1222
1223 /*
1224 * PATM is making life more interesting.
1225 * We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1226 * tell PATM there is a trap in this code and have it take the appropriate actions
1227 * to allow us execute the code in REM.
1228 */
1229 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1230 {
1231 Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
1232
1233 RTGCPTR pNewEip;
1234 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1235 switch (rc)
1236 {
1237 /*
1238 * It's not very useful to emulate a single instruction and then go back to raw
1239 * mode; just execute the whole block until IF is set again.
1240 */
1241 case VINF_SUCCESS:
1242 Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
1243 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1244 pCtx->eip = pNewEip;
1245 Assert(pCtx->eip);
1246
1247 if (pCtx->eflags.Bits.u1IF)
1248 {
1249 /*
1250 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1251 */
1252 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1253 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1254 }
1255 else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1256 {
1257 /* special case: iret, that sets IF, detected a pending irq/event */
1258 return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1259 }
1260 return VINF_EM_RESCHEDULE_REM;
1261
1262 /*
1263 * One instruction.
1264 */
1265 case VINF_PATCH_EMULATE_INSTR:
1266 Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1267 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1268 pCtx->eip = pNewEip;
1269 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1270
1271 /*
1272 * The patch was disabled, hand it to the REM.
1273 */
1274 case VERR_PATCH_DISABLED:
1275 Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
1276 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1277 pCtx->eip = pNewEip;
1278 if (pCtx->eflags.Bits.u1IF)
1279 {
1280 /*
1281 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1282 */
1283 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1284 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1285 }
1286 return VINF_EM_RESCHEDULE_REM;
1287
1288 /* Force continued patch exection; usually due to write monitored stack. */
1289 case VINF_PATCH_CONTINUE:
1290 return VINF_SUCCESS;
1291
1292 default:
1293 AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
1294 return VERR_INTERNAL_ERROR;
1295 }
1296 }
1297
1298#if 0
1299 /* Try our own instruction emulator before falling back to the recompiler. */
1300 DISCPUSTATE Cpu;
1301 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1302 if (RT_SUCCESS(rc))
1303 {
1304 uint32_t size;
1305
1306 switch (Cpu.pCurInstr->opcode)
1307 {
1308 /* @todo we can do more now */
1309 case OP_MOV:
1310 case OP_AND:
1311 case OP_OR:
1312 case OP_XOR:
1313 case OP_POP:
1314 case OP_INC:
1315 case OP_DEC:
1316 case OP_XCHG:
1317 STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1318 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1319 if (RT_SUCCESS(rc))
1320 {
1321 pCtx->rip += Cpu.opsize;
1322#ifdef EM_NOTIFY_HWACCM
1323 if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1324 HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
1325#endif
1326 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1327 return rc;
1328 }
1329 if (rc != VERR_EM_INTERPRETER)
1330 AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
1331 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1332 break;
1333 }
1334 }
1335#endif /* 0 */
1336 STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1337 rc = REMR3EmulateInstruction(pVM);
1338 STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1339
1340#ifdef EM_NOTIFY_HWACCM
1341 if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1342 HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
1343#endif
1344 return rc;
1345}
1346
1347
1348/**
1349 * Executes one (or perhaps a few more) instruction(s).
1350 * This is just a wrapper for discarding pszPrefix in non-logging builds.
1351 *
1352 * @returns VBox status code suitable for EM.
1353 * @param pVM VM handle.
1354 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1355 * instruction and prefix the log output with this text.
1356 * @param rcGC GC return code
1357 */
1358DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1359{
1360#ifdef LOG_ENABLED
1361 return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1362#else
1363 return emR3RawExecuteInstructionWorker(pVM, rcGC);
1364#endif
1365}
1366
1367/**
1368 * Executes one (or perhaps a few more) IO instruction(s).
1369 *
1370 * @returns VBox status code suitable for EM.
1371 * @param pVM VM handle.
1372 */
1373int emR3RawExecuteIOInstruction(PVM pVM)
1374{
1375 int rc;
1376 PCPUMCTX pCtx = pVM->em.s.pCtx;
1377
1378 STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1379
1380 /** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1381 * as io instructions tend to come in packages of more than one
1382 */
1383 DISCPUSTATE Cpu;
1384 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "IO EMU");
1385 if (RT_SUCCESS(rc))
1386 {
1387 rc = VINF_EM_RAW_EMULATE_INSTR;
1388
1389 if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE)))
1390 {
1391 switch (Cpu.pCurInstr->opcode)
1392 {
1393 case OP_IN:
1394 {
1395 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1396 rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1397 break;
1398 }
1399
1400 case OP_OUT:
1401 {
1402 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1403 rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1404 break;
1405 }
1406 }
1407 }
1408 else if (Cpu.prefix & PREFIX_REP)
1409 {
1410 switch (Cpu.pCurInstr->opcode)
1411 {
1412 case OP_INSB:
1413 case OP_INSWD:
1414 {
1415 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1416 rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1417 break;
1418 }
1419
1420 case OP_OUTSB:
1421 case OP_OUTSWD:
1422 {
1423 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1424 rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1425 break;
1426 }
1427 }
1428 }
1429
1430 /*
1431 * Handled the I/O return codes.
1432 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1433 */
1434 if (IOM_SUCCESS(rc))
1435 {
1436 pCtx->rip += Cpu.opsize;
1437 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1438 return rc;
1439 }
1440
1441 if (rc == VINF_EM_RAW_GUEST_TRAP)
1442 {
1443 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1444 rc = emR3RawGuestTrap(pVM);
1445 return rc;
1446 }
1447 AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1448
1449 if (RT_FAILURE(rc))
1450 {
1451 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1452 return rc;
1453 }
1454 AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RESCHEDULE_REM, ("rc=%Rrc\n", rc));
1455 }
1456 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1457 return emR3RawExecuteInstruction(pVM, "IO: ");
1458}
1459
1460
1461/**
1462 * Handle a guest context trap.
1463 *
1464 * @returns VBox status code suitable for EM.
1465 * @param pVM VM handle.
1466 */
1467static int emR3RawGuestTrap(PVM pVM)
1468{
1469 PCPUMCTX pCtx = pVM->em.s.pCtx;
1470
1471 /*
1472 * Get the trap info.
1473 */
1474 uint8_t u8TrapNo;
1475 TRPMEVENT enmType;
1476 RTGCUINT uErrorCode;
1477 RTGCUINTPTR uCR2;
1478 int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1479 if (RT_FAILURE(rc))
1480 {
1481 AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
1482 return rc;
1483 }
1484
1485 /*
1486 * Traps can be directly forwarded in hardware accelerated mode.
1487 */
1488 if (HWACCMR3IsActive(pVM))
1489 {
1490#ifdef LOGGING_ENABLED
1491 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1492 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1493#endif
1494 return VINF_EM_RESCHEDULE_HWACC;
1495 }
1496
1497#if 1 /* Experimental: Review, disable if it causes trouble. */
1498 /*
1499 * Handle traps in patch code first.
1500 *
1501 * We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
1502 * but several traps isn't handled specially by TRPM in RC and we end up here
1503 * instead. One example is #DE.
1504 */
1505 uint32_t uCpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
1506 if ( uCpl == 0
1507 && PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1508 {
1509 LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
1510 return emR3PatchTrap(pVM, pCtx, rc);
1511 }
1512#endif
1513
1514 /*
1515 * If the guest gate is marked unpatched, then we will check again if we can patch it.
1516 * (This assumes that we've already tried and failed to dispatch the trap in
1517 * RC for the gates that already has been patched. Which is true for most high
1518 * volume traps, because these are handled specially, but not for odd ones like #DE.)
1519 */
1520 if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
1521 {
1522 CSAMR3CheckGates(pVM, u8TrapNo, 1);
1523 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
1524
1525 /* If it was successful, then we could go back to raw mode. */
1526 if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
1527 {
1528 /* Must check pending forced actions as our IDT or GDT might be out of sync. */
1529 rc = EMR3CheckRawForcedActions(pVM);
1530 AssertRCReturn(rc, rc);
1531
1532 TRPMERRORCODE enmError = uErrorCode != ~0U
1533 ? TRPM_TRAP_HAS_ERRORCODE
1534 : TRPM_TRAP_NO_ERRORCODE;
1535 rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
1536 if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1537 {
1538 TRPMResetTrap(pVM);
1539 return VINF_EM_RESCHEDULE_RAW;
1540 }
1541 AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
1542 }
1543 }
1544
1545 /*
1546 * Scan kernel code that traps; we might not get another chance.
1547 */
1548 /** @todo move this up before the dispatching? */
1549 if ( (pCtx->ss & X86_SEL_RPL) <= 1
1550 && !pCtx->eflags.Bits.u1VM)
1551 {
1552 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1553 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1554 }
1555
1556 /*
1557 * Trap specific handling.
1558 */
1559 if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1560 {
1561 /*
1562 * If MONITOR & MWAIT are supported, then interpret them here.
1563 */
1564 DISCPUSTATE cpu;
1565 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1566 if ( RT_SUCCESS(rc)
1567 && (cpu.pCurInstr->opcode == OP_MONITOR || cpu.pCurInstr->opcode == OP_MWAIT))
1568 {
1569 uint32_t u32Dummy, u32Features, u32ExtFeatures;
1570 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1571 if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1572 {
1573 rc = TRPMResetTrap(pVM);
1574 AssertRC(rc);
1575
1576 uint32_t opsize;
1577 rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
1578 if (RT_SUCCESS(rc))
1579 {
1580 pCtx->rip += cpu.opsize;
1581#ifdef EM_NOTIFY_HWACCM
1582 if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1583 HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
1584#endif
1585 return rc;
1586 }
1587 return emR3RawExecuteInstruction(pVM, "Monitor: ");
1588 }
1589 }
1590 }
1591 else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1592 {
1593 /*
1594 * Handle I/O bitmap?
1595 */
1596 /** @todo We're not supposed to be here with a false guest trap concerning
1597 * I/O access. We can easily handle those in RC. */
1598 DISCPUSTATE cpu;
1599 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1600 if ( RT_SUCCESS(rc)
1601 && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1602 {
1603 /*
1604 * We should really check the TSS for the IO bitmap, but it's not like this
1605 * lazy approach really makes things worse.
1606 */
1607 rc = TRPMResetTrap(pVM);
1608 AssertRC(rc);
1609 return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1610 }
1611 }
1612
1613#ifdef LOG_ENABLED
1614 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1615 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1616
1617 /* Get guest page information. */
1618 uint64_t fFlags = 0;
1619 RTGCPHYS GCPhys = 0;
1620 int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1621 Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1622 pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1623 fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1624 fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1625#endif
1626
1627 /*
1628 * #PG has CR2.
1629 * (Because of stuff like above we must set CR2 in a delayed fashion.)
1630 */
1631 if (u8TrapNo == 14 /* #PG */)
1632 pCtx->cr2 = uCR2;
1633
1634 return VINF_EM_RESCHEDULE_REM;
1635}
1636
1637
1638/**
1639 * Handle a ring switch trap.
1640 * Need to do statistics and to install patches. The result is going to REM.
1641 *
1642 * @returns VBox status code suitable for EM.
1643 * @param pVM VM handle.
1644 */
1645int emR3RawRingSwitch(PVM pVM)
1646{
1647 int rc;
1648 DISCPUSTATE Cpu;
1649 PCPUMCTX pCtx = pVM->em.s.pCtx;
1650
1651 /*
1652 * sysenter, syscall & callgate
1653 */
1654 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1655 if (RT_SUCCESS(rc))
1656 {
1657 if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1658 {
1659 if (pCtx->SysEnter.cs != 0)
1660 {
1661 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1662 (SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1663 if (RT_SUCCESS(rc))
1664 {
1665 DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1666 return VINF_EM_RESCHEDULE_RAW;
1667 }
1668 }
1669 }
1670
1671#ifdef VBOX_WITH_STATISTICS
1672 switch (Cpu.pCurInstr->opcode)
1673 {
1674 case OP_SYSENTER:
1675 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysEnter);
1676 break;
1677 case OP_SYSEXIT:
1678 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysExit);
1679 break;
1680 case OP_SYSCALL:
1681 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysCall);
1682 break;
1683 case OP_SYSRET:
1684 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysRet);
1685 break;
1686 }
1687#endif
1688 }
1689 else
1690 AssertRC(rc);
1691
1692 /* go to the REM to emulate a single instruction */
1693 return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1694}
1695
1696
1697/**
1698 * Handle a trap (\#PF or \#GP) in patch code
1699 *
1700 * @returns VBox status code suitable for EM.
1701 * @param pVM VM handle.
1702 * @param pCtx CPU context
1703 * @param gcret GC return code
1704 */
1705static int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1706{
1707 uint8_t u8TrapNo;
1708 int rc;
1709 TRPMEVENT enmType;
1710 RTGCUINT uErrorCode;
1711 RTGCUINTPTR uCR2;
1712
1713 Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1714
1715 if (gcret == VINF_PATM_PATCH_INT3)
1716 {
1717 u8TrapNo = 3;
1718 uCR2 = 0;
1719 uErrorCode = 0;
1720 }
1721 else if (gcret == VINF_PATM_PATCH_TRAP_GP)
1722 {
1723 /* No active trap in this case. Kind of ugly. */
1724 u8TrapNo = X86_XCPT_GP;
1725 uCR2 = 0;
1726 uErrorCode = 0;
1727 }
1728 else
1729 {
1730 rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1731 if (RT_FAILURE(rc))
1732 {
1733 AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
1734 return rc;
1735 }
1736 /* Reset the trap as we'll execute the original instruction again. */
1737 TRPMResetTrap(pVM);
1738 }
1739
1740 /*
1741 * Deal with traps inside patch code.
1742 * (This code won't run outside GC.)
1743 */
1744 if (u8TrapNo != 1)
1745 {
1746#ifdef LOG_ENABLED
1747 DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1748 DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1749
1750 DISCPUSTATE Cpu;
1751 int rc;
1752
1753 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1754 if ( RT_SUCCESS(rc)
1755 && Cpu.pCurInstr->opcode == OP_IRET)
1756 {
1757 uint32_t eip, selCS, uEFlags;
1758
1759 /* Iret crashes are bad as we have already changed the flags on the stack */
1760 rc = PGMPhysSimpleReadGCPtr(pVM, &eip, pCtx->esp, 4);
1761 rc |= PGMPhysSimpleReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1762 rc |= PGMPhysSimpleReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1763 if (rc == VINF_SUCCESS)
1764 {
1765 if ( (uEFlags & X86_EFL_VM)
1766 || (selCS & X86_SEL_RPL) == 3)
1767 {
1768 uint32_t selSS, esp;
1769
1770 rc |= PGMPhysSimpleReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1771 rc |= PGMPhysSimpleReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1772
1773 if (uEFlags & X86_EFL_VM)
1774 {
1775 uint32_t selDS, selES, selFS, selGS;
1776 rc = PGMPhysSimpleReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1777 rc |= PGMPhysSimpleReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1778 rc |= PGMPhysSimpleReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1779 rc |= PGMPhysSimpleReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1780 if (rc == VINF_SUCCESS)
1781 {
1782 Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1783 Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1784 }
1785 }
1786 else
1787 Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1788 }
1789 else
1790 Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
1791 }
1792 }
1793#endif /* LOG_ENABLED */
1794 Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1795 pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1796
1797 RTGCPTR pNewEip;
1798 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1799 switch (rc)
1800 {
1801 /*
1802 * Execute the faulting instruction.
1803 */
1804 case VINF_SUCCESS:
1805 {
1806 /** @todo execute a whole block */
1807 Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
1808 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1809 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1810
1811 pCtx->eip = pNewEip;
1812 AssertRelease(pCtx->eip);
1813
1814 if (pCtx->eflags.Bits.u1IF)
1815 {
1816 /* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1817 * int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1818 */
1819 if ( u8TrapNo == X86_XCPT_GP
1820 && PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1821 {
1822 /** @todo move to PATMR3HandleTrap */
1823 Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
1824 PATMR3RemovePatch(pVM, pCtx->eip);
1825 }
1826
1827 /** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1828 /* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
1829
1830 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1831 /* Interrupts are enabled; just go back to the original instruction.
1832 return VINF_SUCCESS; */
1833 }
1834 return VINF_EM_RESCHEDULE_REM;
1835 }
1836
1837 /*
1838 * One instruction.
1839 */
1840 case VINF_PATCH_EMULATE_INSTR:
1841 Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1842 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1843 pCtx->eip = pNewEip;
1844 AssertRelease(pCtx->eip);
1845 return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1846
1847 /*
1848 * The patch was disabled, hand it to the REM.
1849 */
1850 case VERR_PATCH_DISABLED:
1851 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1852 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1853 pCtx->eip = pNewEip;
1854 AssertRelease(pCtx->eip);
1855
1856 if (pCtx->eflags.Bits.u1IF)
1857 {
1858 /*
1859 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1860 */
1861 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1862 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1863 }
1864 return VINF_EM_RESCHEDULE_REM;
1865
1866 /* Force continued patch exection; usually due to write monitored stack. */
1867 case VINF_PATCH_CONTINUE:
1868 return VINF_SUCCESS;
1869
1870 /*
1871 * Anything else is *fatal*.
1872 */
1873 default:
1874 AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
1875 return VERR_INTERNAL_ERROR;
1876 }
1877 }
1878 return VINF_SUCCESS;
1879}
1880
1881
1882/**
1883 * Handle a privileged instruction.
1884 *
1885 * @returns VBox status code suitable for EM.
1886 * @param pVM VM handle.
1887 */
1888int emR3RawPrivileged(PVM pVM)
1889{
1890 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1891 PCPUMCTX pCtx = pVM->em.s.pCtx;
1892
1893 Assert(!pCtx->eflags.Bits.u1VM);
1894
1895 if (PATMIsEnabled(pVM))
1896 {
1897 /*
1898 * Check if in patch code.
1899 */
1900 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1901 {
1902#ifdef LOG_ENABLED
1903 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1904#endif
1905 AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1906 return VERR_EM_RAW_PATCH_CONFLICT;
1907 }
1908 if ( (pCtx->ss & X86_SEL_RPL) == 0
1909 && !pCtx->eflags.Bits.u1VM
1910 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
1911 {
1912 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1913 (SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1914 if (RT_SUCCESS(rc))
1915 {
1916#ifdef LOG_ENABLED
1917 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1918#endif
1919 DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1920 return VINF_SUCCESS;
1921 }
1922 }
1923 }
1924
1925#ifdef LOG_ENABLED
1926 if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1927 {
1928 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1929 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1930 }
1931#endif
1932
1933 /*
1934 * Instruction statistics and logging.
1935 */
1936 DISCPUSTATE Cpu;
1937 int rc;
1938
1939 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1940 if (RT_SUCCESS(rc))
1941 {
1942#ifdef VBOX_WITH_STATISTICS
1943 PEMSTATS pStats = pVM->em.s.CTX_SUFF(pStats);
1944 switch (Cpu.pCurInstr->opcode)
1945 {
1946 case OP_INVLPG:
1947 STAM_COUNTER_INC(&pStats->StatInvlpg);
1948 break;
1949 case OP_IRET:
1950 STAM_COUNTER_INC(&pStats->StatIret);
1951 break;
1952 case OP_CLI:
1953 STAM_COUNTER_INC(&pStats->StatCli);
1954 emR3RecordCli(pVM, pCtx->rip);
1955 break;
1956 case OP_STI:
1957 STAM_COUNTER_INC(&pStats->StatSti);
1958 break;
1959 case OP_INSB:
1960 case OP_INSWD:
1961 case OP_IN:
1962 case OP_OUTSB:
1963 case OP_OUTSWD:
1964 case OP_OUT:
1965 AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1966 break;
1967
1968 case OP_MOV_CR:
1969 if (Cpu.param1.flags & USE_REG_GEN32)
1970 {
1971 //read
1972 Assert(Cpu.param2.flags & USE_REG_CR);
1973 Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1974 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1975 }
1976 else
1977 {
1978 //write
1979 Assert(Cpu.param1.flags & USE_REG_CR);
1980 Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1981 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1982 }
1983 break;
1984
1985 case OP_MOV_DR:
1986 STAM_COUNTER_INC(&pStats->StatMovDRx);
1987 break;
1988 case OP_LLDT:
1989 STAM_COUNTER_INC(&pStats->StatMovLldt);
1990 break;
1991 case OP_LIDT:
1992 STAM_COUNTER_INC(&pStats->StatMovLidt);
1993 break;
1994 case OP_LGDT:
1995 STAM_COUNTER_INC(&pStats->StatMovLgdt);
1996 break;
1997 case OP_SYSENTER:
1998 STAM_COUNTER_INC(&pStats->StatSysEnter);
1999 break;
2000 case OP_SYSEXIT:
2001 STAM_COUNTER_INC(&pStats->StatSysExit);
2002 break;
2003 case OP_SYSCALL:
2004 STAM_COUNTER_INC(&pStats->StatSysCall);
2005 break;
2006 case OP_SYSRET:
2007 STAM_COUNTER_INC(&pStats->StatSysRet);
2008 break;
2009 case OP_HLT:
2010 STAM_COUNTER_INC(&pStats->StatHlt);
2011 break;
2012 default:
2013 STAM_COUNTER_INC(&pStats->StatMisc);
2014 Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
2015 break;
2016 }
2017#endif /* VBOX_WITH_STATISTICS */
2018 if ( (pCtx->ss & X86_SEL_RPL) == 0
2019 && !pCtx->eflags.Bits.u1VM
2020 && SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
2021 {
2022 uint32_t size;
2023
2024 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
2025 switch (Cpu.pCurInstr->opcode)
2026 {
2027 case OP_CLI:
2028 pCtx->eflags.u32 &= ~X86_EFL_IF;
2029 Assert(Cpu.opsize == 1);
2030 pCtx->rip += Cpu.opsize;
2031 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2032 return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
2033
2034 case OP_STI:
2035 pCtx->eflags.u32 |= X86_EFL_IF;
2036 EMSetInhibitInterruptsPC(pVM, pCtx->rip + Cpu.opsize);
2037 Assert(Cpu.opsize == 1);
2038 pCtx->rip += Cpu.opsize;
2039 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2040 return VINF_SUCCESS;
2041
2042 case OP_HLT:
2043 if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
2044 {
2045 PATMTRANSSTATE enmState;
2046 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
2047
2048 if (enmState == PATMTRANS_OVERWRITTEN)
2049 {
2050 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2051 Assert(rc == VERR_PATCH_DISABLED);
2052 /* Conflict detected, patch disabled */
2053 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
2054
2055 enmState = PATMTRANS_SAFE;
2056 }
2057
2058 /* The translation had better be successful. Otherwise we can't recover. */
2059 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
2060 if (enmState != PATMTRANS_OVERWRITTEN)
2061 pCtx->eip = pOrgInstrGC;
2062 }
2063 /* no break; we could just return VINF_EM_HALT here */
2064
2065 case OP_MOV_CR:
2066 case OP_MOV_DR:
2067#ifdef LOG_ENABLED
2068 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2069 {
2070 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2071 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2072 }
2073#endif
2074
2075 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2076 if (RT_SUCCESS(rc))
2077 {
2078 pCtx->rip += Cpu.opsize;
2079#ifdef EM_NOTIFY_HWACCM
2080 if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
2081 HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
2082#endif
2083 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2084
2085 if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2086 && Cpu.param1.flags == USE_REG_CR /* write */
2087 )
2088 {
2089 /* Deal with CR0 updates inside patch code that force
2090 * us to go to the recompiler.
2091 */
2092 if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
2093 && (pCtx->cr0 & (X86_CR0_WP|X86_CR0_PG|X86_CR0_PE)) != (X86_CR0_WP|X86_CR0_PG|X86_CR0_PE))
2094 {
2095 PATMTRANSSTATE enmState;
2096 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
2097
2098 Assert(pCtx->eflags.Bits.u1IF == 0);
2099 Log(("Force recompiler switch due to cr0 (%RGp) update\n", pCtx->cr0));
2100 if (enmState == PATMTRANS_OVERWRITTEN)
2101 {
2102 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2103 Assert(rc == VERR_PATCH_DISABLED);
2104 /* Conflict detected, patch disabled */
2105 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
2106 enmState = PATMTRANS_SAFE;
2107 }
2108 /* The translation had better be successful. Otherwise we can't recover. */
2109 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
2110 if (enmState != PATMTRANS_OVERWRITTEN)
2111 pCtx->rip = pOrgInstrGC;
2112 }
2113
2114 /* Reschedule is necessary as the execution/paging mode might have changed. */
2115 return VINF_EM_RESCHEDULE;
2116 }
2117 return rc; /* can return VINF_EM_HALT as well. */
2118 }
2119 AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
2120 break; /* fall back to the recompiler */
2121 }
2122 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2123 }
2124 }
2125
2126 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2127 return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
2128
2129 return emR3RawExecuteInstruction(pVM, "PRIV");
2130}
2131
2132
2133/**
2134 * Update the forced rawmode execution modifier.
2135 *
2136 * This function is called when we're returning from the raw-mode loop(s). If we're
2137 * in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2138 * if not in patch code, the flag will be cleared.
2139 *
2140 * We should never interrupt patch code while it's being executed. Cli patches can
2141 * contain big code blocks, but they are always executed with IF=0. Other patches
2142 * replace single instructions and should be atomic.
2143 *
2144 * @returns Updated rc.
2145 *
2146 * @param pVM The VM handle.
2147 * @param pCtx The guest CPU context.
2148 * @param rc The result code.
2149 */
2150DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2151{
2152 if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2153 {
2154 /* ignore reschedule attempts. */
2155 switch (rc)
2156 {
2157 case VINF_EM_RESCHEDULE:
2158 case VINF_EM_RESCHEDULE_REM:
2159 rc = VINF_SUCCESS;
2160 break;
2161 }
2162 pVM->em.s.fForceRAW = true;
2163 }
2164 else
2165 pVM->em.s.fForceRAW = false;
2166 return rc;
2167}
2168
2169
2170/**
2171 * Process a subset of the raw-mode return code.
2172 *
2173 * Since we have to share this with raw-mode single stepping, this inline
2174 * function has been created to avoid code duplication.
2175 *
2176 * @returns VINF_SUCCESS if it's ok to continue raw mode.
2177 * @returns VBox status code to return to the EM main loop.
2178 *
2179 * @param pVM The VM handle
2180 * @param rc The return code.
2181 * @param pCtx The guest cpu context.
2182 */
2183DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2184{
2185 switch (rc)
2186 {
2187 /*
2188 * Common & simple ones.
2189 */
2190 case VINF_SUCCESS:
2191 break;
2192 case VINF_EM_RESCHEDULE_RAW:
2193 case VINF_EM_RESCHEDULE_HWACC:
2194 case VINF_EM_RAW_INTERRUPT:
2195 case VINF_EM_RAW_TO_R3:
2196 case VINF_EM_RAW_TIMER_PENDING:
2197 case VINF_EM_PENDING_REQUEST:
2198 rc = VINF_SUCCESS;
2199 break;
2200
2201 /*
2202 * Privileged instruction.
2203 */
2204 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2205 case VINF_PATM_PATCH_TRAP_GP:
2206 rc = emR3RawPrivileged(pVM);
2207 break;
2208
2209 /*
2210 * Got a trap which needs dispatching.
2211 */
2212 case VINF_EM_RAW_GUEST_TRAP:
2213 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2214 {
2215 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2216 rc = VERR_EM_RAW_PATCH_CONFLICT;
2217 break;
2218 }
2219 rc = emR3RawGuestTrap(pVM);
2220 break;
2221
2222 /*
2223 * Trap in patch code.
2224 */
2225 case VINF_PATM_PATCH_TRAP_PF:
2226 case VINF_PATM_PATCH_INT3:
2227 rc = emR3PatchTrap(pVM, pCtx, rc);
2228 break;
2229
2230 case VINF_PATM_DUPLICATE_FUNCTION:
2231 Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2232 rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2233 AssertRC(rc);
2234 rc = VINF_SUCCESS;
2235 break;
2236
2237 case VINF_PATM_CHECK_PATCH_PAGE:
2238 rc = PATMR3HandleMonitoredPage(pVM);
2239 AssertRC(rc);
2240 rc = VINF_SUCCESS;
2241 break;
2242
2243 /*
2244 * Patch manager.
2245 */
2246 case VERR_EM_RAW_PATCH_CONFLICT:
2247 AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
2248 break;
2249
2250#ifdef VBOX_WITH_VMI
2251 /*
2252 * PARAV function.
2253 */
2254 case VINF_EM_RESCHEDULE_PARAV:
2255 rc = PARAVCallFunction(pVM);
2256 break;
2257#endif
2258
2259 /*
2260 * Memory mapped I/O access - attempt to patch the instruction
2261 */
2262 case VINF_PATM_HC_MMIO_PATCH_READ:
2263 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2264 PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2265 if (RT_FAILURE(rc))
2266 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2267 break;
2268
2269 case VINF_PATM_HC_MMIO_PATCH_WRITE:
2270 AssertFailed(); /* not yet implemented. */
2271 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2272 break;
2273
2274 /*
2275 * Conflict or out of page tables.
2276 *
2277 * VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2278 * do here is to execute the pending forced actions.
2279 */
2280 case VINF_PGM_SYNC_CR3:
2281 AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2282 ("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2283 rc = VINF_SUCCESS;
2284 break;
2285
2286 /*
2287 * Paging mode change.
2288 */
2289 case VINF_PGM_CHANGE_MODE:
2290 rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2291 if (RT_SUCCESS(rc))
2292 rc = VINF_EM_RESCHEDULE;
2293 break;
2294
2295 /*
2296 * CSAM wants to perform a task in ring-3. It has set an FF action flag.
2297 */
2298 case VINF_CSAM_PENDING_ACTION:
2299 rc = VINF_SUCCESS;
2300 break;
2301
2302 /*
2303 * Invoked Interrupt gate - must directly (!) go to the recompiler.
2304 */
2305 case VINF_EM_RAW_INTERRUPT_PENDING:
2306 case VINF_EM_RAW_RING_SWITCH_INT:
2307 Assert(TRPMHasTrap(pVM));
2308 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2309
2310 if (TRPMHasTrap(pVM))
2311 {
2312 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2313 uint8_t u8Interrupt = TRPMGetTrapNo(pVM);
2314 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2315 {
2316 CSAMR3CheckGates(pVM, u8Interrupt, 1);
2317 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2318 /* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2319 }
2320 }
2321 rc = VINF_EM_RESCHEDULE_REM;
2322 break;
2323
2324 /*
2325 * Other ring switch types.
2326 */
2327 case VINF_EM_RAW_RING_SWITCH:
2328 rc = emR3RawRingSwitch(pVM);
2329 break;
2330
2331 /*
2332 * REMGCNotifyInvalidatePage() failed because of overflow.
2333 */
2334 case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2335 Assert((pCtx->ss & X86_SEL_RPL) != 1);
2336 REMR3ReplayInvalidatedPages(pVM);
2337 rc = VINF_SUCCESS;
2338 break;
2339
2340 /*
2341 * I/O Port access - emulate the instruction.
2342 */
2343 case VINF_IOM_HC_IOPORT_READ:
2344 case VINF_IOM_HC_IOPORT_WRITE:
2345 rc = emR3RawExecuteIOInstruction(pVM);
2346 break;
2347
2348 /*
2349 * Memory mapped I/O access - emulate the instruction.
2350 */
2351 case VINF_IOM_HC_MMIO_READ:
2352 case VINF_IOM_HC_MMIO_WRITE:
2353 case VINF_IOM_HC_MMIO_READ_WRITE:
2354 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2355 break;
2356
2357 /*
2358 * Execute instruction.
2359 */
2360 case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2361 rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2362 break;
2363 case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2364 rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2365 break;
2366 case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2367 rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2368 break;
2369 case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2370 rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2371 break;
2372 case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2373 rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2374 break;
2375
2376 case VINF_EM_RAW_EMULATE_INSTR_HLT:
2377 /** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2378 rc = emR3RawPrivileged(pVM);
2379 break;
2380
2381 case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2382 rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2383 break;
2384
2385 case VINF_EM_RAW_EMULATE_INSTR:
2386 case VINF_PATCH_EMULATE_INSTR:
2387 rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2388 break;
2389
2390 /*
2391 * Stale selector and iret traps => REM.
2392 */
2393 case VINF_EM_RAW_STALE_SELECTOR:
2394 case VINF_EM_RAW_IRET_TRAP:
2395 /* We will not go to the recompiler if EIP points to patch code. */
2396 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2397 {
2398 pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2399 }
2400 LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
2401 rc = VINF_EM_RESCHEDULE_REM;
2402 break;
2403
2404 /*
2405 * Up a level.
2406 */
2407 case VINF_EM_TERMINATE:
2408 case VINF_EM_OFF:
2409 case VINF_EM_RESET:
2410 case VINF_EM_SUSPEND:
2411 case VINF_EM_HALT:
2412 case VINF_EM_RESUME:
2413 case VINF_EM_RESCHEDULE:
2414 case VINF_EM_RESCHEDULE_REM:
2415 break;
2416
2417 /*
2418 * Up a level and invoke the debugger.
2419 */
2420 case VINF_EM_DBG_STEPPED:
2421 case VINF_EM_DBG_BREAKPOINT:
2422 case VINF_EM_DBG_STEP:
2423 case VINF_EM_DBG_HYPER_BREAKPOINT:
2424 case VINF_EM_DBG_HYPER_STEPPED:
2425 case VINF_EM_DBG_HYPER_ASSERTION:
2426 case VINF_EM_DBG_STOP:
2427 break;
2428
2429 /*
2430 * Up a level, dump and debug.
2431 */
2432 case VERR_TRPM_DONT_PANIC:
2433 case VERR_TRPM_PANIC:
2434 case VERR_VMM_RING0_ASSERTION:
2435 break;
2436
2437 /*
2438 * Up a level, after HwAccM have done some release logging.
2439 */
2440 case VERR_VMX_INVALID_VMCS_FIELD:
2441 case VERR_VMX_INVALID_VMCS_PTR:
2442 case VERR_VMX_INVALID_VMXON_PTR:
2443 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2444 case VERR_VMX_UNEXPECTED_EXCEPTION:
2445 case VERR_VMX_UNEXPECTED_EXIT_CODE:
2446 case VERR_VMX_INVALID_GUEST_STATE:
2447 case VERR_VMX_UNABLE_TO_START_VM:
2448 case VERR_VMX_UNABLE_TO_RESUME_VM:
2449 HWACCMR3CheckError(pVM, rc);
2450 break;
2451 /*
2452 * Anything which is not known to us means an internal error
2453 * and the termination of the VM!
2454 */
2455 default:
2456 AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
2457 break;
2458 }
2459 return rc;
2460}
2461
2462
2463/**
2464 * Check for pending raw actions
2465 *
2466 * @returns VBox status code.
2467 * @param pVM The VM to operate on.
2468 */
2469VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2470{
2471 return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2472}
2473
2474
2475/**
2476 * Process raw-mode specific forced actions.
2477 *
2478 * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2479 *
2480 * @returns VBox status code.
2481 * Only the normal success/failure stuff, no VINF_EM_*.
2482 * @param pVM The VM handle.
2483 * @param pCtx The guest CPUM register context.
2484 */
2485static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2486{
2487 /*
2488 * Note that the order is *vitally* important!
2489 * Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2490 */
2491
2492
2493 /*
2494 * Sync selector tables.
2495 */
2496 if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT))
2497 {
2498 int rc = SELMR3UpdateFromCPUM(pVM);
2499 if (RT_FAILURE(rc))
2500 return rc;
2501 }
2502
2503 /*
2504 * Sync IDT.
2505 */
2506 if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2507 {
2508 int rc = TRPMR3SyncIDT(pVM);
2509 if (RT_FAILURE(rc))
2510 return rc;
2511 }
2512
2513 /*
2514 * Sync TSS.
2515 */
2516 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2517 {
2518 int rc = SELMR3SyncTSS(pVM);
2519 if (RT_FAILURE(rc))
2520 return rc;
2521 }
2522
2523 /*
2524 * Sync page directory.
2525 */
2526 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2527 {
2528 int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2529 if (RT_FAILURE(rc))
2530 return rc;
2531
2532 Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT));
2533
2534 /* Prefetch pages for EIP and ESP */
2535 /** @todo This is rather expensive. Should investigate if it really helps at all. */
2536 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2537 if (rc == VINF_SUCCESS)
2538 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2539 if (rc != VINF_SUCCESS)
2540 {
2541 if (rc != VINF_PGM_SYNC_CR3)
2542 return rc;
2543 rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2544 if (RT_FAILURE(rc))
2545 return rc;
2546 }
2547 /** @todo maybe prefetch the supervisor stack page as well */
2548 }
2549
2550 /*
2551 * Allocate handy pages (just in case the above actions have consumed some pages).
2552 */
2553 if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
2554 {
2555 int rc = PGMR3PhysAllocateHandyPages(pVM);
2556 if (RT_FAILURE(rc))
2557 return rc;
2558 }
2559
2560 return VINF_SUCCESS;
2561}
2562
2563
2564/**
2565 * Executes raw code.
2566 *
2567 * This function contains the raw-mode version of the inner
2568 * execution loop (the outer loop being in EMR3ExecuteVM()).
2569 *
2570 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2571 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2572 *
2573 * @param pVM VM handle.
2574 * @param pfFFDone Where to store an indicator telling whether or not
2575 * FFs were done before returning.
2576 */
2577static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2578{
2579 STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2580
2581 int rc = VERR_INTERNAL_ERROR;
2582 PCPUMCTX pCtx = pVM->em.s.pCtx;
2583 LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2584 pVM->em.s.fForceRAW = false;
2585 *pfFFDone = false;
2586
2587
2588 /*
2589 *
2590 * Spin till we get a forced action or raw mode status code resulting in
2591 * in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2592 *
2593 */
2594 for (;;)
2595 {
2596 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2597
2598 /*
2599 * Check various preconditions.
2600 */
2601#ifdef VBOX_STRICT
2602 Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2603 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) == 3 || (pCtx->ss & X86_SEL_RPL) == 0);
2604 AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2605 || PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2606 ("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2607 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2608 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2609 {
2610 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2611 return VERR_INTERNAL_ERROR;
2612 }
2613#endif /* VBOX_STRICT */
2614
2615 /*
2616 * Process high priority pre-execution raw-mode FFs.
2617 */
2618 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2619 {
2620 rc = emR3RawForcedActions(pVM, pCtx);
2621 if (RT_FAILURE(rc))
2622 break;
2623 }
2624
2625 /*
2626 * If we're going to execute ring-0 code, the guest state needs to
2627 * be modified a bit and some of the state components (IF, SS/CS RPL,
2628 * and perhaps EIP) needs to be stored with PATM.
2629 */
2630 rc = CPUMRawEnter(pVM, NULL);
2631 if (rc != VINF_SUCCESS)
2632 {
2633 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2634 break;
2635 }
2636
2637 /*
2638 * Scan code before executing it. Don't bother with user mode or V86 code
2639 */
2640 if ( (pCtx->ss & X86_SEL_RPL) <= 1
2641 && !pCtx->eflags.Bits.u1VM
2642 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
2643 {
2644 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2645 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2646 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2647 }
2648
2649#ifdef LOG_ENABLED
2650 /*
2651 * Log important stuff before entering GC.
2652 */
2653 PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2654 if (pCtx->eflags.Bits.u1VM)
2655 Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2656 else if ((pCtx->ss & X86_SEL_RPL) == 1)
2657 {
2658 bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2659 Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2660 }
2661 else if ((pCtx->ss & X86_SEL_RPL) == 3)
2662 Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2663#endif /* LOG_ENABLED */
2664
2665
2666
2667 /*
2668 * Execute the code.
2669 */
2670 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2671 STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2672 VMMR3Unlock(pVM);
2673 rc = VMMR3RawRunGC(pVM);
2674 VMMR3Lock(pVM);
2675 STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2676 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2677
2678 LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2679 LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
2680
2681
2682
2683 /*
2684 * Restore the real CPU state and deal with high priority post
2685 * execution FFs before doing anything else.
2686 */
2687 rc = CPUMRawLeave(pVM, NULL, rc);
2688 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2689 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2690 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2691
2692#ifdef VBOX_STRICT
2693 /*
2694 * Assert TSS consistency & rc vs patch code.
2695 */
2696 if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS | VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2697 && EMIsRawRing0Enabled(pVM))
2698 SELMR3CheckTSS(pVM);
2699 switch (rc)
2700 {
2701 case VINF_SUCCESS:
2702 case VINF_EM_RAW_INTERRUPT:
2703 case VINF_PATM_PATCH_TRAP_PF:
2704 case VINF_PATM_PATCH_TRAP_GP:
2705 case VINF_PATM_PATCH_INT3:
2706 case VINF_PATM_CHECK_PATCH_PAGE:
2707 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2708 case VINF_EM_RAW_GUEST_TRAP:
2709 case VINF_EM_RESCHEDULE_RAW:
2710 break;
2711
2712 default:
2713 if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2714 LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVM), rc));
2715 break;
2716 }
2717 /*
2718 * Let's go paranoid!
2719 */
2720 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2721 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2722 {
2723 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2724 return VERR_INTERNAL_ERROR;
2725 }
2726#endif /* VBOX_STRICT */
2727
2728 /*
2729 * Process the returned status code.
2730 */
2731 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2732 {
2733 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2734 break;
2735 }
2736 rc = emR3RawHandleRC(pVM, pCtx, rc);
2737 if (rc != VINF_SUCCESS)
2738 {
2739 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2740 if (rc != VINF_SUCCESS)
2741 {
2742 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2743 break;
2744 }
2745 }
2746
2747 /*
2748 * Check and execute forced actions.
2749 */
2750#ifdef VBOX_HIGH_RES_TIMERS_HACK
2751 TMTimerPoll(pVM);
2752#endif
2753 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2754 if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2755 {
2756 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) != 1);
2757
2758 STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2759 rc = emR3ForcedActions(pVM, rc);
2760 STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2761 if ( rc != VINF_SUCCESS
2762 && rc != VINF_EM_RESCHEDULE_RAW)
2763 {
2764 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2765 if (rc != VINF_SUCCESS)
2766 {
2767 *pfFFDone = true;
2768 break;
2769 }
2770 }
2771 }
2772 }
2773
2774 /*
2775 * Return to outer loop.
2776 */
2777#if defined(LOG_ENABLED) && defined(DEBUG)
2778 RTLogFlush(NULL);
2779#endif
2780 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2781 return rc;
2782}
2783
2784
2785/**
2786 * Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2787 *
2788 * This function contains the raw-mode version of the inner
2789 * execution loop (the outer loop being in EMR3ExecuteVM()).
2790 *
2791 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2792 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2793 *
2794 * @param pVM VM handle.
2795 * @param idCpu VMCPU id.
2796 * @param pfFFDone Where to store an indicator telling whether or not
2797 * FFs were done before returning.
2798 */
2799static int emR3HwAccExecute(PVM pVM, RTCPUID idCpu, bool *pfFFDone)
2800{
2801 int rc = VERR_INTERNAL_ERROR;
2802 PCPUMCTX pCtx = pVM->em.s.pCtx;
2803
2804 LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
2805 *pfFFDone = false;
2806
2807 STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2808
2809#ifdef EM_NOTIFY_HWACCM
2810 HWACCMR3NotifyScheduled(&pVM->aCpus[idCpu]);
2811#endif
2812
2813 /*
2814 * Spin till we get a forced action which returns anything but VINF_SUCCESS.
2815 */
2816 for (;;)
2817 {
2818 STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2819
2820 /*
2821 * Check various preconditions.
2822 */
2823 VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_TSS));
2824
2825 /*
2826 * Process high priority pre-execution raw-mode FFs.
2827 */
2828 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2829 {
2830 rc = emR3RawForcedActions(pVM, pCtx);
2831 if (RT_FAILURE(rc))
2832 break;
2833 }
2834
2835#ifdef LOG_ENABLED
2836 /*
2837 * Log important stuff before entering GC.
2838 */
2839 if (TRPMHasTrap(pVM))
2840 Log(("Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", TRPMGetTrapNo(pVM), pCtx->cs, (RTGCPTR)pCtx->rip));
2841
2842 uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2843 if (pCtx->eflags.Bits.u1VM)
2844 Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2845 else if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
2846 Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2847 else
2848 Log(("HWR%d: %04X:%08X ESP=%08X IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2849#endif /* LOG_ENABLED */
2850
2851 /*
2852 * Execute the code.
2853 */
2854 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2855 STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2856 VMMR3Unlock(pVM);
2857 rc = VMMR3HwAccRunGC(pVM, idCpu);
2858 VMMR3Lock(pVM);
2859 STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2860
2861 /*
2862 * Deal with high priority post execution FFs before doing anything else.
2863 */
2864 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2865 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2866 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2867
2868 /*
2869 * Process the returned status code.
2870 */
2871 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2872 break;
2873
2874 rc = emR3RawHandleRC(pVM, pCtx, rc);
2875 if (rc != VINF_SUCCESS)
2876 break;
2877
2878 /*
2879 * Check and execute forced actions.
2880 */
2881#ifdef VBOX_HIGH_RES_TIMERS_HACK
2882 TMTimerPoll(pVM);
2883#endif
2884 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2885 {
2886 rc = emR3ForcedActions(pVM, rc);
2887 if ( rc != VINF_SUCCESS
2888 && rc != VINF_EM_RESCHEDULE_HWACC)
2889 {
2890 *pfFFDone = true;
2891 break;
2892 }
2893 }
2894 }
2895
2896 /*
2897 * Return to outer loop.
2898 */
2899#if defined(LOG_ENABLED) && defined(DEBUG)
2900 RTLogFlush(NULL);
2901#endif
2902 return rc;
2903}
2904
2905
2906/**
2907 * Decides whether to execute RAW, HWACC or REM.
2908 *
2909 * @returns new EM state
2910 * @param pVM The VM.
2911 * @param pCtx The CPU context.
2912 */
2913static EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2914{
2915 /*
2916 * When forcing raw-mode execution, things are simple.
2917 */
2918 if (pVM->em.s.fForceRAW)
2919 return EMSTATE_RAW;
2920
2921 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2922 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2923 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2924
2925 X86EFLAGS EFlags = pCtx->eflags;
2926 if (HWACCMIsEnabled(pVM))
2927 {
2928 /* Hardware accelerated raw-mode:
2929 *
2930 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2931 */
2932 if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2933 return EMSTATE_HWACC;
2934
2935 /* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
2936 * off monitoring features essential for raw mode! */
2937 return EMSTATE_REM;
2938 }
2939
2940 /*
2941 * Standard raw-mode:
2942 *
2943 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2944 * or 32 bits protected mode ring 0 code
2945 *
2946 * The tests are ordered by the likelyhood of being true during normal execution.
2947 */
2948 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
2949 {
2950 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2951 return EMSTATE_REM;
2952 }
2953
2954#ifndef VBOX_RAW_V86
2955 if (EFlags.u32 & X86_EFL_VM) {
2956 Log2(("raw mode refused: VM_MASK\n"));
2957 return EMSTATE_REM;
2958 }
2959#endif
2960
2961 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2962 uint32_t u32CR0 = pCtx->cr0;
2963 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
2964 {
2965 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2966 return EMSTATE_REM;
2967 }
2968
2969 if (pCtx->cr4 & X86_CR4_PAE)
2970 {
2971 uint32_t u32Dummy, u32Features;
2972
2973 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2974 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
2975 return EMSTATE_REM;
2976 }
2977
2978 unsigned uSS = pCtx->ss;
2979 if ( pCtx->eflags.Bits.u1VM
2980 || (uSS & X86_SEL_RPL) == 3)
2981 {
2982 if (!EMIsRawRing3Enabled(pVM))
2983 return EMSTATE_REM;
2984
2985 if (!(EFlags.u32 & X86_EFL_IF))
2986 {
2987 Log2(("raw mode refused: IF (RawR3)\n"));
2988 return EMSTATE_REM;
2989 }
2990
2991 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2992 {
2993 Log2(("raw mode refused: CR0.WP + RawR0\n"));
2994 return EMSTATE_REM;
2995 }
2996 }
2997 else
2998 {
2999 if (!EMIsRawRing0Enabled(pVM))
3000 return EMSTATE_REM;
3001
3002 /* Only ring 0 supervisor code. */
3003 if ((uSS & X86_SEL_RPL) != 0)
3004 {
3005 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
3006 return EMSTATE_REM;
3007 }
3008
3009 // Let's start with pure 32 bits ring 0 code first
3010 /** @todo What's pure 32-bit mode? flat? */
3011 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
3012 || !(pCtx->csHid.Attr.n.u1DefBig))
3013 {
3014 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
3015 return EMSTATE_REM;
3016 }
3017
3018 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
3019 if (!(u32CR0 & X86_CR0_WP))
3020 {
3021 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
3022 return EMSTATE_REM;
3023 }
3024
3025 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
3026 {
3027 Log2(("raw r0 mode forced: patch code\n"));
3028 return EMSTATE_RAW;
3029 }
3030
3031#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
3032 if (!(EFlags.u32 & X86_EFL_IF))
3033 {
3034 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
3035 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
3036 return EMSTATE_REM;
3037 }
3038#endif
3039
3040 /** @todo still necessary??? */
3041 if (EFlags.Bits.u2IOPL != 0)
3042 {
3043 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
3044 return EMSTATE_REM;
3045 }
3046 }
3047
3048 Assert(PGMPhysIsA20Enabled(pVM));
3049 return EMSTATE_RAW;
3050}
3051
3052
3053/**
3054 * Executes all high priority post execution force actions.
3055 *
3056 * @returns rc or a fatal status code.
3057 *
3058 * @param pVM VM handle.
3059 * @param rc The current rc.
3060 */
3061static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
3062{
3063 if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
3064 PDMR3CritSectFF(pVM);
3065
3066 if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
3067 CSAMR3DoPendingAction(pVM);
3068
3069 return rc;
3070}
3071
3072
3073/**
3074 * Executes all pending forced actions.
3075 *
3076 * Forced actions can cause execution delays and execution
3077 * rescheduling. The first we deal with using action priority, so
3078 * that for instance pending timers aren't scheduled and ran until
3079 * right before execution. The rescheduling we deal with using
3080 * return codes. The same goes for VM termination, only in that case
3081 * we exit everything.
3082 *
3083 * @returns VBox status code of equal or greater importance/severity than rc.
3084 * The most important ones are: VINF_EM_RESCHEDULE,
3085 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3086 *
3087 * @param pVM VM handle.
3088 * @param rc The current rc.
3089 *
3090 */
3091static int emR3ForcedActions(PVM pVM, int rc)
3092{
3093 STAM_REL_PROFILE_START(&pVM->em.s.StatForcedActions, a);
3094#ifdef VBOX_STRICT
3095 int rcIrq = VINF_SUCCESS;
3096#endif
3097 int rc2;
3098#define UPDATE_RC() \
3099 do { \
3100 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
3101 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
3102 break; \
3103 if (!rc || rc2 < rc) \
3104 rc = rc2; \
3105 } while (0)
3106
3107 /*
3108 * Post execution chunk first.
3109 */
3110 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
3111 {
3112 /*
3113 * Termination request.
3114 */
3115 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3116 {
3117 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3118 STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3119 return VINF_EM_TERMINATE;
3120 }
3121
3122 /*
3123 * Debugger Facility polling.
3124 */
3125 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3126 {
3127 rc2 = DBGFR3VMMForcedAction(pVM);
3128 UPDATE_RC();
3129 }
3130
3131 /*
3132 * Postponed reset request.
3133 */
3134 if (VM_FF_ISSET(pVM, VM_FF_RESET))
3135 {
3136 rc2 = VMR3Reset(pVM);
3137 UPDATE_RC();
3138 VM_FF_CLEAR(pVM, VM_FF_RESET);
3139 }
3140
3141 /*
3142 * CSAM page scanning.
3143 */
3144 if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
3145 {
3146 PCPUMCTX pCtx = pVM->em.s.pCtx;
3147
3148 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3149 Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3150
3151 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3152 VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3153 }
3154
3155 /* check that we got them all */
3156 Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_CSAM_SCAN_PAGE)));
3157 }
3158
3159 /*
3160 * Normal priority then.
3161 * (Executed in no particular order.)
3162 */
3163 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3164 {
3165 /*
3166 * PDM Queues are pending.
3167 */
3168 if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3169 PDMR3QueueFlushAll(pVM);
3170
3171 /*
3172 * PDM DMA transfers are pending.
3173 */
3174 if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3175 PDMR3DmaRun(pVM);
3176
3177 /*
3178 * Requests from other threads.
3179 */
3180 if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3181 {
3182 rc2 = VMR3ReqProcessU(pVM->pUVM, VMREQDEST_ANY);
3183 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE)
3184 {
3185 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
3186 STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3187 return rc2;
3188 }
3189 UPDATE_RC();
3190 }
3191
3192 /* Replay the handler notification changes. */
3193 if (VM_FF_ISSET(pVM, VM_FF_REM_HANDLER_NOTIFY))
3194 REMR3ReplayHandlerNotifications(pVM);
3195
3196 /* check that we got them all */
3197 Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY)));
3198 }
3199
3200 /*
3201 * Execute polling function ever so often.
3202 * THIS IS A HACK, IT WILL BE *REPLACED* BY PROPER ASYNC NETWORKING "SOON"!
3203 */
3204 static unsigned cLast = 0;
3205 if (!((++cLast) % 4))
3206 PDMR3Poll(pVM);
3207
3208 /*
3209 * High priority pre execution chunk last.
3210 * (Executed in ascending priority order.)
3211 */
3212 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3213 {
3214 /*
3215 * Timers before interrupts.
3216 */
3217 if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3218 TMR3TimerQueuesDo(pVM);
3219
3220 /*
3221 * The instruction following an emulated STI should *always* be executed!
3222 */
3223 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3224 {
3225 Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3226 if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3227 {
3228 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3229 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3230 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3231 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3232 */
3233 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3234 }
3235 if (HWACCMR3IsActive(pVM))
3236 rc2 = VINF_EM_RESCHEDULE_HWACC;
3237 else
3238 rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3239
3240 UPDATE_RC();
3241 }
3242
3243 /*
3244 * Interrupts.
3245 */
3246 if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3247 && (!rc || rc >= VINF_EM_RESCHEDULE_RAW)
3248 && !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3249 && PATMAreInterruptsEnabled(pVM)
3250 && !HWACCMR3IsEventPending(pVM))
3251 {
3252 if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
3253 {
3254 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3255 /** @todo this really isn't nice, should properly handle this */
3256 rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3257#ifdef VBOX_STRICT
3258 rcIrq = rc2;
3259#endif
3260 UPDATE_RC();
3261 }
3262 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3263 else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3264 {
3265 rc2 = VINF_EM_RESCHEDULE_REM;
3266 UPDATE_RC();
3267 }
3268 }
3269
3270 /*
3271 * Allocate handy pages.
3272 */
3273 if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
3274 {
3275 rc2 = PGMR3PhysAllocateHandyPages(pVM);
3276 UPDATE_RC();
3277 }
3278
3279 /*
3280 * Debugger Facility request.
3281 */
3282 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3283 {
3284 rc2 = DBGFR3VMMForcedAction(pVM);
3285 UPDATE_RC();
3286 }
3287
3288 /*
3289 * Termination request.
3290 */
3291 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3292 {
3293 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3294 STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3295 return VINF_EM_TERMINATE;
3296 }
3297
3298#ifdef DEBUG
3299 /*
3300 * Debug, pause the VM.
3301 */
3302 if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3303 {
3304 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3305 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3306 return VINF_EM_SUSPEND;
3307 }
3308
3309#endif
3310 /* check that we got them all */
3311 Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER | VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC | VM_FF_DBGF | VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_SELM_SYNC_TSS | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TERMINATE | VM_FF_DEBUG_SUSPEND | VM_FF_INHIBIT_INTERRUPTS | VM_FF_PGM_NEED_HANDY_PAGES)));
3312 }
3313
3314#undef UPDATE_RC
3315 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
3316 STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3317 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
3318 return rc;
3319}
3320
3321
3322/**
3323 * Execute VM.
3324 *
3325 * This function is the main loop of the VM. The emulation thread
3326 * calls this function when the VM has been successfully constructed
3327 * and we're ready for executing the VM.
3328 *
3329 * Returning from this function means that the VM is turned off or
3330 * suspended (state already saved) and deconstruction in next in line.
3331 *
3332 * All interaction from other thread are done using forced actions
3333 * and signaling of the wait object.
3334 *
3335 * @returns VBox status code, informational status codes may indicate failure.
3336 * @param pVM The VM to operate on.
3337 * @param idCpu VMCPU id.
3338 */
3339VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, RTCPUID idCpu)
3340{
3341 LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3342 pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3343 VM_ASSERT_EMT(pVM);
3344 Assert(pVM->em.s.enmState == EMSTATE_NONE || pVM->em.s.enmState == EMSTATE_SUSPENDED);
3345
3346 VMMR3Lock(pVM);
3347
3348 int rc = setjmp(pVM->em.s.u.FatalLongJump);
3349 if (rc == 0)
3350 {
3351 /*
3352 * Start the virtual time.
3353 */
3354 rc = TMVirtualResume(pVM);
3355 Assert(rc == VINF_SUCCESS);
3356 rc = TMCpuTickResume(pVM);
3357 Assert(rc == VINF_SUCCESS);
3358
3359 /*
3360 * The Outer Main Loop.
3361 */
3362 bool fFFDone = false;
3363
3364 /* Reschedule right away to start in the right state. */
3365 rc = VINF_SUCCESS;
3366 pVM->em.s.enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3367
3368 STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3369 for (;;)
3370 {
3371 /*
3372 * Before we can schedule anything (we're here because
3373 * scheduling is required) we must service any pending
3374 * forced actions to avoid any pending action causing
3375 * immediate rescheduling upon entering an inner loop
3376 *
3377 * Do forced actions.
3378 */
3379 if ( !fFFDone
3380 && rc != VINF_EM_TERMINATE
3381 && rc != VINF_EM_OFF
3382 && VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3383 {
3384 rc = emR3ForcedActions(pVM, rc);
3385 if ( ( rc == VINF_EM_RESCHEDULE_REM
3386 || rc == VINF_EM_RESCHEDULE_HWACC)
3387 && pVM->em.s.fForceRAW)
3388 rc = VINF_EM_RESCHEDULE_RAW;
3389 }
3390 else if (fFFDone)
3391 fFFDone = false;
3392
3393 /*
3394 * Now what to do?
3395 */
3396 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
3397 switch (rc)
3398 {
3399 /*
3400 * Keep doing what we're currently doing.
3401 */
3402 case VINF_SUCCESS:
3403 break;
3404
3405 /*
3406 * Reschedule - to raw-mode execution.
3407 */
3408 case VINF_EM_RESCHEDULE_RAW:
3409 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3410 pVM->em.s.enmState = EMSTATE_RAW;
3411 break;
3412
3413 /*
3414 * Reschedule - to hardware accelerated raw-mode execution.
3415 */
3416 case VINF_EM_RESCHEDULE_HWACC:
3417 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3418 Assert(!pVM->em.s.fForceRAW);
3419 pVM->em.s.enmState = EMSTATE_HWACC;
3420 break;
3421
3422 /*
3423 * Reschedule - to recompiled execution.
3424 */
3425 case VINF_EM_RESCHEDULE_REM:
3426 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3427 pVM->em.s.enmState = EMSTATE_REM;
3428 break;
3429
3430#ifdef VBOX_WITH_VMI
3431 /*
3432 * Reschedule - parav call.
3433 */
3434 case VINF_EM_RESCHEDULE_PARAV:
3435 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVM->em.s.enmState, EMSTATE_PARAV));
3436 pVM->em.s.enmState = EMSTATE_PARAV;
3437 break;
3438#endif
3439
3440 /*
3441 * Resume.
3442 */
3443 case VINF_EM_RESUME:
3444 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3445 /* fall through and get scheduled. */
3446
3447 /*
3448 * Reschedule.
3449 */
3450 case VINF_EM_RESCHEDULE:
3451 {
3452 EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3453 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3454 pVM->em.s.enmState = enmState;
3455 break;
3456 }
3457
3458 /*
3459 * Halted.
3460 */
3461 case VINF_EM_HALT:
3462 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3463 pVM->em.s.enmState = EMSTATE_HALTED;
3464 break;
3465
3466 /*
3467 * Suspend.
3468 */
3469 case VINF_EM_SUSPEND:
3470 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3471 pVM->em.s.enmState = EMSTATE_SUSPENDED;
3472 break;
3473
3474 /*
3475 * Reset.
3476 * We might end up doing a double reset for now, we'll have to clean up the mess later.
3477 */
3478 case VINF_EM_RESET:
3479 {
3480 EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3481 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3482 pVM->em.s.enmState = enmState;
3483 break;
3484 }
3485
3486 /*
3487 * Power Off.
3488 */
3489 case VINF_EM_OFF:
3490 pVM->em.s.enmState = EMSTATE_TERMINATING;
3491 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3492 TMVirtualPause(pVM);
3493 TMCpuTickPause(pVM);
3494 VMMR3Unlock(pVM);
3495 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3496 return rc;
3497
3498 /*
3499 * Terminate the VM.
3500 */
3501 case VINF_EM_TERMINATE:
3502 pVM->em.s.enmState = EMSTATE_TERMINATING;
3503 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3504 TMVirtualPause(pVM);
3505 TMCpuTickPause(pVM);
3506 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3507 return rc;
3508
3509 /*
3510 * Guest debug events.
3511 */
3512 case VINF_EM_DBG_STEPPED:
3513 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3514 case VINF_EM_DBG_STOP:
3515 case VINF_EM_DBG_BREAKPOINT:
3516 case VINF_EM_DBG_STEP:
3517 if (pVM->em.s.enmState == EMSTATE_RAW)
3518 {
3519 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3520 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3521 }
3522 else
3523 {
3524 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3525 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3526 }
3527 break;
3528
3529 /*
3530 * Hypervisor debug events.
3531 */
3532 case VINF_EM_DBG_HYPER_STEPPED:
3533 case VINF_EM_DBG_HYPER_BREAKPOINT:
3534 case VINF_EM_DBG_HYPER_ASSERTION:
3535 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3536 pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3537 break;
3538
3539 /*
3540 * Guru mediations.
3541 */
3542 case VERR_VMM_RING0_ASSERTION:
3543 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVM->em.s.enmState, EMSTATE_GURU_MEDITATION));
3544 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3545 break;
3546
3547 /*
3548 * Any error code showing up here other than the ones we
3549 * know and process above are considered to be FATAL.
3550 *
3551 * Unknown warnings and informational status codes are also
3552 * included in this.
3553 */
3554 default:
3555 if (RT_SUCCESS(rc))
3556 {
3557 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
3558 rc = VERR_EM_INTERNAL_ERROR;
3559 }
3560 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3561 Log(("EMR3ExecuteVM returns %d\n", rc));
3562 break;
3563 }
3564
3565
3566 /*
3567 * Any waiters can now be woken up
3568 */
3569 VMMR3Unlock(pVM);
3570 VMMR3Lock(pVM);
3571
3572 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3573 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3574
3575 /*
3576 * Act on the state.
3577 */
3578 switch (pVM->em.s.enmState)
3579 {
3580 /*
3581 * Execute raw.
3582 */
3583 case EMSTATE_RAW:
3584 rc = emR3RawExecute(pVM, &fFFDone);
3585 break;
3586
3587 /*
3588 * Execute hardware accelerated raw.
3589 */
3590 case EMSTATE_HWACC:
3591 rc = emR3HwAccExecute(pVM, idCpu, &fFFDone);
3592 break;
3593
3594 /*
3595 * Execute recompiled.
3596 */
3597 case EMSTATE_REM:
3598 rc = emR3RemExecute(pVM, &fFFDone);
3599 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
3600 break;
3601
3602#ifdef VBOX_WITH_VMI
3603 /*
3604 * Execute PARAV function.
3605 */
3606 case EMSTATE_PARAV:
3607 rc = PARAVCallFunction(pVM);
3608 pVM->em.s.enmState = EMSTATE_REM;
3609 break;
3610#endif
3611
3612 /*
3613 * hlt - execution halted until interrupt.
3614 */
3615 case EMSTATE_HALTED:
3616 {
3617 STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3618 rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3619 STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3620 break;
3621 }
3622
3623 /*
3624 * Suspended - return to VM.cpp.
3625 */
3626 case EMSTATE_SUSPENDED:
3627 TMVirtualPause(pVM);
3628 TMCpuTickPause(pVM);
3629 VMMR3Unlock(pVM);
3630 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3631 return VINF_EM_SUSPEND;
3632
3633 /*
3634 * Debugging in the guest.
3635 */
3636 case EMSTATE_DEBUG_GUEST_REM:
3637 case EMSTATE_DEBUG_GUEST_RAW:
3638 TMVirtualPause(pVM);
3639 TMCpuTickPause(pVM);
3640 rc = emR3Debug(pVM, rc);
3641 TMVirtualResume(pVM);
3642 TMCpuTickResume(pVM);
3643 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVM->em.s.enmState));
3644 break;
3645
3646 /*
3647 * Debugging in the hypervisor.
3648 */
3649 case EMSTATE_DEBUG_HYPER:
3650 {
3651 TMVirtualPause(pVM);
3652 TMCpuTickPause(pVM);
3653 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3654
3655 rc = emR3Debug(pVM, rc);
3656 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVM->em.s.enmState));
3657 if (rc != VINF_SUCCESS)
3658 {
3659 /* switch to guru meditation mode */
3660 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3661 VMMR3FatalDump(pVM, rc);
3662 return rc;
3663 }
3664
3665 STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3666 TMVirtualResume(pVM);
3667 TMCpuTickResume(pVM);
3668 break;
3669 }
3670
3671 /*
3672 * Guru meditation takes place in the debugger.
3673 */
3674 case EMSTATE_GURU_MEDITATION:
3675 {
3676 TMVirtualPause(pVM);
3677 TMCpuTickPause(pVM);
3678 VMMR3FatalDump(pVM, rc);
3679 emR3Debug(pVM, rc);
3680 VMMR3Unlock(pVM);
3681 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3682 return rc;
3683 }
3684
3685 /*
3686 * The states we don't expect here.
3687 */
3688 case EMSTATE_NONE:
3689 case EMSTATE_TERMINATING:
3690 default:
3691 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3692 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3693 TMVirtualPause(pVM);
3694 TMCpuTickPause(pVM);
3695 VMMR3Unlock(pVM);
3696 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3697 return VERR_EM_INTERNAL_ERROR;
3698 }
3699 } /* The Outer Main Loop */
3700 }
3701 else
3702 {
3703 /*
3704 * Fatal error.
3705 */
3706 LogFlow(("EMR3ExecuteVM: returns %Rrc (longjmp / fatal error)\n", rc));
3707 TMVirtualPause(pVM);
3708 TMCpuTickPause(pVM);
3709 VMMR3FatalDump(pVM, rc);
3710 emR3Debug(pVM, rc);
3711 VMMR3Unlock(pVM);
3712 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3713 /** @todo change the VM state! */
3714 return rc;
3715 }
3716
3717 /* (won't ever get here). */
3718 AssertFailed();
3719}
3720
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