EM.cpp@ 18485

Last change on this file since 18485 was 18343, checked in by vboxsync, 16 years ago
EM: New IPEs, use VERR_IPE_UNEXPECTED_STATUS.
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1	/* $Id: EM.cpp 18343 2009-03-26 18:35:12Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_em EM - The Execution Monitor / Manager
23	*
24	* The Execution Monitor/Manager is responsible for running the VM, scheduling
25	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26	* Interpreted), and keeping the CPU states in sync. The function
27	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29	* emR3RemExecute).
30	*
31	* The interpreted execution is only used to avoid switching between
32	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33	* The interpretation is thus implemented as part of EM.
34	*
35	* @see grp_em
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_EM
42	#include <VBox/em.h>
43	#include <VBox/vmm.h>
44	#ifdef VBOX_WITH_VMI
45	# include <VBox/parav.h>
46	#endif
47	#include <VBox/patm.h>
48	#include <VBox/csam.h>
49	#include <VBox/selm.h>
50	#include <VBox/trpm.h>
51	#include <VBox/iom.h>
52	#include <VBox/dbgf.h>
53	#include <VBox/pgm.h>
54	#include <VBox/rem.h>
55	#include <VBox/tm.h>
56	#include <VBox/mm.h>
57	#include <VBox/ssm.h>
58	#include <VBox/pdmapi.h>
59	#include <VBox/pdmcritsect.h>
60	#include <VBox/pdmqueue.h>
61	#include <VBox/hwaccm.h>
62	#include <VBox/patm.h>
63	#include "EMInternal.h"
64	#include <VBox/vm.h>
65	#include <VBox/cpumdis.h>
66	#include <VBox/dis.h>
67	#include <VBox/disopcode.h>
68	#include <VBox/dbgf.h>
69
70	#include <VBox/log.h>
71	#include <iprt/thread.h>
72	#include <iprt/assert.h>
73	#include <iprt/asm.h>
74	#include <iprt/semaphore.h>
75	#include <iprt/string.h>
76	#include <iprt/avl.h>
77	#include <iprt/stream.h>
78	#include <VBox/param.h>
79	#include <VBox/err.h>
80
81
82	/*******************************************************************************
83	* Defined Constants And Macros *
84	*******************************************************************************/
85	#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
86	#define EM_NOTIFY_HWACCM
87	#endif
88
89
90	/*******************************************************************************
91	* Internal Functions *
92	*******************************************************************************/
93	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
94	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
95	static int emR3Debug(PVM pVM, int rc);
96	static int emR3RemStep(PVM pVM);
97	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
98	static int emR3RawResumeHyper(PVM pVM);
99	static int emR3RawStep(PVM pVM);
100	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
101	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
102	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
103	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
104	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
105	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
106	static int emR3ForcedActions(PVM pVM, int rc);
107	static int emR3RawGuestTrap(PVM pVM);
108	static int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret);
109	static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations);
110	static EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx);
111
112	/**
113	* Initializes the EM.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	VMMR3DECL(int) EMR3Init(PVM pVM)
119	{
120	LogFlow(("EMR3Init\n"));
121	/*
122	* Assert alignment and sizes.
123	*/
124	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
125	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
126	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
127	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
128
129	/*
130	* Init the structure.
131	*/
132	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
133	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
134	if (RT_FAILURE(rc))
135	pVM->fRawR3Enabled = true;
136	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
137	if (RT_FAILURE(rc))
138	pVM->fRawR0Enabled = true;
139	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
140	pVM->em.s.enmState = EMSTATE_NONE;
141	pVM->em.s.fForceRAW = false;
142
143	pVM->em.s.pCtx = CPUMQueryGuestCtxPtr(pVM);
144	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
145	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
146
147	/*
148	* Saved state.
149	*/
150	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
151	NULL, emR3Save, NULL,
152	NULL, emR3Load, NULL);
153	if (RT_FAILURE(rc))
154	return rc;
155
156	/*
157	* Statistics.
158	*/
159	#ifdef VBOX_WITH_STATISTICS
160	PEMSTATS pStats;
161	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
162	if (RT_FAILURE(rc))
163	return rc;
164	pVM->em.s.pStatsR3 = pStats;
165	pVM->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
166	pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
167
168	STAM_REG(pVM, &pStats->StatRZEmulate, STAMTYPE_PROFILE, "/EM/RZ/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
169	STAM_REG(pVM, &pStats->StatR3Emulate, STAMTYPE_PROFILE, "/EM/R3/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
170
171	STAM_REG(pVM, &pStats->StatRZInterpretSucceeded, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
172	STAM_REG(pVM, &pStats->StatR3InterpretSucceeded, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
173
174	STAM_REG_USED(pVM, &pStats->StatRZAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatR3And, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatRZAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatR3Add, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatRZAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatR3Adc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatRZSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatR3Sub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatRZCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatR3CpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatRZDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatR3Dec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatRZHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatR3Hlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatRZInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatR3Inc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatRZInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatR3InvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatRZIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatR3Iret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatRZLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatR3LLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
196	STAM_REG_USED(pVM, &pStats->StatRZLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
197	STAM_REG_USED(pVM, &pStats->StatR3LIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatRZLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatR3LGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatRZMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatR3Mov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatRZMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatR3MovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
204	STAM_REG_USED(pVM, &pStats->StatRZMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
205	STAM_REG_USED(pVM, &pStats->StatR3MovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
206	STAM_REG_USED(pVM, &pStats->StatRZOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
207	STAM_REG_USED(pVM, &pStats->StatR3Or, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
208	STAM_REG_USED(pVM, &pStats->StatRZPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatR3Pop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatRZRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatR3Rdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatRZSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatR3Sti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatRZXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatR3Xchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatRZXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatR3Xor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatRZMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatR3Monitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatRZMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatR3MWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatRZBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatR3Btr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatRZBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatR3Bts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatRZBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatR3Btc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatRZCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatR3CmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatRZCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatR3CmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatRZXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatR3XAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatR3Rdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatRZRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatR3Wrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
237	STAM_REG_USED(pVM, &pStats->StatRZWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
238	STAM_REG_USED(pVM, &pStats->StatR3StosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
239	STAM_REG_USED(pVM, &pStats->StatRZStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatRZWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatR3WbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatRZLmsw, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was successfully interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatR3Lmsw, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was successfully interpreted.");
244
245	STAM_REG(pVM, &pStats->StatRZInterpretFailed, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
246	STAM_REG(pVM, &pStats->StatR3InterpretFailed, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
247
248	STAM_REG_USED(pVM, &pStats->StatRZFailedAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
249	STAM_REG_USED(pVM, &pStats->StatR3FailedAnd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatRZFailedCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatR3FailedCpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatRZFailedDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatR3FailedDec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatRZFailedHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatR3FailedHlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatRZFailedInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatR3FailedInc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatRZFailedInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatR3FailedInvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatRZFailedIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
261	STAM_REG_USED(pVM, &pStats->StatR3FailedIret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
262	STAM_REG_USED(pVM, &pStats->StatRZFailedLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
263	STAM_REG_USED(pVM, &pStats->StatR3FailedLLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
264	STAM_REG_USED(pVM, &pStats->StatRZFailedLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
265	STAM_REG_USED(pVM, &pStats->StatR3FailedLIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
266	STAM_REG_USED(pVM, &pStats->StatRZFailedLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
267	STAM_REG_USED(pVM, &pStats->StatR3FailedLGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
268	STAM_REG_USED(pVM, &pStats->StatRZFailedMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
269	STAM_REG_USED(pVM, &pStats->StatR3FailedMov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
270	STAM_REG_USED(pVM, &pStats->StatRZFailedMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
271	STAM_REG_USED(pVM, &pStats->StatR3FailedMovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
272	STAM_REG_USED(pVM, &pStats->StatRZFailedMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
273	STAM_REG_USED(pVM, &pStats->StatR3FailedMovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
274	STAM_REG_USED(pVM, &pStats->StatRZFailedOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
275	STAM_REG_USED(pVM, &pStats->StatR3FailedOr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
276	STAM_REG_USED(pVM, &pStats->StatRZFailedPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
277	STAM_REG_USED(pVM, &pStats->StatR3FailedPop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
278	STAM_REG_USED(pVM, &pStats->StatRZFailedSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
279	STAM_REG_USED(pVM, &pStats->StatR3FailedSti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
280	STAM_REG_USED(pVM, &pStats->StatRZFailedXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
281	STAM_REG_USED(pVM, &pStats->StatR3FailedXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
282	STAM_REG_USED(pVM, &pStats->StatRZFailedXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
283	STAM_REG_USED(pVM, &pStats->StatR3FailedXor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
284	STAM_REG_USED(pVM, &pStats->StatRZFailedMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
285	STAM_REG_USED(pVM, &pStats->StatR3FailedMonitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
286	STAM_REG_USED(pVM, &pStats->StatRZFailedMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
287	STAM_REG_USED(pVM, &pStats->StatR3FailedMWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
288	STAM_REG_USED(pVM, &pStats->StatRZFailedRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
289	STAM_REG_USED(pVM, &pStats->StatR3FailedRdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
290	STAM_REG_USED(pVM, &pStats->StatRZFailedRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
291	STAM_REG_USED(pVM, &pStats->StatR3FailedRdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
292	STAM_REG_USED(pVM, &pStats->StatRZFailedWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
293	STAM_REG_USED(pVM, &pStats->StatR3FailedWrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
294	STAM_REG_USED(pVM, &pStats->StatRZFailedLmsw, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was not interpreted.");
295	STAM_REG_USED(pVM, &pStats->StatR3FailedLmsw, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was not interpreted.");
296
297	STAM_REG_USED(pVM, &pStats->StatRZFailedMisc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
298	STAM_REG_USED(pVM, &pStats->StatR3FailedMisc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
299	STAM_REG_USED(pVM, &pStats->StatRZFailedAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
300	STAM_REG_USED(pVM, &pStats->StatR3FailedAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
301	STAM_REG_USED(pVM, &pStats->StatRZFailedAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
302	STAM_REG_USED(pVM, &pStats->StatR3FailedAdc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
303	STAM_REG_USED(pVM, &pStats->StatRZFailedBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
304	STAM_REG_USED(pVM, &pStats->StatR3FailedBtr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
305	STAM_REG_USED(pVM, &pStats->StatRZFailedBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
306	STAM_REG_USED(pVM, &pStats->StatR3FailedBts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
307	STAM_REG_USED(pVM, &pStats->StatRZFailedBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
308	STAM_REG_USED(pVM, &pStats->StatR3FailedBtc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
309	STAM_REG_USED(pVM, &pStats->StatRZFailedCli, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
310	STAM_REG_USED(pVM, &pStats->StatR3FailedCli, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
311	STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
312	STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
313	STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
314	STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
315	STAM_REG_USED(pVM, &pStats->StatRZFailedXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
316	STAM_REG_USED(pVM, &pStats->StatR3FailedXAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
317	STAM_REG_USED(pVM, &pStats->StatRZFailedMovNTPS, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
318	STAM_REG_USED(pVM, &pStats->StatR3FailedMovNTPS, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
319	STAM_REG_USED(pVM, &pStats->StatRZFailedStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
320	STAM_REG_USED(pVM, &pStats->StatR3FailedStosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
321	STAM_REG_USED(pVM, &pStats->StatRZFailedSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
322	STAM_REG_USED(pVM, &pStats->StatR3FailedSub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
323	STAM_REG_USED(pVM, &pStats->StatRZFailedWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
324	STAM_REG_USED(pVM, &pStats->StatR3FailedWbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
325
326	STAM_REG_USED(pVM, &pStats->StatRZFailedUserMode, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
327	STAM_REG_USED(pVM, &pStats->StatR3FailedUserMode, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
328	STAM_REG_USED(pVM, &pStats->StatRZFailedPrefix, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
329	STAM_REG_USED(pVM, &pStats->StatR3FailedPrefix, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
330
331	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
332	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
333	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/R3/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
334	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
335	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
336	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
337	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
338	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
339	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
340	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
341	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
342	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
343	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
344	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
345	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
346	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
347	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
348	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/R3/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
349	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
350	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
351	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
352	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
353	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
354	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
355	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
356	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
357
358	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
359	pVM->em.s.pCliStatTree = 0;
360	#endif /* VBOX_WITH_STATISTICS */
361
362	/* these should be considered for release statistics. */
363	STAM_REL_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
364	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
365	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
366	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
367
368	STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
369	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
370	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
371	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
372	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
373	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
374	STAM_REL_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
375	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
376	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
377	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
378	STAM_REL_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
379	STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
380
381
382	return VINF_SUCCESS;
383	}
384
385
386	/**
387	* Initializes the per-VCPU EM.
388	*
389	* @returns VBox status code.
390	* @param pVM The VM to operate on.
391	*/
392	VMMR3DECL(int) EMR3InitCPU(PVM pVM)
393	{
394	LogFlow(("EMR3InitCPU\n"));
395	return VINF_SUCCESS;
396	}
397
398
399	/**
400	* Applies relocations to data and code managed by this
401	* component. This function will be called at init and
402	* whenever the VMM need to relocate it self inside the GC.
403	*
404	* @param pVM The VM.
405	*/
406	VMMR3DECL(void) EMR3Relocate(PVM pVM)
407	{
408	LogFlow(("EMR3Relocate\n"));
409	if (pVM->em.s.pStatsR3)
410	pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVM->em.s.pStatsR3);
411	}
412
413
414	/**
415	* Reset notification.
416	*
417	* @param pVM
418	*/
419	VMMR3DECL(void) EMR3Reset(PVM pVM)
420	{
421	LogFlow(("EMR3Reset: \n"));
422	pVM->em.s.fForceRAW = false;
423	}
424
425
426	/**
427	* Terminates the EM.
428	*
429	* Termination means cleaning up and freeing all resources,
430	* the VM it self is at this point powered off or suspended.
431	*
432	* @returns VBox status code.
433	* @param pVM The VM to operate on.
434	*/
435	VMMR3DECL(int) EMR3Term(PVM pVM)
436	{
437	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
438
439	return VINF_SUCCESS;
440	}
441
442	/**
443	* Terminates the per-VCPU EM.
444	*
445	* Termination means cleaning up and freeing all resources,
446	* the VM it self is at this point powered off or suspended.
447	*
448	* @returns VBox status code.
449	* @param pVM The VM to operate on.
450	*/
451	VMMR3DECL(int) EMR3TermCPU(PVM pVM)
452	{
453	return 0;
454	}
455
456	/**
457	* Execute state save operation.
458	*
459	* @returns VBox status code.
460	* @param pVM VM Handle.
461	* @param pSSM SSM operation handle.
462	*/
463	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
464	{
465	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
466	}
467
468
469	/**
470	* Execute state load operation.
471	*
472	* @returns VBox status code.
473	* @param pVM VM Handle.
474	* @param pSSM SSM operation handle.
475	* @param u32Version Data layout version.
476	*/
477	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
478	{
479	/*
480	* Validate version.
481	*/
482	if (u32Version != EM_SAVED_STATE_VERSION)
483	{
484	AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
485	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
486	}
487
488	/*
489	* Load the saved state.
490	*/
491	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
492	if (RT_FAILURE(rc))
493	pVM->em.s.fForceRAW = false;
494
495	Assert(!pVM->em.s.pCliStatTree);
496	return rc;
497	}
498
499
500	/**
501	* Enables or disables a set of raw-mode execution modes.
502	*
503	* @returns VINF_SUCCESS on success.
504	* @returns VINF_RESCHEDULE if a rescheduling might be required.
505	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
506	*
507	* @param pVM The VM to operate on.
508	* @param enmMode The execution mode change.
509	* @thread The emulation thread.
510	*/
511	VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
512	{
513	switch (enmMode)
514	{
515	case EMRAW_NONE:
516	pVM->fRawR3Enabled = false;
517	pVM->fRawR0Enabled = false;
518	break;
519	case EMRAW_RING3_ENABLE:
520	pVM->fRawR3Enabled = true;
521	break;
522	case EMRAW_RING3_DISABLE:
523	pVM->fRawR3Enabled = false;
524	break;
525	case EMRAW_RING0_ENABLE:
526	pVM->fRawR0Enabled = true;
527	break;
528	case EMRAW_RING0_DISABLE:
529	pVM->fRawR0Enabled = false;
530	break;
531	default:
532	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
533	return VERR_INVALID_PARAMETER;
534	}
535	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
536	pVM->fRawR3Enabled, pVM->fRawR0Enabled));
537	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
538	}
539
540
541	/**
542	* Raise a fatal error.
543	*
544	* Safely terminate the VM with full state report and stuff. This function
545	* will naturally never return.
546	*
547	* @param pVM VM handle.
548	* @param rc VBox status code.
549	*/
550	VMMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
551	{
552	longjmp(pVM->em.s.u.FatalLongJump, rc);
553	AssertReleaseMsgFailed(("longjmp returned!\n"));
554	}
555
556
557	/**
558	* Gets the EM state name.
559	*
560	* @returns pointer to read only state name,
561	* @param enmState The state.
562	*/
563	VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
564	{
565	switch (enmState)
566	{
567	case EMSTATE_NONE: return "EMSTATE_NONE";
568	case EMSTATE_RAW: return "EMSTATE_RAW";
569	case EMSTATE_HWACC: return "EMSTATE_HWACC";
570	case EMSTATE_REM: return "EMSTATE_REM";
571	case EMSTATE_PARAV: return "EMSTATE_PARAV";
572	case EMSTATE_HALTED: return "EMSTATE_HALTED";
573	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
574	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
575	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
576	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
577	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
578	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
579	default: return "Unknown!";
580	}
581	}
582
583
584	#ifdef VBOX_WITH_STATISTICS
585	/**
586	* Just a braindead function to keep track of cli addresses.
587	* @param pVM VM handle.
588	* @param GCPtrInstr The EIP of the cli instruction.
589	*/
590	static void emR3RecordCli(PVM pVM, RTGCPTR GCPtrInstr)
591	{
592	PCLISTAT pRec;
593
594	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)GCPtrInstr);
595	if (!pRec)
596	{
597	/* New cli instruction; insert into the tree. */
598	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
599	Assert(pRec);
600	if (!pRec)
601	return;
602	pRec->Core.Key = (AVLPVKEY)GCPtrInstr;
603
604	char szCliStatName[32];
605	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
606	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
607
608	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
609	Assert(fRc); NOREF(fRc);
610	}
611	STAM_COUNTER_INC(&pRec->Counter);
612	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
613	}
614	#endif /* VBOX_WITH_STATISTICS */
615
616
617	/**
618	* Debug loop.
619	*
620	* @returns VBox status code for EM.
621	* @param pVM VM handle.
622	* @param rc Current EM VBox status code..
623	*/
624	static int emR3Debug(PVM pVM, int rc)
625	{
626	for (;;)
627	{
628	Log(("emR3Debug: rc=%Rrc\n", rc));
629	const int rcLast = rc;
630
631	/*
632	* Debug related RC.
633	*/
634	switch (rc)
635	{
636	/*
637	* Single step an instruction.
638	*/
639	case VINF_EM_DBG_STEP:
640	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
641	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
642	\|\| pVM->em.s.fForceRAW /* paranoia */)
643	rc = emR3RawStep(pVM);
644	else
645	{
646	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
647	rc = emR3RemStep(pVM);
648	}
649	break;
650
651	/*
652	* Simple events: stepped, breakpoint, stop/assertion.
653	*/
654	case VINF_EM_DBG_STEPPED:
655	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
656	break;
657
658	case VINF_EM_DBG_BREAKPOINT:
659	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
660	break;
661
662	case VINF_EM_DBG_STOP:
663	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
664	break;
665
666	case VINF_EM_DBG_HYPER_STEPPED:
667	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
668	break;
669
670	case VINF_EM_DBG_HYPER_BREAKPOINT:
671	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
672	break;
673
674	case VINF_EM_DBG_HYPER_ASSERTION:
675	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
676	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
677	break;
678
679	/*
680	* Guru meditation.
681	*/
682	case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
683	rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
684	break;
685	case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
686	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
687	break;
688
689	default: /** @todo don't use default for guru, but make special errors code! */
690	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
691	break;
692	}
693
694	/*
695	* Process the result.
696	*/
697	do
698	{
699	switch (rc)
700	{
701	/*
702	* Continue the debugging loop.
703	*/
704	case VINF_EM_DBG_STEP:
705	case VINF_EM_DBG_STOP:
706	case VINF_EM_DBG_STEPPED:
707	case VINF_EM_DBG_BREAKPOINT:
708	case VINF_EM_DBG_HYPER_STEPPED:
709	case VINF_EM_DBG_HYPER_BREAKPOINT:
710	case VINF_EM_DBG_HYPER_ASSERTION:
711	break;
712
713	/*
714	* Resuming execution (in some form) has to be done here if we got
715	* a hypervisor debug event.
716	*/
717	case VINF_SUCCESS:
718	case VINF_EM_RESUME:
719	case VINF_EM_SUSPEND:
720	case VINF_EM_RESCHEDULE:
721	case VINF_EM_RESCHEDULE_RAW:
722	case VINF_EM_RESCHEDULE_REM:
723	case VINF_EM_HALT:
724	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
725	{
726	rc = emR3RawResumeHyper(pVM);
727	if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
728	continue;
729	}
730	if (rc == VINF_SUCCESS)
731	rc = VINF_EM_RESCHEDULE;
732	return rc;
733
734	/*
735	* The debugger isn't attached.
736	* We'll simply turn the thing off since that's the easiest thing to do.
737	*/
738	case VERR_DBGF_NOT_ATTACHED:
739	switch (rcLast)
740	{
741	case VINF_EM_DBG_HYPER_STEPPED:
742	case VINF_EM_DBG_HYPER_BREAKPOINT:
743	case VINF_EM_DBG_HYPER_ASSERTION:
744	case VERR_TRPM_PANIC:
745	case VERR_TRPM_DONT_PANIC:
746	case VERR_VMM_RING0_ASSERTION:
747	return rcLast;
748	}
749	return VINF_EM_OFF;
750
751	/*
752	* Status codes terminating the VM in one or another sense.
753	*/
754	case VINF_EM_TERMINATE:
755	case VINF_EM_OFF:
756	case VINF_EM_RESET:
757	case VINF_EM_RAW_STALE_SELECTOR:
758	case VINF_EM_RAW_IRET_TRAP:
759	case VERR_TRPM_PANIC:
760	case VERR_TRPM_DONT_PANIC:
761	case VERR_VMM_RING0_ASSERTION:
762	case VERR_INTERNAL_ERROR:
763	case VERR_INTERNAL_ERROR_2:
764	case VERR_INTERNAL_ERROR_3:
765	case VERR_INTERNAL_ERROR_4:
766	case VERR_INTERNAL_ERROR_5:
767	case VERR_IPE_UNEXPECTED_STATUS:
768	case VERR_IPE_UNEXPECTED_INFO_STATUS:
769	case VERR_IPE_UNEXPECTED_ERROR_STATUS:
770	return rc;
771
772	/*
773	* The rest is unexpected, and will keep us here.
774	*/
775	default:
776	AssertMsgFailed(("Unxpected rc %Rrc!\n", rc));
777	break;
778	}
779	} while (false);
780	} /* debug for ever */
781	}
782
783
784	/**
785	* Steps recompiled code.
786	*
787	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
788	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
789	*
790	* @param pVM VM handle.
791	*/
792	static int emR3RemStep(PVM pVM)
793	{
794	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
795
796	/*
797	* Switch to REM, step instruction, switch back.
798	*/
799	int rc = REMR3State(pVM);
800	if (RT_SUCCESS(rc))
801	{
802	rc = REMR3Step(pVM);
803	REMR3StateBack(pVM);
804	}
805	LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
806	return rc;
807	}
808
809
810	/**
811	* Executes recompiled code.
812	*
813	* This function contains the recompiler version of the inner
814	* execution loop (the outer loop being in EMR3ExecuteVM()).
815	*
816	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
817	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
818	*
819	* @param pVM VM handle.
820	* @param pfFFDone Where to store an indicator telling wheter or not
821	* FFs were done before returning.
822	*
823	*/
824	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
825	{
826	#ifdef LOG_ENABLED
827	PCPUMCTX pCtx = pVM->em.s.pCtx;
828	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
829
830	if (pCtx->eflags.Bits.u1VM)
831	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
832	else
833	Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
834	#endif
835	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
836
837	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
838	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
839	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
840	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
841	#endif
842
843	/*
844	* Spin till we get a forced action which returns anything but VINF_SUCCESS
845	* or the REM suggests raw-mode execution.
846	*/
847	*pfFFDone = false;
848	bool fInREMState = false;
849	int rc = VINF_SUCCESS;
850	for (;;)
851	{
852	/*
853	* Update REM state if not already in sync.
854	*/
855	if (!fInREMState)
856	{
857	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
858	rc = REMR3State(pVM);
859	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
860	if (RT_FAILURE(rc))
861	break;
862	fInREMState = true;
863
864	/*
865	* We might have missed the raising of VMREQ, TIMER and some other
866	* imporant FFs while we were busy switching the state. So, check again.
867	*/
868	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
869	{
870	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
871	goto l_REMDoForcedActions;
872	}
873	}
874
875
876	/*
877	* Execute REM.
878	*/
879	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
880	rc = REMR3Run(pVM);
881	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
882
883
884	/*
885	* Deal with high priority post execution FFs before doing anything else.
886	*/
887	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
888	rc = emR3HighPriorityPostForcedActions(pVM, rc);
889
890	/*
891	* Process the returned status code.
892	* (Try keep this short! Call functions!)
893	*/
894	if (rc != VINF_SUCCESS)
895	{
896	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
897	break;
898	if (rc != VINF_REM_INTERRUPED_FF)
899	{
900	/*
901	* Anything which is not known to us means an internal error
902	* and the termination of the VM!
903	*/
904	AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
905	break;
906	}
907	}
908
909
910	/*
911	* Check and execute forced actions.
912	* Sync back the VM state before calling any of these.
913	*/
914	#ifdef VBOX_HIGH_RES_TIMERS_HACK
915	TMTimerPoll(pVM);
916	#endif
917	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
918	{
919	l_REMDoForcedActions:
920	if (fInREMState)
921	{
922	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
923	REMR3StateBack(pVM);
924	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
925	fInREMState = false;
926	}
927	STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
928	rc = emR3ForcedActions(pVM, rc);
929	STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
930	if ( rc != VINF_SUCCESS
931	&& rc != VINF_EM_RESCHEDULE_REM)
932	{
933	*pfFFDone = true;
934	break;
935	}
936	}
937
938	} /* The Inner Loop, recompiled execution mode version. */
939
940
941	/*
942	* Returning. Sync back the VM state if required.
943	*/
944	if (fInREMState)
945	{
946	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
947	REMR3StateBack(pVM);
948	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
949	}
950
951	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
952	return rc;
953	}
954
955
956	/**
957	* Resumes executing hypervisor after a debug event.
958	*
959	* This is kind of special since our current guest state is
960	* potentially out of sync.
961	*
962	* @returns VBox status code.
963	* @param pVM The VM handle.
964	*/
965	static int emR3RawResumeHyper(PVM pVM)
966	{
967	int rc;
968	PCPUMCTX pCtx = pVM->em.s.pCtx;
969	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
970	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
971
972	/*
973	* Resume execution.
974	*/
975	CPUMRawEnter(pVM, NULL);
976	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
977	rc = VMMR3ResumeHyper(pVM);
978	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
979	rc = CPUMRawLeave(pVM, NULL, rc);
980	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
981
982	/*
983	* Deal with the return code.
984	*/
985	rc = emR3HighPriorityPostForcedActions(pVM, rc);
986	rc = emR3RawHandleRC(pVM, pCtx, rc);
987	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
988	return rc;
989	}
990
991
992	/**
993	* Steps rawmode.
994	*
995	* @returns VBox status code.
996	* @param pVM The VM handle.
997	*/
998	static int emR3RawStep(PVM pVM)
999	{
1000	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
1001	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
1002	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
1003	int rc;
1004	PCPUMCTX pCtx = pVM->em.s.pCtx;
1005	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
1006	#ifndef DEBUG_sandervl
1007	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
1008	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
1009	#endif
1010	if (fGuest)
1011	{
1012	/*
1013	* Check vital forced actions, but ignore pending interrupts and timers.
1014	*/
1015	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1016	{
1017	rc = emR3RawForcedActions(pVM, pCtx);
1018	if (RT_FAILURE(rc))
1019	return rc;
1020	}
1021
1022	/*
1023	* Set flags for single stepping.
1024	*/
1025	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1026	}
1027	else
1028	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1029
1030	/*
1031	* Single step.
1032	* We do not start time or anything, if anything we should just do a few nanoseconds.
1033	*/
1034	CPUMRawEnter(pVM, NULL);
1035	do
1036	{
1037	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
1038	rc = VMMR3ResumeHyper(pVM);
1039	else
1040	rc = VMMR3RawRunGC(pVM);
1041	#ifndef DEBUG_sandervl
1042	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
1043	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
1044	#endif
1045	} while ( rc == VINF_SUCCESS
1046	\|\| rc == VINF_EM_RAW_INTERRUPT);
1047	rc = CPUMRawLeave(pVM, NULL, rc);
1048	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1049
1050	/*
1051	* Make sure the trap flag is cleared.
1052	* (Too bad if the guest is trying to single step too.)
1053	*/
1054	if (fGuest)
1055	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1056	else
1057	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
1058
1059	/*
1060	* Deal with the return codes.
1061	*/
1062	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1063	rc = emR3RawHandleRC(pVM, pCtx, rc);
1064	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1065	return rc;
1066	}
1067
1068
1069	#ifdef DEBUG
1070
1071	/**
1072	* Steps hardware accelerated mode.
1073	*
1074	* @returns VBox status code.
1075	* @param pVM The VM handle.
1076	* @param idCpu VMCPU id.
1077	*/
1078	static int emR3HwAccStep(PVM pVM, RTCPUID idCpu)
1079	{
1080	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1081
1082	int rc;
1083	PCPUMCTX pCtx = pVM->em.s.pCtx;
1084	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
1085
1086	/*
1087	* Check vital forced actions, but ignore pending interrupts and timers.
1088	*/
1089	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1090	{
1091	rc = emR3RawForcedActions(pVM, pCtx);
1092	if (RT_FAILURE(rc))
1093	return rc;
1094	}
1095	/*
1096	* Set flags for single stepping.
1097	*/
1098	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1099
1100	/*
1101	* Single step.
1102	* We do not start time or anything, if anything we should just do a few nanoseconds.
1103	*/
1104	do
1105	{
1106	rc = VMMR3HwAccRunGC(pVM, idCpu);
1107	} while ( rc == VINF_SUCCESS
1108	\|\| rc == VINF_EM_RAW_INTERRUPT);
1109	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1110
1111	/*
1112	* Make sure the trap flag is cleared.
1113	* (Too bad if the guest is trying to single step too.)
1114	*/
1115	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1116
1117	/*
1118	* Deal with the return codes.
1119	*/
1120	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1121	rc = emR3RawHandleRC(pVM, pCtx, rc);
1122	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1123	return rc;
1124	}
1125
1126
1127	void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1128	{
1129	EMSTATE enmOldState = pVM->em.s.enmState;
1130
1131	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1132
1133	Log(("Single step BEGIN:\n"));
1134	for (uint32_t i = 0; i < cIterations; i++)
1135	{
1136	DBGFR3PrgStep(pVM);
1137	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1138	emR3RawStep(pVM);
1139	}
1140	Log(("Single step END:\n"));
1141	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1142	pVM->em.s.enmState = enmOldState;
1143	}
1144
1145
1146	static int emR3SingleStepExecHwAcc(PVM pVM, RTCPUID idCpu, uint32_t cIterations)
1147	{
1148	EMSTATE enmOldState = pVM->em.s.enmState;
1149
1150	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1151
1152	Log(("Single step BEGIN:\n"));
1153	for (uint32_t i = 0; i < cIterations; i++)
1154	{
1155	DBGFR3PrgStep(pVM);
1156	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1157	emR3HwAccStep(pVM, idCpu);
1158	if (!HWACCMR3CanExecuteGuest(pVM, pVM->em.s.pCtx))
1159	break;
1160	}
1161	Log(("Single step END:\n"));
1162	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1163	pVM->em.s.enmState = enmOldState;
1164	return VINF_EM_RESCHEDULE_REM;
1165	}
1166
1167
1168	static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1169	{
1170	EMSTATE enmOldState = pVM->em.s.enmState;
1171
1172	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1173
1174	Log(("Single step BEGIN:\n"));
1175	for (uint32_t i = 0; i < cIterations; i++)
1176	{
1177	DBGFR3PrgStep(pVM);
1178	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1179	emR3RemStep(pVM);
1180	if (emR3Reschedule(pVM, pVM->em.s.pCtx) != EMSTATE_REM)
1181	break;
1182	}
1183	Log(("Single step END:\n"));
1184	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1185	pVM->em.s.enmState = enmOldState;
1186	return VINF_EM_RESCHEDULE;
1187	}
1188
1189	#endif /* DEBUG */
1190
1191
1192	/**
1193	* Executes one (or perhaps a few more) instruction(s).
1194	*
1195	* @returns VBox status code suitable for EM.
1196	*
1197	* @param pVM VM handle.
1198	* @param rcGC GC return code
1199	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1200	* instruction and prefix the log output with this text.
1201	*/
1202	#ifdef LOG_ENABLED
1203	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1204	#else
1205	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1206	#endif
1207	{
1208	PCPUMCTX pCtx = pVM->em.s.pCtx;
1209	int rc;
1210
1211	/*
1212	*
1213	* The simple solution is to use the recompiler.
1214	* The better solution is to disassemble the current instruction and
1215	* try handle as many as possible without using REM.
1216	*
1217	*/
1218
1219	#ifdef LOG_ENABLED
1220	/*
1221	* Disassemble the instruction if requested.
1222	*/
1223	if (pszPrefix)
1224	{
1225	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1226	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1227	}
1228	#endif /* LOG_ENABLED */
1229
1230	/*
1231	* PATM is making life more interesting.
1232	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1233	* tell PATM there is a trap in this code and have it take the appropriate actions
1234	* to allow us execute the code in REM.
1235	*/
1236	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1237	{
1238	Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
1239
1240	RTGCPTR pNewEip;
1241	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1242	switch (rc)
1243	{
1244	/*
1245	* It's not very useful to emulate a single instruction and then go back to raw
1246	* mode; just execute the whole block until IF is set again.
1247	*/
1248	case VINF_SUCCESS:
1249	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
1250	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1251	pCtx->eip = pNewEip;
1252	Assert(pCtx->eip);
1253
1254	if (pCtx->eflags.Bits.u1IF)
1255	{
1256	/*
1257	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1258	*/
1259	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1260	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1261	}
1262	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1263	{
1264	/* special case: iret, that sets IF, detected a pending irq/event */
1265	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1266	}
1267	return VINF_EM_RESCHEDULE_REM;
1268
1269	/*
1270	* One instruction.
1271	*/
1272	case VINF_PATCH_EMULATE_INSTR:
1273	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1274	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1275	pCtx->eip = pNewEip;
1276	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1277
1278	/*
1279	* The patch was disabled, hand it to the REM.
1280	*/
1281	case VERR_PATCH_DISABLED:
1282	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
1283	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1284	pCtx->eip = pNewEip;
1285	if (pCtx->eflags.Bits.u1IF)
1286	{
1287	/*
1288	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1289	*/
1290	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1291	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1292	}
1293	return VINF_EM_RESCHEDULE_REM;
1294
1295	/* Force continued patch exection; usually due to write monitored stack. */
1296	case VINF_PATCH_CONTINUE:
1297	return VINF_SUCCESS;
1298
1299	default:
1300	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
1301	return VERR_IPE_UNEXPECTED_STATUS;
1302	}
1303	}
1304
1305	#if 0
1306	/* Try our own instruction emulator before falling back to the recompiler. */
1307	DISCPUSTATE Cpu;
1308	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1309	if (RT_SUCCESS(rc))
1310	{
1311	uint32_t size;
1312
1313	switch (Cpu.pCurInstr->opcode)
1314	{
1315	/* @todo we can do more now */
1316	case OP_MOV:
1317	case OP_AND:
1318	case OP_OR:
1319	case OP_XOR:
1320	case OP_POP:
1321	case OP_INC:
1322	case OP_DEC:
1323	case OP_XCHG:
1324	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1325	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1326	if (RT_SUCCESS(rc))
1327	{
1328	pCtx->rip += Cpu.opsize;
1329	#ifdef EM_NOTIFY_HWACCM
1330	if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1331	HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
1332	#endif
1333	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1334	return rc;
1335	}
1336	if (rc != VERR_EM_INTERPRETER)
1337	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
1338	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1339	break;
1340	}
1341	}
1342	#endif /* 0 */
1343	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1344	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
1345	rc = REMR3EmulateInstruction(pVM);
1346	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1347
1348	#ifdef EM_NOTIFY_HWACCM
1349	if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1350	HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
1351	#endif
1352	return rc;
1353	}
1354
1355
1356	/**
1357	* Executes one (or perhaps a few more) instruction(s).
1358	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1359	*
1360	* @returns VBox status code suitable for EM.
1361	* @param pVM VM handle.
1362	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1363	* instruction and prefix the log output with this text.
1364	* @param rcGC GC return code
1365	*/
1366	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1367	{
1368	#ifdef LOG_ENABLED
1369	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1370	#else
1371	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1372	#endif
1373	}
1374
1375	/**
1376	* Executes one (or perhaps a few more) IO instruction(s).
1377	*
1378	* @returns VBox status code suitable for EM.
1379	* @param pVM VM handle.
1380	*/
1381	int emR3RawExecuteIOInstruction(PVM pVM)
1382	{
1383	int rc;
1384	PCPUMCTX pCtx = pVM->em.s.pCtx;
1385
1386	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1387
1388	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1389	* as io instructions tend to come in packages of more than one
1390	*/
1391	DISCPUSTATE Cpu;
1392	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "IO EMU");
1393	if (RT_SUCCESS(rc))
1394	{
1395	rc = VINF_EM_RAW_EMULATE_INSTR;
1396
1397	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1398	{
1399	switch (Cpu.pCurInstr->opcode)
1400	{
1401	case OP_IN:
1402	{
1403	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1404	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1405	break;
1406	}
1407
1408	case OP_OUT:
1409	{
1410	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1411	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1412	break;
1413	}
1414	}
1415	}
1416	else if (Cpu.prefix & PREFIX_REP)
1417	{
1418	switch (Cpu.pCurInstr->opcode)
1419	{
1420	case OP_INSB:
1421	case OP_INSWD:
1422	{
1423	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1424	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1425	break;
1426	}
1427
1428	case OP_OUTSB:
1429	case OP_OUTSWD:
1430	{
1431	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1432	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1433	break;
1434	}
1435	}
1436	}
1437
1438	/*
1439	* Handled the I/O return codes.
1440	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1441	*/
1442	if (IOM_SUCCESS(rc))
1443	{
1444	pCtx->rip += Cpu.opsize;
1445	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1446	return rc;
1447	}
1448
1449	if (rc == VINF_EM_RAW_GUEST_TRAP)
1450	{
1451	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1452	rc = emR3RawGuestTrap(pVM);
1453	return rc;
1454	}
1455	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1456
1457	if (RT_FAILURE(rc))
1458	{
1459	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1460	return rc;
1461	}
1462	AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc=%Rrc\n", rc));
1463	}
1464	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1465	return emR3RawExecuteInstruction(pVM, "IO: ");
1466	}
1467
1468
1469	/**
1470	* Handle a guest context trap.
1471	*
1472	* @returns VBox status code suitable for EM.
1473	* @param pVM VM handle.
1474	*/
1475	static int emR3RawGuestTrap(PVM pVM)
1476	{
1477	PCPUMCTX pCtx = pVM->em.s.pCtx;
1478
1479	/*
1480	* Get the trap info.
1481	*/
1482	uint8_t u8TrapNo;
1483	TRPMEVENT enmType;
1484	RTGCUINT uErrorCode;
1485	RTGCUINTPTR uCR2;
1486	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1487	if (RT_FAILURE(rc))
1488	{
1489	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
1490	return rc;
1491	}
1492
1493	/*
1494	* Traps can be directly forwarded in hardware accelerated mode.
1495	*/
1496	if (HWACCMR3IsActive(pVM))
1497	{
1498	#ifdef LOGGING_ENABLED
1499	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1500	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1501	#endif
1502	return VINF_EM_RESCHEDULE_HWACC;
1503	}
1504
1505	#if 1 /* Experimental: Review, disable if it causes trouble. */
1506	/*
1507	* Handle traps in patch code first.
1508	*
1509	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
1510	* but several traps isn't handled specially by TRPM in RC and we end up here
1511	* instead. One example is #DE.
1512	*/
1513	uint32_t uCpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
1514	if ( uCpl == 0
1515	&& PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1516	{
1517	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
1518	return emR3PatchTrap(pVM, pCtx, rc);
1519	}
1520	#endif
1521
1522	/*
1523	* If the guest gate is marked unpatched, then we will check again if we can patch it.
1524	* (This assumes that we've already tried and failed to dispatch the trap in
1525	* RC for the gates that already has been patched. Which is true for most high
1526	* volume traps, because these are handled specially, but not for odd ones like #DE.)
1527	*/
1528	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
1529	{
1530	CSAMR3CheckGates(pVM, u8TrapNo, 1);
1531	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
1532
1533	/* If it was successful, then we could go back to raw mode. */
1534	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
1535	{
1536	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
1537	rc = EMR3CheckRawForcedActions(pVM);
1538	AssertRCReturn(rc, rc);
1539
1540	TRPMERRORCODE enmError = uErrorCode != ~0U
1541	? TRPM_TRAP_HAS_ERRORCODE
1542	: TRPM_TRAP_NO_ERRORCODE;
1543	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
1544	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1545	{
1546	TRPMResetTrap(pVM);
1547	return VINF_EM_RESCHEDULE_RAW;
1548	}
1549	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
1550	}
1551	}
1552
1553	/*
1554	* Scan kernel code that traps; we might not get another chance.
1555	*/
1556	/** @todo move this up before the dispatching? */
1557	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1558	&& !pCtx->eflags.Bits.u1VM)
1559	{
1560	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1561	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1562	}
1563
1564	/*
1565	* Trap specific handling.
1566	*/
1567	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1568	{
1569	/*
1570	* If MONITOR & MWAIT are supported, then interpret them here.
1571	*/
1572	DISCPUSTATE cpu;
1573	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1574	if ( RT_SUCCESS(rc)
1575	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1576	{
1577	uint32_t u32Dummy, u32Features, u32ExtFeatures;
1578	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1579	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1580	{
1581	rc = TRPMResetTrap(pVM);
1582	AssertRC(rc);
1583
1584	uint32_t opsize;
1585	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
1586	if (RT_SUCCESS(rc))
1587	{
1588	pCtx->rip += cpu.opsize;
1589	#ifdef EM_NOTIFY_HWACCM
1590	if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1591	HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
1592	#endif
1593	return rc;
1594	}
1595	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1596	}
1597	}
1598	}
1599	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1600	{
1601	/*
1602	* Handle I/O bitmap?
1603	*/
1604	/** @todo We're not supposed to be here with a false guest trap concerning
1605	* I/O access. We can easily handle those in RC. */
1606	DISCPUSTATE cpu;
1607	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1608	if ( RT_SUCCESS(rc)
1609	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1610	{
1611	/*
1612	* We should really check the TSS for the IO bitmap, but it's not like this
1613	* lazy approach really makes things worse.
1614	*/
1615	rc = TRPMResetTrap(pVM);
1616	AssertRC(rc);
1617	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1618	}
1619	}
1620
1621	#ifdef LOG_ENABLED
1622	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1623	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1624
1625	/* Get guest page information. */
1626	uint64_t fFlags = 0;
1627	RTGCPHYS GCPhys = 0;
1628	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1629	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1630	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1631	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1632	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1633	#endif
1634
1635	/*
1636	* #PG has CR2.
1637	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1638	*/
1639	if (u8TrapNo == 14 /* #PG */)
1640	pCtx->cr2 = uCR2;
1641
1642	return VINF_EM_RESCHEDULE_REM;
1643	}
1644
1645
1646	/**
1647	* Handle a ring switch trap.
1648	* Need to do statistics and to install patches. The result is going to REM.
1649	*
1650	* @returns VBox status code suitable for EM.
1651	* @param pVM VM handle.
1652	*/
1653	int emR3RawRingSwitch(PVM pVM)
1654	{
1655	int rc;
1656	DISCPUSTATE Cpu;
1657	PCPUMCTX pCtx = pVM->em.s.pCtx;
1658
1659	/*
1660	* sysenter, syscall & callgate
1661	*/
1662	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1663	if (RT_SUCCESS(rc))
1664	{
1665	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1666	{
1667	if (pCtx->SysEnter.cs != 0)
1668	{
1669	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1670	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1671	if (RT_SUCCESS(rc))
1672	{
1673	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1674	return VINF_EM_RESCHEDULE_RAW;
1675	}
1676	}
1677	}
1678
1679	#ifdef VBOX_WITH_STATISTICS
1680	switch (Cpu.pCurInstr->opcode)
1681	{
1682	case OP_SYSENTER:
1683	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysEnter);
1684	break;
1685	case OP_SYSEXIT:
1686	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysExit);
1687	break;
1688	case OP_SYSCALL:
1689	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysCall);
1690	break;
1691	case OP_SYSRET:
1692	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysRet);
1693	break;
1694	}
1695	#endif
1696	}
1697	else
1698	AssertRC(rc);
1699
1700	/* go to the REM to emulate a single instruction */
1701	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1702	}
1703
1704
1705	/**
1706	* Handle a trap (\#PF or \#GP) in patch code
1707	*
1708	* @returns VBox status code suitable for EM.
1709	* @param pVM VM handle.
1710	* @param pCtx CPU context
1711	* @param gcret GC return code
1712	*/
1713	static int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1714	{
1715	uint8_t u8TrapNo;
1716	int rc;
1717	TRPMEVENT enmType;
1718	RTGCUINT uErrorCode;
1719	RTGCUINTPTR uCR2;
1720
1721	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1722
1723	if (gcret == VINF_PATM_PATCH_INT3)
1724	{
1725	u8TrapNo = 3;
1726	uCR2 = 0;
1727	uErrorCode = 0;
1728	}
1729	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
1730	{
1731	/* No active trap in this case. Kind of ugly. */
1732	u8TrapNo = X86_XCPT_GP;
1733	uCR2 = 0;
1734	uErrorCode = 0;
1735	}
1736	else
1737	{
1738	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1739	if (RT_FAILURE(rc))
1740	{
1741	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
1742	return rc;
1743	}
1744	/* Reset the trap as we'll execute the original instruction again. */
1745	TRPMResetTrap(pVM);
1746	}
1747
1748	/*
1749	* Deal with traps inside patch code.
1750	* (This code won't run outside GC.)
1751	*/
1752	if (u8TrapNo != 1)
1753	{
1754	#ifdef LOG_ENABLED
1755	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1756	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1757
1758	DISCPUSTATE Cpu;
1759	int rc;
1760
1761	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1762	if ( RT_SUCCESS(rc)
1763	&& Cpu.pCurInstr->opcode == OP_IRET)
1764	{
1765	uint32_t eip, selCS, uEFlags;
1766
1767	/* Iret crashes are bad as we have already changed the flags on the stack */
1768	rc = PGMPhysSimpleReadGCPtr(pVM, &eip, pCtx->esp, 4);
1769	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1770	rc \|= PGMPhysSimpleReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1771	if (rc == VINF_SUCCESS)
1772	{
1773	if ( (uEFlags & X86_EFL_VM)
1774	\|\| (selCS & X86_SEL_RPL) == 3)
1775	{
1776	uint32_t selSS, esp;
1777
1778	rc \|= PGMPhysSimpleReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1779	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1780
1781	if (uEFlags & X86_EFL_VM)
1782	{
1783	uint32_t selDS, selES, selFS, selGS;
1784	rc = PGMPhysSimpleReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1785	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1786	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1787	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1788	if (rc == VINF_SUCCESS)
1789	{
1790	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1791	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1792	}
1793	}
1794	else
1795	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1796	}
1797	else
1798	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
1799	}
1800	}
1801	#endif /* LOG_ENABLED */
1802	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1803	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1804
1805	RTGCPTR pNewEip;
1806	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1807	switch (rc)
1808	{
1809	/*
1810	* Execute the faulting instruction.
1811	*/
1812	case VINF_SUCCESS:
1813	{
1814	/** @todo execute a whole block */
1815	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
1816	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1817	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1818
1819	pCtx->eip = pNewEip;
1820	AssertRelease(pCtx->eip);
1821
1822	if (pCtx->eflags.Bits.u1IF)
1823	{
1824	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1825	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1826	*/
1827	if ( u8TrapNo == X86_XCPT_GP
1828	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1829	{
1830	/** @todo move to PATMR3HandleTrap */
1831	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
1832	PATMR3RemovePatch(pVM, pCtx->eip);
1833	}
1834
1835	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1836	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
1837
1838	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1839	/* Interrupts are enabled; just go back to the original instruction.
1840	return VINF_SUCCESS; */
1841	}
1842	return VINF_EM_RESCHEDULE_REM;
1843	}
1844
1845	/*
1846	* One instruction.
1847	*/
1848	case VINF_PATCH_EMULATE_INSTR:
1849	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1850	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1851	pCtx->eip = pNewEip;
1852	AssertRelease(pCtx->eip);
1853	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1854
1855	/*
1856	* The patch was disabled, hand it to the REM.
1857	*/
1858	case VERR_PATCH_DISABLED:
1859	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1860	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1861	pCtx->eip = pNewEip;
1862	AssertRelease(pCtx->eip);
1863
1864	if (pCtx->eflags.Bits.u1IF)
1865	{
1866	/*
1867	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1868	*/
1869	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1870	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1871	}
1872	return VINF_EM_RESCHEDULE_REM;
1873
1874	/* Force continued patch exection; usually due to write monitored stack. */
1875	case VINF_PATCH_CONTINUE:
1876	return VINF_SUCCESS;
1877
1878	/*
1879	* Anything else is fatal.
1880	*/
1881	default:
1882	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
1883	return VERR_IPE_UNEXPECTED_STATUS;
1884	}
1885	}
1886	return VINF_SUCCESS;
1887	}
1888
1889
1890	/**
1891	* Handle a privileged instruction.
1892	*
1893	* @returns VBox status code suitable for EM.
1894	* @param pVM VM handle.
1895	*/
1896	int emR3RawPrivileged(PVM pVM)
1897	{
1898	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1899	PCPUMCTX pCtx = pVM->em.s.pCtx;
1900
1901	Assert(!pCtx->eflags.Bits.u1VM);
1902
1903	if (PATMIsEnabled(pVM))
1904	{
1905	/*
1906	* Check if in patch code.
1907	*/
1908	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1909	{
1910	#ifdef LOG_ENABLED
1911	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1912	#endif
1913	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1914	return VERR_EM_RAW_PATCH_CONFLICT;
1915	}
1916	if ( (pCtx->ss & X86_SEL_RPL) == 0
1917	&& !pCtx->eflags.Bits.u1VM
1918	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1919	{
1920	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1921	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1922	if (RT_SUCCESS(rc))
1923	{
1924	#ifdef LOG_ENABLED
1925	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1926	#endif
1927	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1928	return VINF_SUCCESS;
1929	}
1930	}
1931	}
1932
1933	#ifdef LOG_ENABLED
1934	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1935	{
1936	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1937	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1938	}
1939	#endif
1940
1941	/*
1942	* Instruction statistics and logging.
1943	*/
1944	DISCPUSTATE Cpu;
1945	int rc;
1946
1947	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1948	if (RT_SUCCESS(rc))
1949	{
1950	#ifdef VBOX_WITH_STATISTICS
1951	PEMSTATS pStats = pVM->em.s.CTX_SUFF(pStats);
1952	switch (Cpu.pCurInstr->opcode)
1953	{
1954	case OP_INVLPG:
1955	STAM_COUNTER_INC(&pStats->StatInvlpg);
1956	break;
1957	case OP_IRET:
1958	STAM_COUNTER_INC(&pStats->StatIret);
1959	break;
1960	case OP_CLI:
1961	STAM_COUNTER_INC(&pStats->StatCli);
1962	emR3RecordCli(pVM, pCtx->rip);
1963	break;
1964	case OP_STI:
1965	STAM_COUNTER_INC(&pStats->StatSti);
1966	break;
1967	case OP_INSB:
1968	case OP_INSWD:
1969	case OP_IN:
1970	case OP_OUTSB:
1971	case OP_OUTSWD:
1972	case OP_OUT:
1973	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1974	break;
1975
1976	case OP_MOV_CR:
1977	if (Cpu.param1.flags & USE_REG_GEN32)
1978	{
1979	//read
1980	Assert(Cpu.param2.flags & USE_REG_CR);
1981	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1982	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1983	}
1984	else
1985	{
1986	//write
1987	Assert(Cpu.param1.flags & USE_REG_CR);
1988	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1989	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1990	}
1991	break;
1992
1993	case OP_MOV_DR:
1994	STAM_COUNTER_INC(&pStats->StatMovDRx);
1995	break;
1996	case OP_LLDT:
1997	STAM_COUNTER_INC(&pStats->StatMovLldt);
1998	break;
1999	case OP_LIDT:
2000	STAM_COUNTER_INC(&pStats->StatMovLidt);
2001	break;
2002	case OP_LGDT:
2003	STAM_COUNTER_INC(&pStats->StatMovLgdt);
2004	break;
2005	case OP_SYSENTER:
2006	STAM_COUNTER_INC(&pStats->StatSysEnter);
2007	break;
2008	case OP_SYSEXIT:
2009	STAM_COUNTER_INC(&pStats->StatSysExit);
2010	break;
2011	case OP_SYSCALL:
2012	STAM_COUNTER_INC(&pStats->StatSysCall);
2013	break;
2014	case OP_SYSRET:
2015	STAM_COUNTER_INC(&pStats->StatSysRet);
2016	break;
2017	case OP_HLT:
2018	STAM_COUNTER_INC(&pStats->StatHlt);
2019	break;
2020	default:
2021	STAM_COUNTER_INC(&pStats->StatMisc);
2022	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
2023	break;
2024	}
2025	#endif /* VBOX_WITH_STATISTICS */
2026	if ( (pCtx->ss & X86_SEL_RPL) == 0
2027	&& !pCtx->eflags.Bits.u1VM
2028	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
2029	{
2030	uint32_t size;
2031
2032	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
2033	switch (Cpu.pCurInstr->opcode)
2034	{
2035	case OP_CLI:
2036	pCtx->eflags.u32 &= ~X86_EFL_IF;
2037	Assert(Cpu.opsize == 1);
2038	pCtx->rip += Cpu.opsize;
2039	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2040	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
2041
2042	case OP_STI:
2043	pCtx->eflags.u32 \|= X86_EFL_IF;
2044	EMSetInhibitInterruptsPC(pVM, pCtx->rip + Cpu.opsize);
2045	Assert(Cpu.opsize == 1);
2046	pCtx->rip += Cpu.opsize;
2047	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2048	return VINF_SUCCESS;
2049
2050	case OP_HLT:
2051	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
2052	{
2053	PATMTRANSSTATE enmState;
2054	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
2055
2056	if (enmState == PATMTRANS_OVERWRITTEN)
2057	{
2058	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2059	Assert(rc == VERR_PATCH_DISABLED);
2060	/* Conflict detected, patch disabled */
2061	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
2062
2063	enmState = PATMTRANS_SAFE;
2064	}
2065
2066	/* The translation had better be successful. Otherwise we can't recover. */
2067	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
2068	if (enmState != PATMTRANS_OVERWRITTEN)
2069	pCtx->eip = pOrgInstrGC;
2070	}
2071	/* no break; we could just return VINF_EM_HALT here */
2072
2073	case OP_MOV_CR:
2074	case OP_MOV_DR:
2075	#ifdef LOG_ENABLED
2076	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2077	{
2078	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2079	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2080	}
2081	#endif
2082
2083	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2084	if (RT_SUCCESS(rc))
2085	{
2086	pCtx->rip += Cpu.opsize;
2087	#ifdef EM_NOTIFY_HWACCM
2088	if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
2089	HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
2090	#endif
2091	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2092
2093	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2094	&& Cpu.param1.flags == USE_REG_CR /* write */
2095	)
2096	{
2097	/* Deal with CR0 updates inside patch code that force
2098	* us to go to the recompiler.
2099	*/
2100	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
2101	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
2102	{
2103	PATMTRANSSTATE enmState;
2104	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
2105
2106	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
2107	if (enmState == PATMTRANS_OVERWRITTEN)
2108	{
2109	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2110	Assert(rc == VERR_PATCH_DISABLED);
2111	/* Conflict detected, patch disabled */
2112	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
2113	enmState = PATMTRANS_SAFE;
2114	}
2115	/* The translation had better be successful. Otherwise we can't recover. */
2116	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
2117	if (enmState != PATMTRANS_OVERWRITTEN)
2118	pCtx->rip = pOrgInstrGC;
2119	}
2120
2121	/* Reschedule is necessary as the execution/paging mode might have changed. */
2122	return VINF_EM_RESCHEDULE;
2123	}
2124	return rc; /* can return VINF_EM_HALT as well. */
2125	}
2126	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
2127	break; /* fall back to the recompiler */
2128	}
2129	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2130	}
2131	}
2132
2133	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2134	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
2135
2136	return emR3RawExecuteInstruction(pVM, "PRIV");
2137	}
2138
2139
2140	/**
2141	* Update the forced rawmode execution modifier.
2142	*
2143	* This function is called when we're returning from the raw-mode loop(s). If we're
2144	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2145	* if not in patch code, the flag will be cleared.
2146	*
2147	* We should never interrupt patch code while it's being executed. Cli patches can
2148	* contain big code blocks, but they are always executed with IF=0. Other patches
2149	* replace single instructions and should be atomic.
2150	*
2151	* @returns Updated rc.
2152	*
2153	* @param pVM The VM handle.
2154	* @param pCtx The guest CPU context.
2155	* @param rc The result code.
2156	*/
2157	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2158	{
2159	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2160	{
2161	/* ignore reschedule attempts. */
2162	switch (rc)
2163	{
2164	case VINF_EM_RESCHEDULE:
2165	case VINF_EM_RESCHEDULE_REM:
2166	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
2167	rc = VINF_SUCCESS;
2168	break;
2169	}
2170	pVM->em.s.fForceRAW = true;
2171	}
2172	else
2173	pVM->em.s.fForceRAW = false;
2174	return rc;
2175	}
2176
2177
2178	/**
2179	* Process a subset of the raw-mode return code.
2180	*
2181	* Since we have to share this with raw-mode single stepping, this inline
2182	* function has been created to avoid code duplication.
2183	*
2184	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2185	* @returns VBox status code to return to the EM main loop.
2186	*
2187	* @param pVM The VM handle
2188	* @param rc The return code.
2189	* @param pCtx The guest cpu context.
2190	*/
2191	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2192	{
2193	switch (rc)
2194	{
2195	/*
2196	* Common & simple ones.
2197	*/
2198	case VINF_SUCCESS:
2199	break;
2200	case VINF_EM_RESCHEDULE_RAW:
2201	case VINF_EM_RESCHEDULE_HWACC:
2202	case VINF_EM_RAW_INTERRUPT:
2203	case VINF_EM_RAW_TO_R3:
2204	case VINF_EM_RAW_TIMER_PENDING:
2205	case VINF_EM_PENDING_REQUEST:
2206	rc = VINF_SUCCESS;
2207	break;
2208
2209	/*
2210	* Privileged instruction.
2211	*/
2212	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2213	case VINF_PATM_PATCH_TRAP_GP:
2214	rc = emR3RawPrivileged(pVM);
2215	break;
2216
2217	/*
2218	* Got a trap which needs dispatching.
2219	*/
2220	case VINF_EM_RAW_GUEST_TRAP:
2221	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2222	{
2223	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2224	rc = VERR_EM_RAW_PATCH_CONFLICT;
2225	break;
2226	}
2227	rc = emR3RawGuestTrap(pVM);
2228	break;
2229
2230	/*
2231	* Trap in patch code.
2232	*/
2233	case VINF_PATM_PATCH_TRAP_PF:
2234	case VINF_PATM_PATCH_INT3:
2235	rc = emR3PatchTrap(pVM, pCtx, rc);
2236	break;
2237
2238	case VINF_PATM_DUPLICATE_FUNCTION:
2239	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2240	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2241	AssertRC(rc);
2242	rc = VINF_SUCCESS;
2243	break;
2244
2245	case VINF_PATM_CHECK_PATCH_PAGE:
2246	rc = PATMR3HandleMonitoredPage(pVM);
2247	AssertRC(rc);
2248	rc = VINF_SUCCESS;
2249	break;
2250
2251	/*
2252	* Patch manager.
2253	*/
2254	case VERR_EM_RAW_PATCH_CONFLICT:
2255	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
2256	break;
2257
2258	#ifdef VBOX_WITH_VMI
2259	/*
2260	* PARAV function.
2261	*/
2262	case VINF_EM_RESCHEDULE_PARAV:
2263	rc = PARAVCallFunction(pVM);
2264	break;
2265	#endif
2266
2267	/*
2268	* Memory mapped I/O access - attempt to patch the instruction
2269	*/
2270	case VINF_PATM_HC_MMIO_PATCH_READ:
2271	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2272	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2273	if (RT_FAILURE(rc))
2274	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2275	break;
2276
2277	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2278	AssertFailed(); /* not yet implemented. */
2279	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2280	break;
2281
2282	/*
2283	* Conflict or out of page tables.
2284	*
2285	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2286	* do here is to execute the pending forced actions.
2287	*/
2288	case VINF_PGM_SYNC_CR3:
2289	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2290	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2291	rc = VINF_SUCCESS;
2292	break;
2293
2294	/*
2295	* Paging mode change.
2296	*/
2297	case VINF_PGM_CHANGE_MODE:
2298	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2299	if (RT_SUCCESS(rc))
2300	rc = VINF_EM_RESCHEDULE;
2301	break;
2302
2303	/*
2304	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2305	*/
2306	case VINF_CSAM_PENDING_ACTION:
2307	rc = VINF_SUCCESS;
2308	break;
2309
2310	/*
2311	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2312	*/
2313	case VINF_EM_RAW_INTERRUPT_PENDING:
2314	case VINF_EM_RAW_RING_SWITCH_INT:
2315	Assert(TRPMHasTrap(pVM));
2316	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2317
2318	if (TRPMHasTrap(pVM))
2319	{
2320	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2321	uint8_t u8Interrupt = TRPMGetTrapNo(pVM);
2322	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2323	{
2324	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2325	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2326	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2327	}
2328	}
2329	rc = VINF_EM_RESCHEDULE_REM;
2330	break;
2331
2332	/*
2333	* Other ring switch types.
2334	*/
2335	case VINF_EM_RAW_RING_SWITCH:
2336	rc = emR3RawRingSwitch(pVM);
2337	break;
2338
2339	/*
2340	* REMGCNotifyInvalidatePage() failed because of overflow.
2341	*/
2342	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2343	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2344	REMR3ReplayInvalidatedPages(pVM);
2345	rc = VINF_SUCCESS;
2346	break;
2347
2348	/*
2349	* I/O Port access - emulate the instruction.
2350	*/
2351	case VINF_IOM_HC_IOPORT_READ:
2352	case VINF_IOM_HC_IOPORT_WRITE:
2353	rc = emR3RawExecuteIOInstruction(pVM);
2354	break;
2355
2356	/*
2357	* Memory mapped I/O access - emulate the instruction.
2358	*/
2359	case VINF_IOM_HC_MMIO_READ:
2360	case VINF_IOM_HC_MMIO_WRITE:
2361	case VINF_IOM_HC_MMIO_READ_WRITE:
2362	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2363	break;
2364
2365	/*
2366	* (MM)IO intensive code block detected; fall back to the recompiler for better performance
2367	*/
2368	case VINF_EM_RAW_EMULATE_IO_BLOCK:
2369	rc =HWACCMR3EmulateIoBlock(pVM, pCtx);
2370	break;
2371
2372	/*
2373	* Execute instruction.
2374	*/
2375	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2376	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2377	break;
2378	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2379	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2380	break;
2381	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2382	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2383	break;
2384	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2385	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2386	break;
2387	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2388	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2389	break;
2390
2391	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2392	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2393	rc = emR3RawPrivileged(pVM);
2394	break;
2395
2396	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2397	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2398	break;
2399
2400	case VINF_EM_RAW_EMULATE_INSTR:
2401	case VINF_PATCH_EMULATE_INSTR:
2402	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2403	break;
2404
2405	/*
2406	* Stale selector and iret traps => REM.
2407	*/
2408	case VINF_EM_RAW_STALE_SELECTOR:
2409	case VINF_EM_RAW_IRET_TRAP:
2410	/* We will not go to the recompiler if EIP points to patch code. */
2411	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2412	{
2413	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2414	}
2415	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
2416	rc = VINF_EM_RESCHEDULE_REM;
2417	break;
2418
2419	/*
2420	* Up a level.
2421	*/
2422	case VINF_EM_TERMINATE:
2423	case VINF_EM_OFF:
2424	case VINF_EM_RESET:
2425	case VINF_EM_SUSPEND:
2426	case VINF_EM_HALT:
2427	case VINF_EM_RESUME:
2428	case VINF_EM_RESCHEDULE:
2429	case VINF_EM_RESCHEDULE_REM:
2430	break;
2431
2432	/*
2433	* Up a level and invoke the debugger.
2434	*/
2435	case VINF_EM_DBG_STEPPED:
2436	case VINF_EM_DBG_BREAKPOINT:
2437	case VINF_EM_DBG_STEP:
2438	case VINF_EM_DBG_HYPER_BREAKPOINT:
2439	case VINF_EM_DBG_HYPER_STEPPED:
2440	case VINF_EM_DBG_HYPER_ASSERTION:
2441	case VINF_EM_DBG_STOP:
2442	break;
2443
2444	/*
2445	* Up a level, dump and debug.
2446	*/
2447	case VERR_TRPM_DONT_PANIC:
2448	case VERR_TRPM_PANIC:
2449	case VERR_VMM_RING0_ASSERTION:
2450	break;
2451
2452	/*
2453	* Up a level, after HwAccM have done some release logging.
2454	*/
2455	case VERR_VMX_INVALID_VMCS_FIELD:
2456	case VERR_VMX_INVALID_VMCS_PTR:
2457	case VERR_VMX_INVALID_VMXON_PTR:
2458	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2459	case VERR_VMX_UNEXPECTED_EXCEPTION:
2460	case VERR_VMX_UNEXPECTED_EXIT_CODE:
2461	case VERR_VMX_INVALID_GUEST_STATE:
2462	case VERR_VMX_UNABLE_TO_START_VM:
2463	case VERR_VMX_UNABLE_TO_RESUME_VM:
2464	HWACCMR3CheckError(pVM, rc);
2465	break;
2466	/*
2467	* Anything which is not known to us means an internal error
2468	* and the termination of the VM!
2469	*/
2470	default:
2471	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
2472	break;
2473	}
2474	return rc;
2475	}
2476
2477
2478	/**
2479	* Check for pending raw actions
2480	*
2481	* @returns VBox status code.
2482	* @param pVM The VM to operate on.
2483	*/
2484	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2485	{
2486	return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2487	}
2488
2489
2490	/**
2491	* Process raw-mode specific forced actions.
2492	*
2493	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2494	*
2495	* @returns VBox status code.
2496	* Only the normal success/failure stuff, no VINF_EM_*.
2497	* @param pVM The VM handle.
2498	* @param pCtx The guest CPUM register context.
2499	*/
2500	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2501	{
2502	/*
2503	* Note that the order is vitally important!
2504	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2505	*/
2506
2507
2508	/*
2509	* Sync selector tables.
2510	*/
2511	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2512	{
2513	int rc = SELMR3UpdateFromCPUM(pVM);
2514	if (RT_FAILURE(rc))
2515	return rc;
2516	}
2517
2518	/*
2519	* Sync IDT.
2520	*/
2521	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2522	{
2523	int rc = TRPMR3SyncIDT(pVM);
2524	if (RT_FAILURE(rc))
2525	return rc;
2526	}
2527
2528	/*
2529	* Sync TSS.
2530	*/
2531	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2532	{
2533	int rc = SELMR3SyncTSS(pVM);
2534	if (RT_FAILURE(rc))
2535	return rc;
2536	}
2537
2538	/*
2539	* Sync page directory.
2540	*/
2541	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2542	{
2543	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2544	if (RT_FAILURE(rc))
2545	return rc;
2546
2547	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2548
2549	/* Prefetch pages for EIP and ESP */
2550	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2551	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2552	if (rc == VINF_SUCCESS)
2553	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2554	if (rc != VINF_SUCCESS)
2555	{
2556	if (rc != VINF_PGM_SYNC_CR3)
2557	return rc;
2558	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2559	if (RT_FAILURE(rc))
2560	return rc;
2561	}
2562	/** @todo maybe prefetch the supervisor stack page as well */
2563	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2564	}
2565
2566	/*
2567	* Allocate handy pages (just in case the above actions have consumed some pages).
2568	*/
2569	if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
2570	{
2571	int rc = PGMR3PhysAllocateHandyPages(pVM);
2572	if (RT_FAILURE(rc))
2573	return rc;
2574	}
2575
2576	return VINF_SUCCESS;
2577	}
2578
2579
2580	/**
2581	* Executes raw code.
2582	*
2583	* This function contains the raw-mode version of the inner
2584	* execution loop (the outer loop being in EMR3ExecuteVM()).
2585	*
2586	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2587	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2588	*
2589	* @param pVM VM handle.
2590	* @param pfFFDone Where to store an indicator telling whether or not
2591	* FFs were done before returning.
2592	*/
2593	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2594	{
2595	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2596
2597	int rc = VERR_INTERNAL_ERROR;
2598	PCPUMCTX pCtx = pVM->em.s.pCtx;
2599	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2600	pVM->em.s.fForceRAW = false;
2601	*pfFFDone = false;
2602
2603
2604	/*
2605	*
2606	* Spin till we get a forced action or raw mode status code resulting in
2607	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2608	*
2609	*/
2610	for (;;)
2611	{
2612	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2613
2614	/*
2615	* Check various preconditions.
2616	*/
2617	#ifdef VBOX_STRICT
2618	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2619	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2620	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2621	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2622	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2623	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2624	&& PGMMapHasConflicts(pVM))
2625	{
2626	PGMMapCheck(pVM);
2627	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2628	return VERR_INTERNAL_ERROR;
2629	}
2630	#endif /* VBOX_STRICT */
2631
2632	/*
2633	* Process high priority pre-execution raw-mode FFs.
2634	*/
2635	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2636	{
2637	rc = emR3RawForcedActions(pVM, pCtx);
2638	if (RT_FAILURE(rc))
2639	break;
2640	}
2641
2642	/*
2643	* If we're going to execute ring-0 code, the guest state needs to
2644	* be modified a bit and some of the state components (IF, SS/CS RPL,
2645	* and perhaps EIP) needs to be stored with PATM.
2646	*/
2647	rc = CPUMRawEnter(pVM, NULL);
2648	if (rc != VINF_SUCCESS)
2649	{
2650	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2651	break;
2652	}
2653
2654	/*
2655	* Scan code before executing it. Don't bother with user mode or V86 code
2656	*/
2657	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2658	&& !pCtx->eflags.Bits.u1VM
2659	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2660	{
2661	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2662	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2663	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2664	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2665	{
2666	rc = emR3RawForcedActions(pVM, pCtx);
2667	if (RT_FAILURE(rc))
2668	break;
2669	}
2670	}
2671
2672	#ifdef LOG_ENABLED
2673	/*
2674	* Log important stuff before entering GC.
2675	*/
2676	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2677	if (pCtx->eflags.Bits.u1VM)
2678	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2679	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2680	{
2681	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2682	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2683	}
2684	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2685	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2686	#endif /* LOG_ENABLED */
2687
2688
2689
2690	/*
2691	* Execute the code.
2692	*/
2693	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2694	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2695	VMMR3Unlock(pVM);
2696	rc = VMMR3RawRunGC(pVM);
2697	VMMR3Lock(pVM);
2698	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2699	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2700
2701	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2702	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
2703
2704
2705
2706	/*
2707	* Restore the real CPU state and deal with high priority post
2708	* execution FFs before doing anything else.
2709	*/
2710	rc = CPUMRawLeave(pVM, NULL, rc);
2711	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2712	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2713	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2714
2715	#ifdef VBOX_STRICT
2716	/*
2717	* Assert TSS consistency & rc vs patch code.
2718	*/
2719	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2720	&& EMIsRawRing0Enabled(pVM))
2721	SELMR3CheckTSS(pVM);
2722	switch (rc)
2723	{
2724	case VINF_SUCCESS:
2725	case VINF_EM_RAW_INTERRUPT:
2726	case VINF_PATM_PATCH_TRAP_PF:
2727	case VINF_PATM_PATCH_TRAP_GP:
2728	case VINF_PATM_PATCH_INT3:
2729	case VINF_PATM_CHECK_PATCH_PAGE:
2730	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2731	case VINF_EM_RAW_GUEST_TRAP:
2732	case VINF_EM_RESCHEDULE_RAW:
2733	break;
2734
2735	default:
2736	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2737	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVM), rc));
2738	break;
2739	}
2740	/*
2741	* Let's go paranoid!
2742	*/
2743	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2744	&& PGMMapHasConflicts(pVM))
2745	{
2746	PGMMapCheck(pVM);
2747	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
2748	return VERR_INTERNAL_ERROR;
2749	}
2750	#endif /* VBOX_STRICT */
2751
2752	/*
2753	* Process the returned status code.
2754	*/
2755	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2756	{
2757	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2758	break;
2759	}
2760	rc = emR3RawHandleRC(pVM, pCtx, rc);
2761	if (rc != VINF_SUCCESS)
2762	{
2763	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2764	if (rc != VINF_SUCCESS)
2765	{
2766	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2767	break;
2768	}
2769	}
2770
2771	/*
2772	* Check and execute forced actions.
2773	*/
2774	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2775	TMTimerPoll(pVM);
2776	#endif
2777	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2778	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2779	{
2780	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2781
2782	STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2783	rc = emR3ForcedActions(pVM, rc);
2784	STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2785	if ( rc != VINF_SUCCESS
2786	&& rc != VINF_EM_RESCHEDULE_RAW)
2787	{
2788	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2789	if (rc != VINF_SUCCESS)
2790	{
2791	*pfFFDone = true;
2792	break;
2793	}
2794	}
2795	}
2796	}
2797
2798	/*
2799	* Return to outer loop.
2800	*/
2801	#if defined(LOG_ENABLED) && defined(DEBUG)
2802	RTLogFlush(NULL);
2803	#endif
2804	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2805	return rc;
2806	}
2807
2808
2809	/**
2810	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2811	*
2812	* This function contains the raw-mode version of the inner
2813	* execution loop (the outer loop being in EMR3ExecuteVM()).
2814	*
2815	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2816	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2817	*
2818	* @param pVM VM handle.
2819	* @param idCpu VMCPU id.
2820	* @param pfFFDone Where to store an indicator telling whether or not
2821	* FFs were done before returning.
2822	*/
2823	static int emR3HwAccExecute(PVM pVM, RTCPUID idCpu, bool *pfFFDone)
2824	{
2825	int rc = VERR_INTERNAL_ERROR;
2826	PCPUMCTX pCtx = pVM->em.s.pCtx;
2827
2828	LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
2829	*pfFFDone = false;
2830
2831	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2832
2833	#ifdef EM_NOTIFY_HWACCM
2834	HWACCMR3NotifyScheduled(&pVM->aCpus[idCpu]);
2835	#endif
2836
2837	/*
2838	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2839	*/
2840	for (;;)
2841	{
2842	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2843
2844	/*
2845	* Check various preconditions.
2846	*/
2847	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2848
2849	/*
2850	* Process high priority pre-execution raw-mode FFs.
2851	*/
2852	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2853	{
2854	rc = emR3RawForcedActions(pVM, pCtx);
2855	if (RT_FAILURE(rc))
2856	break;
2857	}
2858
2859	#ifdef LOG_ENABLED
2860	/*
2861	* Log important stuff before entering GC.
2862	*/
2863	if (TRPMHasTrap(pVM))
2864	Log(("Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", TRPMGetTrapNo(pVM), pCtx->cs, (RTGCPTR)pCtx->rip));
2865
2866	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2867	if (pCtx->eflags.Bits.u1VM)
2868	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2869	else if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
2870	Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2871	else
2872	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2873	#endif /* LOG_ENABLED */
2874
2875	/*
2876	* Execute the code.
2877	*/
2878	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2879	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2880	VMMR3Unlock(pVM);
2881	rc = VMMR3HwAccRunGC(pVM, idCpu);
2882	VMMR3Lock(pVM);
2883	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2884
2885	/*
2886	* Deal with high priority post execution FFs before doing anything else.
2887	*/
2888	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2889	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2890	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2891
2892	/*
2893	* Process the returned status code.
2894	*/
2895	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2896	break;
2897
2898	rc = emR3RawHandleRC(pVM, pCtx, rc);
2899	if (rc != VINF_SUCCESS)
2900	break;
2901
2902	/*
2903	* Check and execute forced actions.
2904	*/
2905	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2906	TMTimerPoll(pVM);
2907	#endif
2908	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2909	{
2910	rc = emR3ForcedActions(pVM, rc);
2911	if ( rc != VINF_SUCCESS
2912	&& rc != VINF_EM_RESCHEDULE_HWACC)
2913	{
2914	*pfFFDone = true;
2915	break;
2916	}
2917	}
2918	}
2919
2920	/*
2921	* Return to outer loop.
2922	*/
2923	#if defined(LOG_ENABLED) && defined(DEBUG)
2924	RTLogFlush(NULL);
2925	#endif
2926	return rc;
2927	}
2928
2929
2930	/**
2931	* Decides whether to execute RAW, HWACC or REM.
2932	*
2933	* @returns new EM state
2934	* @param pVM The VM.
2935	* @param pCtx The CPU context.
2936	*/
2937	static EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2938	{
2939	/*
2940	* When forcing raw-mode execution, things are simple.
2941	*/
2942	if (pVM->em.s.fForceRAW)
2943	return EMSTATE_RAW;
2944
2945	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2946	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2947	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2948
2949	X86EFLAGS EFlags = pCtx->eflags;
2950	if (HWACCMIsEnabled(pVM))
2951	{
2952	/* Hardware accelerated raw-mode:
2953	*
2954	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2955	*/
2956	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2957	return EMSTATE_HWACC;
2958
2959	/* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
2960	* off monitoring features essential for raw mode! */
2961	return EMSTATE_REM;
2962	}
2963
2964	/*
2965	* Standard raw-mode:
2966	*
2967	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2968	* or 32 bits protected mode ring 0 code
2969	*
2970	* The tests are ordered by the likelyhood of being true during normal execution.
2971	*/
2972	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2973	{
2974	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2975	return EMSTATE_REM;
2976	}
2977
2978	#ifndef VBOX_RAW_V86
2979	if (EFlags.u32 & X86_EFL_VM) {
2980	Log2(("raw mode refused: VM_MASK\n"));
2981	return EMSTATE_REM;
2982	}
2983	#endif
2984
2985	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2986	uint32_t u32CR0 = pCtx->cr0;
2987	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2988	{
2989	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2990	return EMSTATE_REM;
2991	}
2992
2993	if (pCtx->cr4 & X86_CR4_PAE)
2994	{
2995	uint32_t u32Dummy, u32Features;
2996
2997	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2998	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
2999	return EMSTATE_REM;
3000	}
3001
3002	unsigned uSS = pCtx->ss;
3003	if ( pCtx->eflags.Bits.u1VM
3004	\|\| (uSS & X86_SEL_RPL) == 3)
3005	{
3006	if (!EMIsRawRing3Enabled(pVM))
3007	return EMSTATE_REM;
3008
3009	if (!(EFlags.u32 & X86_EFL_IF))
3010	{
3011	Log2(("raw mode refused: IF (RawR3)\n"));
3012	return EMSTATE_REM;
3013	}
3014
3015	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
3016	{
3017	Log2(("raw mode refused: CR0.WP + RawR0\n"));
3018	return EMSTATE_REM;
3019	}
3020	}
3021	else
3022	{
3023	if (!EMIsRawRing0Enabled(pVM))
3024	return EMSTATE_REM;
3025
3026	/* Only ring 0 supervisor code. */
3027	if ((uSS & X86_SEL_RPL) != 0)
3028	{
3029	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
3030	return EMSTATE_REM;
3031	}
3032
3033	// Let's start with pure 32 bits ring 0 code first
3034	/** @todo What's pure 32-bit mode? flat? */
3035	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
3036	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
3037	{
3038	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
3039	return EMSTATE_REM;
3040	}
3041
3042	/* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
3043	if (!(u32CR0 & X86_CR0_WP))
3044	{
3045	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
3046	return EMSTATE_REM;
3047	}
3048
3049	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
3050	{
3051	Log2(("raw r0 mode forced: patch code\n"));
3052	return EMSTATE_RAW;
3053	}
3054
3055	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
3056	if (!(EFlags.u32 & X86_EFL_IF))
3057	{
3058	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
3059	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
3060	return EMSTATE_REM;
3061	}
3062	#endif
3063
3064	/** @todo still necessary??? */
3065	if (EFlags.Bits.u2IOPL != 0)
3066	{
3067	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
3068	return EMSTATE_REM;
3069	}
3070	}
3071
3072	Assert(PGMPhysIsA20Enabled(pVM));
3073	return EMSTATE_RAW;
3074	}
3075
3076
3077	/**
3078	* Executes all high priority post execution force actions.
3079	*
3080	* @returns rc or a fatal status code.
3081	*
3082	* @param pVM VM handle.
3083	* @param rc The current rc.
3084	*/
3085	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
3086	{
3087	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
3088	PDMR3CritSectFF(pVM);
3089
3090	if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
3091	CSAMR3DoPendingAction(pVM);
3092
3093	return rc;
3094	}
3095
3096
3097	/**
3098	* Executes all pending forced actions.
3099	*
3100	* Forced actions can cause execution delays and execution
3101	* rescheduling. The first we deal with using action priority, so
3102	* that for instance pending timers aren't scheduled and ran until
3103	* right before execution. The rescheduling we deal with using
3104	* return codes. The same goes for VM termination, only in that case
3105	* we exit everything.
3106	*
3107	* @returns VBox status code of equal or greater importance/severity than rc.
3108	* The most important ones are: VINF_EM_RESCHEDULE,
3109	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3110	*
3111	* @param pVM VM handle.
3112	* @param rc The current rc.
3113	*
3114	*/
3115	static int emR3ForcedActions(PVM pVM, int rc)
3116	{
3117	STAM_REL_PROFILE_START(&pVM->em.s.StatForcedActions, a);
3118	#ifdef VBOX_STRICT
3119	int rcIrq = VINF_SUCCESS;
3120	#endif
3121	int rc2;
3122	#define UPDATE_RC() \
3123	do { \
3124	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
3125	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
3126	break; \
3127	if (!rc \|\| rc2 < rc) \
3128	rc = rc2; \
3129	} while (0)
3130
3131	/*
3132	* Post execution chunk first.
3133	*/
3134	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
3135	{
3136	/*
3137	* Termination request.
3138	*/
3139	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3140	{
3141	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3142	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3143	return VINF_EM_TERMINATE;
3144	}
3145
3146	/*
3147	* Debugger Facility polling.
3148	*/
3149	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3150	{
3151	rc2 = DBGFR3VMMForcedAction(pVM);
3152	UPDATE_RC();
3153	}
3154
3155	/*
3156	* Postponed reset request.
3157	*/
3158	if (VM_FF_ISSET(pVM, VM_FF_RESET))
3159	{
3160	rc2 = VMR3Reset(pVM);
3161	UPDATE_RC();
3162	VM_FF_CLEAR(pVM, VM_FF_RESET);
3163	}
3164
3165	/*
3166	* CSAM page scanning.
3167	*/
3168	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
3169	{
3170	PCPUMCTX pCtx = pVM->em.s.pCtx;
3171
3172	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3173	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3174
3175	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3176	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3177	}
3178
3179	/* check that we got them all */
3180	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
3181	}
3182
3183	/*
3184	* Normal priority then.
3185	* (Executed in no particular order.)
3186	*/
3187	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3188	{
3189	/*
3190	* PDM Queues are pending.
3191	*/
3192	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3193	PDMR3QueueFlushAll(pVM);
3194
3195	/*
3196	* PDM DMA transfers are pending.
3197	*/
3198	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3199	PDMR3DmaRun(pVM);
3200
3201	/*
3202	* Requests from other threads.
3203	*/
3204	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3205	{
3206	rc2 = VMR3ReqProcessU(pVM->pUVM, VMREQDEST_ANY);
3207	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3208	{
3209	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
3210	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3211	return rc2;
3212	}
3213	UPDATE_RC();
3214	}
3215
3216	/* Replay the handler notification changes. */
3217	if (VM_FF_ISSET(pVM, VM_FF_REM_HANDLER_NOTIFY))
3218	REMR3ReplayHandlerNotifications(pVM);
3219
3220	/* check that we got them all */
3221	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY)));
3222	}
3223
3224	/*
3225	* Execute polling function ever so often.
3226	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING "SOON"!
3227	*/
3228	static unsigned cLast = 0;
3229	if (!((++cLast) % 4))
3230	PDMR3Poll(pVM);
3231
3232	/*
3233	* High priority pre execution chunk last.
3234	* (Executed in ascending priority order.)
3235	*/
3236	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3237	{
3238	/*
3239	* Timers before interrupts.
3240	*/
3241	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3242	TMR3TimerQueuesDo(pVM);
3243
3244	/*
3245	* The instruction following an emulated STI should always be executed!
3246	*/
3247	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3248	{
3249	Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3250	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3251	{
3252	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3253	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3254	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3255	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3256	*/
3257	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3258	}
3259	if (HWACCMR3IsActive(pVM))
3260	rc2 = VINF_EM_RESCHEDULE_HWACC;
3261	else
3262	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3263
3264	UPDATE_RC();
3265	}
3266
3267	/*
3268	* Interrupts.
3269	*/
3270	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3271	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_HWACC)
3272	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3273	&& PATMAreInterruptsEnabled(pVM)
3274	&& !HWACCMR3IsEventPending(pVM))
3275	{
3276	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3277	{
3278	/* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3279	/** @todo this really isn't nice, should properly handle this */
3280	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3281	#ifdef VBOX_STRICT
3282	rcIrq = rc2;
3283	#endif
3284	UPDATE_RC();
3285	}
3286	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3287	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3288	{
3289	rc2 = VINF_EM_RESCHEDULE_REM;
3290	UPDATE_RC();
3291	}
3292	}
3293
3294	/*
3295	* Allocate handy pages.
3296	*/
3297	if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
3298	{
3299	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3300	UPDATE_RC();
3301	}
3302
3303	/*
3304	* Debugger Facility request.
3305	*/
3306	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3307	{
3308	rc2 = DBGFR3VMMForcedAction(pVM);
3309	UPDATE_RC();
3310	}
3311
3312	/*
3313	* Termination request.
3314	*/
3315	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3316	{
3317	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3318	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3319	return VINF_EM_TERMINATE;
3320	}
3321
3322	#ifdef DEBUG
3323	/*
3324	* Debug, pause the VM.
3325	*/
3326	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3327	{
3328	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3329	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3330	return VINF_EM_SUSPEND;
3331	}
3332
3333	#endif
3334	/* check that we got them all */
3335	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS \| VM_FF_PGM_NEED_HANDY_PAGES)));
3336	}
3337
3338	#undef UPDATE_RC
3339	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
3340	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3341	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3342	return rc;
3343	}
3344
3345
3346	/**
3347	* Execute VM.
3348	*
3349	* This function is the main loop of the VM. The emulation thread
3350	* calls this function when the VM has been successfully constructed
3351	* and we're ready for executing the VM.
3352	*
3353	* Returning from this function means that the VM is turned off or
3354	* suspended (state already saved) and deconstruction in next in line.
3355	*
3356	* All interaction from other thread are done using forced actions
3357	* and signaling of the wait object.
3358	*
3359	* @returns VBox status code, informational status codes may indicate failure.
3360	* @param pVM The VM to operate on.
3361	* @param idCpu VMCPU id.
3362	*/
3363	VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, RTCPUID idCpu)
3364	{
3365	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3366	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3367	VM_ASSERT_EMT(pVM);
3368	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3369
3370	VMMR3Lock(pVM);
3371
3372	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3373	if (rc == 0)
3374	{
3375	/*
3376	* Start the virtual time.
3377	*/
3378	rc = TMVirtualResume(pVM);
3379	Assert(rc == VINF_SUCCESS);
3380	rc = TMCpuTickResume(pVM);
3381	Assert(rc == VINF_SUCCESS);
3382
3383	/*
3384	* The Outer Main Loop.
3385	*/
3386	bool fFFDone = false;
3387
3388	/* Reschedule right away to start in the right state. */
3389	rc = VINF_SUCCESS;
3390	pVM->em.s.enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3391
3392	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3393	for (;;)
3394	{
3395	/*
3396	* Before we can schedule anything (we're here because
3397	* scheduling is required) we must service any pending
3398	* forced actions to avoid any pending action causing
3399	* immediate rescheduling upon entering an inner loop
3400	*
3401	* Do forced actions.
3402	*/
3403	if ( !fFFDone
3404	&& rc != VINF_EM_TERMINATE
3405	&& rc != VINF_EM_OFF
3406	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3407	{
3408	rc = emR3ForcedActions(pVM, rc);
3409	if ( ( rc == VINF_EM_RESCHEDULE_REM
3410	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3411	&& pVM->em.s.fForceRAW)
3412	rc = VINF_EM_RESCHEDULE_RAW;
3413	}
3414	else if (fFFDone)
3415	fFFDone = false;
3416
3417	/*
3418	* Now what to do?
3419	*/
3420	Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
3421	switch (rc)
3422	{
3423	/*
3424	* Keep doing what we're currently doing.
3425	*/
3426	case VINF_SUCCESS:
3427	break;
3428
3429	/*
3430	* Reschedule - to raw-mode execution.
3431	*/
3432	case VINF_EM_RESCHEDULE_RAW:
3433	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3434	pVM->em.s.enmState = EMSTATE_RAW;
3435	break;
3436
3437	/*
3438	* Reschedule - to hardware accelerated raw-mode execution.
3439	*/
3440	case VINF_EM_RESCHEDULE_HWACC:
3441	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3442	Assert(!pVM->em.s.fForceRAW);
3443	pVM->em.s.enmState = EMSTATE_HWACC;
3444	break;
3445
3446	/*
3447	* Reschedule - to recompiled execution.
3448	*/
3449	case VINF_EM_RESCHEDULE_REM:
3450	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3451	pVM->em.s.enmState = EMSTATE_REM;
3452	break;
3453
3454	#ifdef VBOX_WITH_VMI
3455	/*
3456	* Reschedule - parav call.
3457	*/
3458	case VINF_EM_RESCHEDULE_PARAV:
3459	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVM->em.s.enmState, EMSTATE_PARAV));
3460	pVM->em.s.enmState = EMSTATE_PARAV;
3461	break;
3462	#endif
3463
3464	/*
3465	* Resume.
3466	*/
3467	case VINF_EM_RESUME:
3468	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3469	/* fall through and get scheduled. */
3470
3471	/*
3472	* Reschedule.
3473	*/
3474	case VINF_EM_RESCHEDULE:
3475	{
3476	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3477	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3478	pVM->em.s.enmState = enmState;
3479	break;
3480	}
3481
3482	/*
3483	* Halted.
3484	*/
3485	case VINF_EM_HALT:
3486	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3487	pVM->em.s.enmState = EMSTATE_HALTED;
3488	break;
3489
3490	/*
3491	* Suspend.
3492	*/
3493	case VINF_EM_SUSPEND:
3494	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3495	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3496	break;
3497
3498	/*
3499	* Reset.
3500	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3501	*/
3502	case VINF_EM_RESET:
3503	{
3504	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3505	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3506	pVM->em.s.enmState = enmState;
3507	break;
3508	}
3509
3510	/*
3511	* Power Off.
3512	*/
3513	case VINF_EM_OFF:
3514	pVM->em.s.enmState = EMSTATE_TERMINATING;
3515	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3516	TMVirtualPause(pVM);
3517	TMCpuTickPause(pVM);
3518	VMMR3Unlock(pVM);
3519	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3520	return rc;
3521
3522	/*
3523	* Terminate the VM.
3524	*/
3525	case VINF_EM_TERMINATE:
3526	pVM->em.s.enmState = EMSTATE_TERMINATING;
3527	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3528	TMVirtualPause(pVM);
3529	TMCpuTickPause(pVM);
3530	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3531	return rc;
3532
3533	/*
3534	* Guest debug events.
3535	*/
3536	case VINF_EM_DBG_STEPPED:
3537	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3538	case VINF_EM_DBG_STOP:
3539	case VINF_EM_DBG_BREAKPOINT:
3540	case VINF_EM_DBG_STEP:
3541	if (pVM->em.s.enmState == EMSTATE_RAW)
3542	{
3543	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3544	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3545	}
3546	else
3547	{
3548	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3549	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3550	}
3551	break;
3552
3553	/*
3554	* Hypervisor debug events.
3555	*/
3556	case VINF_EM_DBG_HYPER_STEPPED:
3557	case VINF_EM_DBG_HYPER_BREAKPOINT:
3558	case VINF_EM_DBG_HYPER_ASSERTION:
3559	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3560	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3561	break;
3562
3563	/*
3564	* Guru mediations.
3565	*/
3566	case VERR_VMM_RING0_ASSERTION:
3567	Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVM->em.s.enmState, EMSTATE_GURU_MEDITATION));
3568	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3569	break;
3570
3571	/*
3572	* Any error code showing up here other than the ones we
3573	* know and process above are considered to be FATAL.
3574	*
3575	* Unknown warnings and informational status codes are also
3576	* included in this.
3577	*/
3578	default:
3579	if (RT_SUCCESS(rc))
3580	{
3581	AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
3582	rc = VERR_EM_INTERNAL_ERROR;
3583	}
3584	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3585	Log(("EMR3ExecuteVM returns %d\n", rc));
3586	break;
3587	}
3588
3589
3590	/*
3591	* Any waiters can now be woken up
3592	*/
3593	VMMR3Unlock(pVM);
3594	VMMR3Lock(pVM);
3595
3596	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3597	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3598
3599	/*
3600	* Act on the state.
3601	*/
3602	switch (pVM->em.s.enmState)
3603	{
3604	/*
3605	* Execute raw.
3606	*/
3607	case EMSTATE_RAW:
3608	rc = emR3RawExecute(pVM, &fFFDone);
3609	break;
3610
3611	/*
3612	* Execute hardware accelerated raw.
3613	*/
3614	case EMSTATE_HWACC:
3615	rc = emR3HwAccExecute(pVM, idCpu, &fFFDone);
3616	break;
3617
3618	/*
3619	* Execute recompiled.
3620	*/
3621	case EMSTATE_REM:
3622	rc = emR3RemExecute(pVM, &fFFDone);
3623	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
3624	break;
3625
3626	#ifdef VBOX_WITH_VMI
3627	/*
3628	* Execute PARAV function.
3629	*/
3630	case EMSTATE_PARAV:
3631	rc = PARAVCallFunction(pVM);
3632	pVM->em.s.enmState = EMSTATE_REM;
3633	break;
3634	#endif
3635
3636	/*
3637	* hlt - execution halted until interrupt.
3638	*/
3639	case EMSTATE_HALTED:
3640	{
3641	STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3642	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3643	STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3644	break;
3645	}
3646
3647	/*
3648	* Suspended - return to VM.cpp.
3649	*/
3650	case EMSTATE_SUSPENDED:
3651	TMVirtualPause(pVM);
3652	TMCpuTickPause(pVM);
3653	VMMR3Unlock(pVM);
3654	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3655	return VINF_EM_SUSPEND;
3656
3657	/*
3658	* Debugging in the guest.
3659	*/
3660	case EMSTATE_DEBUG_GUEST_REM:
3661	case EMSTATE_DEBUG_GUEST_RAW:
3662	TMVirtualPause(pVM);
3663	TMCpuTickPause(pVM);
3664	rc = emR3Debug(pVM, rc);
3665	TMVirtualResume(pVM);
3666	TMCpuTickResume(pVM);
3667	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVM->em.s.enmState));
3668	break;
3669
3670	/*
3671	* Debugging in the hypervisor.
3672	*/
3673	case EMSTATE_DEBUG_HYPER:
3674	{
3675	TMVirtualPause(pVM);
3676	TMCpuTickPause(pVM);
3677	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3678
3679	rc = emR3Debug(pVM, rc);
3680	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVM->em.s.enmState));
3681	if (rc != VINF_SUCCESS)
3682	{
3683	/* switch to guru meditation mode */
3684	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3685	VMMR3FatalDump(pVM, rc);
3686	return rc;
3687	}
3688
3689	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3690	TMVirtualResume(pVM);
3691	TMCpuTickResume(pVM);
3692	break;
3693	}
3694
3695	/*
3696	* Guru meditation takes place in the debugger.
3697	*/
3698	case EMSTATE_GURU_MEDITATION:
3699	{
3700	TMVirtualPause(pVM);
3701	TMCpuTickPause(pVM);
3702	VMMR3FatalDump(pVM, rc);
3703	emR3Debug(pVM, rc);
3704	VMMR3Unlock(pVM);
3705	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3706	return rc;
3707	}
3708
3709	/*
3710	* The states we don't expect here.
3711	*/
3712	case EMSTATE_NONE:
3713	case EMSTATE_TERMINATING:
3714	default:
3715	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3716	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3717	TMVirtualPause(pVM);
3718	TMCpuTickPause(pVM);
3719	VMMR3Unlock(pVM);
3720	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3721	return VERR_EM_INTERNAL_ERROR;
3722	}
3723	} /* The Outer Main Loop */
3724	}
3725	else
3726	{
3727	/*
3728	* Fatal error.
3729	*/
3730	LogFlow(("EMR3ExecuteVM: returns %Rrc (longjmp / fatal error)\n", rc));
3731	TMVirtualPause(pVM);
3732	TMCpuTickPause(pVM);
3733	VMMR3FatalDump(pVM, rc);
3734	emR3Debug(pVM, rc);
3735	VMMR3Unlock(pVM);
3736	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3737	/** @todo change the VM state! */
3738	return rc;
3739	}
3740
3741	/* (won't ever get here). */
3742	AssertFailed();
3743	}
3744

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 18485

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