EM.cpp@ 18709

Last change on this file since 18709 was 18655, checked in by vboxsync, 16 years ago
EM: fixed resuming from an out of memory condition.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 158.0 KB

Line
1	/* $Id: EM.cpp 18655 2009-04-02 16:41:05Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_em EM - The Execution Monitor / Manager
23	*
24	* The Execution Monitor/Manager is responsible for running the VM, scheduling
25	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26	* Interpreted), and keeping the CPU states in sync. The function
27	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29	* emR3RemExecute).
30	*
31	* The interpreted execution is only used to avoid switching between
32	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33	* The interpretation is thus implemented as part of EM.
34	*
35	* @see grp_em
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_EM
42	#include <VBox/em.h>
43	#include <VBox/vmm.h>
44	#ifdef VBOX_WITH_VMI
45	# include <VBox/parav.h>
46	#endif
47	#include <VBox/patm.h>
48	#include <VBox/csam.h>
49	#include <VBox/selm.h>
50	#include <VBox/trpm.h>
51	#include <VBox/iom.h>
52	#include <VBox/dbgf.h>
53	#include <VBox/pgm.h>
54	#include <VBox/rem.h>
55	#include <VBox/tm.h>
56	#include <VBox/mm.h>
57	#include <VBox/ssm.h>
58	#include <VBox/pdmapi.h>
59	#include <VBox/pdmcritsect.h>
60	#include <VBox/pdmqueue.h>
61	#include <VBox/hwaccm.h>
62	#include <VBox/patm.h>
63	#include "EMInternal.h"
64	#include <VBox/vm.h>
65	#include <VBox/cpumdis.h>
66	#include <VBox/dis.h>
67	#include <VBox/disopcode.h>
68	#include <VBox/dbgf.h>
69
70	#include <VBox/log.h>
71	#include <iprt/thread.h>
72	#include <iprt/assert.h>
73	#include <iprt/asm.h>
74	#include <iprt/semaphore.h>
75	#include <iprt/string.h>
76	#include <iprt/avl.h>
77	#include <iprt/stream.h>
78	#include <VBox/param.h>
79	#include <VBox/err.h>
80
81
82	/*******************************************************************************
83	* Defined Constants And Macros *
84	*******************************************************************************/
85	#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
86	#define EM_NOTIFY_HWACCM
87	#endif
88
89
90	/*******************************************************************************
91	* Internal Functions *
92	*******************************************************************************/
93	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
94	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
95	static int emR3Debug(PVM pVM, int rc);
96	static int emR3RemStep(PVM pVM);
97	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
98	static int emR3RawResumeHyper(PVM pVM);
99	static int emR3RawStep(PVM pVM);
100	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
101	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
102	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
103	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
104	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
105	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
106	static int emR3ForcedActions(PVM pVM, int rc);
107	static int emR3RawGuestTrap(PVM pVM);
108	static int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret);
109	static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations);
110	static EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx);
111
112	/**
113	* Initializes the EM.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	VMMR3DECL(int) EMR3Init(PVM pVM)
119	{
120	LogFlow(("EMR3Init\n"));
121	/*
122	* Assert alignment and sizes.
123	*/
124	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
125	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
126	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
127	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
128
129	/*
130	* Init the structure.
131	*/
132	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
133	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
134	if (RT_FAILURE(rc))
135	pVM->fRawR3Enabled = true;
136	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
137	if (RT_FAILURE(rc))
138	pVM->fRawR0Enabled = true;
139	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
140	pVM->em.s.enmState = EMSTATE_NONE;
141	pVM->em.s.fForceRAW = false;
142
143	pVM->em.s.pCtx = CPUMQueryGuestCtxPtr(pVM);
144	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
145	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
146
147	/*
148	* Saved state.
149	*/
150	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
151	NULL, emR3Save, NULL,
152	NULL, emR3Load, NULL);
153	if (RT_FAILURE(rc))
154	return rc;
155
156	/*
157	* Statistics.
158	*/
159	#ifdef VBOX_WITH_STATISTICS
160	PEMSTATS pStats;
161	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
162	if (RT_FAILURE(rc))
163	return rc;
164	pVM->em.s.pStatsR3 = pStats;
165	pVM->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
166	pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
167
168	STAM_REG(pVM, &pStats->StatRZEmulate, STAMTYPE_PROFILE, "/EM/RZ/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
169	STAM_REG(pVM, &pStats->StatR3Emulate, STAMTYPE_PROFILE, "/EM/R3/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
170
171	STAM_REG(pVM, &pStats->StatRZInterpretSucceeded, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
172	STAM_REG(pVM, &pStats->StatR3InterpretSucceeded, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
173
174	STAM_REG_USED(pVM, &pStats->StatRZAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatR3And, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatRZAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatR3Add, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatRZAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatR3Adc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatRZSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatR3Sub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatRZCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatR3CpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatRZDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatR3Dec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatRZHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatR3Hlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatRZInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatR3Inc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatRZInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatR3InvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatRZIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatR3Iret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatRZLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatR3LLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
196	STAM_REG_USED(pVM, &pStats->StatRZLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
197	STAM_REG_USED(pVM, &pStats->StatR3LIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatRZLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatR3LGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatRZMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatR3Mov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatRZMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatR3MovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
204	STAM_REG_USED(pVM, &pStats->StatRZMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
205	STAM_REG_USED(pVM, &pStats->StatR3MovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
206	STAM_REG_USED(pVM, &pStats->StatRZOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
207	STAM_REG_USED(pVM, &pStats->StatR3Or, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
208	STAM_REG_USED(pVM, &pStats->StatRZPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatR3Pop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatRZRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatR3Rdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatRZSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatR3Sti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatRZXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatR3Xchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatRZXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatR3Xor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatRZMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatR3Monitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatRZMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatR3MWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatRZBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatR3Btr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatRZBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatR3Bts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatRZBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatR3Btc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatRZCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatR3CmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatRZCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatR3CmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatRZXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatR3XAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatR3Rdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatRZRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatR3Wrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
237	STAM_REG_USED(pVM, &pStats->StatRZWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
238	STAM_REG_USED(pVM, &pStats->StatR3StosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
239	STAM_REG_USED(pVM, &pStats->StatRZStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatRZWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatR3WbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatRZLmsw, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was successfully interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatR3Lmsw, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was successfully interpreted.");
244
245	STAM_REG(pVM, &pStats->StatRZInterpretFailed, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
246	STAM_REG(pVM, &pStats->StatR3InterpretFailed, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
247
248	STAM_REG_USED(pVM, &pStats->StatRZFailedAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
249	STAM_REG_USED(pVM, &pStats->StatR3FailedAnd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatRZFailedCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatR3FailedCpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatRZFailedDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatR3FailedDec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatRZFailedHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatR3FailedHlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatRZFailedInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatR3FailedInc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatRZFailedInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatR3FailedInvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatRZFailedIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
261	STAM_REG_USED(pVM, &pStats->StatR3FailedIret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
262	STAM_REG_USED(pVM, &pStats->StatRZFailedLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
263	STAM_REG_USED(pVM, &pStats->StatR3FailedLLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
264	STAM_REG_USED(pVM, &pStats->StatRZFailedLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
265	STAM_REG_USED(pVM, &pStats->StatR3FailedLIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
266	STAM_REG_USED(pVM, &pStats->StatRZFailedLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
267	STAM_REG_USED(pVM, &pStats->StatR3FailedLGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
268	STAM_REG_USED(pVM, &pStats->StatRZFailedMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
269	STAM_REG_USED(pVM, &pStats->StatR3FailedMov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
270	STAM_REG_USED(pVM, &pStats->StatRZFailedMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
271	STAM_REG_USED(pVM, &pStats->StatR3FailedMovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
272	STAM_REG_USED(pVM, &pStats->StatRZFailedMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
273	STAM_REG_USED(pVM, &pStats->StatR3FailedMovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
274	STAM_REG_USED(pVM, &pStats->StatRZFailedOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
275	STAM_REG_USED(pVM, &pStats->StatR3FailedOr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
276	STAM_REG_USED(pVM, &pStats->StatRZFailedPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
277	STAM_REG_USED(pVM, &pStats->StatR3FailedPop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
278	STAM_REG_USED(pVM, &pStats->StatRZFailedSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
279	STAM_REG_USED(pVM, &pStats->StatR3FailedSti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
280	STAM_REG_USED(pVM, &pStats->StatRZFailedXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
281	STAM_REG_USED(pVM, &pStats->StatR3FailedXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
282	STAM_REG_USED(pVM, &pStats->StatRZFailedXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
283	STAM_REG_USED(pVM, &pStats->StatR3FailedXor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
284	STAM_REG_USED(pVM, &pStats->StatRZFailedMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
285	STAM_REG_USED(pVM, &pStats->StatR3FailedMonitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
286	STAM_REG_USED(pVM, &pStats->StatRZFailedMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
287	STAM_REG_USED(pVM, &pStats->StatR3FailedMWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
288	STAM_REG_USED(pVM, &pStats->StatRZFailedRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
289	STAM_REG_USED(pVM, &pStats->StatR3FailedRdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
290	STAM_REG_USED(pVM, &pStats->StatRZFailedRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
291	STAM_REG_USED(pVM, &pStats->StatR3FailedRdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
292	STAM_REG_USED(pVM, &pStats->StatRZFailedWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
293	STAM_REG_USED(pVM, &pStats->StatR3FailedWrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
294	STAM_REG_USED(pVM, &pStats->StatRZFailedLmsw, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was not interpreted.");
295	STAM_REG_USED(pVM, &pStats->StatR3FailedLmsw, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was not interpreted.");
296
297	STAM_REG_USED(pVM, &pStats->StatRZFailedMisc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
298	STAM_REG_USED(pVM, &pStats->StatR3FailedMisc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
299	STAM_REG_USED(pVM, &pStats->StatRZFailedAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
300	STAM_REG_USED(pVM, &pStats->StatR3FailedAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
301	STAM_REG_USED(pVM, &pStats->StatRZFailedAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
302	STAM_REG_USED(pVM, &pStats->StatR3FailedAdc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
303	STAM_REG_USED(pVM, &pStats->StatRZFailedBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
304	STAM_REG_USED(pVM, &pStats->StatR3FailedBtr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
305	STAM_REG_USED(pVM, &pStats->StatRZFailedBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
306	STAM_REG_USED(pVM, &pStats->StatR3FailedBts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
307	STAM_REG_USED(pVM, &pStats->StatRZFailedBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
308	STAM_REG_USED(pVM, &pStats->StatR3FailedBtc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
309	STAM_REG_USED(pVM, &pStats->StatRZFailedCli, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
310	STAM_REG_USED(pVM, &pStats->StatR3FailedCli, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
311	STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
312	STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
313	STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
314	STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
315	STAM_REG_USED(pVM, &pStats->StatRZFailedXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
316	STAM_REG_USED(pVM, &pStats->StatR3FailedXAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
317	STAM_REG_USED(pVM, &pStats->StatRZFailedMovNTPS, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
318	STAM_REG_USED(pVM, &pStats->StatR3FailedMovNTPS, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
319	STAM_REG_USED(pVM, &pStats->StatRZFailedStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
320	STAM_REG_USED(pVM, &pStats->StatR3FailedStosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
321	STAM_REG_USED(pVM, &pStats->StatRZFailedSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
322	STAM_REG_USED(pVM, &pStats->StatR3FailedSub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
323	STAM_REG_USED(pVM, &pStats->StatRZFailedWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
324	STAM_REG_USED(pVM, &pStats->StatR3FailedWbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
325
326	STAM_REG_USED(pVM, &pStats->StatRZFailedUserMode, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
327	STAM_REG_USED(pVM, &pStats->StatR3FailedUserMode, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
328	STAM_REG_USED(pVM, &pStats->StatRZFailedPrefix, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
329	STAM_REG_USED(pVM, &pStats->StatR3FailedPrefix, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
330
331	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
332	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
333	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/R3/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
334	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
335	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
336	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
337	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
338	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
339	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
340	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
341	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
342	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
343	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
344	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
345	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
346	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
347	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
348	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/R3/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
349	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
350	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
351	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
352	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
353	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
354	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
355	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
356	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
357
358	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
359	pVM->em.s.pCliStatTree = 0;
360	#endif /* VBOX_WITH_STATISTICS */
361
362	/* these should be considered for release statistics. */
363	STAM_REL_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
364	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
365	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
366	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
367
368	STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
369	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
370	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
371	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
372	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
373	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
374	STAM_REL_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
375	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
376	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
377	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
378	STAM_REL_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
379	STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
380
381
382	return VINF_SUCCESS;
383	}
384
385
386	/**
387	* Initializes the per-VCPU EM.
388	*
389	* @returns VBox status code.
390	* @param pVM The VM to operate on.
391	*/
392	VMMR3DECL(int) EMR3InitCPU(PVM pVM)
393	{
394	LogFlow(("EMR3InitCPU\n"));
395	return VINF_SUCCESS;
396	}
397
398
399	/**
400	* Applies relocations to data and code managed by this
401	* component. This function will be called at init and
402	* whenever the VMM need to relocate it self inside the GC.
403	*
404	* @param pVM The VM.
405	*/
406	VMMR3DECL(void) EMR3Relocate(PVM pVM)
407	{
408	LogFlow(("EMR3Relocate\n"));
409	if (pVM->em.s.pStatsR3)
410	pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVM->em.s.pStatsR3);
411	}
412
413
414	/**
415	* Reset notification.
416	*
417	* @param pVM
418	*/
419	VMMR3DECL(void) EMR3Reset(PVM pVM)
420	{
421	LogFlow(("EMR3Reset: \n"));
422	pVM->em.s.fForceRAW = false;
423	}
424
425
426	/**
427	* Terminates the EM.
428	*
429	* Termination means cleaning up and freeing all resources,
430	* the VM it self is at this point powered off or suspended.
431	*
432	* @returns VBox status code.
433	* @param pVM The VM to operate on.
434	*/
435	VMMR3DECL(int) EMR3Term(PVM pVM)
436	{
437	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
438
439	return VINF_SUCCESS;
440	}
441
442	/**
443	* Terminates the per-VCPU EM.
444	*
445	* Termination means cleaning up and freeing all resources,
446	* the VM it self is at this point powered off or suspended.
447	*
448	* @returns VBox status code.
449	* @param pVM The VM to operate on.
450	*/
451	VMMR3DECL(int) EMR3TermCPU(PVM pVM)
452	{
453	return 0;
454	}
455
456	/**
457	* Execute state save operation.
458	*
459	* @returns VBox status code.
460	* @param pVM VM Handle.
461	* @param pSSM SSM operation handle.
462	*/
463	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
464	{
465	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
466	}
467
468
469	/**
470	* Execute state load operation.
471	*
472	* @returns VBox status code.
473	* @param pVM VM Handle.
474	* @param pSSM SSM operation handle.
475	* @param u32Version Data layout version.
476	*/
477	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
478	{
479	/*
480	* Validate version.
481	*/
482	if (u32Version != EM_SAVED_STATE_VERSION)
483	{
484	AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
485	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
486	}
487
488	/*
489	* Load the saved state.
490	*/
491	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
492	if (RT_FAILURE(rc))
493	pVM->em.s.fForceRAW = false;
494
495	Assert(!pVM->em.s.pCliStatTree);
496	return rc;
497	}
498
499
500	/**
501	* Enables or disables a set of raw-mode execution modes.
502	*
503	* @returns VINF_SUCCESS on success.
504	* @returns VINF_RESCHEDULE if a rescheduling might be required.
505	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
506	*
507	* @param pVM The VM to operate on.
508	* @param enmMode The execution mode change.
509	* @thread The emulation thread.
510	*/
511	VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
512	{
513	switch (enmMode)
514	{
515	case EMRAW_NONE:
516	pVM->fRawR3Enabled = false;
517	pVM->fRawR0Enabled = false;
518	break;
519	case EMRAW_RING3_ENABLE:
520	pVM->fRawR3Enabled = true;
521	break;
522	case EMRAW_RING3_DISABLE:
523	pVM->fRawR3Enabled = false;
524	break;
525	case EMRAW_RING0_ENABLE:
526	pVM->fRawR0Enabled = true;
527	break;
528	case EMRAW_RING0_DISABLE:
529	pVM->fRawR0Enabled = false;
530	break;
531	default:
532	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
533	return VERR_INVALID_PARAMETER;
534	}
535	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
536	pVM->fRawR3Enabled, pVM->fRawR0Enabled));
537	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
538	}
539
540
541	/**
542	* Raise a fatal error.
543	*
544	* Safely terminate the VM with full state report and stuff. This function
545	* will naturally never return.
546	*
547	* @param pVM VM handle.
548	* @param rc VBox status code.
549	*/
550	VMMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
551	{
552	longjmp(pVM->em.s.u.FatalLongJump, rc);
553	AssertReleaseMsgFailed(("longjmp returned!\n"));
554	}
555
556
557	/**
558	* Gets the EM state name.
559	*
560	* @returns pointer to read only state name,
561	* @param enmState The state.
562	*/
563	VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
564	{
565	switch (enmState)
566	{
567	case EMSTATE_NONE: return "EMSTATE_NONE";
568	case EMSTATE_RAW: return "EMSTATE_RAW";
569	case EMSTATE_HWACC: return "EMSTATE_HWACC";
570	case EMSTATE_REM: return "EMSTATE_REM";
571	case EMSTATE_PARAV: return "EMSTATE_PARAV";
572	case EMSTATE_HALTED: return "EMSTATE_HALTED";
573	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
574	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
575	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
576	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
577	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
578	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
579	default: return "Unknown!";
580	}
581	}
582
583
584	#ifdef VBOX_WITH_STATISTICS
585	/**
586	* Just a braindead function to keep track of cli addresses.
587	* @param pVM VM handle.
588	* @param GCPtrInstr The EIP of the cli instruction.
589	*/
590	static void emR3RecordCli(PVM pVM, RTGCPTR GCPtrInstr)
591	{
592	PCLISTAT pRec;
593
594	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)GCPtrInstr);
595	if (!pRec)
596	{
597	/* New cli instruction; insert into the tree. */
598	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
599	Assert(pRec);
600	if (!pRec)
601	return;
602	pRec->Core.Key = (AVLPVKEY)GCPtrInstr;
603
604	char szCliStatName[32];
605	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
606	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
607
608	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
609	Assert(fRc); NOREF(fRc);
610	}
611	STAM_COUNTER_INC(&pRec->Counter);
612	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
613	}
614	#endif /* VBOX_WITH_STATISTICS */
615
616
617	/**
618	* Debug loop.
619	*
620	* @returns VBox status code for EM.
621	* @param pVM VM handle.
622	* @param rc Current EM VBox status code..
623	*/
624	static int emR3Debug(PVM pVM, int rc)
625	{
626	for (;;)
627	{
628	Log(("emR3Debug: rc=%Rrc\n", rc));
629	const int rcLast = rc;
630
631	/*
632	* Debug related RC.
633	*/
634	switch (rc)
635	{
636	/*
637	* Single step an instruction.
638	*/
639	case VINF_EM_DBG_STEP:
640	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
641	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
642	\|\| pVM->em.s.fForceRAW /* paranoia */)
643	rc = emR3RawStep(pVM);
644	else
645	{
646	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
647	rc = emR3RemStep(pVM);
648	}
649	break;
650
651	/*
652	* Simple events: stepped, breakpoint, stop/assertion.
653	*/
654	case VINF_EM_DBG_STEPPED:
655	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
656	break;
657
658	case VINF_EM_DBG_BREAKPOINT:
659	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
660	break;
661
662	case VINF_EM_DBG_STOP:
663	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
664	break;
665
666	case VINF_EM_DBG_HYPER_STEPPED:
667	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
668	break;
669
670	case VINF_EM_DBG_HYPER_BREAKPOINT:
671	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
672	break;
673
674	case VINF_EM_DBG_HYPER_ASSERTION:
675	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
676	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
677	break;
678
679	/*
680	* Guru meditation.
681	*/
682	case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
683	rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
684	break;
685	case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
686	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
687	break;
688
689	default: /** @todo don't use default for guru, but make special errors code! */
690	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
691	break;
692	}
693
694	/*
695	* Process the result.
696	*/
697	do
698	{
699	switch (rc)
700	{
701	/*
702	* Continue the debugging loop.
703	*/
704	case VINF_EM_DBG_STEP:
705	case VINF_EM_DBG_STOP:
706	case VINF_EM_DBG_STEPPED:
707	case VINF_EM_DBG_BREAKPOINT:
708	case VINF_EM_DBG_HYPER_STEPPED:
709	case VINF_EM_DBG_HYPER_BREAKPOINT:
710	case VINF_EM_DBG_HYPER_ASSERTION:
711	break;
712
713	/*
714	* Resuming execution (in some form) has to be done here if we got
715	* a hypervisor debug event.
716	*/
717	case VINF_SUCCESS:
718	case VINF_EM_RESUME:
719	case VINF_EM_SUSPEND:
720	case VINF_EM_RESCHEDULE:
721	case VINF_EM_RESCHEDULE_RAW:
722	case VINF_EM_RESCHEDULE_REM:
723	case VINF_EM_HALT:
724	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
725	{
726	rc = emR3RawResumeHyper(pVM);
727	if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
728	continue;
729	}
730	if (rc == VINF_SUCCESS)
731	rc = VINF_EM_RESCHEDULE;
732	return rc;
733
734	/*
735	* The debugger isn't attached.
736	* We'll simply turn the thing off since that's the easiest thing to do.
737	*/
738	case VERR_DBGF_NOT_ATTACHED:
739	switch (rcLast)
740	{
741	case VINF_EM_DBG_HYPER_STEPPED:
742	case VINF_EM_DBG_HYPER_BREAKPOINT:
743	case VINF_EM_DBG_HYPER_ASSERTION:
744	case VERR_TRPM_PANIC:
745	case VERR_TRPM_DONT_PANIC:
746	case VERR_VMM_RING0_ASSERTION:
747	return rcLast;
748	}
749	return VINF_EM_OFF;
750
751	/*
752	* Status codes terminating the VM in one or another sense.
753	*/
754	case VINF_EM_TERMINATE:
755	case VINF_EM_OFF:
756	case VINF_EM_RESET:
757	case VINF_EM_NO_MEMORY:
758	case VINF_EM_RAW_STALE_SELECTOR:
759	case VINF_EM_RAW_IRET_TRAP:
760	case VERR_TRPM_PANIC:
761	case VERR_TRPM_DONT_PANIC:
762	case VERR_VMM_RING0_ASSERTION:
763	case VERR_INTERNAL_ERROR:
764	case VERR_INTERNAL_ERROR_2:
765	case VERR_INTERNAL_ERROR_3:
766	case VERR_INTERNAL_ERROR_4:
767	case VERR_INTERNAL_ERROR_5:
768	case VERR_IPE_UNEXPECTED_STATUS:
769	case VERR_IPE_UNEXPECTED_INFO_STATUS:
770	case VERR_IPE_UNEXPECTED_ERROR_STATUS:
771	return rc;
772
773	/*
774	* The rest is unexpected, and will keep us here.
775	*/
776	default:
777	AssertMsgFailed(("Unxpected rc %Rrc!\n", rc));
778	break;
779	}
780	} while (false);
781	} /* debug for ever */
782	}
783
784
785	/**
786	* Steps recompiled code.
787	*
788	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
789	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
790	*
791	* @param pVM VM handle.
792	*/
793	static int emR3RemStep(PVM pVM)
794	{
795	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
796
797	/*
798	* Switch to REM, step instruction, switch back.
799	*/
800	int rc = REMR3State(pVM);
801	if (RT_SUCCESS(rc))
802	{
803	rc = REMR3Step(pVM);
804	REMR3StateBack(pVM);
805	}
806	LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
807	return rc;
808	}
809
810
811	/**
812	* Executes recompiled code.
813	*
814	* This function contains the recompiler version of the inner
815	* execution loop (the outer loop being in EMR3ExecuteVM()).
816	*
817	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
818	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
819	*
820	* @param pVM VM handle.
821	* @param pfFFDone Where to store an indicator telling wheter or not
822	* FFs were done before returning.
823	*
824	*/
825	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
826	{
827	#ifdef LOG_ENABLED
828	PCPUMCTX pCtx = pVM->em.s.pCtx;
829	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
830
831	if (pCtx->eflags.Bits.u1VM)
832	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
833	else
834	Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
835	#endif
836	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
837
838	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
839	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
840	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
841	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
842	#endif
843
844	/*
845	* Spin till we get a forced action which returns anything but VINF_SUCCESS
846	* or the REM suggests raw-mode execution.
847	*/
848	*pfFFDone = false;
849	bool fInREMState = false;
850	int rc = VINF_SUCCESS;
851	for (;;)
852	{
853	/*
854	* Update REM state if not already in sync.
855	*/
856	if (!fInREMState)
857	{
858	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
859	rc = REMR3State(pVM);
860	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
861	if (RT_FAILURE(rc))
862	break;
863	fInREMState = true;
864
865	/*
866	* We might have missed the raising of VMREQ, TIMER and some other
867	* imporant FFs while we were busy switching the state. So, check again.
868	*/
869	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
870	{
871	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
872	goto l_REMDoForcedActions;
873	}
874	}
875
876
877	/*
878	* Execute REM.
879	*/
880	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
881	rc = REMR3Run(pVM);
882	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
883
884
885	/*
886	* Deal with high priority post execution FFs before doing anything else.
887	*/
888	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
889	rc = emR3HighPriorityPostForcedActions(pVM, rc);
890
891	/*
892	* Process the returned status code.
893	* (Try keep this short! Call functions!)
894	*/
895	if (rc != VINF_SUCCESS)
896	{
897	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
898	break;
899	if (rc != VINF_REM_INTERRUPED_FF)
900	{
901	/*
902	* Anything which is not known to us means an internal error
903	* and the termination of the VM!
904	*/
905	AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
906	break;
907	}
908	}
909
910
911	/*
912	* Check and execute forced actions.
913	* Sync back the VM state before calling any of these.
914	*/
915	#ifdef VBOX_HIGH_RES_TIMERS_HACK
916	TMTimerPoll(pVM);
917	#endif
918	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
919	{
920	l_REMDoForcedActions:
921	if (fInREMState)
922	{
923	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
924	REMR3StateBack(pVM);
925	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
926	fInREMState = false;
927	}
928	STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
929	rc = emR3ForcedActions(pVM, rc);
930	STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
931	if ( rc != VINF_SUCCESS
932	&& rc != VINF_EM_RESCHEDULE_REM)
933	{
934	*pfFFDone = true;
935	break;
936	}
937	}
938
939	} /* The Inner Loop, recompiled execution mode version. */
940
941
942	/*
943	* Returning. Sync back the VM state if required.
944	*/
945	if (fInREMState)
946	{
947	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
948	REMR3StateBack(pVM);
949	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
950	}
951
952	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
953	return rc;
954	}
955
956
957	/**
958	* Resumes executing hypervisor after a debug event.
959	*
960	* This is kind of special since our current guest state is
961	* potentially out of sync.
962	*
963	* @returns VBox status code.
964	* @param pVM The VM handle.
965	*/
966	static int emR3RawResumeHyper(PVM pVM)
967	{
968	int rc;
969	PCPUMCTX pCtx = pVM->em.s.pCtx;
970	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
971	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
972
973	/*
974	* Resume execution.
975	*/
976	CPUMRawEnter(pVM, NULL);
977	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
978	rc = VMMR3ResumeHyper(pVM);
979	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
980	rc = CPUMRawLeave(pVM, NULL, rc);
981	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
982
983	/*
984	* Deal with the return code.
985	*/
986	rc = emR3HighPriorityPostForcedActions(pVM, rc);
987	rc = emR3RawHandleRC(pVM, pCtx, rc);
988	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
989	return rc;
990	}
991
992
993	/**
994	* Steps rawmode.
995	*
996	* @returns VBox status code.
997	* @param pVM The VM handle.
998	*/
999	static int emR3RawStep(PVM pVM)
1000	{
1001	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
1002	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
1003	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
1004	int rc;
1005	PCPUMCTX pCtx = pVM->em.s.pCtx;
1006	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
1007	#ifndef DEBUG_sandervl
1008	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
1009	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
1010	#endif
1011	if (fGuest)
1012	{
1013	/*
1014	* Check vital forced actions, but ignore pending interrupts and timers.
1015	*/
1016	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1017	{
1018	rc = emR3RawForcedActions(pVM, pCtx);
1019	if (rc != VINF_SUCCESS)
1020	return rc;
1021	}
1022
1023	/*
1024	* Set flags for single stepping.
1025	*/
1026	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1027	}
1028	else
1029	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1030
1031	/*
1032	* Single step.
1033	* We do not start time or anything, if anything we should just do a few nanoseconds.
1034	*/
1035	CPUMRawEnter(pVM, NULL);
1036	do
1037	{
1038	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
1039	rc = VMMR3ResumeHyper(pVM);
1040	else
1041	rc = VMMR3RawRunGC(pVM);
1042	#ifndef DEBUG_sandervl
1043	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
1044	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
1045	#endif
1046	} while ( rc == VINF_SUCCESS
1047	\|\| rc == VINF_EM_RAW_INTERRUPT);
1048	rc = CPUMRawLeave(pVM, NULL, rc);
1049	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1050
1051	/*
1052	* Make sure the trap flag is cleared.
1053	* (Too bad if the guest is trying to single step too.)
1054	*/
1055	if (fGuest)
1056	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1057	else
1058	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
1059
1060	/*
1061	* Deal with the return codes.
1062	*/
1063	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1064	rc = emR3RawHandleRC(pVM, pCtx, rc);
1065	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1066	return rc;
1067	}
1068
1069
1070	#ifdef DEBUG
1071
1072	/**
1073	* Steps hardware accelerated mode.
1074	*
1075	* @returns VBox status code.
1076	* @param pVM The VM handle.
1077	* @param idCpu VMCPU id.
1078	*/
1079	static int emR3HwAccStep(PVM pVM, RTCPUID idCpu)
1080	{
1081	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1082
1083	int rc;
1084	PCPUMCTX pCtx = pVM->em.s.pCtx;
1085	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
1086
1087	/*
1088	* Check vital forced actions, but ignore pending interrupts and timers.
1089	*/
1090	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1091	{
1092	rc = emR3RawForcedActions(pVM, pCtx);
1093	if (rc != VINF_SUCCESS)
1094	return rc;
1095	}
1096	/*
1097	* Set flags for single stepping.
1098	*/
1099	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1100
1101	/*
1102	* Single step.
1103	* We do not start time or anything, if anything we should just do a few nanoseconds.
1104	*/
1105	do
1106	{
1107	rc = VMMR3HwAccRunGC(pVM, idCpu);
1108	} while ( rc == VINF_SUCCESS
1109	\|\| rc == VINF_EM_RAW_INTERRUPT);
1110	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1111
1112	/*
1113	* Make sure the trap flag is cleared.
1114	* (Too bad if the guest is trying to single step too.)
1115	*/
1116	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1117
1118	/*
1119	* Deal with the return codes.
1120	*/
1121	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1122	rc = emR3RawHandleRC(pVM, pCtx, rc);
1123	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1124	return rc;
1125	}
1126
1127
1128	int emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1129	{
1130	int rc = VINF_SUCCESS;
1131	EMSTATE enmOldState = pVM->em.s.enmState;
1132	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1133
1134	Log(("Single step BEGIN:\n"));
1135	for (uint32_t i = 0; i < cIterations; i++)
1136	{
1137	DBGFR3PrgStep(pVM);
1138	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1139	rc = emR3RawStep(pVM);
1140	if (rc != VINF_SUCCESS)
1141	break;
1142	}
1143	Log(("Single step END: rc=%Rrc\n", rc));
1144	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1145	pVM->em.s.enmState = enmOldState;
1146	return rc;
1147	}
1148
1149
1150	static int emR3SingleStepExecHwAcc(PVM pVM, RTCPUID idCpu, uint32_t cIterations)
1151	{
1152	int rc = VINF_SUCCESS;
1153	EMSTATE enmOldState = pVM->em.s.enmState;
1154	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1155
1156	Log(("Single step BEGIN:\n"));
1157	for (uint32_t i = 0; i < cIterations; i++)
1158	{
1159	DBGFR3PrgStep(pVM);
1160	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1161	rc = emR3HwAccStep(pVM, idCpu);
1162	if ( rc != VINF_SUCCESS
1163	\|\| !HWACCMR3CanExecuteGuest(pVM, pVM->em.s.pCtx))
1164	break;
1165	}
1166	Log(("Single step END: rc=%Rrc\n", rc));
1167	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1168	pVM->em.s.enmState = enmOldState;
1169	return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
1170	}
1171
1172
1173	static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1174	{
1175	EMSTATE enmOldState = pVM->em.s.enmState;
1176
1177	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1178
1179	Log(("Single step BEGIN:\n"));
1180	for (uint32_t i = 0; i < cIterations; i++)
1181	{
1182	DBGFR3PrgStep(pVM);
1183	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1184	emR3RemStep(pVM);
1185	if (emR3Reschedule(pVM, pVM->em.s.pCtx) != EMSTATE_REM)
1186	break;
1187	}
1188	Log(("Single step END:\n"));
1189	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1190	pVM->em.s.enmState = enmOldState;
1191	return VINF_EM_RESCHEDULE;
1192	}
1193
1194	#endif /* DEBUG */
1195
1196
1197	/**
1198	* Executes one (or perhaps a few more) instruction(s).
1199	*
1200	* @returns VBox status code suitable for EM.
1201	*
1202	* @param pVM VM handle.
1203	* @param rcGC GC return code
1204	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1205	* instruction and prefix the log output with this text.
1206	*/
1207	#ifdef LOG_ENABLED
1208	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1209	#else
1210	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1211	#endif
1212	{
1213	PCPUMCTX pCtx = pVM->em.s.pCtx;
1214	int rc;
1215
1216	/*
1217	*
1218	* The simple solution is to use the recompiler.
1219	* The better solution is to disassemble the current instruction and
1220	* try handle as many as possible without using REM.
1221	*
1222	*/
1223
1224	#ifdef LOG_ENABLED
1225	/*
1226	* Disassemble the instruction if requested.
1227	*/
1228	if (pszPrefix)
1229	{
1230	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1231	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1232	}
1233	#endif /* LOG_ENABLED */
1234
1235	/*
1236	* PATM is making life more interesting.
1237	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1238	* tell PATM there is a trap in this code and have it take the appropriate actions
1239	* to allow us execute the code in REM.
1240	*/
1241	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1242	{
1243	Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
1244
1245	RTGCPTR pNewEip;
1246	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1247	switch (rc)
1248	{
1249	/*
1250	* It's not very useful to emulate a single instruction and then go back to raw
1251	* mode; just execute the whole block until IF is set again.
1252	*/
1253	case VINF_SUCCESS:
1254	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
1255	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1256	pCtx->eip = pNewEip;
1257	Assert(pCtx->eip);
1258
1259	if (pCtx->eflags.Bits.u1IF)
1260	{
1261	/*
1262	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1263	*/
1264	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1265	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1266	}
1267	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1268	{
1269	/* special case: iret, that sets IF, detected a pending irq/event */
1270	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1271	}
1272	return VINF_EM_RESCHEDULE_REM;
1273
1274	/*
1275	* One instruction.
1276	*/
1277	case VINF_PATCH_EMULATE_INSTR:
1278	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1279	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1280	pCtx->eip = pNewEip;
1281	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1282
1283	/*
1284	* The patch was disabled, hand it to the REM.
1285	*/
1286	case VERR_PATCH_DISABLED:
1287	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
1288	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1289	pCtx->eip = pNewEip;
1290	if (pCtx->eflags.Bits.u1IF)
1291	{
1292	/*
1293	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1294	*/
1295	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1296	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1297	}
1298	return VINF_EM_RESCHEDULE_REM;
1299
1300	/* Force continued patch exection; usually due to write monitored stack. */
1301	case VINF_PATCH_CONTINUE:
1302	return VINF_SUCCESS;
1303
1304	default:
1305	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
1306	return VERR_IPE_UNEXPECTED_STATUS;
1307	}
1308	}
1309
1310	#if 0
1311	/* Try our own instruction emulator before falling back to the recompiler. */
1312	DISCPUSTATE Cpu;
1313	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1314	if (RT_SUCCESS(rc))
1315	{
1316	uint32_t size;
1317
1318	switch (Cpu.pCurInstr->opcode)
1319	{
1320	/* @todo we can do more now */
1321	case OP_MOV:
1322	case OP_AND:
1323	case OP_OR:
1324	case OP_XOR:
1325	case OP_POP:
1326	case OP_INC:
1327	case OP_DEC:
1328	case OP_XCHG:
1329	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1330	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1331	if (RT_SUCCESS(rc))
1332	{
1333	pCtx->rip += Cpu.opsize;
1334	#ifdef EM_NOTIFY_HWACCM
1335	if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1336	HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
1337	#endif
1338	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1339	return rc;
1340	}
1341	if (rc != VERR_EM_INTERPRETER)
1342	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
1343	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1344	break;
1345	}
1346	}
1347	#endif /* 0 */
1348	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1349	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
1350	rc = REMR3EmulateInstruction(pVM);
1351	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1352
1353	#ifdef EM_NOTIFY_HWACCM
1354	if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1355	HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
1356	#endif
1357	return rc;
1358	}
1359
1360
1361	/**
1362	* Executes one (or perhaps a few more) instruction(s).
1363	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1364	*
1365	* @returns VBox status code suitable for EM.
1366	* @param pVM VM handle.
1367	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1368	* instruction and prefix the log output with this text.
1369	* @param rcGC GC return code
1370	*/
1371	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1372	{
1373	#ifdef LOG_ENABLED
1374	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1375	#else
1376	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1377	#endif
1378	}
1379
1380	/**
1381	* Executes one (or perhaps a few more) IO instruction(s).
1382	*
1383	* @returns VBox status code suitable for EM.
1384	* @param pVM VM handle.
1385	*/
1386	int emR3RawExecuteIOInstruction(PVM pVM)
1387	{
1388	int rc;
1389	PCPUMCTX pCtx = pVM->em.s.pCtx;
1390
1391	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1392
1393	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1394	* as io instructions tend to come in packages of more than one
1395	*/
1396	DISCPUSTATE Cpu;
1397	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "IO EMU");
1398	if (RT_SUCCESS(rc))
1399	{
1400	rc = VINF_EM_RAW_EMULATE_INSTR;
1401
1402	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1403	{
1404	switch (Cpu.pCurInstr->opcode)
1405	{
1406	case OP_IN:
1407	{
1408	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1409	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1410	break;
1411	}
1412
1413	case OP_OUT:
1414	{
1415	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1416	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1417	break;
1418	}
1419	}
1420	}
1421	else if (Cpu.prefix & PREFIX_REP)
1422	{
1423	switch (Cpu.pCurInstr->opcode)
1424	{
1425	case OP_INSB:
1426	case OP_INSWD:
1427	{
1428	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1429	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1430	break;
1431	}
1432
1433	case OP_OUTSB:
1434	case OP_OUTSWD:
1435	{
1436	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1437	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1438	break;
1439	}
1440	}
1441	}
1442
1443	/*
1444	* Handled the I/O return codes.
1445	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1446	*/
1447	if (IOM_SUCCESS(rc))
1448	{
1449	pCtx->rip += Cpu.opsize;
1450	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1451	return rc;
1452	}
1453
1454	if (rc == VINF_EM_RAW_GUEST_TRAP)
1455	{
1456	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1457	rc = emR3RawGuestTrap(pVM);
1458	return rc;
1459	}
1460	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1461
1462	if (RT_FAILURE(rc))
1463	{
1464	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1465	return rc;
1466	}
1467	AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc=%Rrc\n", rc));
1468	}
1469	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1470	return emR3RawExecuteInstruction(pVM, "IO: ");
1471	}
1472
1473
1474	/**
1475	* Handle a guest context trap.
1476	*
1477	* @returns VBox status code suitable for EM.
1478	* @param pVM VM handle.
1479	*/
1480	static int emR3RawGuestTrap(PVM pVM)
1481	{
1482	PCPUMCTX pCtx = pVM->em.s.pCtx;
1483
1484	/*
1485	* Get the trap info.
1486	*/
1487	uint8_t u8TrapNo;
1488	TRPMEVENT enmType;
1489	RTGCUINT uErrorCode;
1490	RTGCUINTPTR uCR2;
1491	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1492	if (RT_FAILURE(rc))
1493	{
1494	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
1495	return rc;
1496	}
1497
1498	/*
1499	* Traps can be directly forwarded in hardware accelerated mode.
1500	*/
1501	if (HWACCMR3IsActive(pVM))
1502	{
1503	#ifdef LOGGING_ENABLED
1504	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1505	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1506	#endif
1507	return VINF_EM_RESCHEDULE_HWACC;
1508	}
1509
1510	#if 1 /* Experimental: Review, disable if it causes trouble. */
1511	/*
1512	* Handle traps in patch code first.
1513	*
1514	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
1515	* but several traps isn't handled specially by TRPM in RC and we end up here
1516	* instead. One example is #DE.
1517	*/
1518	uint32_t uCpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
1519	if ( uCpl == 0
1520	&& PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1521	{
1522	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
1523	return emR3PatchTrap(pVM, pCtx, rc);
1524	}
1525	#endif
1526
1527	/*
1528	* If the guest gate is marked unpatched, then we will check again if we can patch it.
1529	* (This assumes that we've already tried and failed to dispatch the trap in
1530	* RC for the gates that already has been patched. Which is true for most high
1531	* volume traps, because these are handled specially, but not for odd ones like #DE.)
1532	*/
1533	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
1534	{
1535	CSAMR3CheckGates(pVM, u8TrapNo, 1);
1536	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
1537
1538	/* If it was successful, then we could go back to raw mode. */
1539	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
1540	{
1541	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
1542	rc = EMR3CheckRawForcedActions(pVM);
1543	AssertRCReturn(rc, rc);
1544
1545	TRPMERRORCODE enmError = uErrorCode != ~0U
1546	? TRPM_TRAP_HAS_ERRORCODE
1547	: TRPM_TRAP_NO_ERRORCODE;
1548	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
1549	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1550	{
1551	TRPMResetTrap(pVM);
1552	return VINF_EM_RESCHEDULE_RAW;
1553	}
1554	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
1555	}
1556	}
1557
1558	/*
1559	* Scan kernel code that traps; we might not get another chance.
1560	*/
1561	/** @todo move this up before the dispatching? */
1562	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1563	&& !pCtx->eflags.Bits.u1VM)
1564	{
1565	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1566	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1567	}
1568
1569	/*
1570	* Trap specific handling.
1571	*/
1572	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1573	{
1574	/*
1575	* If MONITOR & MWAIT are supported, then interpret them here.
1576	*/
1577	DISCPUSTATE cpu;
1578	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1579	if ( RT_SUCCESS(rc)
1580	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1581	{
1582	uint32_t u32Dummy, u32Features, u32ExtFeatures;
1583	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1584	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1585	{
1586	rc = TRPMResetTrap(pVM);
1587	AssertRC(rc);
1588
1589	uint32_t opsize;
1590	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
1591	if (RT_SUCCESS(rc))
1592	{
1593	pCtx->rip += cpu.opsize;
1594	#ifdef EM_NOTIFY_HWACCM
1595	if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1596	HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
1597	#endif
1598	return rc;
1599	}
1600	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1601	}
1602	}
1603	}
1604	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1605	{
1606	/*
1607	* Handle I/O bitmap?
1608	*/
1609	/** @todo We're not supposed to be here with a false guest trap concerning
1610	* I/O access. We can easily handle those in RC. */
1611	DISCPUSTATE cpu;
1612	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1613	if ( RT_SUCCESS(rc)
1614	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1615	{
1616	/*
1617	* We should really check the TSS for the IO bitmap, but it's not like this
1618	* lazy approach really makes things worse.
1619	*/
1620	rc = TRPMResetTrap(pVM);
1621	AssertRC(rc);
1622	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1623	}
1624	}
1625
1626	#ifdef LOG_ENABLED
1627	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1628	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1629
1630	/* Get guest page information. */
1631	uint64_t fFlags = 0;
1632	RTGCPHYS GCPhys = 0;
1633	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1634	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1635	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1636	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1637	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1638	#endif
1639
1640	/*
1641	* #PG has CR2.
1642	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1643	*/
1644	if (u8TrapNo == 14 /* #PG */)
1645	pCtx->cr2 = uCR2;
1646
1647	return VINF_EM_RESCHEDULE_REM;
1648	}
1649
1650
1651	/**
1652	* Handle a ring switch trap.
1653	* Need to do statistics and to install patches. The result is going to REM.
1654	*
1655	* @returns VBox status code suitable for EM.
1656	* @param pVM VM handle.
1657	*/
1658	int emR3RawRingSwitch(PVM pVM)
1659	{
1660	int rc;
1661	DISCPUSTATE Cpu;
1662	PCPUMCTX pCtx = pVM->em.s.pCtx;
1663
1664	/*
1665	* sysenter, syscall & callgate
1666	*/
1667	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1668	if (RT_SUCCESS(rc))
1669	{
1670	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1671	{
1672	if (pCtx->SysEnter.cs != 0)
1673	{
1674	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1675	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1676	if (RT_SUCCESS(rc))
1677	{
1678	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1679	return VINF_EM_RESCHEDULE_RAW;
1680	}
1681	}
1682	}
1683
1684	#ifdef VBOX_WITH_STATISTICS
1685	switch (Cpu.pCurInstr->opcode)
1686	{
1687	case OP_SYSENTER:
1688	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysEnter);
1689	break;
1690	case OP_SYSEXIT:
1691	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysExit);
1692	break;
1693	case OP_SYSCALL:
1694	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysCall);
1695	break;
1696	case OP_SYSRET:
1697	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysRet);
1698	break;
1699	}
1700	#endif
1701	}
1702	else
1703	AssertRC(rc);
1704
1705	/* go to the REM to emulate a single instruction */
1706	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1707	}
1708
1709
1710	/**
1711	* Handle a trap (\#PF or \#GP) in patch code
1712	*
1713	* @returns VBox status code suitable for EM.
1714	* @param pVM VM handle.
1715	* @param pCtx CPU context
1716	* @param gcret GC return code
1717	*/
1718	static int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1719	{
1720	uint8_t u8TrapNo;
1721	int rc;
1722	TRPMEVENT enmType;
1723	RTGCUINT uErrorCode;
1724	RTGCUINTPTR uCR2;
1725
1726	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1727
1728	if (gcret == VINF_PATM_PATCH_INT3)
1729	{
1730	u8TrapNo = 3;
1731	uCR2 = 0;
1732	uErrorCode = 0;
1733	}
1734	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
1735	{
1736	/* No active trap in this case. Kind of ugly. */
1737	u8TrapNo = X86_XCPT_GP;
1738	uCR2 = 0;
1739	uErrorCode = 0;
1740	}
1741	else
1742	{
1743	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1744	if (RT_FAILURE(rc))
1745	{
1746	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
1747	return rc;
1748	}
1749	/* Reset the trap as we'll execute the original instruction again. */
1750	TRPMResetTrap(pVM);
1751	}
1752
1753	/*
1754	* Deal with traps inside patch code.
1755	* (This code won't run outside GC.)
1756	*/
1757	if (u8TrapNo != 1)
1758	{
1759	#ifdef LOG_ENABLED
1760	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1761	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1762
1763	DISCPUSTATE Cpu;
1764	int rc;
1765
1766	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1767	if ( RT_SUCCESS(rc)
1768	&& Cpu.pCurInstr->opcode == OP_IRET)
1769	{
1770	uint32_t eip, selCS, uEFlags;
1771
1772	/* Iret crashes are bad as we have already changed the flags on the stack */
1773	rc = PGMPhysSimpleReadGCPtr(pVM, &eip, pCtx->esp, 4);
1774	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1775	rc \|= PGMPhysSimpleReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1776	if (rc == VINF_SUCCESS)
1777	{
1778	if ( (uEFlags & X86_EFL_VM)
1779	\|\| (selCS & X86_SEL_RPL) == 3)
1780	{
1781	uint32_t selSS, esp;
1782
1783	rc \|= PGMPhysSimpleReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1784	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1785
1786	if (uEFlags & X86_EFL_VM)
1787	{
1788	uint32_t selDS, selES, selFS, selGS;
1789	rc = PGMPhysSimpleReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1790	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1791	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1792	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1793	if (rc == VINF_SUCCESS)
1794	{
1795	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1796	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1797	}
1798	}
1799	else
1800	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1801	}
1802	else
1803	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
1804	}
1805	}
1806	#endif /* LOG_ENABLED */
1807	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1808	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1809
1810	RTGCPTR pNewEip;
1811	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1812	switch (rc)
1813	{
1814	/*
1815	* Execute the faulting instruction.
1816	*/
1817	case VINF_SUCCESS:
1818	{
1819	/** @todo execute a whole block */
1820	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
1821	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1822	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1823
1824	pCtx->eip = pNewEip;
1825	AssertRelease(pCtx->eip);
1826
1827	if (pCtx->eflags.Bits.u1IF)
1828	{
1829	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1830	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1831	*/
1832	if ( u8TrapNo == X86_XCPT_GP
1833	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1834	{
1835	/** @todo move to PATMR3HandleTrap */
1836	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
1837	PATMR3RemovePatch(pVM, pCtx->eip);
1838	}
1839
1840	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1841	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
1842
1843	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1844	/* Interrupts are enabled; just go back to the original instruction.
1845	return VINF_SUCCESS; */
1846	}
1847	return VINF_EM_RESCHEDULE_REM;
1848	}
1849
1850	/*
1851	* One instruction.
1852	*/
1853	case VINF_PATCH_EMULATE_INSTR:
1854	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1855	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1856	pCtx->eip = pNewEip;
1857	AssertRelease(pCtx->eip);
1858	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1859
1860	/*
1861	* The patch was disabled, hand it to the REM.
1862	*/
1863	case VERR_PATCH_DISABLED:
1864	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1865	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1866	pCtx->eip = pNewEip;
1867	AssertRelease(pCtx->eip);
1868
1869	if (pCtx->eflags.Bits.u1IF)
1870	{
1871	/*
1872	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1873	*/
1874	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1875	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1876	}
1877	return VINF_EM_RESCHEDULE_REM;
1878
1879	/* Force continued patch exection; usually due to write monitored stack. */
1880	case VINF_PATCH_CONTINUE:
1881	return VINF_SUCCESS;
1882
1883	/*
1884	* Anything else is fatal.
1885	*/
1886	default:
1887	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
1888	return VERR_IPE_UNEXPECTED_STATUS;
1889	}
1890	}
1891	return VINF_SUCCESS;
1892	}
1893
1894
1895	/**
1896	* Handle a privileged instruction.
1897	*
1898	* @returns VBox status code suitable for EM.
1899	* @param pVM VM handle.
1900	*/
1901	int emR3RawPrivileged(PVM pVM)
1902	{
1903	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1904	PCPUMCTX pCtx = pVM->em.s.pCtx;
1905
1906	Assert(!pCtx->eflags.Bits.u1VM);
1907
1908	if (PATMIsEnabled(pVM))
1909	{
1910	/*
1911	* Check if in patch code.
1912	*/
1913	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1914	{
1915	#ifdef LOG_ENABLED
1916	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1917	#endif
1918	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1919	return VERR_EM_RAW_PATCH_CONFLICT;
1920	}
1921	if ( (pCtx->ss & X86_SEL_RPL) == 0
1922	&& !pCtx->eflags.Bits.u1VM
1923	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1924	{
1925	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1926	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1927	if (RT_SUCCESS(rc))
1928	{
1929	#ifdef LOG_ENABLED
1930	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1931	#endif
1932	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1933	return VINF_SUCCESS;
1934	}
1935	}
1936	}
1937
1938	#ifdef LOG_ENABLED
1939	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1940	{
1941	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1942	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1943	}
1944	#endif
1945
1946	/*
1947	* Instruction statistics and logging.
1948	*/
1949	DISCPUSTATE Cpu;
1950	int rc;
1951
1952	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1953	if (RT_SUCCESS(rc))
1954	{
1955	#ifdef VBOX_WITH_STATISTICS
1956	PEMSTATS pStats = pVM->em.s.CTX_SUFF(pStats);
1957	switch (Cpu.pCurInstr->opcode)
1958	{
1959	case OP_INVLPG:
1960	STAM_COUNTER_INC(&pStats->StatInvlpg);
1961	break;
1962	case OP_IRET:
1963	STAM_COUNTER_INC(&pStats->StatIret);
1964	break;
1965	case OP_CLI:
1966	STAM_COUNTER_INC(&pStats->StatCli);
1967	emR3RecordCli(pVM, pCtx->rip);
1968	break;
1969	case OP_STI:
1970	STAM_COUNTER_INC(&pStats->StatSti);
1971	break;
1972	case OP_INSB:
1973	case OP_INSWD:
1974	case OP_IN:
1975	case OP_OUTSB:
1976	case OP_OUTSWD:
1977	case OP_OUT:
1978	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1979	break;
1980
1981	case OP_MOV_CR:
1982	if (Cpu.param1.flags & USE_REG_GEN32)
1983	{
1984	//read
1985	Assert(Cpu.param2.flags & USE_REG_CR);
1986	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1987	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1988	}
1989	else
1990	{
1991	//write
1992	Assert(Cpu.param1.flags & USE_REG_CR);
1993	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1994	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1995	}
1996	break;
1997
1998	case OP_MOV_DR:
1999	STAM_COUNTER_INC(&pStats->StatMovDRx);
2000	break;
2001	case OP_LLDT:
2002	STAM_COUNTER_INC(&pStats->StatMovLldt);
2003	break;
2004	case OP_LIDT:
2005	STAM_COUNTER_INC(&pStats->StatMovLidt);
2006	break;
2007	case OP_LGDT:
2008	STAM_COUNTER_INC(&pStats->StatMovLgdt);
2009	break;
2010	case OP_SYSENTER:
2011	STAM_COUNTER_INC(&pStats->StatSysEnter);
2012	break;
2013	case OP_SYSEXIT:
2014	STAM_COUNTER_INC(&pStats->StatSysExit);
2015	break;
2016	case OP_SYSCALL:
2017	STAM_COUNTER_INC(&pStats->StatSysCall);
2018	break;
2019	case OP_SYSRET:
2020	STAM_COUNTER_INC(&pStats->StatSysRet);
2021	break;
2022	case OP_HLT:
2023	STAM_COUNTER_INC(&pStats->StatHlt);
2024	break;
2025	default:
2026	STAM_COUNTER_INC(&pStats->StatMisc);
2027	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
2028	break;
2029	}
2030	#endif /* VBOX_WITH_STATISTICS */
2031	if ( (pCtx->ss & X86_SEL_RPL) == 0
2032	&& !pCtx->eflags.Bits.u1VM
2033	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
2034	{
2035	uint32_t size;
2036
2037	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
2038	switch (Cpu.pCurInstr->opcode)
2039	{
2040	case OP_CLI:
2041	pCtx->eflags.u32 &= ~X86_EFL_IF;
2042	Assert(Cpu.opsize == 1);
2043	pCtx->rip += Cpu.opsize;
2044	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2045	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
2046
2047	case OP_STI:
2048	pCtx->eflags.u32 \|= X86_EFL_IF;
2049	EMSetInhibitInterruptsPC(pVM, pCtx->rip + Cpu.opsize);
2050	Assert(Cpu.opsize == 1);
2051	pCtx->rip += Cpu.opsize;
2052	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2053	return VINF_SUCCESS;
2054
2055	case OP_HLT:
2056	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
2057	{
2058	PATMTRANSSTATE enmState;
2059	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
2060
2061	if (enmState == PATMTRANS_OVERWRITTEN)
2062	{
2063	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2064	Assert(rc == VERR_PATCH_DISABLED);
2065	/* Conflict detected, patch disabled */
2066	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
2067
2068	enmState = PATMTRANS_SAFE;
2069	}
2070
2071	/* The translation had better be successful. Otherwise we can't recover. */
2072	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
2073	if (enmState != PATMTRANS_OVERWRITTEN)
2074	pCtx->eip = pOrgInstrGC;
2075	}
2076	/* no break; we could just return VINF_EM_HALT here */
2077
2078	case OP_MOV_CR:
2079	case OP_MOV_DR:
2080	#ifdef LOG_ENABLED
2081	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2082	{
2083	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2084	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2085	}
2086	#endif
2087
2088	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2089	if (RT_SUCCESS(rc))
2090	{
2091	pCtx->rip += Cpu.opsize;
2092	#ifdef EM_NOTIFY_HWACCM
2093	if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
2094	HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
2095	#endif
2096	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2097
2098	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2099	&& Cpu.param1.flags == USE_REG_CR /* write */
2100	)
2101	{
2102	/* Deal with CR0 updates inside patch code that force
2103	* us to go to the recompiler.
2104	*/
2105	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
2106	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
2107	{
2108	PATMTRANSSTATE enmState;
2109	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
2110
2111	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
2112	if (enmState == PATMTRANS_OVERWRITTEN)
2113	{
2114	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2115	Assert(rc == VERR_PATCH_DISABLED);
2116	/* Conflict detected, patch disabled */
2117	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
2118	enmState = PATMTRANS_SAFE;
2119	}
2120	/* The translation had better be successful. Otherwise we can't recover. */
2121	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
2122	if (enmState != PATMTRANS_OVERWRITTEN)
2123	pCtx->rip = pOrgInstrGC;
2124	}
2125
2126	/* Reschedule is necessary as the execution/paging mode might have changed. */
2127	return VINF_EM_RESCHEDULE;
2128	}
2129	return rc; /* can return VINF_EM_HALT as well. */
2130	}
2131	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
2132	break; /* fall back to the recompiler */
2133	}
2134	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2135	}
2136	}
2137
2138	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2139	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
2140
2141	return emR3RawExecuteInstruction(pVM, "PRIV");
2142	}
2143
2144
2145	/**
2146	* Update the forced rawmode execution modifier.
2147	*
2148	* This function is called when we're returning from the raw-mode loop(s). If we're
2149	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2150	* if not in patch code, the flag will be cleared.
2151	*
2152	* We should never interrupt patch code while it's being executed. Cli patches can
2153	* contain big code blocks, but they are always executed with IF=0. Other patches
2154	* replace single instructions and should be atomic.
2155	*
2156	* @returns Updated rc.
2157	*
2158	* @param pVM The VM handle.
2159	* @param pCtx The guest CPU context.
2160	* @param rc The result code.
2161	*/
2162	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2163	{
2164	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2165	{
2166	/* ignore reschedule attempts. */
2167	switch (rc)
2168	{
2169	case VINF_EM_RESCHEDULE:
2170	case VINF_EM_RESCHEDULE_REM:
2171	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
2172	rc = VINF_SUCCESS;
2173	break;
2174	}
2175	pVM->em.s.fForceRAW = true;
2176	}
2177	else
2178	pVM->em.s.fForceRAW = false;
2179	return rc;
2180	}
2181
2182
2183	/**
2184	* Process a subset of the raw-mode return code.
2185	*
2186	* Since we have to share this with raw-mode single stepping, this inline
2187	* function has been created to avoid code duplication.
2188	*
2189	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2190	* @returns VBox status code to return to the EM main loop.
2191	*
2192	* @param pVM The VM handle
2193	* @param rc The return code.
2194	* @param pCtx The guest cpu context.
2195	*/
2196	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2197	{
2198	switch (rc)
2199	{
2200	/*
2201	* Common & simple ones.
2202	*/
2203	case VINF_SUCCESS:
2204	break;
2205	case VINF_EM_RESCHEDULE_RAW:
2206	case VINF_EM_RESCHEDULE_HWACC:
2207	case VINF_EM_RAW_INTERRUPT:
2208	case VINF_EM_RAW_TO_R3:
2209	case VINF_EM_RAW_TIMER_PENDING:
2210	case VINF_EM_PENDING_REQUEST:
2211	rc = VINF_SUCCESS;
2212	break;
2213
2214	/*
2215	* Privileged instruction.
2216	*/
2217	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2218	case VINF_PATM_PATCH_TRAP_GP:
2219	rc = emR3RawPrivileged(pVM);
2220	break;
2221
2222	/*
2223	* Got a trap which needs dispatching.
2224	*/
2225	case VINF_EM_RAW_GUEST_TRAP:
2226	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2227	{
2228	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2229	rc = VERR_EM_RAW_PATCH_CONFLICT;
2230	break;
2231	}
2232	rc = emR3RawGuestTrap(pVM);
2233	break;
2234
2235	/*
2236	* Trap in patch code.
2237	*/
2238	case VINF_PATM_PATCH_TRAP_PF:
2239	case VINF_PATM_PATCH_INT3:
2240	rc = emR3PatchTrap(pVM, pCtx, rc);
2241	break;
2242
2243	case VINF_PATM_DUPLICATE_FUNCTION:
2244	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2245	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2246	AssertRC(rc);
2247	rc = VINF_SUCCESS;
2248	break;
2249
2250	case VINF_PATM_CHECK_PATCH_PAGE:
2251	rc = PATMR3HandleMonitoredPage(pVM);
2252	AssertRC(rc);
2253	rc = VINF_SUCCESS;
2254	break;
2255
2256	/*
2257	* Patch manager.
2258	*/
2259	case VERR_EM_RAW_PATCH_CONFLICT:
2260	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
2261	break;
2262
2263	#ifdef VBOX_WITH_VMI
2264	/*
2265	* PARAV function.
2266	*/
2267	case VINF_EM_RESCHEDULE_PARAV:
2268	rc = PARAVCallFunction(pVM);
2269	break;
2270	#endif
2271
2272	/*
2273	* Memory mapped I/O access - attempt to patch the instruction
2274	*/
2275	case VINF_PATM_HC_MMIO_PATCH_READ:
2276	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2277	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2278	if (RT_FAILURE(rc))
2279	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2280	break;
2281
2282	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2283	AssertFailed(); /* not yet implemented. */
2284	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2285	break;
2286
2287	/*
2288	* Conflict or out of page tables.
2289	*
2290	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2291	* do here is to execute the pending forced actions.
2292	*/
2293	case VINF_PGM_SYNC_CR3:
2294	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2295	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2296	rc = VINF_SUCCESS;
2297	break;
2298
2299	/*
2300	* Paging mode change.
2301	*/
2302	case VINF_PGM_CHANGE_MODE:
2303	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2304	if (rc == VINF_SUCCESS)
2305	rc = VINF_EM_RESCHEDULE;
2306	AssertMsg(RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
2307	break;
2308
2309	/*
2310	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2311	*/
2312	case VINF_CSAM_PENDING_ACTION:
2313	rc = VINF_SUCCESS;
2314	break;
2315
2316	/*
2317	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2318	*/
2319	case VINF_EM_RAW_INTERRUPT_PENDING:
2320	case VINF_EM_RAW_RING_SWITCH_INT:
2321	Assert(TRPMHasTrap(pVM));
2322	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2323
2324	if (TRPMHasTrap(pVM))
2325	{
2326	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2327	uint8_t u8Interrupt = TRPMGetTrapNo(pVM);
2328	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2329	{
2330	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2331	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2332	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2333	}
2334	}
2335	rc = VINF_EM_RESCHEDULE_REM;
2336	break;
2337
2338	/*
2339	* Other ring switch types.
2340	*/
2341	case VINF_EM_RAW_RING_SWITCH:
2342	rc = emR3RawRingSwitch(pVM);
2343	break;
2344
2345	/*
2346	* REMGCNotifyInvalidatePage() failed because of overflow.
2347	*/
2348	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2349	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2350	REMR3ReplayInvalidatedPages(pVM);
2351	rc = VINF_SUCCESS;
2352	break;
2353
2354	/*
2355	* I/O Port access - emulate the instruction.
2356	*/
2357	case VINF_IOM_HC_IOPORT_READ:
2358	case VINF_IOM_HC_IOPORT_WRITE:
2359	rc = emR3RawExecuteIOInstruction(pVM);
2360	break;
2361
2362	/*
2363	* Memory mapped I/O access - emulate the instruction.
2364	*/
2365	case VINF_IOM_HC_MMIO_READ:
2366	case VINF_IOM_HC_MMIO_WRITE:
2367	case VINF_IOM_HC_MMIO_READ_WRITE:
2368	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2369	break;
2370
2371	/*
2372	* (MM)IO intensive code block detected; fall back to the recompiler for better performance
2373	*/
2374	case VINF_EM_RAW_EMULATE_IO_BLOCK:
2375	rc =HWACCMR3EmulateIoBlock(pVM, pCtx);
2376	break;
2377
2378	/*
2379	* Execute instruction.
2380	*/
2381	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2382	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2383	break;
2384	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2385	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2386	break;
2387	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2388	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2389	break;
2390	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2391	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2392	break;
2393	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2394	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2395	break;
2396
2397	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2398	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2399	rc = emR3RawPrivileged(pVM);
2400	break;
2401
2402	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2403	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2404	break;
2405
2406	case VINF_EM_RAW_EMULATE_INSTR:
2407	case VINF_PATCH_EMULATE_INSTR:
2408	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2409	break;
2410
2411	/*
2412	* Stale selector and iret traps => REM.
2413	*/
2414	case VINF_EM_RAW_STALE_SELECTOR:
2415	case VINF_EM_RAW_IRET_TRAP:
2416	/* We will not go to the recompiler if EIP points to patch code. */
2417	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2418	{
2419	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2420	}
2421	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
2422	rc = VINF_EM_RESCHEDULE_REM;
2423	break;
2424
2425	/*
2426	* Up a level.
2427	*/
2428	case VINF_EM_TERMINATE:
2429	case VINF_EM_OFF:
2430	case VINF_EM_RESET:
2431	case VINF_EM_SUSPEND:
2432	case VINF_EM_HALT:
2433	case VINF_EM_RESUME:
2434	case VINF_EM_NO_MEMORY:
2435	case VINF_EM_RESCHEDULE:
2436	case VINF_EM_RESCHEDULE_REM:
2437	break;
2438
2439	/*
2440	* Up a level and invoke the debugger.
2441	*/
2442	case VINF_EM_DBG_STEPPED:
2443	case VINF_EM_DBG_BREAKPOINT:
2444	case VINF_EM_DBG_STEP:
2445	case VINF_EM_DBG_HYPER_BREAKPOINT:
2446	case VINF_EM_DBG_HYPER_STEPPED:
2447	case VINF_EM_DBG_HYPER_ASSERTION:
2448	case VINF_EM_DBG_STOP:
2449	break;
2450
2451	/*
2452	* Up a level, dump and debug.
2453	*/
2454	case VERR_TRPM_DONT_PANIC:
2455	case VERR_TRPM_PANIC:
2456	case VERR_VMM_RING0_ASSERTION:
2457	break;
2458
2459	/*
2460	* Up a level, after HwAccM have done some release logging.
2461	*/
2462	case VERR_VMX_INVALID_VMCS_FIELD:
2463	case VERR_VMX_INVALID_VMCS_PTR:
2464	case VERR_VMX_INVALID_VMXON_PTR:
2465	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2466	case VERR_VMX_UNEXPECTED_EXCEPTION:
2467	case VERR_VMX_UNEXPECTED_EXIT_CODE:
2468	case VERR_VMX_INVALID_GUEST_STATE:
2469	case VERR_VMX_UNABLE_TO_START_VM:
2470	case VERR_VMX_UNABLE_TO_RESUME_VM:
2471	HWACCMR3CheckError(pVM, rc);
2472	break;
2473	/*
2474	* Anything which is not known to us means an internal error
2475	* and the termination of the VM!
2476	*/
2477	default:
2478	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
2479	break;
2480	}
2481	return rc;
2482	}
2483
2484
2485	/**
2486	* Check for pending raw actions
2487	*
2488	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
2489	* EM statuses.
2490	* @param pVM The VM to operate on.
2491	*/
2492	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2493	{
2494	return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2495	}
2496
2497
2498	/**
2499	* Process raw-mode specific forced actions.
2500	*
2501	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2502	*
2503	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
2504	* EM statuses.
2505	* @param pVM The VM handle.
2506	* @param pCtx The guest CPUM register context.
2507	*/
2508	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2509	{
2510	/*
2511	* Note that the order is vitally important!
2512	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2513	*/
2514
2515
2516	/*
2517	* Sync selector tables.
2518	*/
2519	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2520	{
2521	int rc = SELMR3UpdateFromCPUM(pVM);
2522	if (RT_FAILURE(rc))
2523	return rc;
2524	}
2525
2526	/*
2527	* Sync IDT.
2528	*/
2529	if (VM_FF_ISPENDING(pVM, VM_FF_TRPM_SYNC_IDT))
2530	{
2531	int rc = TRPMR3SyncIDT(pVM);
2532	if (RT_FAILURE(rc))
2533	return rc;
2534	}
2535
2536	/*
2537	* Sync TSS.
2538	*/
2539	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS))
2540	{
2541	int rc = SELMR3SyncTSS(pVM);
2542	if (RT_FAILURE(rc))
2543	return rc;
2544	}
2545
2546	/*
2547	* Sync page directory.
2548	*/
2549	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2550	{
2551	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2552	if (RT_FAILURE(rc))
2553	return rc;
2554
2555	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2556
2557	/* Prefetch pages for EIP and ESP */
2558	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2559	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2560	if (rc == VINF_SUCCESS)
2561	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2562	if (rc != VINF_SUCCESS)
2563	{
2564	if (rc != VINF_PGM_SYNC_CR3)
2565	{
2566	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
2567	return rc;
2568	}
2569	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2570	if (RT_FAILURE(rc))
2571	return rc;
2572	}
2573	/** @todo maybe prefetch the supervisor stack page as well */
2574	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2575	}
2576
2577	/*
2578	* Allocate handy pages (just in case the above actions have consumed some pages).
2579	*/
2580	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
2581	{
2582	int rc = PGMR3PhysAllocateHandyPages(pVM);
2583	if (RT_FAILURE(rc))
2584	return rc;
2585	}
2586
2587	/*
2588	* Check whether we're out of memory now.
2589	*
2590	* This may stem from some of the above actions or operations that has been executed
2591	* since we ran FFs. The allocate handy pages must for instance always be followed by
2592	* this check.
2593	*/
2594	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2595	return VINF_EM_NO_MEMORY;
2596
2597	return VINF_SUCCESS;
2598	}
2599
2600
2601	/**
2602	* Executes raw code.
2603	*
2604	* This function contains the raw-mode version of the inner
2605	* execution loop (the outer loop being in EMR3ExecuteVM()).
2606	*
2607	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2608	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2609	*
2610	* @param pVM VM handle.
2611	* @param pfFFDone Where to store an indicator telling whether or not
2612	* FFs were done before returning.
2613	*/
2614	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2615	{
2616	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2617
2618	int rc = VERR_INTERNAL_ERROR;
2619	PCPUMCTX pCtx = pVM->em.s.pCtx;
2620	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2621	pVM->em.s.fForceRAW = false;
2622	*pfFFDone = false;
2623
2624
2625	/*
2626	*
2627	* Spin till we get a forced action or raw mode status code resulting in
2628	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2629	*
2630	*/
2631	for (;;)
2632	{
2633	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2634
2635	/*
2636	* Check various preconditions.
2637	*/
2638	#ifdef VBOX_STRICT
2639	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2640	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2641	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2642	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2643	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2644	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2645	&& PGMMapHasConflicts(pVM))
2646	{
2647	PGMMapCheck(pVM);
2648	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2649	return VERR_INTERNAL_ERROR;
2650	}
2651	#endif /* VBOX_STRICT */
2652
2653	/*
2654	* Process high priority pre-execution raw-mode FFs.
2655	*/
2656	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2657	{
2658	rc = emR3RawForcedActions(pVM, pCtx);
2659	if (rc != VINF_SUCCESS)
2660	break;
2661	}
2662
2663	/*
2664	* If we're going to execute ring-0 code, the guest state needs to
2665	* be modified a bit and some of the state components (IF, SS/CS RPL,
2666	* and perhaps EIP) needs to be stored with PATM.
2667	*/
2668	rc = CPUMRawEnter(pVM, NULL);
2669	if (rc != VINF_SUCCESS)
2670	{
2671	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2672	break;
2673	}
2674
2675	/*
2676	* Scan code before executing it. Don't bother with user mode or V86 code
2677	*/
2678	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2679	&& !pCtx->eflags.Bits.u1VM
2680	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2681	{
2682	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2683	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2684	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2685	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2686	{
2687	rc = emR3RawForcedActions(pVM, pCtx);
2688	if (rc != VINF_SUCCESS)
2689	break;
2690	}
2691	}
2692
2693	#ifdef LOG_ENABLED
2694	/*
2695	* Log important stuff before entering GC.
2696	*/
2697	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2698	if (pCtx->eflags.Bits.u1VM)
2699	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2700	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2701	{
2702	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2703	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2704	}
2705	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2706	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2707	#endif /* LOG_ENABLED */
2708
2709
2710
2711	/*
2712	* Execute the code.
2713	*/
2714	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2715	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2716	VMMR3Unlock(pVM);
2717	rc = VMMR3RawRunGC(pVM);
2718	VMMR3Lock(pVM);
2719	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2720	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2721
2722	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2723	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
2724
2725
2726
2727	/*
2728	* Restore the real CPU state and deal with high priority post
2729	* execution FFs before doing anything else.
2730	*/
2731	rc = CPUMRawLeave(pVM, NULL, rc);
2732	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2733	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2734	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2735
2736	#ifdef VBOX_STRICT
2737	/*
2738	* Assert TSS consistency & rc vs patch code.
2739	*/
2740	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2741	&& EMIsRawRing0Enabled(pVM))
2742	SELMR3CheckTSS(pVM);
2743	switch (rc)
2744	{
2745	case VINF_SUCCESS:
2746	case VINF_EM_RAW_INTERRUPT:
2747	case VINF_PATM_PATCH_TRAP_PF:
2748	case VINF_PATM_PATCH_TRAP_GP:
2749	case VINF_PATM_PATCH_INT3:
2750	case VINF_PATM_CHECK_PATCH_PAGE:
2751	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2752	case VINF_EM_RAW_GUEST_TRAP:
2753	case VINF_EM_RESCHEDULE_RAW:
2754	break;
2755
2756	default:
2757	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2758	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVM), rc));
2759	break;
2760	}
2761	/*
2762	* Let's go paranoid!
2763	*/
2764	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2765	&& PGMMapHasConflicts(pVM))
2766	{
2767	PGMMapCheck(pVM);
2768	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
2769	return VERR_INTERNAL_ERROR;
2770	}
2771	#endif /* VBOX_STRICT */
2772
2773	/*
2774	* Process the returned status code.
2775	*/
2776	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2777	{
2778	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2779	break;
2780	}
2781	rc = emR3RawHandleRC(pVM, pCtx, rc);
2782	if (rc != VINF_SUCCESS)
2783	{
2784	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2785	if (rc != VINF_SUCCESS)
2786	{
2787	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2788	break;
2789	}
2790	}
2791
2792	/*
2793	* Check and execute forced actions.
2794	*/
2795	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2796	TMTimerPoll(pVM);
2797	#endif
2798	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2799	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY))
2800	{
2801	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2802
2803	STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2804	rc = emR3ForcedActions(pVM, rc);
2805	STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2806	if ( rc != VINF_SUCCESS
2807	&& rc != VINF_EM_RESCHEDULE_RAW)
2808	{
2809	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2810	if (rc != VINF_SUCCESS)
2811	{
2812	*pfFFDone = true;
2813	break;
2814	}
2815	}
2816	}
2817	}
2818
2819	/*
2820	* Return to outer loop.
2821	*/
2822	#if defined(LOG_ENABLED) && defined(DEBUG)
2823	RTLogFlush(NULL);
2824	#endif
2825	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2826	return rc;
2827	}
2828
2829
2830	/**
2831	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2832	*
2833	* This function contains the raw-mode version of the inner
2834	* execution loop (the outer loop being in EMR3ExecuteVM()).
2835	*
2836	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2837	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2838	*
2839	* @param pVM VM handle.
2840	* @param idCpu VMCPU id.
2841	* @param pfFFDone Where to store an indicator telling whether or not
2842	* FFs were done before returning.
2843	*/
2844	static int emR3HwAccExecute(PVM pVM, RTCPUID idCpu, bool *pfFFDone)
2845	{
2846	int rc = VERR_INTERNAL_ERROR;
2847	PCPUMCTX pCtx = pVM->em.s.pCtx;
2848
2849	LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
2850	*pfFFDone = false;
2851
2852	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2853
2854	#ifdef EM_NOTIFY_HWACCM
2855	HWACCMR3NotifyScheduled(&pVM->aCpus[idCpu]);
2856	#endif
2857
2858	/*
2859	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2860	*/
2861	for (;;)
2862	{
2863	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2864
2865	/*
2866	* Process high priority pre-execution raw-mode FFs.
2867	*/
2868	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
2869	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2870	{
2871	rc = emR3RawForcedActions(pVM, pCtx);
2872	if (rc != VINF_SUCCESS)
2873	break;
2874	}
2875
2876	#ifdef LOG_ENABLED
2877	/*
2878	* Log important stuff before entering GC.
2879	*/
2880	if (TRPMHasTrap(pVM))
2881	Log(("Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", TRPMGetTrapNo(pVM), pCtx->cs, (RTGCPTR)pCtx->rip));
2882
2883	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2884	if (pCtx->eflags.Bits.u1VM)
2885	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2886	else if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
2887	Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2888	else
2889	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2890	#endif /* LOG_ENABLED */
2891
2892	/*
2893	* Execute the code.
2894	*/
2895	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2896	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2897	VMMR3Unlock(pVM);
2898	rc = VMMR3HwAccRunGC(pVM, idCpu);
2899	VMMR3Lock(pVM);
2900	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2901
2902	/*
2903	* Deal with high priority post execution FFs before doing anything else.
2904	*/
2905	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2906	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2907	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2908
2909	/*
2910	* Process the returned status code.
2911	*/
2912	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2913	break;
2914
2915	rc = emR3RawHandleRC(pVM, pCtx, rc);
2916	if (rc != VINF_SUCCESS)
2917	break;
2918
2919	/*
2920	* Check and execute forced actions.
2921	*/
2922	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2923	TMTimerPoll(pVM);
2924	#endif
2925	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2926	{
2927	rc = emR3ForcedActions(pVM, rc);
2928	if ( rc != VINF_SUCCESS
2929	&& rc != VINF_EM_RESCHEDULE_HWACC)
2930	{
2931	*pfFFDone = true;
2932	break;
2933	}
2934	}
2935	}
2936
2937	/*
2938	* Return to outer loop.
2939	*/
2940	#if defined(LOG_ENABLED) && defined(DEBUG)
2941	RTLogFlush(NULL);
2942	#endif
2943	return rc;
2944	}
2945
2946
2947	/**
2948	* Decides whether to execute RAW, HWACC or REM.
2949	*
2950	* @returns new EM state
2951	* @param pVM The VM.
2952	* @param pCtx The CPU context.
2953	*/
2954	static EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2955	{
2956	/*
2957	* When forcing raw-mode execution, things are simple.
2958	*/
2959	if (pVM->em.s.fForceRAW)
2960	return EMSTATE_RAW;
2961
2962	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2963	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2964	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2965
2966	X86EFLAGS EFlags = pCtx->eflags;
2967	if (HWACCMIsEnabled(pVM))
2968	{
2969	/* Hardware accelerated raw-mode:
2970	*
2971	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2972	*/
2973	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2974	return EMSTATE_HWACC;
2975
2976	/* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
2977	* off monitoring features essential for raw mode! */
2978	return EMSTATE_REM;
2979	}
2980
2981	/*
2982	* Standard raw-mode:
2983	*
2984	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2985	* or 32 bits protected mode ring 0 code
2986	*
2987	* The tests are ordered by the likelyhood of being true during normal execution.
2988	*/
2989	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2990	{
2991	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2992	return EMSTATE_REM;
2993	}
2994
2995	#ifndef VBOX_RAW_V86
2996	if (EFlags.u32 & X86_EFL_VM) {
2997	Log2(("raw mode refused: VM_MASK\n"));
2998	return EMSTATE_REM;
2999	}
3000	#endif
3001
3002	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
3003	uint32_t u32CR0 = pCtx->cr0;
3004	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
3005	{
3006	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
3007	return EMSTATE_REM;
3008	}
3009
3010	if (pCtx->cr4 & X86_CR4_PAE)
3011	{
3012	uint32_t u32Dummy, u32Features;
3013
3014	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3015	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3016	return EMSTATE_REM;
3017	}
3018
3019	unsigned uSS = pCtx->ss;
3020	if ( pCtx->eflags.Bits.u1VM
3021	\|\| (uSS & X86_SEL_RPL) == 3)
3022	{
3023	if (!EMIsRawRing3Enabled(pVM))
3024	return EMSTATE_REM;
3025
3026	if (!(EFlags.u32 & X86_EFL_IF))
3027	{
3028	Log2(("raw mode refused: IF (RawR3)\n"));
3029	return EMSTATE_REM;
3030	}
3031
3032	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
3033	{
3034	Log2(("raw mode refused: CR0.WP + RawR0\n"));
3035	return EMSTATE_REM;
3036	}
3037	}
3038	else
3039	{
3040	if (!EMIsRawRing0Enabled(pVM))
3041	return EMSTATE_REM;
3042
3043	/* Only ring 0 supervisor code. */
3044	if ((uSS & X86_SEL_RPL) != 0)
3045	{
3046	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
3047	return EMSTATE_REM;
3048	}
3049
3050	// Let's start with pure 32 bits ring 0 code first
3051	/** @todo What's pure 32-bit mode? flat? */
3052	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
3053	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
3054	{
3055	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
3056	return EMSTATE_REM;
3057	}
3058
3059	/* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
3060	if (!(u32CR0 & X86_CR0_WP))
3061	{
3062	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
3063	return EMSTATE_REM;
3064	}
3065
3066	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
3067	{
3068	Log2(("raw r0 mode forced: patch code\n"));
3069	return EMSTATE_RAW;
3070	}
3071
3072	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
3073	if (!(EFlags.u32 & X86_EFL_IF))
3074	{
3075	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
3076	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
3077	return EMSTATE_REM;
3078	}
3079	#endif
3080
3081	/** @todo still necessary??? */
3082	if (EFlags.Bits.u2IOPL != 0)
3083	{
3084	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
3085	return EMSTATE_REM;
3086	}
3087	}
3088
3089	Assert(PGMPhysIsA20Enabled(pVM));
3090	return EMSTATE_RAW;
3091	}
3092
3093
3094	/**
3095	* Executes all high priority post execution force actions.
3096	*
3097	* @returns rc or a fatal status code.
3098	*
3099	* @param pVM VM handle.
3100	* @param rc The current rc.
3101	*/
3102	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
3103	{
3104	if (VM_FF_ISPENDING(pVM, VM_FF_PDM_CRITSECT))
3105	PDMR3CritSectFF(pVM);
3106
3107	if (VM_FF_ISPENDING(pVM, VM_FF_CSAM_PENDING_ACTION))
3108	CSAMR3DoPendingAction(pVM);
3109
3110	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3111	{
3112	if ( rc > VINF_EM_NO_MEMORY
3113	&& rc <= VINF_EM_LAST)
3114	rc = VINF_EM_NO_MEMORY;
3115	}
3116
3117	return rc;
3118	}
3119
3120
3121	/**
3122	* Executes all pending forced actions.
3123	*
3124	* Forced actions can cause execution delays and execution
3125	* rescheduling. The first we deal with using action priority, so
3126	* that for instance pending timers aren't scheduled and ran until
3127	* right before execution. The rescheduling we deal with using
3128	* return codes. The same goes for VM termination, only in that case
3129	* we exit everything.
3130	*
3131	* @returns VBox status code of equal or greater importance/severity than rc.
3132	* The most important ones are: VINF_EM_RESCHEDULE,
3133	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3134	*
3135	* @param pVM VM handle.
3136	* @param rc The current rc.
3137	*
3138	*/
3139	static int emR3ForcedActions(PVM pVM, int rc)
3140	{
3141	STAM_REL_PROFILE_START(&pVM->em.s.StatForcedActions, a);
3142	#ifdef VBOX_STRICT
3143	int rcIrq = VINF_SUCCESS;
3144	#endif
3145	int rc2;
3146	#define UPDATE_RC() \
3147	do { \
3148	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
3149	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
3150	break; \
3151	if (!rc \|\| rc2 < rc) \
3152	rc = rc2; \
3153	} while (0)
3154
3155	/*
3156	* Post execution chunk first.
3157	*/
3158	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
3159	{
3160	/*
3161	* Termination request.
3162	*/
3163	if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
3164	{
3165	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3166	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3167	return VINF_EM_TERMINATE;
3168	}
3169
3170	/*
3171	* Debugger Facility polling.
3172	*/
3173	if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
3174	{
3175	rc2 = DBGFR3VMMForcedAction(pVM);
3176	UPDATE_RC();
3177	}
3178
3179	/*
3180	* Postponed reset request.
3181	*/
3182	if (VM_FF_ISPENDING(pVM, VM_FF_RESET))
3183	{
3184	rc2 = VMR3Reset(pVM);
3185	UPDATE_RC();
3186	VM_FF_CLEAR(pVM, VM_FF_RESET);
3187	}
3188
3189	/*
3190	* CSAM page scanning.
3191	*/
3192	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_CSAM_SCAN_PAGE, VM_FF_PGM_NO_MEMORY))
3193	{
3194	PCPUMCTX pCtx = pVM->em.s.pCtx;
3195
3196	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3197	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3198
3199	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3200	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3201	}
3202
3203	/*
3204	* Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
3205	*/
3206	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3207	{
3208	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3209	UPDATE_RC();
3210	if (rc == VINF_EM_NO_MEMORY)
3211	return rc;
3212	}
3213
3214	/* check that we got them all */
3215	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE \| VM_FF_PGM_NO_MEMORY)));
3216	}
3217
3218	/*
3219	* Normal priority then.
3220	* (Executed in no particular order.)
3221	*/
3222	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
3223	{
3224	/*
3225	* PDM Queues are pending.
3226	*/
3227	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
3228	PDMR3QueueFlushAll(pVM);
3229
3230	/*
3231	* PDM DMA transfers are pending.
3232	*/
3233	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
3234	PDMR3DmaRun(pVM);
3235
3236	/*
3237	* Requests from other threads.
3238	*/
3239	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
3240	{
3241	rc2 = VMR3ReqProcessU(pVM->pUVM, VMREQDEST_ANY);
3242	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3243	{
3244	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
3245	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3246	return rc2;
3247	}
3248	UPDATE_RC();
3249	}
3250
3251	/* Replay the handler notification changes. */
3252	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
3253	REMR3ReplayHandlerNotifications(pVM);
3254
3255	/* check that we got them all */
3256	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY)));
3257	}
3258
3259	/*
3260	* High priority pre execution chunk last.
3261	* (Executed in ascending priority order.)
3262	*/
3263	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3264	{
3265	/*
3266	* Timers before interrupts.
3267	*/
3268	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_TIMER, VM_FF_PGM_NO_MEMORY))
3269	TMR3TimerQueuesDo(pVM);
3270
3271	/*
3272	* The instruction following an emulated STI should always be executed!
3273	*/
3274	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_INHIBIT_INTERRUPTS, VM_FF_PGM_NO_MEMORY))
3275	{
3276	Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3277	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3278	{
3279	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3280	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3281	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3282	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3283	*/
3284	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3285	}
3286	if (HWACCMR3IsActive(pVM))
3287	rc2 = VINF_EM_RESCHEDULE_HWACC;
3288	else
3289	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3290
3291	UPDATE_RC();
3292	}
3293
3294	/*
3295	* Interrupts.
3296	*/
3297	if ( !VM_FF_ISPENDING(pVM, VM_FF_INHIBIT_INTERRUPTS \| VM_FF_PGM_NO_MEMORY)
3298	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_HWACC)
3299	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3300	&& PATMAreInterruptsEnabled(pVM)
3301	&& !HWACCMR3IsEventPending(pVM))
3302	{
3303	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3304	{
3305	/* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3306	/** @todo this really isn't nice, should properly handle this */
3307	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3308	#ifdef VBOX_STRICT
3309	rcIrq = rc2;
3310	#endif
3311	UPDATE_RC();
3312	}
3313	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3314	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3315	{
3316	rc2 = VINF_EM_RESCHEDULE_REM;
3317	UPDATE_RC();
3318	}
3319	}
3320
3321	/*
3322	* Allocate handy pages.
3323	*/
3324	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
3325	{
3326	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3327	UPDATE_RC();
3328	}
3329
3330	/*
3331	* Debugger Facility request.
3332	*/
3333	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
3334	{
3335	rc2 = DBGFR3VMMForcedAction(pVM);
3336	UPDATE_RC();
3337	}
3338
3339	/*
3340	* Termination request.
3341	*/
3342	if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
3343	{
3344	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3345	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3346	return VINF_EM_TERMINATE;
3347	}
3348
3349	/*
3350	* Out of memory? Since most of our fellow high priority actions may cause us
3351	* to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
3352	* at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
3353	* than us since we can terminate without allocating more memory.
3354	*/
3355	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3356	{
3357	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3358	UPDATE_RC();
3359	if (rc == VINF_EM_NO_MEMORY)
3360	return rc;
3361	}
3362
3363	#ifdef DEBUG
3364	/*
3365	* Debug, pause the VM.
3366	*/
3367	if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
3368	{
3369	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3370	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3371	return VINF_EM_SUSPEND;
3372	}
3373
3374	#endif
3375	/* check that we got them all */
3376	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)));
3377	}
3378
3379	#undef UPDATE_RC
3380	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
3381	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3382	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3383	return rc;
3384	}
3385
3386
3387	/**
3388	* Execute VM.
3389	*
3390	* This function is the main loop of the VM. The emulation thread
3391	* calls this function when the VM has been successfully constructed
3392	* and we're ready for executing the VM.
3393	*
3394	* Returning from this function means that the VM is turned off or
3395	* suspended (state already saved) and deconstruction in next in line.
3396	*
3397	* All interaction from other thread are done using forced actions
3398	* and signaling of the wait object.
3399	*
3400	* @returns VBox status code, informational status codes may indicate failure.
3401	* @param pVM The VM to operate on.
3402	* @param idCpu VMCPU id.
3403	*/
3404	VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, RTCPUID idCpu)
3405	{
3406	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3407	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3408	VM_ASSERT_EMT(pVM);
3409	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3410
3411	VMMR3Lock(pVM);
3412
3413	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3414	if (rc == 0)
3415	{
3416	/*
3417	* Start the virtual time.
3418	*/
3419	rc = TMVirtualResume(pVM);
3420	Assert(rc == VINF_SUCCESS);
3421	rc = TMCpuTickResume(pVM);
3422	Assert(rc == VINF_SUCCESS);
3423
3424	/*
3425	* The Outer Main Loop.
3426	*/
3427	bool fFFDone = false;
3428
3429	/* Reschedule right away to start in the right state. */
3430	rc = VINF_SUCCESS;
3431	pVM->em.s.enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3432
3433	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3434	for (;;)
3435	{
3436	/*
3437	* Before we can schedule anything (we're here because
3438	* scheduling is required) we must service any pending
3439	* forced actions to avoid any pending action causing
3440	* immediate rescheduling upon entering an inner loop
3441	*
3442	* Do forced actions.
3443	*/
3444	if ( !fFFDone
3445	&& rc != VINF_EM_TERMINATE
3446	&& rc != VINF_EM_OFF
3447	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3448	{
3449	rc = emR3ForcedActions(pVM, rc);
3450	if ( ( rc == VINF_EM_RESCHEDULE_REM
3451	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3452	&& pVM->em.s.fForceRAW)
3453	rc = VINF_EM_RESCHEDULE_RAW;
3454	}
3455	else if (fFFDone)
3456	fFFDone = false;
3457
3458	/*
3459	* Now what to do?
3460	*/
3461	Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
3462	switch (rc)
3463	{
3464	/*
3465	* Keep doing what we're currently doing.
3466	*/
3467	case VINF_SUCCESS:
3468	break;
3469
3470	/*
3471	* Reschedule - to raw-mode execution.
3472	*/
3473	case VINF_EM_RESCHEDULE_RAW:
3474	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3475	pVM->em.s.enmState = EMSTATE_RAW;
3476	break;
3477
3478	/*
3479	* Reschedule - to hardware accelerated raw-mode execution.
3480	*/
3481	case VINF_EM_RESCHEDULE_HWACC:
3482	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3483	Assert(!pVM->em.s.fForceRAW);
3484	pVM->em.s.enmState = EMSTATE_HWACC;
3485	break;
3486
3487	/*
3488	* Reschedule - to recompiled execution.
3489	*/
3490	case VINF_EM_RESCHEDULE_REM:
3491	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3492	pVM->em.s.enmState = EMSTATE_REM;
3493	break;
3494
3495	#ifdef VBOX_WITH_VMI
3496	/*
3497	* Reschedule - parav call.
3498	*/
3499	case VINF_EM_RESCHEDULE_PARAV:
3500	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVM->em.s.enmState, EMSTATE_PARAV));
3501	pVM->em.s.enmState = EMSTATE_PARAV;
3502	break;
3503	#endif
3504
3505	/*
3506	* Resume.
3507	*/
3508	case VINF_EM_RESUME:
3509	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3510	/* fall through and get scheduled. */
3511
3512	/*
3513	* Reschedule.
3514	*/
3515	case VINF_EM_RESCHEDULE:
3516	{
3517	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3518	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3519	pVM->em.s.enmState = enmState;
3520	break;
3521	}
3522
3523	/*
3524	* Halted.
3525	*/
3526	case VINF_EM_HALT:
3527	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3528	pVM->em.s.enmState = EMSTATE_HALTED;
3529	break;
3530
3531	/*
3532	* Suspend.
3533	*/
3534	case VINF_EM_SUSPEND:
3535	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3536	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3537	break;
3538
3539	/*
3540	* Reset.
3541	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3542	*/
3543	case VINF_EM_RESET:
3544	{
3545	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3546	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3547	pVM->em.s.enmState = enmState;
3548	break;
3549	}
3550
3551	/*
3552	* Power Off.
3553	*/
3554	case VINF_EM_OFF:
3555	pVM->em.s.enmState = EMSTATE_TERMINATING;
3556	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3557	TMVirtualPause(pVM);
3558	TMCpuTickPause(pVM);
3559	VMMR3Unlock(pVM);
3560	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3561	return rc;
3562
3563	/*
3564	* Terminate the VM.
3565	*/
3566	case VINF_EM_TERMINATE:
3567	pVM->em.s.enmState = EMSTATE_TERMINATING;
3568	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3569	TMVirtualPause(pVM);
3570	TMCpuTickPause(pVM);
3571	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3572	return rc;
3573
3574
3575	/*
3576	* Out of memory, suspend the VM and stuff.
3577	*/
3578	case VINF_EM_NO_MEMORY:
3579	Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3580	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3581	TMVirtualPause(pVM);
3582	TMCpuTickPause(pVM);
3583	VMMR3Unlock(pVM);
3584	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3585
3586	rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
3587	N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
3588	if (rc != VINF_EM_SUSPEND)
3589	{
3590	if (RT_SUCCESS_NP(rc))
3591	{
3592	AssertLogRelMsgFailed(("%Rrc\n", rc));
3593	rc = VERR_EM_INTERNAL_ERROR;
3594	}
3595	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3596	}
3597	return rc;
3598
3599	/*
3600	* Guest debug events.
3601	*/
3602	case VINF_EM_DBG_STEPPED:
3603	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3604	case VINF_EM_DBG_STOP:
3605	case VINF_EM_DBG_BREAKPOINT:
3606	case VINF_EM_DBG_STEP:
3607	if (pVM->em.s.enmState == EMSTATE_RAW)
3608	{
3609	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3610	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3611	}
3612	else
3613	{
3614	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3615	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3616	}
3617	break;
3618
3619	/*
3620	* Hypervisor debug events.
3621	*/
3622	case VINF_EM_DBG_HYPER_STEPPED:
3623	case VINF_EM_DBG_HYPER_BREAKPOINT:
3624	case VINF_EM_DBG_HYPER_ASSERTION:
3625	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3626	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3627	break;
3628
3629	/*
3630	* Guru mediations.
3631	*/
3632	case VERR_VMM_RING0_ASSERTION:
3633	Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVM->em.s.enmState, EMSTATE_GURU_MEDITATION));
3634	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3635	break;
3636
3637	/*
3638	* Any error code showing up here other than the ones we
3639	* know and process above are considered to be FATAL.
3640	*
3641	* Unknown warnings and informational status codes are also
3642	* included in this.
3643	*/
3644	default:
3645	if (RT_SUCCESS_NP(rc))
3646	{
3647	AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
3648	rc = VERR_EM_INTERNAL_ERROR;
3649	}
3650	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3651	Log(("EMR3ExecuteVM returns %d\n", rc));
3652	break;
3653	}
3654
3655
3656	/*
3657	* Any waiters can now be woken up
3658	*/
3659	VMMR3Unlock(pVM);
3660	VMMR3Lock(pVM);
3661
3662	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3663	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3664
3665	/*
3666	* Act on the state.
3667	*/
3668	switch (pVM->em.s.enmState)
3669	{
3670	/*
3671	* Execute raw.
3672	*/
3673	case EMSTATE_RAW:
3674	rc = emR3RawExecute(pVM, &fFFDone);
3675	break;
3676
3677	/*
3678	* Execute hardware accelerated raw.
3679	*/
3680	case EMSTATE_HWACC:
3681	rc = emR3HwAccExecute(pVM, idCpu, &fFFDone);
3682	break;
3683
3684	/*
3685	* Execute recompiled.
3686	*/
3687	case EMSTATE_REM:
3688	rc = emR3RemExecute(pVM, &fFFDone);
3689	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
3690	break;
3691
3692	#ifdef VBOX_WITH_VMI
3693	/*
3694	* Execute PARAV function.
3695	*/
3696	case EMSTATE_PARAV:
3697	rc = PARAVCallFunction(pVM);
3698	pVM->em.s.enmState = EMSTATE_REM;
3699	break;
3700	#endif
3701
3702	/*
3703	* hlt - execution halted until interrupt.
3704	*/
3705	case EMSTATE_HALTED:
3706	{
3707	STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3708	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3709	STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3710	break;
3711	}
3712
3713	/*
3714	* Suspended - return to VM.cpp.
3715	*/
3716	case EMSTATE_SUSPENDED:
3717	TMVirtualPause(pVM);
3718	TMCpuTickPause(pVM);
3719	VMMR3Unlock(pVM);
3720	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3721	return VINF_EM_SUSPEND;
3722
3723	/*
3724	* Debugging in the guest.
3725	*/
3726	case EMSTATE_DEBUG_GUEST_REM:
3727	case EMSTATE_DEBUG_GUEST_RAW:
3728	TMVirtualPause(pVM);
3729	TMCpuTickPause(pVM);
3730	rc = emR3Debug(pVM, rc);
3731	TMVirtualResume(pVM);
3732	TMCpuTickResume(pVM);
3733	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVM->em.s.enmState));
3734	break;
3735
3736	/*
3737	* Debugging in the hypervisor.
3738	*/
3739	case EMSTATE_DEBUG_HYPER:
3740	{
3741	TMVirtualPause(pVM);
3742	TMCpuTickPause(pVM);
3743	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3744
3745	rc = emR3Debug(pVM, rc);
3746	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVM->em.s.enmState));
3747	if (rc != VINF_SUCCESS)
3748	{
3749	/* switch to guru meditation mode */
3750	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3751	VMMR3FatalDump(pVM, rc);
3752	return rc;
3753	}
3754
3755	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3756	TMVirtualResume(pVM);
3757	TMCpuTickResume(pVM);
3758	break;
3759	}
3760
3761	/*
3762	* Guru meditation takes place in the debugger.
3763	*/
3764	case EMSTATE_GURU_MEDITATION:
3765	{
3766	TMVirtualPause(pVM);
3767	TMCpuTickPause(pVM);
3768	VMMR3FatalDump(pVM, rc);
3769	emR3Debug(pVM, rc);
3770	VMMR3Unlock(pVM);
3771	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3772	return rc;
3773	}
3774
3775	/*
3776	* The states we don't expect here.
3777	*/
3778	case EMSTATE_NONE:
3779	case EMSTATE_TERMINATING:
3780	default:
3781	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3782	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3783	TMVirtualPause(pVM);
3784	TMCpuTickPause(pVM);
3785	VMMR3Unlock(pVM);
3786	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3787	return VERR_EM_INTERNAL_ERROR;
3788	}
3789	} /* The Outer Main Loop */
3790	}
3791	else
3792	{
3793	/*
3794	* Fatal error.
3795	*/
3796	LogFlow(("EMR3ExecuteVM: returns %Rrc (longjmp / fatal error)\n", rc));
3797	TMVirtualPause(pVM);
3798	TMCpuTickPause(pVM);
3799	VMMR3FatalDump(pVM, rc);
3800	emR3Debug(pVM, rc);
3801	VMMR3Unlock(pVM);
3802	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3803	/** @todo change the VM state! */
3804	return rc;
3805	}
3806
3807	/* (won't ever get here). */
3808	AssertFailed();
3809	}
3810

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 18709

Download in other formats: