EM.cpp@ 18790

Last change on this file since 18790 was 18770, checked in by vboxsync, 16 years ago
Fake rdpmc instead of causing an invalid opcode exception.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 158.8 KB

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1	/* $Id: EM.cpp 18770 2009-04-06 15:00:15Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_em EM - The Execution Monitor / Manager
23	*
24	* The Execution Monitor/Manager is responsible for running the VM, scheduling
25	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26	* Interpreted), and keeping the CPU states in sync. The function
27	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29	* emR3RemExecute).
30	*
31	* The interpreted execution is only used to avoid switching between
32	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33	* The interpretation is thus implemented as part of EM.
34	*
35	* @see grp_em
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_EM
42	#include <VBox/em.h>
43	#include <VBox/vmm.h>
44	#ifdef VBOX_WITH_VMI
45	# include <VBox/parav.h>
46	#endif
47	#include <VBox/patm.h>
48	#include <VBox/csam.h>
49	#include <VBox/selm.h>
50	#include <VBox/trpm.h>
51	#include <VBox/iom.h>
52	#include <VBox/dbgf.h>
53	#include <VBox/pgm.h>
54	#include <VBox/rem.h>
55	#include <VBox/tm.h>
56	#include <VBox/mm.h>
57	#include <VBox/ssm.h>
58	#include <VBox/pdmapi.h>
59	#include <VBox/pdmcritsect.h>
60	#include <VBox/pdmqueue.h>
61	#include <VBox/hwaccm.h>
62	#include <VBox/patm.h>
63	#include "EMInternal.h"
64	#include <VBox/vm.h>
65	#include <VBox/cpumdis.h>
66	#include <VBox/dis.h>
67	#include <VBox/disopcode.h>
68	#include <VBox/dbgf.h>
69
70	#include <VBox/log.h>
71	#include <iprt/thread.h>
72	#include <iprt/assert.h>
73	#include <iprt/asm.h>
74	#include <iprt/semaphore.h>
75	#include <iprt/string.h>
76	#include <iprt/avl.h>
77	#include <iprt/stream.h>
78	#include <VBox/param.h>
79	#include <VBox/err.h>
80
81
82	/*******************************************************************************
83	* Defined Constants And Macros *
84	*******************************************************************************/
85	#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
86	#define EM_NOTIFY_HWACCM
87	#endif
88
89
90	/*******************************************************************************
91	* Internal Functions *
92	*******************************************************************************/
93	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
94	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
95	static int emR3Debug(PVM pVM, int rc);
96	static int emR3RemStep(PVM pVM);
97	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
98	static int emR3RawResumeHyper(PVM pVM);
99	static int emR3RawStep(PVM pVM);
100	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
101	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
102	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
103	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
104	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
105	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
106	static int emR3ForcedActions(PVM pVM, int rc);
107	static int emR3RawGuestTrap(PVM pVM);
108	static int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret);
109	static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations);
110	static EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx);
111
112	/**
113	* Initializes the EM.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	VMMR3DECL(int) EMR3Init(PVM pVM)
119	{
120	LogFlow(("EMR3Init\n"));
121	/*
122	* Assert alignment and sizes.
123	*/
124	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
125	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
126	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
127	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
128
129	/*
130	* Init the structure.
131	*/
132	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
133	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
134	if (RT_FAILURE(rc))
135	pVM->fRawR3Enabled = true;
136	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
137	if (RT_FAILURE(rc))
138	pVM->fRawR0Enabled = true;
139	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
140	pVM->em.s.enmState = EMSTATE_NONE;
141	pVM->em.s.fForceRAW = false;
142
143	pVM->em.s.pCtx = CPUMQueryGuestCtxPtr(pVM);
144	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
145	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
146
147	/*
148	* Saved state.
149	*/
150	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
151	NULL, emR3Save, NULL,
152	NULL, emR3Load, NULL);
153	if (RT_FAILURE(rc))
154	return rc;
155
156	/*
157	* Statistics.
158	*/
159	#ifdef VBOX_WITH_STATISTICS
160	PEMSTATS pStats;
161	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
162	if (RT_FAILURE(rc))
163	return rc;
164	pVM->em.s.pStatsR3 = pStats;
165	pVM->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
166	pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
167
168	STAM_REG(pVM, &pStats->StatRZEmulate, STAMTYPE_PROFILE, "/EM/RZ/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
169	STAM_REG(pVM, &pStats->StatR3Emulate, STAMTYPE_PROFILE, "/EM/R3/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
170
171	STAM_REG(pVM, &pStats->StatRZInterpretSucceeded, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
172	STAM_REG(pVM, &pStats->StatR3InterpretSucceeded, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
173
174	STAM_REG_USED(pVM, &pStats->StatRZAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatR3And, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatRZAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatR3Add, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatRZAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatR3Adc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatRZSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatR3Sub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatRZCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatR3CpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatRZDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatR3Dec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatRZHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatR3Hlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatRZInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatR3Inc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatRZInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatR3InvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatRZIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatR3Iret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatRZLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatR3LLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
196	STAM_REG_USED(pVM, &pStats->StatRZLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
197	STAM_REG_USED(pVM, &pStats->StatR3LIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatRZLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatR3LGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatRZMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatR3Mov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatRZMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatR3MovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
204	STAM_REG_USED(pVM, &pStats->StatRZMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
205	STAM_REG_USED(pVM, &pStats->StatR3MovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
206	STAM_REG_USED(pVM, &pStats->StatRZOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
207	STAM_REG_USED(pVM, &pStats->StatR3Or, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
208	STAM_REG_USED(pVM, &pStats->StatRZPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatR3Pop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatRZRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatR3Rdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatRZRdpmc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdpmc", STAMUNIT_OCCURENCES, "The number of times RDPMC was successfully interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatR3Rdpmc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdpmc", STAMUNIT_OCCURENCES, "The number of times RDPMC was successfully interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatRZSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatR3Sti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatRZXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatR3Xchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatRZXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatR3Xor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatRZMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatR3Monitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatRZMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatR3MWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatRZBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatR3Btr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatRZBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatR3Bts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatRZBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatR3Btc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatRZCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatR3CmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatRZCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatR3CmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatRZXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatR3XAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatR3Rdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
237	STAM_REG_USED(pVM, &pStats->StatRZRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
238	STAM_REG_USED(pVM, &pStats->StatR3Wrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
239	STAM_REG_USED(pVM, &pStats->StatRZWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatR3StosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatRZStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatRZWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatR3WbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatRZLmsw, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was successfully interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatR3Lmsw, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was successfully interpreted.");
246
247	STAM_REG(pVM, &pStats->StatRZInterpretFailed, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
248	STAM_REG(pVM, &pStats->StatR3InterpretFailed, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
249
250	STAM_REG_USED(pVM, &pStats->StatRZFailedAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatR3FailedAnd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatRZFailedCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatR3FailedCpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatRZFailedDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatR3FailedDec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatRZFailedHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatR3FailedHlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatRZFailedInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatR3FailedInc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatRZFailedInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
261	STAM_REG_USED(pVM, &pStats->StatR3FailedInvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
262	STAM_REG_USED(pVM, &pStats->StatRZFailedIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
263	STAM_REG_USED(pVM, &pStats->StatR3FailedIret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
264	STAM_REG_USED(pVM, &pStats->StatRZFailedLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
265	STAM_REG_USED(pVM, &pStats->StatR3FailedLLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
266	STAM_REG_USED(pVM, &pStats->StatRZFailedLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
267	STAM_REG_USED(pVM, &pStats->StatR3FailedLIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
268	STAM_REG_USED(pVM, &pStats->StatRZFailedLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
269	STAM_REG_USED(pVM, &pStats->StatR3FailedLGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
270	STAM_REG_USED(pVM, &pStats->StatRZFailedMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
271	STAM_REG_USED(pVM, &pStats->StatR3FailedMov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
272	STAM_REG_USED(pVM, &pStats->StatRZFailedMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
273	STAM_REG_USED(pVM, &pStats->StatR3FailedMovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
274	STAM_REG_USED(pVM, &pStats->StatRZFailedMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
275	STAM_REG_USED(pVM, &pStats->StatR3FailedMovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
276	STAM_REG_USED(pVM, &pStats->StatRZFailedOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
277	STAM_REG_USED(pVM, &pStats->StatR3FailedOr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
278	STAM_REG_USED(pVM, &pStats->StatRZFailedPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
279	STAM_REG_USED(pVM, &pStats->StatR3FailedPop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
280	STAM_REG_USED(pVM, &pStats->StatRZFailedSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
281	STAM_REG_USED(pVM, &pStats->StatR3FailedSti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
282	STAM_REG_USED(pVM, &pStats->StatRZFailedXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
283	STAM_REG_USED(pVM, &pStats->StatR3FailedXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
284	STAM_REG_USED(pVM, &pStats->StatRZFailedXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
285	STAM_REG_USED(pVM, &pStats->StatR3FailedXor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
286	STAM_REG_USED(pVM, &pStats->StatRZFailedMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
287	STAM_REG_USED(pVM, &pStats->StatR3FailedMonitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
288	STAM_REG_USED(pVM, &pStats->StatRZFailedMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
289	STAM_REG_USED(pVM, &pStats->StatR3FailedMWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
290	STAM_REG_USED(pVM, &pStats->StatRZFailedRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
291	STAM_REG_USED(pVM, &pStats->StatR3FailedRdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
292	STAM_REG_USED(pVM, &pStats->StatRZFailedRdpmc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdpmc", STAMUNIT_OCCURENCES, "The number of times RDPMC was not interpreted.");
293	STAM_REG_USED(pVM, &pStats->StatR3FailedRdpmc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdpmc", STAMUNIT_OCCURENCES, "The number of times RDPMC was not interpreted.");
294	STAM_REG_USED(pVM, &pStats->StatRZFailedRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
295	STAM_REG_USED(pVM, &pStats->StatR3FailedRdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
296	STAM_REG_USED(pVM, &pStats->StatRZFailedWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
297	STAM_REG_USED(pVM, &pStats->StatR3FailedWrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
298	STAM_REG_USED(pVM, &pStats->StatRZFailedLmsw, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was not interpreted.");
299	STAM_REG_USED(pVM, &pStats->StatR3FailedLmsw, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was not interpreted.");
300
301	STAM_REG_USED(pVM, &pStats->StatRZFailedMisc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
302	STAM_REG_USED(pVM, &pStats->StatR3FailedMisc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
303	STAM_REG_USED(pVM, &pStats->StatRZFailedAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
304	STAM_REG_USED(pVM, &pStats->StatR3FailedAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
305	STAM_REG_USED(pVM, &pStats->StatRZFailedAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
306	STAM_REG_USED(pVM, &pStats->StatR3FailedAdc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
307	STAM_REG_USED(pVM, &pStats->StatRZFailedBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
308	STAM_REG_USED(pVM, &pStats->StatR3FailedBtr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
309	STAM_REG_USED(pVM, &pStats->StatRZFailedBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
310	STAM_REG_USED(pVM, &pStats->StatR3FailedBts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
311	STAM_REG_USED(pVM, &pStats->StatRZFailedBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
312	STAM_REG_USED(pVM, &pStats->StatR3FailedBtc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
313	STAM_REG_USED(pVM, &pStats->StatRZFailedCli, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
314	STAM_REG_USED(pVM, &pStats->StatR3FailedCli, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
315	STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
316	STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
317	STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
318	STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
319	STAM_REG_USED(pVM, &pStats->StatRZFailedXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
320	STAM_REG_USED(pVM, &pStats->StatR3FailedXAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
321	STAM_REG_USED(pVM, &pStats->StatRZFailedMovNTPS, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
322	STAM_REG_USED(pVM, &pStats->StatR3FailedMovNTPS, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
323	STAM_REG_USED(pVM, &pStats->StatRZFailedStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
324	STAM_REG_USED(pVM, &pStats->StatR3FailedStosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
325	STAM_REG_USED(pVM, &pStats->StatRZFailedSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
326	STAM_REG_USED(pVM, &pStats->StatR3FailedSub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
327	STAM_REG_USED(pVM, &pStats->StatRZFailedWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
328	STAM_REG_USED(pVM, &pStats->StatR3FailedWbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
329
330	STAM_REG_USED(pVM, &pStats->StatRZFailedUserMode, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
331	STAM_REG_USED(pVM, &pStats->StatR3FailedUserMode, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
332	STAM_REG_USED(pVM, &pStats->StatRZFailedPrefix, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
333	STAM_REG_USED(pVM, &pStats->StatR3FailedPrefix, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
334
335	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
336	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
337	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/R3/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
338	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
339	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
340	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
341	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
342	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
343	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
344	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
345	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
346	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
347	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
348	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
349	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
350	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
351	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
352	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/R3/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
353	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
354	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
355	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
356	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
357	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
358	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
359	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
360	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
361
362	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
363	pVM->em.s.pCliStatTree = 0;
364	#endif /* VBOX_WITH_STATISTICS */
365
366	/* these should be considered for release statistics. */
367	STAM_REL_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
368	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
369	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
370	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
371
372	STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
373	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
374	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
375	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
376	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
377	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
378	STAM_REL_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
379	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
380	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
381	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
382	STAM_REL_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
383	STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
384
385
386	return VINF_SUCCESS;
387	}
388
389
390	/**
391	* Initializes the per-VCPU EM.
392	*
393	* @returns VBox status code.
394	* @param pVM The VM to operate on.
395	*/
396	VMMR3DECL(int) EMR3InitCPU(PVM pVM)
397	{
398	LogFlow(("EMR3InitCPU\n"));
399	return VINF_SUCCESS;
400	}
401
402
403	/**
404	* Applies relocations to data and code managed by this
405	* component. This function will be called at init and
406	* whenever the VMM need to relocate it self inside the GC.
407	*
408	* @param pVM The VM.
409	*/
410	VMMR3DECL(void) EMR3Relocate(PVM pVM)
411	{
412	LogFlow(("EMR3Relocate\n"));
413	if (pVM->em.s.pStatsR3)
414	pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVM->em.s.pStatsR3);
415	}
416
417
418	/**
419	* Reset notification.
420	*
421	* @param pVM
422	*/
423	VMMR3DECL(void) EMR3Reset(PVM pVM)
424	{
425	LogFlow(("EMR3Reset: \n"));
426	pVM->em.s.fForceRAW = false;
427	}
428
429
430	/**
431	* Terminates the EM.
432	*
433	* Termination means cleaning up and freeing all resources,
434	* the VM it self is at this point powered off or suspended.
435	*
436	* @returns VBox status code.
437	* @param pVM The VM to operate on.
438	*/
439	VMMR3DECL(int) EMR3Term(PVM pVM)
440	{
441	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
442
443	return VINF_SUCCESS;
444	}
445
446	/**
447	* Terminates the per-VCPU EM.
448	*
449	* Termination means cleaning up and freeing all resources,
450	* the VM it self is at this point powered off or suspended.
451	*
452	* @returns VBox status code.
453	* @param pVM The VM to operate on.
454	*/
455	VMMR3DECL(int) EMR3TermCPU(PVM pVM)
456	{
457	return 0;
458	}
459
460	/**
461	* Execute state save operation.
462	*
463	* @returns VBox status code.
464	* @param pVM VM Handle.
465	* @param pSSM SSM operation handle.
466	*/
467	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
468	{
469	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
470	}
471
472
473	/**
474	* Execute state load operation.
475	*
476	* @returns VBox status code.
477	* @param pVM VM Handle.
478	* @param pSSM SSM operation handle.
479	* @param u32Version Data layout version.
480	*/
481	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
482	{
483	/*
484	* Validate version.
485	*/
486	if (u32Version != EM_SAVED_STATE_VERSION)
487	{
488	AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
489	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
490	}
491
492	/*
493	* Load the saved state.
494	*/
495	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
496	if (RT_FAILURE(rc))
497	pVM->em.s.fForceRAW = false;
498
499	Assert(!pVM->em.s.pCliStatTree);
500	return rc;
501	}
502
503
504	/**
505	* Enables or disables a set of raw-mode execution modes.
506	*
507	* @returns VINF_SUCCESS on success.
508	* @returns VINF_RESCHEDULE if a rescheduling might be required.
509	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
510	*
511	* @param pVM The VM to operate on.
512	* @param enmMode The execution mode change.
513	* @thread The emulation thread.
514	*/
515	VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
516	{
517	switch (enmMode)
518	{
519	case EMRAW_NONE:
520	pVM->fRawR3Enabled = false;
521	pVM->fRawR0Enabled = false;
522	break;
523	case EMRAW_RING3_ENABLE:
524	pVM->fRawR3Enabled = true;
525	break;
526	case EMRAW_RING3_DISABLE:
527	pVM->fRawR3Enabled = false;
528	break;
529	case EMRAW_RING0_ENABLE:
530	pVM->fRawR0Enabled = true;
531	break;
532	case EMRAW_RING0_DISABLE:
533	pVM->fRawR0Enabled = false;
534	break;
535	default:
536	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
537	return VERR_INVALID_PARAMETER;
538	}
539	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
540	pVM->fRawR3Enabled, pVM->fRawR0Enabled));
541	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
542	}
543
544
545	/**
546	* Raise a fatal error.
547	*
548	* Safely terminate the VM with full state report and stuff. This function
549	* will naturally never return.
550	*
551	* @param pVM VM handle.
552	* @param rc VBox status code.
553	*/
554	VMMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
555	{
556	longjmp(pVM->em.s.u.FatalLongJump, rc);
557	AssertReleaseMsgFailed(("longjmp returned!\n"));
558	}
559
560
561	/**
562	* Gets the EM state name.
563	*
564	* @returns pointer to read only state name,
565	* @param enmState The state.
566	*/
567	VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
568	{
569	switch (enmState)
570	{
571	case EMSTATE_NONE: return "EMSTATE_NONE";
572	case EMSTATE_RAW: return "EMSTATE_RAW";
573	case EMSTATE_HWACC: return "EMSTATE_HWACC";
574	case EMSTATE_REM: return "EMSTATE_REM";
575	case EMSTATE_PARAV: return "EMSTATE_PARAV";
576	case EMSTATE_HALTED: return "EMSTATE_HALTED";
577	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
578	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
579	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
580	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
581	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
582	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
583	default: return "Unknown!";
584	}
585	}
586
587
588	#ifdef VBOX_WITH_STATISTICS
589	/**
590	* Just a braindead function to keep track of cli addresses.
591	* @param pVM VM handle.
592	* @param GCPtrInstr The EIP of the cli instruction.
593	*/
594	static void emR3RecordCli(PVM pVM, RTGCPTR GCPtrInstr)
595	{
596	PCLISTAT pRec;
597
598	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)GCPtrInstr);
599	if (!pRec)
600	{
601	/* New cli instruction; insert into the tree. */
602	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
603	Assert(pRec);
604	if (!pRec)
605	return;
606	pRec->Core.Key = (AVLPVKEY)GCPtrInstr;
607
608	char szCliStatName[32];
609	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
610	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
611
612	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
613	Assert(fRc); NOREF(fRc);
614	}
615	STAM_COUNTER_INC(&pRec->Counter);
616	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
617	}
618	#endif /* VBOX_WITH_STATISTICS */
619
620
621	/**
622	* Debug loop.
623	*
624	* @returns VBox status code for EM.
625	* @param pVM VM handle.
626	* @param rc Current EM VBox status code..
627	*/
628	static int emR3Debug(PVM pVM, int rc)
629	{
630	for (;;)
631	{
632	Log(("emR3Debug: rc=%Rrc\n", rc));
633	const int rcLast = rc;
634
635	/*
636	* Debug related RC.
637	*/
638	switch (rc)
639	{
640	/*
641	* Single step an instruction.
642	*/
643	case VINF_EM_DBG_STEP:
644	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
645	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
646	\|\| pVM->em.s.fForceRAW /* paranoia */)
647	rc = emR3RawStep(pVM);
648	else
649	{
650	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
651	rc = emR3RemStep(pVM);
652	}
653	break;
654
655	/*
656	* Simple events: stepped, breakpoint, stop/assertion.
657	*/
658	case VINF_EM_DBG_STEPPED:
659	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
660	break;
661
662	case VINF_EM_DBG_BREAKPOINT:
663	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
664	break;
665
666	case VINF_EM_DBG_STOP:
667	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
668	break;
669
670	case VINF_EM_DBG_HYPER_STEPPED:
671	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
672	break;
673
674	case VINF_EM_DBG_HYPER_BREAKPOINT:
675	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
676	break;
677
678	case VINF_EM_DBG_HYPER_ASSERTION:
679	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
680	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
681	break;
682
683	/*
684	* Guru meditation.
685	*/
686	case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
687	rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
688	break;
689	case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
690	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
691	break;
692
693	default: /** @todo don't use default for guru, but make special errors code! */
694	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
695	break;
696	}
697
698	/*
699	* Process the result.
700	*/
701	do
702	{
703	switch (rc)
704	{
705	/*
706	* Continue the debugging loop.
707	*/
708	case VINF_EM_DBG_STEP:
709	case VINF_EM_DBG_STOP:
710	case VINF_EM_DBG_STEPPED:
711	case VINF_EM_DBG_BREAKPOINT:
712	case VINF_EM_DBG_HYPER_STEPPED:
713	case VINF_EM_DBG_HYPER_BREAKPOINT:
714	case VINF_EM_DBG_HYPER_ASSERTION:
715	break;
716
717	/*
718	* Resuming execution (in some form) has to be done here if we got
719	* a hypervisor debug event.
720	*/
721	case VINF_SUCCESS:
722	case VINF_EM_RESUME:
723	case VINF_EM_SUSPEND:
724	case VINF_EM_RESCHEDULE:
725	case VINF_EM_RESCHEDULE_RAW:
726	case VINF_EM_RESCHEDULE_REM:
727	case VINF_EM_HALT:
728	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
729	{
730	rc = emR3RawResumeHyper(pVM);
731	if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
732	continue;
733	}
734	if (rc == VINF_SUCCESS)
735	rc = VINF_EM_RESCHEDULE;
736	return rc;
737
738	/*
739	* The debugger isn't attached.
740	* We'll simply turn the thing off since that's the easiest thing to do.
741	*/
742	case VERR_DBGF_NOT_ATTACHED:
743	switch (rcLast)
744	{
745	case VINF_EM_DBG_HYPER_STEPPED:
746	case VINF_EM_DBG_HYPER_BREAKPOINT:
747	case VINF_EM_DBG_HYPER_ASSERTION:
748	case VERR_TRPM_PANIC:
749	case VERR_TRPM_DONT_PANIC:
750	case VERR_VMM_RING0_ASSERTION:
751	return rcLast;
752	}
753	return VINF_EM_OFF;
754
755	/*
756	* Status codes terminating the VM in one or another sense.
757	*/
758	case VINF_EM_TERMINATE:
759	case VINF_EM_OFF:
760	case VINF_EM_RESET:
761	case VINF_EM_NO_MEMORY:
762	case VINF_EM_RAW_STALE_SELECTOR:
763	case VINF_EM_RAW_IRET_TRAP:
764	case VERR_TRPM_PANIC:
765	case VERR_TRPM_DONT_PANIC:
766	case VERR_VMM_RING0_ASSERTION:
767	case VERR_INTERNAL_ERROR:
768	case VERR_INTERNAL_ERROR_2:
769	case VERR_INTERNAL_ERROR_3:
770	case VERR_INTERNAL_ERROR_4:
771	case VERR_INTERNAL_ERROR_5:
772	case VERR_IPE_UNEXPECTED_STATUS:
773	case VERR_IPE_UNEXPECTED_INFO_STATUS:
774	case VERR_IPE_UNEXPECTED_ERROR_STATUS:
775	return rc;
776
777	/*
778	* The rest is unexpected, and will keep us here.
779	*/
780	default:
781	AssertMsgFailed(("Unxpected rc %Rrc!\n", rc));
782	break;
783	}
784	} while (false);
785	} /* debug for ever */
786	}
787
788
789	/**
790	* Steps recompiled code.
791	*
792	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
793	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
794	*
795	* @param pVM VM handle.
796	*/
797	static int emR3RemStep(PVM pVM)
798	{
799	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
800
801	/*
802	* Switch to REM, step instruction, switch back.
803	*/
804	int rc = REMR3State(pVM);
805	if (RT_SUCCESS(rc))
806	{
807	rc = REMR3Step(pVM);
808	REMR3StateBack(pVM);
809	}
810	LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
811	return rc;
812	}
813
814
815	/**
816	* Executes recompiled code.
817	*
818	* This function contains the recompiler version of the inner
819	* execution loop (the outer loop being in EMR3ExecuteVM()).
820	*
821	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
822	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
823	*
824	* @param pVM VM handle.
825	* @param pfFFDone Where to store an indicator telling wheter or not
826	* FFs were done before returning.
827	*
828	*/
829	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
830	{
831	#ifdef LOG_ENABLED
832	PCPUMCTX pCtx = pVM->em.s.pCtx;
833	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
834
835	if (pCtx->eflags.Bits.u1VM)
836	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
837	else
838	Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
839	#endif
840	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
841
842	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
843	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
844	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
845	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
846	#endif
847
848	/*
849	* Spin till we get a forced action which returns anything but VINF_SUCCESS
850	* or the REM suggests raw-mode execution.
851	*/
852	*pfFFDone = false;
853	bool fInREMState = false;
854	int rc = VINF_SUCCESS;
855	for (;;)
856	{
857	/*
858	* Update REM state if not already in sync.
859	*/
860	if (!fInREMState)
861	{
862	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
863	rc = REMR3State(pVM);
864	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
865	if (RT_FAILURE(rc))
866	break;
867	fInREMState = true;
868
869	/*
870	* We might have missed the raising of VMREQ, TIMER and some other
871	* imporant FFs while we were busy switching the state. So, check again.
872	*/
873	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
874	{
875	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
876	goto l_REMDoForcedActions;
877	}
878	}
879
880
881	/*
882	* Execute REM.
883	*/
884	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
885	rc = REMR3Run(pVM);
886	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
887
888
889	/*
890	* Deal with high priority post execution FFs before doing anything else.
891	*/
892	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
893	rc = emR3HighPriorityPostForcedActions(pVM, rc);
894
895	/*
896	* Process the returned status code.
897	* (Try keep this short! Call functions!)
898	*/
899	if (rc != VINF_SUCCESS)
900	{
901	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
902	break;
903	if (rc != VINF_REM_INTERRUPED_FF)
904	{
905	/*
906	* Anything which is not known to us means an internal error
907	* and the termination of the VM!
908	*/
909	AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
910	break;
911	}
912	}
913
914
915	/*
916	* Check and execute forced actions.
917	* Sync back the VM state before calling any of these.
918	*/
919	#ifdef VBOX_HIGH_RES_TIMERS_HACK
920	TMTimerPoll(pVM);
921	#endif
922	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
923	{
924	l_REMDoForcedActions:
925	if (fInREMState)
926	{
927	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
928	REMR3StateBack(pVM);
929	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
930	fInREMState = false;
931	}
932	STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
933	rc = emR3ForcedActions(pVM, rc);
934	STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
935	if ( rc != VINF_SUCCESS
936	&& rc != VINF_EM_RESCHEDULE_REM)
937	{
938	*pfFFDone = true;
939	break;
940	}
941	}
942
943	} /* The Inner Loop, recompiled execution mode version. */
944
945
946	/*
947	* Returning. Sync back the VM state if required.
948	*/
949	if (fInREMState)
950	{
951	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
952	REMR3StateBack(pVM);
953	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
954	}
955
956	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
957	return rc;
958	}
959
960
961	/**
962	* Resumes executing hypervisor after a debug event.
963	*
964	* This is kind of special since our current guest state is
965	* potentially out of sync.
966	*
967	* @returns VBox status code.
968	* @param pVM The VM handle.
969	*/
970	static int emR3RawResumeHyper(PVM pVM)
971	{
972	int rc;
973	PCPUMCTX pCtx = pVM->em.s.pCtx;
974	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
975	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
976
977	/*
978	* Resume execution.
979	*/
980	CPUMRawEnter(pVM, NULL);
981	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
982	rc = VMMR3ResumeHyper(pVM);
983	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
984	rc = CPUMRawLeave(pVM, NULL, rc);
985	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
986
987	/*
988	* Deal with the return code.
989	*/
990	rc = emR3HighPriorityPostForcedActions(pVM, rc);
991	rc = emR3RawHandleRC(pVM, pCtx, rc);
992	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
993	return rc;
994	}
995
996
997	/**
998	* Steps rawmode.
999	*
1000	* @returns VBox status code.
1001	* @param pVM The VM handle.
1002	*/
1003	static int emR3RawStep(PVM pVM)
1004	{
1005	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
1006	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
1007	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
1008	int rc;
1009	PCPUMCTX pCtx = pVM->em.s.pCtx;
1010	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
1011	#ifndef DEBUG_sandervl
1012	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
1013	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
1014	#endif
1015	if (fGuest)
1016	{
1017	/*
1018	* Check vital forced actions, but ignore pending interrupts and timers.
1019	*/
1020	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1021	{
1022	rc = emR3RawForcedActions(pVM, pCtx);
1023	if (rc != VINF_SUCCESS)
1024	return rc;
1025	}
1026
1027	/*
1028	* Set flags for single stepping.
1029	*/
1030	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1031	}
1032	else
1033	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1034
1035	/*
1036	* Single step.
1037	* We do not start time or anything, if anything we should just do a few nanoseconds.
1038	*/
1039	CPUMRawEnter(pVM, NULL);
1040	do
1041	{
1042	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
1043	rc = VMMR3ResumeHyper(pVM);
1044	else
1045	rc = VMMR3RawRunGC(pVM);
1046	#ifndef DEBUG_sandervl
1047	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
1048	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
1049	#endif
1050	} while ( rc == VINF_SUCCESS
1051	\|\| rc == VINF_EM_RAW_INTERRUPT);
1052	rc = CPUMRawLeave(pVM, NULL, rc);
1053	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1054
1055	/*
1056	* Make sure the trap flag is cleared.
1057	* (Too bad if the guest is trying to single step too.)
1058	*/
1059	if (fGuest)
1060	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1061	else
1062	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
1063
1064	/*
1065	* Deal with the return codes.
1066	*/
1067	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1068	rc = emR3RawHandleRC(pVM, pCtx, rc);
1069	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1070	return rc;
1071	}
1072
1073
1074	#ifdef DEBUG
1075
1076	/**
1077	* Steps hardware accelerated mode.
1078	*
1079	* @returns VBox status code.
1080	* @param pVM The VM handle.
1081	* @param idCpu VMCPU id.
1082	*/
1083	static int emR3HwAccStep(PVM pVM, RTCPUID idCpu)
1084	{
1085	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1086
1087	int rc;
1088	PCPUMCTX pCtx = pVM->em.s.pCtx;
1089	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
1090
1091	/*
1092	* Check vital forced actions, but ignore pending interrupts and timers.
1093	*/
1094	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1095	{
1096	rc = emR3RawForcedActions(pVM, pCtx);
1097	if (rc != VINF_SUCCESS)
1098	return rc;
1099	}
1100	/*
1101	* Set flags for single stepping.
1102	*/
1103	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1104
1105	/*
1106	* Single step.
1107	* We do not start time or anything, if anything we should just do a few nanoseconds.
1108	*/
1109	do
1110	{
1111	rc = VMMR3HwAccRunGC(pVM, idCpu);
1112	} while ( rc == VINF_SUCCESS
1113	\|\| rc == VINF_EM_RAW_INTERRUPT);
1114	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1115
1116	/*
1117	* Make sure the trap flag is cleared.
1118	* (Too bad if the guest is trying to single step too.)
1119	*/
1120	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1121
1122	/*
1123	* Deal with the return codes.
1124	*/
1125	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1126	rc = emR3RawHandleRC(pVM, pCtx, rc);
1127	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1128	return rc;
1129	}
1130
1131
1132	int emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1133	{
1134	int rc = VINF_SUCCESS;
1135	EMSTATE enmOldState = pVM->em.s.enmState;
1136	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1137
1138	Log(("Single step BEGIN:\n"));
1139	for (uint32_t i = 0; i < cIterations; i++)
1140	{
1141	DBGFR3PrgStep(pVM);
1142	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1143	rc = emR3RawStep(pVM);
1144	if (rc != VINF_SUCCESS)
1145	break;
1146	}
1147	Log(("Single step END: rc=%Rrc\n", rc));
1148	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1149	pVM->em.s.enmState = enmOldState;
1150	return rc;
1151	}
1152
1153
1154	static int emR3SingleStepExecHwAcc(PVM pVM, RTCPUID idCpu, uint32_t cIterations)
1155	{
1156	int rc = VINF_SUCCESS;
1157	EMSTATE enmOldState = pVM->em.s.enmState;
1158	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1159
1160	Log(("Single step BEGIN:\n"));
1161	for (uint32_t i = 0; i < cIterations; i++)
1162	{
1163	DBGFR3PrgStep(pVM);
1164	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1165	rc = emR3HwAccStep(pVM, idCpu);
1166	if ( rc != VINF_SUCCESS
1167	\|\| !HWACCMR3CanExecuteGuest(pVM, pVM->em.s.pCtx))
1168	break;
1169	}
1170	Log(("Single step END: rc=%Rrc\n", rc));
1171	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1172	pVM->em.s.enmState = enmOldState;
1173	return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
1174	}
1175
1176
1177	static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1178	{
1179	EMSTATE enmOldState = pVM->em.s.enmState;
1180
1181	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1182
1183	Log(("Single step BEGIN:\n"));
1184	for (uint32_t i = 0; i < cIterations; i++)
1185	{
1186	DBGFR3PrgStep(pVM);
1187	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1188	emR3RemStep(pVM);
1189	if (emR3Reschedule(pVM, pVM->em.s.pCtx) != EMSTATE_REM)
1190	break;
1191	}
1192	Log(("Single step END:\n"));
1193	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1194	pVM->em.s.enmState = enmOldState;
1195	return VINF_EM_RESCHEDULE;
1196	}
1197
1198	#endif /* DEBUG */
1199
1200
1201	/**
1202	* Executes one (or perhaps a few more) instruction(s).
1203	*
1204	* @returns VBox status code suitable for EM.
1205	*
1206	* @param pVM VM handle.
1207	* @param rcGC GC return code
1208	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1209	* instruction and prefix the log output with this text.
1210	*/
1211	#ifdef LOG_ENABLED
1212	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1213	#else
1214	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1215	#endif
1216	{
1217	PCPUMCTX pCtx = pVM->em.s.pCtx;
1218	int rc;
1219
1220	/*
1221	*
1222	* The simple solution is to use the recompiler.
1223	* The better solution is to disassemble the current instruction and
1224	* try handle as many as possible without using REM.
1225	*
1226	*/
1227
1228	#ifdef LOG_ENABLED
1229	/*
1230	* Disassemble the instruction if requested.
1231	*/
1232	if (pszPrefix)
1233	{
1234	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1235	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1236	}
1237	#endif /* LOG_ENABLED */
1238
1239	/*
1240	* PATM is making life more interesting.
1241	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1242	* tell PATM there is a trap in this code and have it take the appropriate actions
1243	* to allow us execute the code in REM.
1244	*/
1245	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1246	{
1247	Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
1248
1249	RTGCPTR pNewEip;
1250	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1251	switch (rc)
1252	{
1253	/*
1254	* It's not very useful to emulate a single instruction and then go back to raw
1255	* mode; just execute the whole block until IF is set again.
1256	*/
1257	case VINF_SUCCESS:
1258	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
1259	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1260	pCtx->eip = pNewEip;
1261	Assert(pCtx->eip);
1262
1263	if (pCtx->eflags.Bits.u1IF)
1264	{
1265	/*
1266	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1267	*/
1268	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1269	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1270	}
1271	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1272	{
1273	/* special case: iret, that sets IF, detected a pending irq/event */
1274	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1275	}
1276	return VINF_EM_RESCHEDULE_REM;
1277
1278	/*
1279	* One instruction.
1280	*/
1281	case VINF_PATCH_EMULATE_INSTR:
1282	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1283	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1284	pCtx->eip = pNewEip;
1285	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1286
1287	/*
1288	* The patch was disabled, hand it to the REM.
1289	*/
1290	case VERR_PATCH_DISABLED:
1291	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
1292	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1293	pCtx->eip = pNewEip;
1294	if (pCtx->eflags.Bits.u1IF)
1295	{
1296	/*
1297	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1298	*/
1299	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1300	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1301	}
1302	return VINF_EM_RESCHEDULE_REM;
1303
1304	/* Force continued patch exection; usually due to write monitored stack. */
1305	case VINF_PATCH_CONTINUE:
1306	return VINF_SUCCESS;
1307
1308	default:
1309	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
1310	return VERR_IPE_UNEXPECTED_STATUS;
1311	}
1312	}
1313
1314	#if 0
1315	/* Try our own instruction emulator before falling back to the recompiler. */
1316	DISCPUSTATE Cpu;
1317	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1318	if (RT_SUCCESS(rc))
1319	{
1320	uint32_t size;
1321
1322	switch (Cpu.pCurInstr->opcode)
1323	{
1324	/* @todo we can do more now */
1325	case OP_MOV:
1326	case OP_AND:
1327	case OP_OR:
1328	case OP_XOR:
1329	case OP_POP:
1330	case OP_INC:
1331	case OP_DEC:
1332	case OP_XCHG:
1333	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1334	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1335	if (RT_SUCCESS(rc))
1336	{
1337	pCtx->rip += Cpu.opsize;
1338	#ifdef EM_NOTIFY_HWACCM
1339	if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1340	HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
1341	#endif
1342	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1343	return rc;
1344	}
1345	if (rc != VERR_EM_INTERPRETER)
1346	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
1347	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1348	break;
1349	}
1350	}
1351	#endif /* 0 */
1352	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1353	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
1354	rc = REMR3EmulateInstruction(pVM);
1355	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1356
1357	#ifdef EM_NOTIFY_HWACCM
1358	if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1359	HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
1360	#endif
1361	return rc;
1362	}
1363
1364
1365	/**
1366	* Executes one (or perhaps a few more) instruction(s).
1367	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1368	*
1369	* @returns VBox status code suitable for EM.
1370	* @param pVM VM handle.
1371	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1372	* instruction and prefix the log output with this text.
1373	* @param rcGC GC return code
1374	*/
1375	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1376	{
1377	#ifdef LOG_ENABLED
1378	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1379	#else
1380	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1381	#endif
1382	}
1383
1384	/**
1385	* Executes one (or perhaps a few more) IO instruction(s).
1386	*
1387	* @returns VBox status code suitable for EM.
1388	* @param pVM VM handle.
1389	*/
1390	int emR3RawExecuteIOInstruction(PVM pVM)
1391	{
1392	int rc;
1393	PCPUMCTX pCtx = pVM->em.s.pCtx;
1394
1395	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1396
1397	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1398	* as io instructions tend to come in packages of more than one
1399	*/
1400	DISCPUSTATE Cpu;
1401	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "IO EMU");
1402	if (RT_SUCCESS(rc))
1403	{
1404	rc = VINF_EM_RAW_EMULATE_INSTR;
1405
1406	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1407	{
1408	switch (Cpu.pCurInstr->opcode)
1409	{
1410	case OP_IN:
1411	{
1412	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1413	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1414	break;
1415	}
1416
1417	case OP_OUT:
1418	{
1419	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1420	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1421	break;
1422	}
1423	}
1424	}
1425	else if (Cpu.prefix & PREFIX_REP)
1426	{
1427	switch (Cpu.pCurInstr->opcode)
1428	{
1429	case OP_INSB:
1430	case OP_INSWD:
1431	{
1432	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1433	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1434	break;
1435	}
1436
1437	case OP_OUTSB:
1438	case OP_OUTSWD:
1439	{
1440	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1441	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1442	break;
1443	}
1444	}
1445	}
1446
1447	/*
1448	* Handled the I/O return codes.
1449	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1450	*/
1451	if (IOM_SUCCESS(rc))
1452	{
1453	pCtx->rip += Cpu.opsize;
1454	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1455	return rc;
1456	}
1457
1458	if (rc == VINF_EM_RAW_GUEST_TRAP)
1459	{
1460	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1461	rc = emR3RawGuestTrap(pVM);
1462	return rc;
1463	}
1464	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1465
1466	if (RT_FAILURE(rc))
1467	{
1468	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1469	return rc;
1470	}
1471	AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc=%Rrc\n", rc));
1472	}
1473	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1474	return emR3RawExecuteInstruction(pVM, "IO: ");
1475	}
1476
1477
1478	/**
1479	* Handle a guest context trap.
1480	*
1481	* @returns VBox status code suitable for EM.
1482	* @param pVM VM handle.
1483	*/
1484	static int emR3RawGuestTrap(PVM pVM)
1485	{
1486	PCPUMCTX pCtx = pVM->em.s.pCtx;
1487
1488	/*
1489	* Get the trap info.
1490	*/
1491	uint8_t u8TrapNo;
1492	TRPMEVENT enmType;
1493	RTGCUINT uErrorCode;
1494	RTGCUINTPTR uCR2;
1495	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1496	if (RT_FAILURE(rc))
1497	{
1498	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
1499	return rc;
1500	}
1501
1502	/*
1503	* Traps can be directly forwarded in hardware accelerated mode.
1504	*/
1505	if (HWACCMR3IsActive(pVM))
1506	{
1507	#ifdef LOGGING_ENABLED
1508	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1509	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1510	#endif
1511	return VINF_EM_RESCHEDULE_HWACC;
1512	}
1513
1514	#if 1 /* Experimental: Review, disable if it causes trouble. */
1515	/*
1516	* Handle traps in patch code first.
1517	*
1518	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
1519	* but several traps isn't handled specially by TRPM in RC and we end up here
1520	* instead. One example is #DE.
1521	*/
1522	uint32_t uCpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
1523	if ( uCpl == 0
1524	&& PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1525	{
1526	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
1527	return emR3PatchTrap(pVM, pCtx, rc);
1528	}
1529	#endif
1530
1531	/*
1532	* If the guest gate is marked unpatched, then we will check again if we can patch it.
1533	* (This assumes that we've already tried and failed to dispatch the trap in
1534	* RC for the gates that already has been patched. Which is true for most high
1535	* volume traps, because these are handled specially, but not for odd ones like #DE.)
1536	*/
1537	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
1538	{
1539	CSAMR3CheckGates(pVM, u8TrapNo, 1);
1540	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
1541
1542	/* If it was successful, then we could go back to raw mode. */
1543	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
1544	{
1545	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
1546	rc = EMR3CheckRawForcedActions(pVM);
1547	AssertRCReturn(rc, rc);
1548
1549	TRPMERRORCODE enmError = uErrorCode != ~0U
1550	? TRPM_TRAP_HAS_ERRORCODE
1551	: TRPM_TRAP_NO_ERRORCODE;
1552	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
1553	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1554	{
1555	TRPMResetTrap(pVM);
1556	return VINF_EM_RESCHEDULE_RAW;
1557	}
1558	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
1559	}
1560	}
1561
1562	/*
1563	* Scan kernel code that traps; we might not get another chance.
1564	*/
1565	/** @todo move this up before the dispatching? */
1566	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1567	&& !pCtx->eflags.Bits.u1VM)
1568	{
1569	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1570	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1571	}
1572
1573	/*
1574	* Trap specific handling.
1575	*/
1576	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1577	{
1578	/*
1579	* If MONITOR & MWAIT are supported, then interpret them here.
1580	*/
1581	DISCPUSTATE cpu;
1582	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1583	if ( RT_SUCCESS(rc)
1584	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1585	{
1586	uint32_t u32Dummy, u32Features, u32ExtFeatures;
1587	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1588	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1589	{
1590	rc = TRPMResetTrap(pVM);
1591	AssertRC(rc);
1592
1593	uint32_t opsize;
1594	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
1595	if (RT_SUCCESS(rc))
1596	{
1597	pCtx->rip += cpu.opsize;
1598	#ifdef EM_NOTIFY_HWACCM
1599	if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1600	HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
1601	#endif
1602	return rc;
1603	}
1604	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1605	}
1606	}
1607	}
1608	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1609	{
1610	/*
1611	* Handle I/O bitmap?
1612	*/
1613	/** @todo We're not supposed to be here with a false guest trap concerning
1614	* I/O access. We can easily handle those in RC. */
1615	DISCPUSTATE cpu;
1616	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1617	if ( RT_SUCCESS(rc)
1618	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1619	{
1620	/*
1621	* We should really check the TSS for the IO bitmap, but it's not like this
1622	* lazy approach really makes things worse.
1623	*/
1624	rc = TRPMResetTrap(pVM);
1625	AssertRC(rc);
1626	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1627	}
1628	}
1629
1630	#ifdef LOG_ENABLED
1631	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1632	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1633
1634	/* Get guest page information. */
1635	uint64_t fFlags = 0;
1636	RTGCPHYS GCPhys = 0;
1637	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1638	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1639	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1640	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1641	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1642	#endif
1643
1644	/*
1645	* #PG has CR2.
1646	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1647	*/
1648	if (u8TrapNo == 14 /* #PG */)
1649	pCtx->cr2 = uCR2;
1650
1651	return VINF_EM_RESCHEDULE_REM;
1652	}
1653
1654
1655	/**
1656	* Handle a ring switch trap.
1657	* Need to do statistics and to install patches. The result is going to REM.
1658	*
1659	* @returns VBox status code suitable for EM.
1660	* @param pVM VM handle.
1661	*/
1662	int emR3RawRingSwitch(PVM pVM)
1663	{
1664	int rc;
1665	DISCPUSTATE Cpu;
1666	PCPUMCTX pCtx = pVM->em.s.pCtx;
1667
1668	/*
1669	* sysenter, syscall & callgate
1670	*/
1671	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1672	if (RT_SUCCESS(rc))
1673	{
1674	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1675	{
1676	if (pCtx->SysEnter.cs != 0)
1677	{
1678	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1679	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1680	if (RT_SUCCESS(rc))
1681	{
1682	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1683	return VINF_EM_RESCHEDULE_RAW;
1684	}
1685	}
1686	}
1687
1688	#ifdef VBOX_WITH_STATISTICS
1689	switch (Cpu.pCurInstr->opcode)
1690	{
1691	case OP_SYSENTER:
1692	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysEnter);
1693	break;
1694	case OP_SYSEXIT:
1695	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysExit);
1696	break;
1697	case OP_SYSCALL:
1698	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysCall);
1699	break;
1700	case OP_SYSRET:
1701	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysRet);
1702	break;
1703	}
1704	#endif
1705	}
1706	else
1707	AssertRC(rc);
1708
1709	/* go to the REM to emulate a single instruction */
1710	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1711	}
1712
1713
1714	/**
1715	* Handle a trap (\#PF or \#GP) in patch code
1716	*
1717	* @returns VBox status code suitable for EM.
1718	* @param pVM VM handle.
1719	* @param pCtx CPU context
1720	* @param gcret GC return code
1721	*/
1722	static int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1723	{
1724	uint8_t u8TrapNo;
1725	int rc;
1726	TRPMEVENT enmType;
1727	RTGCUINT uErrorCode;
1728	RTGCUINTPTR uCR2;
1729
1730	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1731
1732	if (gcret == VINF_PATM_PATCH_INT3)
1733	{
1734	u8TrapNo = 3;
1735	uCR2 = 0;
1736	uErrorCode = 0;
1737	}
1738	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
1739	{
1740	/* No active trap in this case. Kind of ugly. */
1741	u8TrapNo = X86_XCPT_GP;
1742	uCR2 = 0;
1743	uErrorCode = 0;
1744	}
1745	else
1746	{
1747	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1748	if (RT_FAILURE(rc))
1749	{
1750	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
1751	return rc;
1752	}
1753	/* Reset the trap as we'll execute the original instruction again. */
1754	TRPMResetTrap(pVM);
1755	}
1756
1757	/*
1758	* Deal with traps inside patch code.
1759	* (This code won't run outside GC.)
1760	*/
1761	if (u8TrapNo != 1)
1762	{
1763	#ifdef LOG_ENABLED
1764	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1765	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1766
1767	DISCPUSTATE Cpu;
1768	int rc;
1769
1770	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1771	if ( RT_SUCCESS(rc)
1772	&& Cpu.pCurInstr->opcode == OP_IRET)
1773	{
1774	uint32_t eip, selCS, uEFlags;
1775
1776	/* Iret crashes are bad as we have already changed the flags on the stack */
1777	rc = PGMPhysSimpleReadGCPtr(pVM, &eip, pCtx->esp, 4);
1778	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1779	rc \|= PGMPhysSimpleReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1780	if (rc == VINF_SUCCESS)
1781	{
1782	if ( (uEFlags & X86_EFL_VM)
1783	\|\| (selCS & X86_SEL_RPL) == 3)
1784	{
1785	uint32_t selSS, esp;
1786
1787	rc \|= PGMPhysSimpleReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1788	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1789
1790	if (uEFlags & X86_EFL_VM)
1791	{
1792	uint32_t selDS, selES, selFS, selGS;
1793	rc = PGMPhysSimpleReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1794	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1795	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1796	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1797	if (rc == VINF_SUCCESS)
1798	{
1799	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1800	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1801	}
1802	}
1803	else
1804	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1805	}
1806	else
1807	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
1808	}
1809	}
1810	#endif /* LOG_ENABLED */
1811	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1812	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1813
1814	RTGCPTR pNewEip;
1815	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1816	switch (rc)
1817	{
1818	/*
1819	* Execute the faulting instruction.
1820	*/
1821	case VINF_SUCCESS:
1822	{
1823	/** @todo execute a whole block */
1824	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
1825	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1826	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1827
1828	pCtx->eip = pNewEip;
1829	AssertRelease(pCtx->eip);
1830
1831	if (pCtx->eflags.Bits.u1IF)
1832	{
1833	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1834	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1835	*/
1836	if ( u8TrapNo == X86_XCPT_GP
1837	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1838	{
1839	/** @todo move to PATMR3HandleTrap */
1840	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
1841	PATMR3RemovePatch(pVM, pCtx->eip);
1842	}
1843
1844	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1845	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
1846
1847	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1848	/* Interrupts are enabled; just go back to the original instruction.
1849	return VINF_SUCCESS; */
1850	}
1851	return VINF_EM_RESCHEDULE_REM;
1852	}
1853
1854	/*
1855	* One instruction.
1856	*/
1857	case VINF_PATCH_EMULATE_INSTR:
1858	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1859	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1860	pCtx->eip = pNewEip;
1861	AssertRelease(pCtx->eip);
1862	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1863
1864	/*
1865	* The patch was disabled, hand it to the REM.
1866	*/
1867	case VERR_PATCH_DISABLED:
1868	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1869	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1870	pCtx->eip = pNewEip;
1871	AssertRelease(pCtx->eip);
1872
1873	if (pCtx->eflags.Bits.u1IF)
1874	{
1875	/*
1876	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1877	*/
1878	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1879	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1880	}
1881	return VINF_EM_RESCHEDULE_REM;
1882
1883	/* Force continued patch exection; usually due to write monitored stack. */
1884	case VINF_PATCH_CONTINUE:
1885	return VINF_SUCCESS;
1886
1887	/*
1888	* Anything else is fatal.
1889	*/
1890	default:
1891	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
1892	return VERR_IPE_UNEXPECTED_STATUS;
1893	}
1894	}
1895	return VINF_SUCCESS;
1896	}
1897
1898
1899	/**
1900	* Handle a privileged instruction.
1901	*
1902	* @returns VBox status code suitable for EM.
1903	* @param pVM VM handle.
1904	*/
1905	int emR3RawPrivileged(PVM pVM)
1906	{
1907	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1908	PCPUMCTX pCtx = pVM->em.s.pCtx;
1909
1910	Assert(!pCtx->eflags.Bits.u1VM);
1911
1912	if (PATMIsEnabled(pVM))
1913	{
1914	/*
1915	* Check if in patch code.
1916	*/
1917	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1918	{
1919	#ifdef LOG_ENABLED
1920	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1921	#endif
1922	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1923	return VERR_EM_RAW_PATCH_CONFLICT;
1924	}
1925	if ( (pCtx->ss & X86_SEL_RPL) == 0
1926	&& !pCtx->eflags.Bits.u1VM
1927	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1928	{
1929	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1930	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1931	if (RT_SUCCESS(rc))
1932	{
1933	#ifdef LOG_ENABLED
1934	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1935	#endif
1936	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1937	return VINF_SUCCESS;
1938	}
1939	}
1940	}
1941
1942	#ifdef LOG_ENABLED
1943	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1944	{
1945	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1946	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1947	}
1948	#endif
1949
1950	/*
1951	* Instruction statistics and logging.
1952	*/
1953	DISCPUSTATE Cpu;
1954	int rc;
1955
1956	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1957	if (RT_SUCCESS(rc))
1958	{
1959	#ifdef VBOX_WITH_STATISTICS
1960	PEMSTATS pStats = pVM->em.s.CTX_SUFF(pStats);
1961	switch (Cpu.pCurInstr->opcode)
1962	{
1963	case OP_INVLPG:
1964	STAM_COUNTER_INC(&pStats->StatInvlpg);
1965	break;
1966	case OP_IRET:
1967	STAM_COUNTER_INC(&pStats->StatIret);
1968	break;
1969	case OP_CLI:
1970	STAM_COUNTER_INC(&pStats->StatCli);
1971	emR3RecordCli(pVM, pCtx->rip);
1972	break;
1973	case OP_STI:
1974	STAM_COUNTER_INC(&pStats->StatSti);
1975	break;
1976	case OP_INSB:
1977	case OP_INSWD:
1978	case OP_IN:
1979	case OP_OUTSB:
1980	case OP_OUTSWD:
1981	case OP_OUT:
1982	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1983	break;
1984
1985	case OP_MOV_CR:
1986	if (Cpu.param1.flags & USE_REG_GEN32)
1987	{
1988	//read
1989	Assert(Cpu.param2.flags & USE_REG_CR);
1990	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1991	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1992	}
1993	else
1994	{
1995	//write
1996	Assert(Cpu.param1.flags & USE_REG_CR);
1997	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1998	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1999	}
2000	break;
2001
2002	case OP_MOV_DR:
2003	STAM_COUNTER_INC(&pStats->StatMovDRx);
2004	break;
2005	case OP_LLDT:
2006	STAM_COUNTER_INC(&pStats->StatMovLldt);
2007	break;
2008	case OP_LIDT:
2009	STAM_COUNTER_INC(&pStats->StatMovLidt);
2010	break;
2011	case OP_LGDT:
2012	STAM_COUNTER_INC(&pStats->StatMovLgdt);
2013	break;
2014	case OP_SYSENTER:
2015	STAM_COUNTER_INC(&pStats->StatSysEnter);
2016	break;
2017	case OP_SYSEXIT:
2018	STAM_COUNTER_INC(&pStats->StatSysExit);
2019	break;
2020	case OP_SYSCALL:
2021	STAM_COUNTER_INC(&pStats->StatSysCall);
2022	break;
2023	case OP_SYSRET:
2024	STAM_COUNTER_INC(&pStats->StatSysRet);
2025	break;
2026	case OP_HLT:
2027	STAM_COUNTER_INC(&pStats->StatHlt);
2028	break;
2029	default:
2030	STAM_COUNTER_INC(&pStats->StatMisc);
2031	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
2032	break;
2033	}
2034	#endif /* VBOX_WITH_STATISTICS */
2035	if ( (pCtx->ss & X86_SEL_RPL) == 0
2036	&& !pCtx->eflags.Bits.u1VM
2037	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
2038	{
2039	uint32_t size;
2040
2041	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
2042	switch (Cpu.pCurInstr->opcode)
2043	{
2044	case OP_CLI:
2045	pCtx->eflags.u32 &= ~X86_EFL_IF;
2046	Assert(Cpu.opsize == 1);
2047	pCtx->rip += Cpu.opsize;
2048	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2049	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
2050
2051	case OP_STI:
2052	pCtx->eflags.u32 \|= X86_EFL_IF;
2053	EMSetInhibitInterruptsPC(pVM, pCtx->rip + Cpu.opsize);
2054	Assert(Cpu.opsize == 1);
2055	pCtx->rip += Cpu.opsize;
2056	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2057	return VINF_SUCCESS;
2058
2059	case OP_HLT:
2060	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
2061	{
2062	PATMTRANSSTATE enmState;
2063	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
2064
2065	if (enmState == PATMTRANS_OVERWRITTEN)
2066	{
2067	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2068	Assert(rc == VERR_PATCH_DISABLED);
2069	/* Conflict detected, patch disabled */
2070	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
2071
2072	enmState = PATMTRANS_SAFE;
2073	}
2074
2075	/* The translation had better be successful. Otherwise we can't recover. */
2076	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
2077	if (enmState != PATMTRANS_OVERWRITTEN)
2078	pCtx->eip = pOrgInstrGC;
2079	}
2080	/* no break; we could just return VINF_EM_HALT here */
2081
2082	case OP_MOV_CR:
2083	case OP_MOV_DR:
2084	#ifdef LOG_ENABLED
2085	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2086	{
2087	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2088	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2089	}
2090	#endif
2091
2092	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2093	if (RT_SUCCESS(rc))
2094	{
2095	pCtx->rip += Cpu.opsize;
2096	#ifdef EM_NOTIFY_HWACCM
2097	if (pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
2098	HWACCMR3NotifyEmulated(VMMGetCpu(pVM));
2099	#endif
2100	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2101
2102	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2103	&& Cpu.param1.flags == USE_REG_CR /* write */
2104	)
2105	{
2106	/* Deal with CR0 updates inside patch code that force
2107	* us to go to the recompiler.
2108	*/
2109	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
2110	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
2111	{
2112	PATMTRANSSTATE enmState;
2113	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
2114
2115	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
2116	if (enmState == PATMTRANS_OVERWRITTEN)
2117	{
2118	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2119	Assert(rc == VERR_PATCH_DISABLED);
2120	/* Conflict detected, patch disabled */
2121	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
2122	enmState = PATMTRANS_SAFE;
2123	}
2124	/* The translation had better be successful. Otherwise we can't recover. */
2125	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
2126	if (enmState != PATMTRANS_OVERWRITTEN)
2127	pCtx->rip = pOrgInstrGC;
2128	}
2129
2130	/* Reschedule is necessary as the execution/paging mode might have changed. */
2131	return VINF_EM_RESCHEDULE;
2132	}
2133	return rc; /* can return VINF_EM_HALT as well. */
2134	}
2135	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
2136	break; /* fall back to the recompiler */
2137	}
2138	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2139	}
2140	}
2141
2142	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2143	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
2144
2145	return emR3RawExecuteInstruction(pVM, "PRIV");
2146	}
2147
2148
2149	/**
2150	* Update the forced rawmode execution modifier.
2151	*
2152	* This function is called when we're returning from the raw-mode loop(s). If we're
2153	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2154	* if not in patch code, the flag will be cleared.
2155	*
2156	* We should never interrupt patch code while it's being executed. Cli patches can
2157	* contain big code blocks, but they are always executed with IF=0. Other patches
2158	* replace single instructions and should be atomic.
2159	*
2160	* @returns Updated rc.
2161	*
2162	* @param pVM The VM handle.
2163	* @param pCtx The guest CPU context.
2164	* @param rc The result code.
2165	*/
2166	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2167	{
2168	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2169	{
2170	/* ignore reschedule attempts. */
2171	switch (rc)
2172	{
2173	case VINF_EM_RESCHEDULE:
2174	case VINF_EM_RESCHEDULE_REM:
2175	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
2176	rc = VINF_SUCCESS;
2177	break;
2178	}
2179	pVM->em.s.fForceRAW = true;
2180	}
2181	else
2182	pVM->em.s.fForceRAW = false;
2183	return rc;
2184	}
2185
2186
2187	/**
2188	* Process a subset of the raw-mode return code.
2189	*
2190	* Since we have to share this with raw-mode single stepping, this inline
2191	* function has been created to avoid code duplication.
2192	*
2193	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2194	* @returns VBox status code to return to the EM main loop.
2195	*
2196	* @param pVM The VM handle
2197	* @param rc The return code.
2198	* @param pCtx The guest cpu context.
2199	*/
2200	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2201	{
2202	switch (rc)
2203	{
2204	/*
2205	* Common & simple ones.
2206	*/
2207	case VINF_SUCCESS:
2208	break;
2209	case VINF_EM_RESCHEDULE_RAW:
2210	case VINF_EM_RESCHEDULE_HWACC:
2211	case VINF_EM_RAW_INTERRUPT:
2212	case VINF_EM_RAW_TO_R3:
2213	case VINF_EM_RAW_TIMER_PENDING:
2214	case VINF_EM_PENDING_REQUEST:
2215	rc = VINF_SUCCESS;
2216	break;
2217
2218	/*
2219	* Privileged instruction.
2220	*/
2221	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2222	case VINF_PATM_PATCH_TRAP_GP:
2223	rc = emR3RawPrivileged(pVM);
2224	break;
2225
2226	/*
2227	* Got a trap which needs dispatching.
2228	*/
2229	case VINF_EM_RAW_GUEST_TRAP:
2230	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2231	{
2232	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2233	rc = VERR_EM_RAW_PATCH_CONFLICT;
2234	break;
2235	}
2236	rc = emR3RawGuestTrap(pVM);
2237	break;
2238
2239	/*
2240	* Trap in patch code.
2241	*/
2242	case VINF_PATM_PATCH_TRAP_PF:
2243	case VINF_PATM_PATCH_INT3:
2244	rc = emR3PatchTrap(pVM, pCtx, rc);
2245	break;
2246
2247	case VINF_PATM_DUPLICATE_FUNCTION:
2248	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2249	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2250	AssertRC(rc);
2251	rc = VINF_SUCCESS;
2252	break;
2253
2254	case VINF_PATM_CHECK_PATCH_PAGE:
2255	rc = PATMR3HandleMonitoredPage(pVM);
2256	AssertRC(rc);
2257	rc = VINF_SUCCESS;
2258	break;
2259
2260	/*
2261	* Patch manager.
2262	*/
2263	case VERR_EM_RAW_PATCH_CONFLICT:
2264	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
2265	break;
2266
2267	#ifdef VBOX_WITH_VMI
2268	/*
2269	* PARAV function.
2270	*/
2271	case VINF_EM_RESCHEDULE_PARAV:
2272	rc = PARAVCallFunction(pVM);
2273	break;
2274	#endif
2275
2276	/*
2277	* Memory mapped I/O access - attempt to patch the instruction
2278	*/
2279	case VINF_PATM_HC_MMIO_PATCH_READ:
2280	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2281	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2282	if (RT_FAILURE(rc))
2283	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2284	break;
2285
2286	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2287	AssertFailed(); /* not yet implemented. */
2288	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2289	break;
2290
2291	/*
2292	* Conflict or out of page tables.
2293	*
2294	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2295	* do here is to execute the pending forced actions.
2296	*/
2297	case VINF_PGM_SYNC_CR3:
2298	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2299	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2300	rc = VINF_SUCCESS;
2301	break;
2302
2303	/*
2304	* Paging mode change.
2305	*/
2306	case VINF_PGM_CHANGE_MODE:
2307	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2308	if (rc == VINF_SUCCESS)
2309	rc = VINF_EM_RESCHEDULE;
2310	AssertMsg(RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
2311	break;
2312
2313	/*
2314	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2315	*/
2316	case VINF_CSAM_PENDING_ACTION:
2317	rc = VINF_SUCCESS;
2318	break;
2319
2320	/*
2321	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2322	*/
2323	case VINF_EM_RAW_INTERRUPT_PENDING:
2324	case VINF_EM_RAW_RING_SWITCH_INT:
2325	Assert(TRPMHasTrap(pVM));
2326	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2327
2328	if (TRPMHasTrap(pVM))
2329	{
2330	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2331	uint8_t u8Interrupt = TRPMGetTrapNo(pVM);
2332	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2333	{
2334	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2335	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2336	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2337	}
2338	}
2339	rc = VINF_EM_RESCHEDULE_REM;
2340	break;
2341
2342	/*
2343	* Other ring switch types.
2344	*/
2345	case VINF_EM_RAW_RING_SWITCH:
2346	rc = emR3RawRingSwitch(pVM);
2347	break;
2348
2349	/*
2350	* REMGCNotifyInvalidatePage() failed because of overflow.
2351	*/
2352	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2353	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2354	REMR3ReplayInvalidatedPages(pVM);
2355	rc = VINF_SUCCESS;
2356	break;
2357
2358	/*
2359	* I/O Port access - emulate the instruction.
2360	*/
2361	case VINF_IOM_HC_IOPORT_READ:
2362	case VINF_IOM_HC_IOPORT_WRITE:
2363	rc = emR3RawExecuteIOInstruction(pVM);
2364	break;
2365
2366	/*
2367	* Memory mapped I/O access - emulate the instruction.
2368	*/
2369	case VINF_IOM_HC_MMIO_READ:
2370	case VINF_IOM_HC_MMIO_WRITE:
2371	case VINF_IOM_HC_MMIO_READ_WRITE:
2372	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2373	break;
2374
2375	/*
2376	* (MM)IO intensive code block detected; fall back to the recompiler for better performance
2377	*/
2378	case VINF_EM_RAW_EMULATE_IO_BLOCK:
2379	rc =HWACCMR3EmulateIoBlock(pVM, pCtx);
2380	break;
2381
2382	/*
2383	* Execute instruction.
2384	*/
2385	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2386	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2387	break;
2388	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2389	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2390	break;
2391	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2392	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2393	break;
2394	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2395	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2396	break;
2397	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2398	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2399	break;
2400
2401	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2402	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2403	rc = emR3RawPrivileged(pVM);
2404	break;
2405
2406	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2407	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2408	break;
2409
2410	case VINF_EM_RAW_EMULATE_INSTR:
2411	case VINF_PATCH_EMULATE_INSTR:
2412	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2413	break;
2414
2415	/*
2416	* Stale selector and iret traps => REM.
2417	*/
2418	case VINF_EM_RAW_STALE_SELECTOR:
2419	case VINF_EM_RAW_IRET_TRAP:
2420	/* We will not go to the recompiler if EIP points to patch code. */
2421	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2422	{
2423	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2424	}
2425	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
2426	rc = VINF_EM_RESCHEDULE_REM;
2427	break;
2428
2429	/*
2430	* Up a level.
2431	*/
2432	case VINF_EM_TERMINATE:
2433	case VINF_EM_OFF:
2434	case VINF_EM_RESET:
2435	case VINF_EM_SUSPEND:
2436	case VINF_EM_HALT:
2437	case VINF_EM_RESUME:
2438	case VINF_EM_NO_MEMORY:
2439	case VINF_EM_RESCHEDULE:
2440	case VINF_EM_RESCHEDULE_REM:
2441	break;
2442
2443	/*
2444	* Up a level and invoke the debugger.
2445	*/
2446	case VINF_EM_DBG_STEPPED:
2447	case VINF_EM_DBG_BREAKPOINT:
2448	case VINF_EM_DBG_STEP:
2449	case VINF_EM_DBG_HYPER_BREAKPOINT:
2450	case VINF_EM_DBG_HYPER_STEPPED:
2451	case VINF_EM_DBG_HYPER_ASSERTION:
2452	case VINF_EM_DBG_STOP:
2453	break;
2454
2455	/*
2456	* Up a level, dump and debug.
2457	*/
2458	case VERR_TRPM_DONT_PANIC:
2459	case VERR_TRPM_PANIC:
2460	case VERR_VMM_RING0_ASSERTION:
2461	break;
2462
2463	/*
2464	* Up a level, after HwAccM have done some release logging.
2465	*/
2466	case VERR_VMX_INVALID_VMCS_FIELD:
2467	case VERR_VMX_INVALID_VMCS_PTR:
2468	case VERR_VMX_INVALID_VMXON_PTR:
2469	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2470	case VERR_VMX_UNEXPECTED_EXCEPTION:
2471	case VERR_VMX_UNEXPECTED_EXIT_CODE:
2472	case VERR_VMX_INVALID_GUEST_STATE:
2473	case VERR_VMX_UNABLE_TO_START_VM:
2474	case VERR_VMX_UNABLE_TO_RESUME_VM:
2475	HWACCMR3CheckError(pVM, rc);
2476	break;
2477	/*
2478	* Anything which is not known to us means an internal error
2479	* and the termination of the VM!
2480	*/
2481	default:
2482	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
2483	break;
2484	}
2485	return rc;
2486	}
2487
2488
2489	/**
2490	* Check for pending raw actions
2491	*
2492	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
2493	* EM statuses.
2494	* @param pVM The VM to operate on.
2495	*/
2496	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2497	{
2498	return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2499	}
2500
2501
2502	/**
2503	* Process raw-mode specific forced actions.
2504	*
2505	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2506	*
2507	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
2508	* EM statuses.
2509	* @param pVM The VM handle.
2510	* @param pCtx The guest CPUM register context.
2511	*/
2512	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2513	{
2514	/*
2515	* Note that the order is vitally important!
2516	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2517	*/
2518
2519
2520	/*
2521	* Sync selector tables.
2522	*/
2523	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2524	{
2525	int rc = SELMR3UpdateFromCPUM(pVM);
2526	if (RT_FAILURE(rc))
2527	return rc;
2528	}
2529
2530	/*
2531	* Sync IDT.
2532	*/
2533	if (VM_FF_ISPENDING(pVM, VM_FF_TRPM_SYNC_IDT))
2534	{
2535	int rc = TRPMR3SyncIDT(pVM);
2536	if (RT_FAILURE(rc))
2537	return rc;
2538	}
2539
2540	/*
2541	* Sync TSS.
2542	*/
2543	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS))
2544	{
2545	int rc = SELMR3SyncTSS(pVM);
2546	if (RT_FAILURE(rc))
2547	return rc;
2548	}
2549
2550	/*
2551	* Sync page directory.
2552	*/
2553	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2554	{
2555	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2556	if (RT_FAILURE(rc))
2557	return rc;
2558
2559	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2560
2561	/* Prefetch pages for EIP and ESP */
2562	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2563	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2564	if (rc == VINF_SUCCESS)
2565	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2566	if (rc != VINF_SUCCESS)
2567	{
2568	if (rc != VINF_PGM_SYNC_CR3)
2569	{
2570	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
2571	return rc;
2572	}
2573	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2574	if (RT_FAILURE(rc))
2575	return rc;
2576	}
2577	/** @todo maybe prefetch the supervisor stack page as well */
2578	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2579	}
2580
2581	/*
2582	* Allocate handy pages (just in case the above actions have consumed some pages).
2583	*/
2584	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
2585	{
2586	int rc = PGMR3PhysAllocateHandyPages(pVM);
2587	if (RT_FAILURE(rc))
2588	return rc;
2589	}
2590
2591	/*
2592	* Check whether we're out of memory now.
2593	*
2594	* This may stem from some of the above actions or operations that has been executed
2595	* since we ran FFs. The allocate handy pages must for instance always be followed by
2596	* this check.
2597	*/
2598	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2599	return VINF_EM_NO_MEMORY;
2600
2601	return VINF_SUCCESS;
2602	}
2603
2604
2605	/**
2606	* Executes raw code.
2607	*
2608	* This function contains the raw-mode version of the inner
2609	* execution loop (the outer loop being in EMR3ExecuteVM()).
2610	*
2611	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2612	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2613	*
2614	* @param pVM VM handle.
2615	* @param pfFFDone Where to store an indicator telling whether or not
2616	* FFs were done before returning.
2617	*/
2618	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2619	{
2620	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2621
2622	int rc = VERR_INTERNAL_ERROR;
2623	PCPUMCTX pCtx = pVM->em.s.pCtx;
2624	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2625	pVM->em.s.fForceRAW = false;
2626	*pfFFDone = false;
2627
2628
2629	/*
2630	*
2631	* Spin till we get a forced action or raw mode status code resulting in
2632	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2633	*
2634	*/
2635	for (;;)
2636	{
2637	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2638
2639	/*
2640	* Check various preconditions.
2641	*/
2642	#ifdef VBOX_STRICT
2643	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2644	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2645	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2646	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2647	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2648	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2649	&& PGMMapHasConflicts(pVM))
2650	{
2651	PGMMapCheck(pVM);
2652	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2653	return VERR_INTERNAL_ERROR;
2654	}
2655	#endif /* VBOX_STRICT */
2656
2657	/*
2658	* Process high priority pre-execution raw-mode FFs.
2659	*/
2660	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2661	{
2662	rc = emR3RawForcedActions(pVM, pCtx);
2663	if (rc != VINF_SUCCESS)
2664	break;
2665	}
2666
2667	/*
2668	* If we're going to execute ring-0 code, the guest state needs to
2669	* be modified a bit and some of the state components (IF, SS/CS RPL,
2670	* and perhaps EIP) needs to be stored with PATM.
2671	*/
2672	rc = CPUMRawEnter(pVM, NULL);
2673	if (rc != VINF_SUCCESS)
2674	{
2675	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2676	break;
2677	}
2678
2679	/*
2680	* Scan code before executing it. Don't bother with user mode or V86 code
2681	*/
2682	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2683	&& !pCtx->eflags.Bits.u1VM
2684	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2685	{
2686	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2687	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2688	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2689	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2690	{
2691	rc = emR3RawForcedActions(pVM, pCtx);
2692	if (rc != VINF_SUCCESS)
2693	break;
2694	}
2695	}
2696
2697	#ifdef LOG_ENABLED
2698	/*
2699	* Log important stuff before entering GC.
2700	*/
2701	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2702	if (pCtx->eflags.Bits.u1VM)
2703	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2704	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2705	{
2706	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2707	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2708	}
2709	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2710	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2711	#endif /* LOG_ENABLED */
2712
2713
2714
2715	/*
2716	* Execute the code.
2717	*/
2718	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2719	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2720	VMMR3Unlock(pVM);
2721	rc = VMMR3RawRunGC(pVM);
2722	VMMR3Lock(pVM);
2723	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2724	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2725
2726	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2727	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
2728
2729
2730
2731	/*
2732	* Restore the real CPU state and deal with high priority post
2733	* execution FFs before doing anything else.
2734	*/
2735	rc = CPUMRawLeave(pVM, NULL, rc);
2736	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2737	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2738	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2739
2740	#ifdef VBOX_STRICT
2741	/*
2742	* Assert TSS consistency & rc vs patch code.
2743	*/
2744	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2745	&& EMIsRawRing0Enabled(pVM))
2746	SELMR3CheckTSS(pVM);
2747	switch (rc)
2748	{
2749	case VINF_SUCCESS:
2750	case VINF_EM_RAW_INTERRUPT:
2751	case VINF_PATM_PATCH_TRAP_PF:
2752	case VINF_PATM_PATCH_TRAP_GP:
2753	case VINF_PATM_PATCH_INT3:
2754	case VINF_PATM_CHECK_PATCH_PAGE:
2755	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2756	case VINF_EM_RAW_GUEST_TRAP:
2757	case VINF_EM_RESCHEDULE_RAW:
2758	break;
2759
2760	default:
2761	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2762	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVM), rc));
2763	break;
2764	}
2765	/*
2766	* Let's go paranoid!
2767	*/
2768	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2769	&& PGMMapHasConflicts(pVM))
2770	{
2771	PGMMapCheck(pVM);
2772	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
2773	return VERR_INTERNAL_ERROR;
2774	}
2775	#endif /* VBOX_STRICT */
2776
2777	/*
2778	* Process the returned status code.
2779	*/
2780	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2781	{
2782	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2783	break;
2784	}
2785	rc = emR3RawHandleRC(pVM, pCtx, rc);
2786	if (rc != VINF_SUCCESS)
2787	{
2788	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2789	if (rc != VINF_SUCCESS)
2790	{
2791	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2792	break;
2793	}
2794	}
2795
2796	/*
2797	* Check and execute forced actions.
2798	*/
2799	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2800	TMTimerPoll(pVM);
2801	#endif
2802	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2803	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY))
2804	{
2805	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2806
2807	STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2808	rc = emR3ForcedActions(pVM, rc);
2809	STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2810	if ( rc != VINF_SUCCESS
2811	&& rc != VINF_EM_RESCHEDULE_RAW)
2812	{
2813	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2814	if (rc != VINF_SUCCESS)
2815	{
2816	*pfFFDone = true;
2817	break;
2818	}
2819	}
2820	}
2821	}
2822
2823	/*
2824	* Return to outer loop.
2825	*/
2826	#if defined(LOG_ENABLED) && defined(DEBUG)
2827	RTLogFlush(NULL);
2828	#endif
2829	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2830	return rc;
2831	}
2832
2833
2834	/**
2835	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2836	*
2837	* This function contains the raw-mode version of the inner
2838	* execution loop (the outer loop being in EMR3ExecuteVM()).
2839	*
2840	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2841	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2842	*
2843	* @param pVM VM handle.
2844	* @param idCpu VMCPU id.
2845	* @param pfFFDone Where to store an indicator telling whether or not
2846	* FFs were done before returning.
2847	*/
2848	static int emR3HwAccExecute(PVM pVM, RTCPUID idCpu, bool *pfFFDone)
2849	{
2850	int rc = VERR_INTERNAL_ERROR;
2851	PCPUMCTX pCtx = pVM->em.s.pCtx;
2852
2853	LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
2854	*pfFFDone = false;
2855
2856	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2857
2858	#ifdef EM_NOTIFY_HWACCM
2859	HWACCMR3NotifyScheduled(&pVM->aCpus[idCpu]);
2860	#endif
2861
2862	/*
2863	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2864	*/
2865	for (;;)
2866	{
2867	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2868
2869	/*
2870	* Process high priority pre-execution raw-mode FFs.
2871	*/
2872	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
2873	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2874	{
2875	rc = emR3RawForcedActions(pVM, pCtx);
2876	if (rc != VINF_SUCCESS)
2877	break;
2878	}
2879
2880	#ifdef LOG_ENABLED
2881	/*
2882	* Log important stuff before entering GC.
2883	*/
2884	if (TRPMHasTrap(pVM))
2885	Log(("Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", TRPMGetTrapNo(pVM), pCtx->cs, (RTGCPTR)pCtx->rip));
2886
2887	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2888	if (pCtx->eflags.Bits.u1VM)
2889	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2890	else if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
2891	Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2892	else
2893	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2894	#endif /* LOG_ENABLED */
2895
2896	/*
2897	* Execute the code.
2898	*/
2899	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2900	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2901	VMMR3Unlock(pVM);
2902	rc = VMMR3HwAccRunGC(pVM, idCpu);
2903	VMMR3Lock(pVM);
2904	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2905
2906	/*
2907	* Deal with high priority post execution FFs before doing anything else.
2908	*/
2909	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2910	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2911	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2912
2913	/*
2914	* Process the returned status code.
2915	*/
2916	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2917	break;
2918
2919	rc = emR3RawHandleRC(pVM, pCtx, rc);
2920	if (rc != VINF_SUCCESS)
2921	break;
2922
2923	/*
2924	* Check and execute forced actions.
2925	*/
2926	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2927	TMTimerPoll(pVM);
2928	#endif
2929	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2930	{
2931	rc = emR3ForcedActions(pVM, rc);
2932	if ( rc != VINF_SUCCESS
2933	&& rc != VINF_EM_RESCHEDULE_HWACC)
2934	{
2935	*pfFFDone = true;
2936	break;
2937	}
2938	}
2939	}
2940
2941	/*
2942	* Return to outer loop.
2943	*/
2944	#if defined(LOG_ENABLED) && defined(DEBUG)
2945	RTLogFlush(NULL);
2946	#endif
2947	return rc;
2948	}
2949
2950
2951	/**
2952	* Decides whether to execute RAW, HWACC or REM.
2953	*
2954	* @returns new EM state
2955	* @param pVM The VM.
2956	* @param pCtx The CPU context.
2957	*/
2958	static EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2959	{
2960	/*
2961	* When forcing raw-mode execution, things are simple.
2962	*/
2963	if (pVM->em.s.fForceRAW)
2964	return EMSTATE_RAW;
2965
2966	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2967	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2968	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2969
2970	X86EFLAGS EFlags = pCtx->eflags;
2971	if (HWACCMIsEnabled(pVM))
2972	{
2973	/* Hardware accelerated raw-mode:
2974	*
2975	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2976	*/
2977	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2978	return EMSTATE_HWACC;
2979
2980	/* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
2981	* off monitoring features essential for raw mode! */
2982	return EMSTATE_REM;
2983	}
2984
2985	/*
2986	* Standard raw-mode:
2987	*
2988	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2989	* or 32 bits protected mode ring 0 code
2990	*
2991	* The tests are ordered by the likelyhood of being true during normal execution.
2992	*/
2993	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2994	{
2995	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2996	return EMSTATE_REM;
2997	}
2998
2999	#ifndef VBOX_RAW_V86
3000	if (EFlags.u32 & X86_EFL_VM) {
3001	Log2(("raw mode refused: VM_MASK\n"));
3002	return EMSTATE_REM;
3003	}
3004	#endif
3005
3006	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
3007	uint32_t u32CR0 = pCtx->cr0;
3008	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
3009	{
3010	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
3011	return EMSTATE_REM;
3012	}
3013
3014	if (pCtx->cr4 & X86_CR4_PAE)
3015	{
3016	uint32_t u32Dummy, u32Features;
3017
3018	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3019	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3020	return EMSTATE_REM;
3021	}
3022
3023	unsigned uSS = pCtx->ss;
3024	if ( pCtx->eflags.Bits.u1VM
3025	\|\| (uSS & X86_SEL_RPL) == 3)
3026	{
3027	if (!EMIsRawRing3Enabled(pVM))
3028	return EMSTATE_REM;
3029
3030	if (!(EFlags.u32 & X86_EFL_IF))
3031	{
3032	Log2(("raw mode refused: IF (RawR3)\n"));
3033	return EMSTATE_REM;
3034	}
3035
3036	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
3037	{
3038	Log2(("raw mode refused: CR0.WP + RawR0\n"));
3039	return EMSTATE_REM;
3040	}
3041	}
3042	else
3043	{
3044	if (!EMIsRawRing0Enabled(pVM))
3045	return EMSTATE_REM;
3046
3047	/* Only ring 0 supervisor code. */
3048	if ((uSS & X86_SEL_RPL) != 0)
3049	{
3050	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
3051	return EMSTATE_REM;
3052	}
3053
3054	// Let's start with pure 32 bits ring 0 code first
3055	/** @todo What's pure 32-bit mode? flat? */
3056	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
3057	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
3058	{
3059	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
3060	return EMSTATE_REM;
3061	}
3062
3063	/* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
3064	if (!(u32CR0 & X86_CR0_WP))
3065	{
3066	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
3067	return EMSTATE_REM;
3068	}
3069
3070	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
3071	{
3072	Log2(("raw r0 mode forced: patch code\n"));
3073	return EMSTATE_RAW;
3074	}
3075
3076	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
3077	if (!(EFlags.u32 & X86_EFL_IF))
3078	{
3079	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
3080	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
3081	return EMSTATE_REM;
3082	}
3083	#endif
3084
3085	/** @todo still necessary??? */
3086	if (EFlags.Bits.u2IOPL != 0)
3087	{
3088	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
3089	return EMSTATE_REM;
3090	}
3091	}
3092
3093	Assert(PGMPhysIsA20Enabled(pVM));
3094	return EMSTATE_RAW;
3095	}
3096
3097
3098	/**
3099	* Executes all high priority post execution force actions.
3100	*
3101	* @returns rc or a fatal status code.
3102	*
3103	* @param pVM VM handle.
3104	* @param rc The current rc.
3105	*/
3106	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
3107	{
3108	if (VM_FF_ISPENDING(pVM, VM_FF_PDM_CRITSECT))
3109	PDMR3CritSectFF(pVM);
3110
3111	if (VM_FF_ISPENDING(pVM, VM_FF_CSAM_PENDING_ACTION))
3112	CSAMR3DoPendingAction(pVM);
3113
3114	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3115	{
3116	if ( rc > VINF_EM_NO_MEMORY
3117	&& rc <= VINF_EM_LAST)
3118	rc = VINF_EM_NO_MEMORY;
3119	}
3120
3121	return rc;
3122	}
3123
3124
3125	/**
3126	* Executes all pending forced actions.
3127	*
3128	* Forced actions can cause execution delays and execution
3129	* rescheduling. The first we deal with using action priority, so
3130	* that for instance pending timers aren't scheduled and ran until
3131	* right before execution. The rescheduling we deal with using
3132	* return codes. The same goes for VM termination, only in that case
3133	* we exit everything.
3134	*
3135	* @returns VBox status code of equal or greater importance/severity than rc.
3136	* The most important ones are: VINF_EM_RESCHEDULE,
3137	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3138	*
3139	* @param pVM VM handle.
3140	* @param rc The current rc.
3141	*
3142	*/
3143	static int emR3ForcedActions(PVM pVM, int rc)
3144	{
3145	STAM_REL_PROFILE_START(&pVM->em.s.StatForcedActions, a);
3146	#ifdef VBOX_STRICT
3147	int rcIrq = VINF_SUCCESS;
3148	#endif
3149	int rc2;
3150	#define UPDATE_RC() \
3151	do { \
3152	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
3153	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
3154	break; \
3155	if (!rc \|\| rc2 < rc) \
3156	rc = rc2; \
3157	} while (0)
3158
3159	/*
3160	* Post execution chunk first.
3161	*/
3162	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
3163	{
3164	/*
3165	* Termination request.
3166	*/
3167	if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
3168	{
3169	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3170	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3171	return VINF_EM_TERMINATE;
3172	}
3173
3174	/*
3175	* Debugger Facility polling.
3176	*/
3177	if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
3178	{
3179	rc2 = DBGFR3VMMForcedAction(pVM);
3180	UPDATE_RC();
3181	}
3182
3183	/*
3184	* Postponed reset request.
3185	*/
3186	if (VM_FF_ISPENDING(pVM, VM_FF_RESET))
3187	{
3188	rc2 = VMR3Reset(pVM);
3189	UPDATE_RC();
3190	VM_FF_CLEAR(pVM, VM_FF_RESET);
3191	}
3192
3193	/*
3194	* CSAM page scanning.
3195	*/
3196	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_CSAM_SCAN_PAGE, VM_FF_PGM_NO_MEMORY))
3197	{
3198	PCPUMCTX pCtx = pVM->em.s.pCtx;
3199
3200	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3201	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3202
3203	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3204	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3205	}
3206
3207	/*
3208	* Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
3209	*/
3210	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3211	{
3212	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3213	UPDATE_RC();
3214	if (rc == VINF_EM_NO_MEMORY)
3215	return rc;
3216	}
3217
3218	/* check that we got them all */
3219	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE \| VM_FF_PGM_NO_MEMORY)));
3220	}
3221
3222	/*
3223	* Normal priority then.
3224	* (Executed in no particular order.)
3225	*/
3226	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
3227	{
3228	/*
3229	* PDM Queues are pending.
3230	*/
3231	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
3232	PDMR3QueueFlushAll(pVM);
3233
3234	/*
3235	* PDM DMA transfers are pending.
3236	*/
3237	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
3238	PDMR3DmaRun(pVM);
3239
3240	/*
3241	* Requests from other threads.
3242	*/
3243	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
3244	{
3245	rc2 = VMR3ReqProcessU(pVM->pUVM, VMREQDEST_ANY);
3246	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3247	{
3248	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
3249	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3250	return rc2;
3251	}
3252	UPDATE_RC();
3253	}
3254
3255	/* Replay the handler notification changes. */
3256	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
3257	REMR3ReplayHandlerNotifications(pVM);
3258
3259	/* check that we got them all */
3260	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY)));
3261	}
3262
3263	/*
3264	* High priority pre execution chunk last.
3265	* (Executed in ascending priority order.)
3266	*/
3267	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3268	{
3269	/*
3270	* Timers before interrupts.
3271	*/
3272	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_TIMER, VM_FF_PGM_NO_MEMORY))
3273	TMR3TimerQueuesDo(pVM);
3274
3275	/*
3276	* The instruction following an emulated STI should always be executed!
3277	*/
3278	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_INHIBIT_INTERRUPTS, VM_FF_PGM_NO_MEMORY))
3279	{
3280	Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3281	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3282	{
3283	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3284	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3285	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3286	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3287	*/
3288	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3289	}
3290	if (HWACCMR3IsActive(pVM))
3291	rc2 = VINF_EM_RESCHEDULE_HWACC;
3292	else
3293	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3294
3295	UPDATE_RC();
3296	}
3297
3298	/*
3299	* Interrupts.
3300	*/
3301	if ( !VM_FF_ISPENDING(pVM, VM_FF_INHIBIT_INTERRUPTS \| VM_FF_PGM_NO_MEMORY)
3302	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_HWACC)
3303	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3304	&& PATMAreInterruptsEnabled(pVM)
3305	&& !HWACCMR3IsEventPending(pVM))
3306	{
3307	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3308	{
3309	/* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3310	/** @todo this really isn't nice, should properly handle this */
3311	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3312	#ifdef VBOX_STRICT
3313	rcIrq = rc2;
3314	#endif
3315	UPDATE_RC();
3316	}
3317	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3318	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3319	{
3320	rc2 = VINF_EM_RESCHEDULE_REM;
3321	UPDATE_RC();
3322	}
3323	}
3324
3325	/*
3326	* Allocate handy pages.
3327	*/
3328	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
3329	{
3330	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3331	UPDATE_RC();
3332	}
3333
3334	/*
3335	* Debugger Facility request.
3336	*/
3337	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
3338	{
3339	rc2 = DBGFR3VMMForcedAction(pVM);
3340	UPDATE_RC();
3341	}
3342
3343	/*
3344	* Termination request.
3345	*/
3346	if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
3347	{
3348	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3349	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3350	return VINF_EM_TERMINATE;
3351	}
3352
3353	/*
3354	* Out of memory? Since most of our fellow high priority actions may cause us
3355	* to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
3356	* at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
3357	* than us since we can terminate without allocating more memory.
3358	*/
3359	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3360	{
3361	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3362	UPDATE_RC();
3363	if (rc == VINF_EM_NO_MEMORY)
3364	return rc;
3365	}
3366
3367	#ifdef DEBUG
3368	/*
3369	* Debug, pause the VM.
3370	*/
3371	if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
3372	{
3373	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3374	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3375	return VINF_EM_SUSPEND;
3376	}
3377
3378	#endif
3379	/* check that we got them all */
3380	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)));
3381	}
3382
3383	#undef UPDATE_RC
3384	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
3385	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3386	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3387	return rc;
3388	}
3389
3390
3391	/**
3392	* Execute VM.
3393	*
3394	* This function is the main loop of the VM. The emulation thread
3395	* calls this function when the VM has been successfully constructed
3396	* and we're ready for executing the VM.
3397	*
3398	* Returning from this function means that the VM is turned off or
3399	* suspended (state already saved) and deconstruction in next in line.
3400	*
3401	* All interaction from other thread are done using forced actions
3402	* and signaling of the wait object.
3403	*
3404	* @returns VBox status code, informational status codes may indicate failure.
3405	* @param pVM The VM to operate on.
3406	* @param idCpu VMCPU id.
3407	*/
3408	VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, RTCPUID idCpu)
3409	{
3410	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3411	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3412	VM_ASSERT_EMT(pVM);
3413	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3414
3415	VMMR3Lock(pVM);
3416
3417	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3418	if (rc == 0)
3419	{
3420	/*
3421	* Start the virtual time.
3422	*/
3423	rc = TMVirtualResume(pVM);
3424	Assert(rc == VINF_SUCCESS);
3425	rc = TMCpuTickResume(pVM);
3426	Assert(rc == VINF_SUCCESS);
3427
3428	/*
3429	* The Outer Main Loop.
3430	*/
3431	bool fFFDone = false;
3432
3433	/* Reschedule right away to start in the right state. */
3434	rc = VINF_SUCCESS;
3435	pVM->em.s.enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3436
3437	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3438	for (;;)
3439	{
3440	/*
3441	* Before we can schedule anything (we're here because
3442	* scheduling is required) we must service any pending
3443	* forced actions to avoid any pending action causing
3444	* immediate rescheduling upon entering an inner loop
3445	*
3446	* Do forced actions.
3447	*/
3448	if ( !fFFDone
3449	&& rc != VINF_EM_TERMINATE
3450	&& rc != VINF_EM_OFF
3451	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3452	{
3453	rc = emR3ForcedActions(pVM, rc);
3454	if ( ( rc == VINF_EM_RESCHEDULE_REM
3455	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3456	&& pVM->em.s.fForceRAW)
3457	rc = VINF_EM_RESCHEDULE_RAW;
3458	}
3459	else if (fFFDone)
3460	fFFDone = false;
3461
3462	/*
3463	* Now what to do?
3464	*/
3465	Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
3466	switch (rc)
3467	{
3468	/*
3469	* Keep doing what we're currently doing.
3470	*/
3471	case VINF_SUCCESS:
3472	break;
3473
3474	/*
3475	* Reschedule - to raw-mode execution.
3476	*/
3477	case VINF_EM_RESCHEDULE_RAW:
3478	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3479	pVM->em.s.enmState = EMSTATE_RAW;
3480	break;
3481
3482	/*
3483	* Reschedule - to hardware accelerated raw-mode execution.
3484	*/
3485	case VINF_EM_RESCHEDULE_HWACC:
3486	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3487	Assert(!pVM->em.s.fForceRAW);
3488	pVM->em.s.enmState = EMSTATE_HWACC;
3489	break;
3490
3491	/*
3492	* Reschedule - to recompiled execution.
3493	*/
3494	case VINF_EM_RESCHEDULE_REM:
3495	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3496	pVM->em.s.enmState = EMSTATE_REM;
3497	break;
3498
3499	#ifdef VBOX_WITH_VMI
3500	/*
3501	* Reschedule - parav call.
3502	*/
3503	case VINF_EM_RESCHEDULE_PARAV:
3504	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVM->em.s.enmState, EMSTATE_PARAV));
3505	pVM->em.s.enmState = EMSTATE_PARAV;
3506	break;
3507	#endif
3508
3509	/*
3510	* Resume.
3511	*/
3512	case VINF_EM_RESUME:
3513	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3514	/* fall through and get scheduled. */
3515
3516	/*
3517	* Reschedule.
3518	*/
3519	case VINF_EM_RESCHEDULE:
3520	{
3521	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3522	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3523	pVM->em.s.enmState = enmState;
3524	break;
3525	}
3526
3527	/*
3528	* Halted.
3529	*/
3530	case VINF_EM_HALT:
3531	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3532	pVM->em.s.enmState = EMSTATE_HALTED;
3533	break;
3534
3535	/*
3536	* Suspend.
3537	*/
3538	case VINF_EM_SUSPEND:
3539	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3540	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3541	break;
3542
3543	/*
3544	* Reset.
3545	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3546	*/
3547	case VINF_EM_RESET:
3548	{
3549	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3550	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3551	pVM->em.s.enmState = enmState;
3552	break;
3553	}
3554
3555	/*
3556	* Power Off.
3557	*/
3558	case VINF_EM_OFF:
3559	pVM->em.s.enmState = EMSTATE_TERMINATING;
3560	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3561	TMVirtualPause(pVM);
3562	TMCpuTickPause(pVM);
3563	VMMR3Unlock(pVM);
3564	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3565	return rc;
3566
3567	/*
3568	* Terminate the VM.
3569	*/
3570	case VINF_EM_TERMINATE:
3571	pVM->em.s.enmState = EMSTATE_TERMINATING;
3572	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3573	TMVirtualPause(pVM);
3574	TMCpuTickPause(pVM);
3575	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3576	return rc;
3577
3578
3579	/*
3580	* Out of memory, suspend the VM and stuff.
3581	*/
3582	case VINF_EM_NO_MEMORY:
3583	Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3584	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3585	TMVirtualPause(pVM);
3586	TMCpuTickPause(pVM);
3587	VMMR3Unlock(pVM);
3588	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3589
3590	rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
3591	N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
3592	if (rc != VINF_EM_SUSPEND)
3593	{
3594	if (RT_SUCCESS_NP(rc))
3595	{
3596	AssertLogRelMsgFailed(("%Rrc\n", rc));
3597	rc = VERR_EM_INTERNAL_ERROR;
3598	}
3599	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3600	}
3601	return rc;
3602
3603	/*
3604	* Guest debug events.
3605	*/
3606	case VINF_EM_DBG_STEPPED:
3607	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3608	case VINF_EM_DBG_STOP:
3609	case VINF_EM_DBG_BREAKPOINT:
3610	case VINF_EM_DBG_STEP:
3611	if (pVM->em.s.enmState == EMSTATE_RAW)
3612	{
3613	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3614	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3615	}
3616	else
3617	{
3618	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3619	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3620	}
3621	break;
3622
3623	/*
3624	* Hypervisor debug events.
3625	*/
3626	case VINF_EM_DBG_HYPER_STEPPED:
3627	case VINF_EM_DBG_HYPER_BREAKPOINT:
3628	case VINF_EM_DBG_HYPER_ASSERTION:
3629	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3630	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3631	break;
3632
3633	/*
3634	* Guru mediations.
3635	*/
3636	case VERR_VMM_RING0_ASSERTION:
3637	Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVM->em.s.enmState, EMSTATE_GURU_MEDITATION));
3638	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3639	break;
3640
3641	/*
3642	* Any error code showing up here other than the ones we
3643	* know and process above are considered to be FATAL.
3644	*
3645	* Unknown warnings and informational status codes are also
3646	* included in this.
3647	*/
3648	default:
3649	if (RT_SUCCESS_NP(rc))
3650	{
3651	AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
3652	rc = VERR_EM_INTERNAL_ERROR;
3653	}
3654	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3655	Log(("EMR3ExecuteVM returns %d\n", rc));
3656	break;
3657	}
3658
3659
3660	/*
3661	* Any waiters can now be woken up
3662	*/
3663	VMMR3Unlock(pVM);
3664	VMMR3Lock(pVM);
3665
3666	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3667	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3668
3669	/*
3670	* Act on the state.
3671	*/
3672	switch (pVM->em.s.enmState)
3673	{
3674	/*
3675	* Execute raw.
3676	*/
3677	case EMSTATE_RAW:
3678	rc = emR3RawExecute(pVM, &fFFDone);
3679	break;
3680
3681	/*
3682	* Execute hardware accelerated raw.
3683	*/
3684	case EMSTATE_HWACC:
3685	rc = emR3HwAccExecute(pVM, idCpu, &fFFDone);
3686	break;
3687
3688	/*
3689	* Execute recompiled.
3690	*/
3691	case EMSTATE_REM:
3692	rc = emR3RemExecute(pVM, &fFFDone);
3693	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
3694	break;
3695
3696	#ifdef VBOX_WITH_VMI
3697	/*
3698	* Execute PARAV function.
3699	*/
3700	case EMSTATE_PARAV:
3701	rc = PARAVCallFunction(pVM);
3702	pVM->em.s.enmState = EMSTATE_REM;
3703	break;
3704	#endif
3705
3706	/*
3707	* hlt - execution halted until interrupt.
3708	*/
3709	case EMSTATE_HALTED:
3710	{
3711	STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3712	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3713	STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3714	break;
3715	}
3716
3717	/*
3718	* Suspended - return to VM.cpp.
3719	*/
3720	case EMSTATE_SUSPENDED:
3721	TMVirtualPause(pVM);
3722	TMCpuTickPause(pVM);
3723	VMMR3Unlock(pVM);
3724	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3725	return VINF_EM_SUSPEND;
3726
3727	/*
3728	* Debugging in the guest.
3729	*/
3730	case EMSTATE_DEBUG_GUEST_REM:
3731	case EMSTATE_DEBUG_GUEST_RAW:
3732	TMVirtualPause(pVM);
3733	TMCpuTickPause(pVM);
3734	rc = emR3Debug(pVM, rc);
3735	TMVirtualResume(pVM);
3736	TMCpuTickResume(pVM);
3737	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVM->em.s.enmState));
3738	break;
3739
3740	/*
3741	* Debugging in the hypervisor.
3742	*/
3743	case EMSTATE_DEBUG_HYPER:
3744	{
3745	TMVirtualPause(pVM);
3746	TMCpuTickPause(pVM);
3747	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3748
3749	rc = emR3Debug(pVM, rc);
3750	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVM->em.s.enmState));
3751	if (rc != VINF_SUCCESS)
3752	{
3753	/* switch to guru meditation mode */
3754	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3755	VMMR3FatalDump(pVM, rc);
3756	return rc;
3757	}
3758
3759	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3760	TMVirtualResume(pVM);
3761	TMCpuTickResume(pVM);
3762	break;
3763	}
3764
3765	/*
3766	* Guru meditation takes place in the debugger.
3767	*/
3768	case EMSTATE_GURU_MEDITATION:
3769	{
3770	TMVirtualPause(pVM);
3771	TMCpuTickPause(pVM);
3772	VMMR3FatalDump(pVM, rc);
3773	emR3Debug(pVM, rc);
3774	VMMR3Unlock(pVM);
3775	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3776	return rc;
3777	}
3778
3779	/*
3780	* The states we don't expect here.
3781	*/
3782	case EMSTATE_NONE:
3783	case EMSTATE_TERMINATING:
3784	default:
3785	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3786	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3787	TMVirtualPause(pVM);
3788	TMCpuTickPause(pVM);
3789	VMMR3Unlock(pVM);
3790	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3791	return VERR_EM_INTERNAL_ERROR;
3792	}
3793	} /* The Outer Main Loop */
3794	}
3795	else
3796	{
3797	/*
3798	* Fatal error.
3799	*/
3800	LogFlow(("EMR3ExecuteVM: returns %Rrc (longjmp / fatal error)\n", rc));
3801	TMVirtualPause(pVM);
3802	TMCpuTickPause(pVM);
3803	VMMR3FatalDump(pVM, rc);
3804	emR3Debug(pVM, rc);
3805	VMMR3Unlock(pVM);
3806	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3807	/** @todo change the VM state! */
3808	return rc;
3809	}
3810
3811	/* (won't ever get here). */
3812	AssertFailed();
3813	}
3814

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 18790

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