EM.cpp@ 19253

Last change on this file since 19253 was 19241, checked in by vboxsync, 16 years ago
Statistics registration fix for SMP guests
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File size: 159.7 KB

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1	/* $Id: EM.cpp 19241 2009-04-28 13:40:52Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_em EM - The Execution Monitor / Manager
23	*
24	* The Execution Monitor/Manager is responsible for running the VM, scheduling
25	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26	* Interpreted), and keeping the CPU states in sync. The function
27	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29	* emR3RemExecute).
30	*
31	* The interpreted execution is only used to avoid switching between
32	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33	* The interpretation is thus implemented as part of EM.
34	*
35	* @see grp_em
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_EM
42	#include <VBox/em.h>
43	#include <VBox/vmm.h>
44	#ifdef VBOX_WITH_VMI
45	# include <VBox/parav.h>
46	#endif
47	#include <VBox/patm.h>
48	#include <VBox/csam.h>
49	#include <VBox/selm.h>
50	#include <VBox/trpm.h>
51	#include <VBox/iom.h>
52	#include <VBox/dbgf.h>
53	#include <VBox/pgm.h>
54	#include <VBox/rem.h>
55	#include <VBox/tm.h>
56	#include <VBox/mm.h>
57	#include <VBox/ssm.h>
58	#include <VBox/pdmapi.h>
59	#include <VBox/pdmcritsect.h>
60	#include <VBox/pdmqueue.h>
61	#include <VBox/hwaccm.h>
62	#include <VBox/patm.h>
63	#include "EMInternal.h"
64	#include <VBox/vm.h>
65	#include <VBox/cpumdis.h>
66	#include <VBox/dis.h>
67	#include <VBox/disopcode.h>
68	#include <VBox/dbgf.h>
69
70	#include <VBox/log.h>
71	#include <iprt/thread.h>
72	#include <iprt/assert.h>
73	#include <iprt/asm.h>
74	#include <iprt/semaphore.h>
75	#include <iprt/string.h>
76	#include <iprt/avl.h>
77	#include <iprt/stream.h>
78	#include <VBox/param.h>
79	#include <VBox/err.h>
80
81
82	/*******************************************************************************
83	* Defined Constants And Macros *
84	*******************************************************************************/
85	#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
86	#define EM_NOTIFY_HWACCM
87	#endif
88
89
90	/*******************************************************************************
91	* Internal Functions *
92	*******************************************************************************/
93	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
94	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
95	static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
96	static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
97	static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
98	static int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu);
99	static int emR3RawStep(PVM pVM, PVMCPU pVCpu);
100	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
101	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
102	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
103	static int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
104	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
105	static int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
106	static int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
107	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
108	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
109	static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations);
110	static EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
111
112	/**
113	* Initializes the EM.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	VMMR3DECL(int) EMR3Init(PVM pVM)
119	{
120	LogFlow(("EMR3Init\n"));
121	/*
122	* Assert alignment and sizes.
123	*/
124	AssertCompileMemberAlignment(VM, em.s, 32);
125	AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
126	AssertReleaseMsg(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump),
127	("%d bytes, padding %d\n", sizeof(pVM->aCpus[0].em.s.u.FatalLongJump), sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump)));
128
129	/*
130	* Init the structure.
131	*/
132	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
133	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
134	if (RT_FAILURE(rc))
135	pVM->fRawR3Enabled = true;
136	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
137	if (RT_FAILURE(rc))
138	pVM->fRawR0Enabled = true;
139	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
140
141	/*
142	* Saved state.
143	*/
144	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
145	NULL, emR3Save, NULL,
146	NULL, emR3Load, NULL);
147	if (RT_FAILURE(rc))
148	return rc;
149
150	for (unsigned i=0;i<pVM->cCPUs;i++)
151	{
152	PVMCPU pVCpu = &pVM->aCpus[i];
153
154	pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
155
156	pVCpu->em.s.enmState = EMSTATE_NONE;
157	pVCpu->em.s.fForceRAW = false;
158
159	pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
160	pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
161	AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
162
163	# define EM_REG_COUNTER(a, b, c) \
164	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
165	AssertRC(rc);
166
167	# define EM_REG_COUNTER_USED(a, b, c) \
168	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
169	AssertRC(rc);
170
171	# define EM_REG_PROFILE(a, b, c) \
172	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
173	AssertRC(rc);
174
175	# define EM_REG_PROFILE_ADV(a, b, c) \
176	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
177	AssertRC(rc);
178
179	/*
180	* Statistics.
181	*/
182	#ifdef VBOX_WITH_STATISTICS
183	PEMSTATS pStats;
184	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
185	if (RT_FAILURE(rc))
186	return rc;
187
188	pVCpu->em.s.pStatsR3 = pStats;
189	pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
190	pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
191
192	EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
193	EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
194
195	EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
196	EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
197
198	EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
199	EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
200	EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
201	EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
202	EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
203	EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
204	EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
205	EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
206	EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
207	EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
208	EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
209	EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
210	EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
211	EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
212	EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
213	EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
214	EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
215	EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
216	EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
217	EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
218	EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
219	EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
220	EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
221	EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
222	EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
223	EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
224	EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
225	EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
226	EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
227	EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
228	EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
229	EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
230	EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
231	EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
232	EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
233	EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
234	EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
235	EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
236	EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
237	EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
238	EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
239	EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
240	EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
241	EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
242	EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
243	EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
244	EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
245	EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
246	EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
247	EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
248	EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
249	EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
250	EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
251	EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
252	EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
253	EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
254	EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
255	EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
256	EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
257	EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
258	EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
259	EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
260	EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
261	EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
262	EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
263	EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
264	EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
265	EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
266	EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
267	EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
268	EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
269	EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
270
271	EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
272	EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
273
274	EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
275	EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
276	EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
277	EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
278	EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
279	EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
280	EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
281	EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
282	EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
283	EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
284	EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
285	EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
286	EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
287	EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
288	EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
289	EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
290	EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
291	EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
292	EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
293	EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
294	EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
295	EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
296	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
297	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
298	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
299	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
300	EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
301	EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
302	EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
303	EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
304	EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
305	EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
306	EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
307	EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
308	EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
309	EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
310	EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
311	EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
312	EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
313	EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
314	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
315	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
316	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
317	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
318	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
319	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
320	EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
321	EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
322	EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
323	EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
324
325	EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
326	EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
327	EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
328	EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
329	EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
330	EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
331	EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
332	EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
333	EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
334	EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
335	EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
336	EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
337	EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
338	EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
339	EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
340	EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
341	EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
342	EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
343	EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
344	EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
345	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
346	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
347	EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
348	EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
349	EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
350	EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
351	EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
352	EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
353
354	EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
355	EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
356	EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
357	EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
358
359	EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
360	EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
361	EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
362	EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
363	EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
364	EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
365	EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
366	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 read instructions.");
367	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 read instructions.");
368	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 read instructions.");
369	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 read instructions.");
370	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 read instructions.");
371	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 write instructions.");
372	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 write instructions.");
373	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 write instructions.");
374	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 write instructions.");
375	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 write instructions.");
376	EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
377	EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
378	EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
379	EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
380	EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
381	EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
382	EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
383	EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
384	EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
385
386	EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
387	pVCpu->em.s.pCliStatTree = 0;
388
389	/* these should be considered for release statistics. */
390	EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
391	EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
392	EM_REG_COUNTER(&pVCpu->em.s.StatMiscEmu, "/PROF/CPU%d/EM/Emulation/Misc", "Profiling of emR3RawExecuteInstruction.");
393	EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
394	EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
395	EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
396	EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
397	EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
398	EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
399	EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
400	EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
401
402	#endif /* VBOX_WITH_STATISTICS */
403
404	EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
405	EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
406	EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
407	EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
408
409	EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
410	}
411
412	return VINF_SUCCESS;
413	}
414
415
416	/**
417	* Initializes the per-VCPU EM.
418	*
419	* @returns VBox status code.
420	* @param pVM The VM to operate on.
421	*/
422	VMMR3DECL(int) EMR3InitCPU(PVM pVM)
423	{
424	LogFlow(("EMR3InitCPU\n"));
425	return VINF_SUCCESS;
426	}
427
428
429	/**
430	* Applies relocations to data and code managed by this
431	* component. This function will be called at init and
432	* whenever the VMM need to relocate it self inside the GC.
433	*
434	* @param pVM The VM.
435	*/
436	VMMR3DECL(void) EMR3Relocate(PVM pVM)
437	{
438	LogFlow(("EMR3Relocate\n"));
439	for (unsigned i=0;i<pVM->cCPUs;i++)
440	{
441	PVMCPU pVCpu = &pVM->aCpus[i];
442
443	if (pVCpu->em.s.pStatsR3)
444	pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
445	}
446	}
447
448
449	/**
450	* Reset notification.
451	*
452	* @param pVM
453	*/
454	VMMR3DECL(void) EMR3Reset(PVM pVM)
455	{
456	LogFlow(("EMR3Reset: \n"));
457	for (unsigned i=0;i<pVM->cCPUs;i++)
458	{
459	PVMCPU pVCpu = &pVM->aCpus[i];
460
461	pVCpu->em.s.fForceRAW = false;
462	}
463	}
464
465
466	/**
467	* Terminates the EM.
468	*
469	* Termination means cleaning up and freeing all resources,
470	* the VM it self is at this point powered off or suspended.
471	*
472	* @returns VBox status code.
473	* @param pVM The VM to operate on.
474	*/
475	VMMR3DECL(int) EMR3Term(PVM pVM)
476	{
477	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
478	return VINF_SUCCESS;
479	}
480
481	/**
482	* Terminates the per-VCPU EM.
483	*
484	* Termination means cleaning up and freeing all resources,
485	* the VM it self is at this point powered off or suspended.
486	*
487	* @returns VBox status code.
488	* @param pVM The VM to operate on.
489	*/
490	VMMR3DECL(int) EMR3TermCPU(PVM pVM)
491	{
492	return 0;
493	}
494
495	/**
496	* Execute state save operation.
497	*
498	* @returns VBox status code.
499	* @param pVM VM Handle.
500	* @param pSSM SSM operation handle.
501	*/
502	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
503	{
504	for (unsigned i=0;i<pVM->cCPUs;i++)
505	{
506	PVMCPU pVCpu = &pVM->aCpus[i];
507
508	int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
509	AssertRCReturn(rc, rc);
510	}
511	return VINF_SUCCESS;
512	}
513
514
515	/**
516	* Execute state load operation.
517	*
518	* @returns VBox status code.
519	* @param pVM VM Handle.
520	* @param pSSM SSM operation handle.
521	* @param u32Version Data layout version.
522	*/
523	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
524	{
525	int rc = VINF_SUCCESS;
526
527	/*
528	* Validate version.
529	*/
530	if (u32Version != EM_SAVED_STATE_VERSION)
531	{
532	AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
533	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
534	}
535
536	/*
537	* Load the saved state.
538	*/
539	for (unsigned i=0;i<pVM->cCPUs;i++)
540	{
541	PVMCPU pVCpu = &pVM->aCpus[i];
542
543	rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
544	if (RT_FAILURE(rc))
545	pVCpu->em.s.fForceRAW = false;
546
547	Assert(!pVCpu->em.s.pCliStatTree);
548	}
549	return rc;
550	}
551
552
553	/**
554	* Enables or disables a set of raw-mode execution modes.
555	*
556	* @returns VINF_SUCCESS on success.
557	* @returns VINF_RESCHEDULE if a rescheduling might be required.
558	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
559	*
560	* @param pVM The VM to operate on.
561	* @param enmMode The execution mode change.
562	* @thread The emulation thread.
563	*/
564	VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
565	{
566	switch (enmMode)
567	{
568	case EMRAW_NONE:
569	pVM->fRawR3Enabled = false;
570	pVM->fRawR0Enabled = false;
571	break;
572	case EMRAW_RING3_ENABLE:
573	pVM->fRawR3Enabled = true;
574	break;
575	case EMRAW_RING3_DISABLE:
576	pVM->fRawR3Enabled = false;
577	break;
578	case EMRAW_RING0_ENABLE:
579	pVM->fRawR0Enabled = true;
580	break;
581	case EMRAW_RING0_DISABLE:
582	pVM->fRawR0Enabled = false;
583	break;
584	default:
585	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
586	return VERR_INVALID_PARAMETER;
587	}
588	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
589	pVM->fRawR3Enabled, pVM->fRawR0Enabled));
590	return pVM->aCpus[0].em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
591	}
592
593
594	/**
595	* Raise a fatal error.
596	*
597	* Safely terminate the VM with full state report and stuff. This function
598	* will naturally never return.
599	*
600	* @param pVCpu VMCPU handle.
601	* @param rc VBox status code.
602	*/
603	VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
604	{
605	longjmp(pVCpu->em.s.u.FatalLongJump, rc);
606	AssertReleaseMsgFailed(("longjmp returned!\n"));
607	}
608
609
610	/**
611	* Gets the EM state name.
612	*
613	* @returns pointer to read only state name,
614	* @param enmState The state.
615	*/
616	VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
617	{
618	switch (enmState)
619	{
620	case EMSTATE_NONE: return "EMSTATE_NONE";
621	case EMSTATE_RAW: return "EMSTATE_RAW";
622	case EMSTATE_HWACC: return "EMSTATE_HWACC";
623	case EMSTATE_REM: return "EMSTATE_REM";
624	case EMSTATE_PARAV: return "EMSTATE_PARAV";
625	case EMSTATE_HALTED: return "EMSTATE_HALTED";
626	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
627	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
628	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
629	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
630	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
631	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
632	default: return "Unknown!";
633	}
634	}
635
636
637	#ifdef VBOX_WITH_STATISTICS
638	/**
639	* Just a braindead function to keep track of cli addresses.
640	* @param pVM VM handle.
641	* @param pVMCPU VMCPU handle.
642	* @param GCPtrInstr The EIP of the cli instruction.
643	*/
644	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
645	{
646	PCLISTAT pRec;
647
648	pRec = (PCLISTAT)RTAvlPVGet(&pVCpu->em.s.pCliStatTree, (AVLPVKEY)GCPtrInstr);
649	if (!pRec)
650	{
651	/* New cli instruction; insert into the tree. */
652	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
653	Assert(pRec);
654	if (!pRec)
655	return;
656	pRec->Core.Key = (AVLPVKEY)GCPtrInstr;
657
658	char szCliStatName[32];
659	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
660	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
661
662	bool fRc = RTAvlPVInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
663	Assert(fRc); NOREF(fRc);
664	}
665	STAM_COUNTER_INC(&pRec->Counter);
666	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
667	}
668	#endif /* VBOX_WITH_STATISTICS */
669
670
671	/**
672	* Debug loop.
673	*
674	* @returns VBox status code for EM.
675	* @param pVM VM handle.
676	* @param pVCpu VMCPU handle.
677	* @param rc Current EM VBox status code..
678	*/
679	static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
680	{
681	for (;;)
682	{
683	Log(("emR3Debug: rc=%Rrc\n", rc));
684	const int rcLast = rc;
685
686	/*
687	* Debug related RC.
688	*/
689	switch (rc)
690	{
691	/*
692	* Single step an instruction.
693	*/
694	case VINF_EM_DBG_STEP:
695	if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
696	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
697	\|\| pVCpu->em.s.fForceRAW /* paranoia */)
698	rc = emR3RawStep(pVM, pVCpu);
699	else
700	{
701	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
702	rc = emR3RemStep(pVM, pVCpu);
703	}
704	break;
705
706	/*
707	* Simple events: stepped, breakpoint, stop/assertion.
708	*/
709	case VINF_EM_DBG_STEPPED:
710	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
711	break;
712
713	case VINF_EM_DBG_BREAKPOINT:
714	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
715	break;
716
717	case VINF_EM_DBG_STOP:
718	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
719	break;
720
721	case VINF_EM_DBG_HYPER_STEPPED:
722	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
723	break;
724
725	case VINF_EM_DBG_HYPER_BREAKPOINT:
726	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
727	break;
728
729	case VINF_EM_DBG_HYPER_ASSERTION:
730	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
731	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
732	break;
733
734	/*
735	* Guru meditation.
736	*/
737	case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
738	rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
739	break;
740	case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
741	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
742	break;
743
744	default: /** @todo don't use default for guru, but make special errors code! */
745	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
746	break;
747	}
748
749	/*
750	* Process the result.
751	*/
752	do
753	{
754	switch (rc)
755	{
756	/*
757	* Continue the debugging loop.
758	*/
759	case VINF_EM_DBG_STEP:
760	case VINF_EM_DBG_STOP:
761	case VINF_EM_DBG_STEPPED:
762	case VINF_EM_DBG_BREAKPOINT:
763	case VINF_EM_DBG_HYPER_STEPPED:
764	case VINF_EM_DBG_HYPER_BREAKPOINT:
765	case VINF_EM_DBG_HYPER_ASSERTION:
766	break;
767
768	/*
769	* Resuming execution (in some form) has to be done here if we got
770	* a hypervisor debug event.
771	*/
772	case VINF_SUCCESS:
773	case VINF_EM_RESUME:
774	case VINF_EM_SUSPEND:
775	case VINF_EM_RESCHEDULE:
776	case VINF_EM_RESCHEDULE_RAW:
777	case VINF_EM_RESCHEDULE_REM:
778	case VINF_EM_HALT:
779	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
780	{
781	rc = emR3RawResumeHyper(pVM, pVCpu);
782	if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
783	continue;
784	}
785	if (rc == VINF_SUCCESS)
786	rc = VINF_EM_RESCHEDULE;
787	return rc;
788
789	/*
790	* The debugger isn't attached.
791	* We'll simply turn the thing off since that's the easiest thing to do.
792	*/
793	case VERR_DBGF_NOT_ATTACHED:
794	switch (rcLast)
795	{
796	case VINF_EM_DBG_HYPER_STEPPED:
797	case VINF_EM_DBG_HYPER_BREAKPOINT:
798	case VINF_EM_DBG_HYPER_ASSERTION:
799	case VERR_TRPM_PANIC:
800	case VERR_TRPM_DONT_PANIC:
801	case VERR_VMM_RING0_ASSERTION:
802	return rcLast;
803	}
804	return VINF_EM_OFF;
805
806	/*
807	* Status codes terminating the VM in one or another sense.
808	*/
809	case VINF_EM_TERMINATE:
810	case VINF_EM_OFF:
811	case VINF_EM_RESET:
812	case VINF_EM_NO_MEMORY:
813	case VINF_EM_RAW_STALE_SELECTOR:
814	case VINF_EM_RAW_IRET_TRAP:
815	case VERR_TRPM_PANIC:
816	case VERR_TRPM_DONT_PANIC:
817	case VERR_VMM_RING0_ASSERTION:
818	case VERR_INTERNAL_ERROR:
819	case VERR_INTERNAL_ERROR_2:
820	case VERR_INTERNAL_ERROR_3:
821	case VERR_INTERNAL_ERROR_4:
822	case VERR_INTERNAL_ERROR_5:
823	case VERR_IPE_UNEXPECTED_STATUS:
824	case VERR_IPE_UNEXPECTED_INFO_STATUS:
825	case VERR_IPE_UNEXPECTED_ERROR_STATUS:
826	return rc;
827
828	/*
829	* The rest is unexpected, and will keep us here.
830	*/
831	default:
832	AssertMsgFailed(("Unxpected rc %Rrc!\n", rc));
833	break;
834	}
835	} while (false);
836	} /* debug for ever */
837	}
838
839
840	/**
841	* Steps recompiled code.
842	*
843	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
844	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
845	*
846	* @param pVM VM handle.
847	* @param pVCpu VMCPU handle.
848	*/
849	static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
850	{
851	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
852
853	/*
854	* Switch to REM, step instruction, switch back.
855	*/
856	int rc = REMR3State(pVM, pVCpu);
857	if (RT_SUCCESS(rc))
858	{
859	rc = REMR3Step(pVM, pVCpu);
860	REMR3StateBack(pVM, pVCpu);
861	}
862	LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
863	return rc;
864	}
865
866
867	/**
868	* Executes recompiled code.
869	*
870	* This function contains the recompiler version of the inner
871	* execution loop (the outer loop being in EMR3ExecuteVM()).
872	*
873	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
874	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
875	*
876	* @param pVM VM handle.
877	* @param pVCpu VMCPU handle.
878	* @param pfFFDone Where to store an indicator telling wheter or not
879	* FFs were done before returning.
880	*
881	*/
882	static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
883	{
884	#ifdef LOG_ENABLED
885	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
886	uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
887
888	if (pCtx->eflags.Bits.u1VM)
889	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
890	else
891	Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
892	#endif
893	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
894
895	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
896	AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
897	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo #1419 - get flat address. */
898	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
899	#endif
900
901	/*
902	* Spin till we get a forced action which returns anything but VINF_SUCCESS
903	* or the REM suggests raw-mode execution.
904	*/
905	*pfFFDone = false;
906	bool fInREMState = false;
907	int rc = VINF_SUCCESS;
908	for (;;)
909	{
910	/*
911	* Update REM state if not already in sync.
912	*/
913	if (!fInREMState)
914	{
915	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
916	rc = REMR3State(pVM, pVCpu);
917	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
918	if (RT_FAILURE(rc))
919	break;
920	fInREMState = true;
921
922	/*
923	* We might have missed the raising of VMREQ, TIMER and some other
924	* imporant FFs while we were busy switching the state. So, check again.
925	*/
926	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
927	{
928	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
929	goto l_REMDoForcedActions;
930	}
931	}
932
933
934	/*
935	* Execute REM.
936	*/
937	STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
938	rc = REMR3Run(pVM, pVCpu);
939	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
940
941
942	/*
943	* Deal with high priority post execution FFs before doing anything else.
944	*/
945	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
946	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
947	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
948
949	/*
950	* Process the returned status code.
951	* (Try keep this short! Call functions!)
952	*/
953	if (rc != VINF_SUCCESS)
954	{
955	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
956	break;
957	if (rc != VINF_REM_INTERRUPED_FF)
958	{
959	/*
960	* Anything which is not known to us means an internal error
961	* and the termination of the VM!
962	*/
963	AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
964	break;
965	}
966	}
967
968
969	/*
970	* Check and execute forced actions.
971	* Sync back the VM state before calling any of these.
972	*/
973	#ifdef VBOX_HIGH_RES_TIMERS_HACK
974	TMTimerPoll(pVM);
975	#endif
976	if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
977	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE)))
978	{
979	l_REMDoForcedActions:
980	if (fInREMState)
981	{
982	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, d);
983	REMR3StateBack(pVM, pVCpu);
984	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, d);
985	fInREMState = false;
986	}
987	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
988	rc = emR3ForcedActions(pVM, pVCpu, rc);
989	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
990	if ( rc != VINF_SUCCESS
991	&& rc != VINF_EM_RESCHEDULE_REM)
992	{
993	*pfFFDone = true;
994	break;
995	}
996	}
997
998	} /* The Inner Loop, recompiled execution mode version. */
999
1000
1001	/*
1002	* Returning. Sync back the VM state if required.
1003	*/
1004	if (fInREMState)
1005	{
1006	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, e);
1007	REMR3StateBack(pVM, pVCpu);
1008	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, e);
1009	}
1010
1011	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1012	return rc;
1013	}
1014
1015
1016	/**
1017	* Resumes executing hypervisor after a debug event.
1018	*
1019	* This is kind of special since our current guest state is
1020	* potentially out of sync.
1021	*
1022	* @returns VBox status code.
1023	* @param pVM The VM handle.
1024	* @param pVCpu The VMCPU handle.
1025	*/
1026	static int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
1027	{
1028	int rc;
1029	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1030	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
1031	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
1032
1033	/*
1034	* Resume execution.
1035	*/
1036	CPUMRawEnter(pVCpu, NULL);
1037	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
1038	rc = VMMR3ResumeHyper(pVM, pVCpu);
1039	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
1040	rc = CPUMRawLeave(pVCpu, NULL, rc);
1041	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1042
1043	/*
1044	* Deal with the return code.
1045	*/
1046	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1047	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1048	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1049	return rc;
1050	}
1051
1052
1053	/**
1054	* Steps rawmode.
1055	*
1056	* @returns VBox status code.
1057	* @param pVM The VM handle.
1058	* @param pVCpu The VMCPU handle.
1059	*/
1060	static int emR3RawStep(PVM pVM, PVMCPU pVCpu)
1061	{
1062	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
1063	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
1064	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
1065	int rc;
1066	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1067	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
1068	#ifndef DEBUG_sandervl
1069	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
1070	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
1071	#endif
1072	if (fGuest)
1073	{
1074	/*
1075	* Check vital forced actions, but ignore pending interrupts and timers.
1076	*/
1077	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1078	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1079	{
1080	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1081	if (rc != VINF_SUCCESS)
1082	return rc;
1083	}
1084
1085	/*
1086	* Set flags for single stepping.
1087	*/
1088	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
1089	}
1090	else
1091	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
1092
1093	/*
1094	* Single step.
1095	* We do not start time or anything, if anything we should just do a few nanoseconds.
1096	*/
1097	CPUMRawEnter(pVCpu, NULL);
1098	do
1099	{
1100	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
1101	rc = VMMR3ResumeHyper(pVM, pVCpu);
1102	else
1103	rc = VMMR3RawRunGC(pVM, pVCpu);
1104	#ifndef DEBUG_sandervl
1105	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
1106	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
1107	#endif
1108	} while ( rc == VINF_SUCCESS
1109	\|\| rc == VINF_EM_RAW_INTERRUPT);
1110	rc = CPUMRawLeave(pVCpu, NULL, rc);
1111	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1112
1113	/*
1114	* Make sure the trap flag is cleared.
1115	* (Too bad if the guest is trying to single step too.)
1116	*/
1117	if (fGuest)
1118	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1119	else
1120	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
1121
1122	/*
1123	* Deal with the return codes.
1124	*/
1125	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1126	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1127	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1128	return rc;
1129	}
1130
1131
1132	#ifdef DEBUG
1133
1134	/**
1135	* Steps hardware accelerated mode.
1136	*
1137	* @returns VBox status code.
1138	* @param pVM The VM handle.
1139	* @param pVCpu The VMCPU handle.
1140	*/
1141	static int emR3HwAccStep(PVM pVM, PVMCPU pVCpu)
1142	{
1143	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1144
1145	int rc;
1146	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1147	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1148
1149	/*
1150	* Check vital forced actions, but ignore pending interrupts and timers.
1151	*/
1152	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1153	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1154	{
1155	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1156	if (rc != VINF_SUCCESS)
1157	return rc;
1158	}
1159	/*
1160	* Set flags for single stepping.
1161	*/
1162	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
1163
1164	/*
1165	* Single step.
1166	* We do not start time or anything, if anything we should just do a few nanoseconds.
1167	*/
1168	do
1169	{
1170	rc = VMMR3HwAccRunGC(pVM, pVCpu);
1171	} while ( rc == VINF_SUCCESS
1172	\|\| rc == VINF_EM_RAW_INTERRUPT);
1173	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1174
1175	/*
1176	* Make sure the trap flag is cleared.
1177	* (Too bad if the guest is trying to single step too.)
1178	*/
1179	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1180
1181	/*
1182	* Deal with the return codes.
1183	*/
1184	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1185	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1186	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1187	return rc;
1188	}
1189
1190
1191	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1192	{
1193	int rc = VINF_SUCCESS;
1194	EMSTATE enmOldState = pVCpu->em.s.enmState;
1195	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1196
1197	Log(("Single step BEGIN:\n"));
1198	for (uint32_t i = 0; i < cIterations; i++)
1199	{
1200	DBGFR3PrgStep(pVM);
1201	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1202	rc = emR3RawStep(pVM, pVCpu);
1203	if (rc != VINF_SUCCESS)
1204	break;
1205	}
1206	Log(("Single step END: rc=%Rrc\n", rc));
1207	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1208	pVCpu->em.s.enmState = enmOldState;
1209	return rc;
1210	}
1211
1212
1213	static int emR3SingleStepExecHwAcc(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1214	{
1215	int rc = VINF_SUCCESS;
1216	EMSTATE enmOldState = pVCpu->em.s.enmState;
1217	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1218
1219	Log(("Single step BEGIN:\n"));
1220	for (uint32_t i = 0; i < cIterations; i++)
1221	{
1222	DBGFR3PrgStep(pVM);
1223	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1224	rc = emR3HwAccStep(pVM, pVCpu);
1225	if ( rc != VINF_SUCCESS
1226	\|\| !HWACCMR3CanExecuteGuest(pVM, pVCpu->em.s.pCtx))
1227	break;
1228	}
1229	Log(("Single step END: rc=%Rrc\n", rc));
1230	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1231	pVCpu->em.s.enmState = enmOldState;
1232	return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
1233	}
1234
1235
1236	static int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1237	{
1238	EMSTATE enmOldState = pVCpu->em.s.enmState;
1239
1240	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1241
1242	Log(("Single step BEGIN:\n"));
1243	for (uint32_t i = 0; i < cIterations; i++)
1244	{
1245	DBGFR3PrgStep(pVM);
1246	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1247	emR3RemStep(pVM, pVCpu);
1248	if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1249	break;
1250	}
1251	Log(("Single step END:\n"));
1252	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1253	pVCpu->em.s.enmState = enmOldState;
1254	return VINF_EM_RESCHEDULE;
1255	}
1256
1257	#endif /* DEBUG */
1258
1259
1260	/**
1261	* Executes one (or perhaps a few more) instruction(s).
1262	*
1263	* @returns VBox status code suitable for EM.
1264	*
1265	* @param pVM VM handle.
1266	* @param pVCpu VMCPU handle
1267	* @param rcGC GC return code
1268	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1269	* instruction and prefix the log output with this text.
1270	*/
1271	#ifdef LOG_ENABLED
1272	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
1273	#else
1274	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
1275	#endif
1276	{
1277	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1278	int rc;
1279
1280	/*
1281	*
1282	* The simple solution is to use the recompiler.
1283	* The better solution is to disassemble the current instruction and
1284	* try handle as many as possible without using REM.
1285	*
1286	*/
1287
1288	#ifdef LOG_ENABLED
1289	/*
1290	* Disassemble the instruction if requested.
1291	*/
1292	if (pszPrefix)
1293	{
1294	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1295	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1296	}
1297	#endif /* LOG_ENABLED */
1298
1299	/*
1300	* PATM is making life more interesting.
1301	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1302	* tell PATM there is a trap in this code and have it take the appropriate actions
1303	* to allow us execute the code in REM.
1304	*/
1305	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1306	{
1307	Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
1308
1309	RTGCPTR pNewEip;
1310	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1311	switch (rc)
1312	{
1313	/*
1314	* It's not very useful to emulate a single instruction and then go back to raw
1315	* mode; just execute the whole block until IF is set again.
1316	*/
1317	case VINF_SUCCESS:
1318	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
1319	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1320	pCtx->eip = pNewEip;
1321	Assert(pCtx->eip);
1322
1323	if (pCtx->eflags.Bits.u1IF)
1324	{
1325	/*
1326	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1327	*/
1328	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1329	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1330	}
1331	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1332	{
1333	/* special case: iret, that sets IF, detected a pending irq/event */
1334	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET");
1335	}
1336	return VINF_EM_RESCHEDULE_REM;
1337
1338	/*
1339	* One instruction.
1340	*/
1341	case VINF_PATCH_EMULATE_INSTR:
1342	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1343	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1344	pCtx->eip = pNewEip;
1345	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1346
1347	/*
1348	* The patch was disabled, hand it to the REM.
1349	*/
1350	case VERR_PATCH_DISABLED:
1351	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
1352	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1353	pCtx->eip = pNewEip;
1354	if (pCtx->eflags.Bits.u1IF)
1355	{
1356	/*
1357	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1358	*/
1359	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1360	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1361	}
1362	return VINF_EM_RESCHEDULE_REM;
1363
1364	/* Force continued patch exection; usually due to write monitored stack. */
1365	case VINF_PATCH_CONTINUE:
1366	return VINF_SUCCESS;
1367
1368	default:
1369	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
1370	return VERR_IPE_UNEXPECTED_STATUS;
1371	}
1372	}
1373
1374	#if 0
1375	/* Try our own instruction emulator before falling back to the recompiler. */
1376	DISCPUSTATE Cpu;
1377	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1378	if (RT_SUCCESS(rc))
1379	{
1380	uint32_t size;
1381
1382	switch (Cpu.pCurInstr->opcode)
1383	{
1384	/* @todo we can do more now */
1385	case OP_MOV:
1386	case OP_AND:
1387	case OP_OR:
1388	case OP_XOR:
1389	case OP_POP:
1390	case OP_INC:
1391	case OP_DEC:
1392	case OP_XCHG:
1393	STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
1394	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1395	if (RT_SUCCESS(rc))
1396	{
1397	pCtx->rip += Cpu.opsize;
1398	#ifdef EM_NOTIFY_HWACCM
1399	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1400	HWACCMR3NotifyEmulated(pVCpu);
1401	#endif
1402	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
1403	return rc;
1404	}
1405	if (rc != VERR_EM_INTERPRETER)
1406	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
1407	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
1408	break;
1409	}
1410	}
1411	#endif /* 0 */
1412	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
1413	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
1414	rc = REMR3EmulateInstruction(pVM, pVCpu);
1415	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
1416
1417	#ifdef EM_NOTIFY_HWACCM
1418	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1419	HWACCMR3NotifyEmulated(pVCpu);
1420	#endif
1421	return rc;
1422	}
1423
1424
1425	/**
1426	* Executes one (or perhaps a few more) instruction(s).
1427	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1428	*
1429	* @returns VBox status code suitable for EM.
1430	* @param pVM VM handle.
1431	* @param pVCpu VMCPU handle.
1432	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1433	* instruction and prefix the log output with this text.
1434	* @param rcGC GC return code
1435	*/
1436	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
1437	{
1438	#ifdef LOG_ENABLED
1439	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
1440	#else
1441	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
1442	#endif
1443	}
1444
1445	/**
1446	* Executes one (or perhaps a few more) IO instruction(s).
1447	*
1448	* @returns VBox status code suitable for EM.
1449	* @param pVM VM handle.
1450	* @param pVCpu VMCPU handle.
1451	*/
1452	int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
1453	{
1454	int rc;
1455	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1456
1457	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
1458
1459	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1460	* as io instructions tend to come in packages of more than one
1461	*/
1462	DISCPUSTATE Cpu;
1463	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
1464	if (RT_SUCCESS(rc))
1465	{
1466	rc = VINF_EM_RAW_EMULATE_INSTR;
1467
1468	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1469	{
1470	switch (Cpu.pCurInstr->opcode)
1471	{
1472	case OP_IN:
1473	{
1474	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
1475	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1476	break;
1477	}
1478
1479	case OP_OUT:
1480	{
1481	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
1482	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1483	break;
1484	}
1485	}
1486	}
1487	else if (Cpu.prefix & PREFIX_REP)
1488	{
1489	switch (Cpu.pCurInstr->opcode)
1490	{
1491	case OP_INSB:
1492	case OP_INSWD:
1493	{
1494	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
1495	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1496	break;
1497	}
1498
1499	case OP_OUTSB:
1500	case OP_OUTSWD:
1501	{
1502	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
1503	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1504	break;
1505	}
1506	}
1507	}
1508
1509	/*
1510	* Handled the I/O return codes.
1511	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1512	*/
1513	if (IOM_SUCCESS(rc))
1514	{
1515	pCtx->rip += Cpu.opsize;
1516	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1517	return rc;
1518	}
1519
1520	if (rc == VINF_EM_RAW_GUEST_TRAP)
1521	{
1522	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1523	rc = emR3RawGuestTrap(pVM, pVCpu);
1524	return rc;
1525	}
1526	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1527
1528	if (RT_FAILURE(rc))
1529	{
1530	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1531	return rc;
1532	}
1533	AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc=%Rrc\n", rc));
1534	}
1535	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1536	return emR3RawExecuteInstruction(pVM, pVCpu, "IO: ");
1537	}
1538
1539
1540	/**
1541	* Handle a guest context trap.
1542	*
1543	* @returns VBox status code suitable for EM.
1544	* @param pVM VM handle.
1545	* @param pVCpu VMCPU handle.
1546	*/
1547	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
1548	{
1549	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1550
1551	/*
1552	* Get the trap info.
1553	*/
1554	uint8_t u8TrapNo;
1555	TRPMEVENT enmType;
1556	RTGCUINT uErrorCode;
1557	RTGCUINTPTR uCR2;
1558	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1559	if (RT_FAILURE(rc))
1560	{
1561	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
1562	return rc;
1563	}
1564
1565	/*
1566	* Traps can be directly forwarded in hardware accelerated mode.
1567	*/
1568	if (HWACCMR3IsActive(pVM))
1569	{
1570	#ifdef LOGGING_ENABLED
1571	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1572	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1573	#endif
1574	return VINF_EM_RESCHEDULE_HWACC;
1575	}
1576
1577	#if 1 /* Experimental: Review, disable if it causes trouble. */
1578	/*
1579	* Handle traps in patch code first.
1580	*
1581	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
1582	* but several traps isn't handled specially by TRPM in RC and we end up here
1583	* instead. One example is #DE.
1584	*/
1585	uint32_t uCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
1586	if ( uCpl == 0
1587	&& PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1588	{
1589	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
1590	return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
1591	}
1592	#endif
1593
1594	/*
1595	* If the guest gate is marked unpatched, then we will check again if we can patch it.
1596	* (This assumes that we've already tried and failed to dispatch the trap in
1597	* RC for the gates that already has been patched. Which is true for most high
1598	* volume traps, because these are handled specially, but not for odd ones like #DE.)
1599	*/
1600	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
1601	{
1602	CSAMR3CheckGates(pVM, u8TrapNo, 1);
1603	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
1604
1605	/* If it was successful, then we could go back to raw mode. */
1606	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
1607	{
1608	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
1609	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1610	AssertRCReturn(rc, rc);
1611
1612	TRPMERRORCODE enmError = uErrorCode != ~0U
1613	? TRPM_TRAP_HAS_ERRORCODE
1614	: TRPM_TRAP_NO_ERRORCODE;
1615	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
1616	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1617	{
1618	TRPMResetTrap(pVCpu);
1619	return VINF_EM_RESCHEDULE_RAW;
1620	}
1621	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
1622	}
1623	}
1624
1625	/*
1626	* Scan kernel code that traps; we might not get another chance.
1627	*/
1628	/** @todo move this up before the dispatching? */
1629	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1630	&& !pCtx->eflags.Bits.u1VM)
1631	{
1632	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1633	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1634	}
1635
1636	/*
1637	* Trap specific handling.
1638	*/
1639	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1640	{
1641	/*
1642	* If MONITOR & MWAIT are supported, then interpret them here.
1643	*/
1644	DISCPUSTATE cpu;
1645	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1646	if ( RT_SUCCESS(rc)
1647	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1648	{
1649	uint32_t u32Dummy, u32Features, u32ExtFeatures;
1650	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1651	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1652	{
1653	rc = TRPMResetTrap(pVCpu);
1654	AssertRC(rc);
1655
1656	uint32_t opsize;
1657	rc = EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
1658	if (RT_SUCCESS(rc))
1659	{
1660	pCtx->rip += cpu.opsize;
1661	#ifdef EM_NOTIFY_HWACCM
1662	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1663	HWACCMR3NotifyEmulated(pVCpu);
1664	#endif
1665	return rc;
1666	}
1667	return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: ");
1668	}
1669	}
1670	}
1671	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1672	{
1673	/*
1674	* Handle I/O bitmap?
1675	*/
1676	/** @todo We're not supposed to be here with a false guest trap concerning
1677	* I/O access. We can easily handle those in RC. */
1678	DISCPUSTATE cpu;
1679	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1680	if ( RT_SUCCESS(rc)
1681	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1682	{
1683	/*
1684	* We should really check the TSS for the IO bitmap, but it's not like this
1685	* lazy approach really makes things worse.
1686	*/
1687	rc = TRPMResetTrap(pVCpu);
1688	AssertRC(rc);
1689	return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
1690	}
1691	}
1692
1693	#ifdef LOG_ENABLED
1694	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1695	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1696
1697	/* Get guest page information. */
1698	uint64_t fFlags = 0;
1699	RTGCPHYS GCPhys = 0;
1700	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
1701	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1702	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1703	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1704	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1705	#endif
1706
1707	/*
1708	* #PG has CR2.
1709	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1710	*/
1711	if (u8TrapNo == 14 /* #PG */)
1712	pCtx->cr2 = uCR2;
1713
1714	return VINF_EM_RESCHEDULE_REM;
1715	}
1716
1717
1718	/**
1719	* Handle a ring switch trap.
1720	* Need to do statistics and to install patches. The result is going to REM.
1721	*
1722	* @returns VBox status code suitable for EM.
1723	* @param pVM VM handle.
1724	* @param pVCpu VMCPU handle.
1725	*/
1726	int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
1727	{
1728	int rc;
1729	DISCPUSTATE Cpu;
1730	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1731
1732	/*
1733	* sysenter, syscall & callgate
1734	*/
1735	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1736	if (RT_SUCCESS(rc))
1737	{
1738	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1739	{
1740	if (pCtx->SysEnter.cs != 0)
1741	{
1742	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1743	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1744	if (RT_SUCCESS(rc))
1745	{
1746	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1747	return VINF_EM_RESCHEDULE_RAW;
1748	}
1749	}
1750	}
1751
1752	#ifdef VBOX_WITH_STATISTICS
1753	switch (Cpu.pCurInstr->opcode)
1754	{
1755	case OP_SYSENTER:
1756	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
1757	break;
1758	case OP_SYSEXIT:
1759	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
1760	break;
1761	case OP_SYSCALL:
1762	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
1763	break;
1764	case OP_SYSRET:
1765	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
1766	break;
1767	}
1768	#endif
1769	}
1770	else
1771	AssertRC(rc);
1772
1773	/* go to the REM to emulate a single instruction */
1774	return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
1775	}
1776
1777
1778	/**
1779	* Handle a trap (\#PF or \#GP) in patch code
1780	*
1781	* @returns VBox status code suitable for EM.
1782	* @param pVM VM handle.
1783	* @param pVCpu VMCPU handle.
1784	* @param pCtx CPU context
1785	* @param gcret GC return code
1786	*/
1787	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
1788	{
1789	uint8_t u8TrapNo;
1790	int rc;
1791	TRPMEVENT enmType;
1792	RTGCUINT uErrorCode;
1793	RTGCUINTPTR uCR2;
1794
1795	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1796
1797	if (gcret == VINF_PATM_PATCH_INT3)
1798	{
1799	u8TrapNo = 3;
1800	uCR2 = 0;
1801	uErrorCode = 0;
1802	}
1803	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
1804	{
1805	/* No active trap in this case. Kind of ugly. */
1806	u8TrapNo = X86_XCPT_GP;
1807	uCR2 = 0;
1808	uErrorCode = 0;
1809	}
1810	else
1811	{
1812	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1813	if (RT_FAILURE(rc))
1814	{
1815	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
1816	return rc;
1817	}
1818	/* Reset the trap as we'll execute the original instruction again. */
1819	TRPMResetTrap(pVCpu);
1820	}
1821
1822	/*
1823	* Deal with traps inside patch code.
1824	* (This code won't run outside GC.)
1825	*/
1826	if (u8TrapNo != 1)
1827	{
1828	#ifdef LOG_ENABLED
1829	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1830	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1831
1832	DISCPUSTATE Cpu;
1833	int rc;
1834
1835	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1836	if ( RT_SUCCESS(rc)
1837	&& Cpu.pCurInstr->opcode == OP_IRET)
1838	{
1839	uint32_t eip, selCS, uEFlags;
1840
1841	/* Iret crashes are bad as we have already changed the flags on the stack */
1842	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
1843	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
1844	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
1845	if (rc == VINF_SUCCESS)
1846	{
1847	if ( (uEFlags & X86_EFL_VM)
1848	\|\| (selCS & X86_SEL_RPL) == 3)
1849	{
1850	uint32_t selSS, esp;
1851
1852	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
1853	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
1854
1855	if (uEFlags & X86_EFL_VM)
1856	{
1857	uint32_t selDS, selES, selFS, selGS;
1858	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
1859	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
1860	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
1861	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
1862	if (rc == VINF_SUCCESS)
1863	{
1864	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1865	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1866	}
1867	}
1868	else
1869	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1870	}
1871	else
1872	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
1873	}
1874	}
1875	#endif /* LOG_ENABLED */
1876	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1877	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1878
1879	RTGCPTR pNewEip;
1880	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1881	switch (rc)
1882	{
1883	/*
1884	* Execute the faulting instruction.
1885	*/
1886	case VINF_SUCCESS:
1887	{
1888	/** @todo execute a whole block */
1889	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
1890	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1891	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1892
1893	pCtx->eip = pNewEip;
1894	AssertRelease(pCtx->eip);
1895
1896	if (pCtx->eflags.Bits.u1IF)
1897	{
1898	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1899	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1900	*/
1901	if ( u8TrapNo == X86_XCPT_GP
1902	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1903	{
1904	/** @todo move to PATMR3HandleTrap */
1905	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
1906	PATMR3RemovePatch(pVM, pCtx->eip);
1907	}
1908
1909	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1910	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
1911
1912	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1913	/* Interrupts are enabled; just go back to the original instruction.
1914	return VINF_SUCCESS; */
1915	}
1916	return VINF_EM_RESCHEDULE_REM;
1917	}
1918
1919	/*
1920	* One instruction.
1921	*/
1922	case VINF_PATCH_EMULATE_INSTR:
1923	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1924	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1925	pCtx->eip = pNewEip;
1926	AssertRelease(pCtx->eip);
1927	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
1928
1929	/*
1930	* The patch was disabled, hand it to the REM.
1931	*/
1932	case VERR_PATCH_DISABLED:
1933	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1934	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1935	pCtx->eip = pNewEip;
1936	AssertRelease(pCtx->eip);
1937
1938	if (pCtx->eflags.Bits.u1IF)
1939	{
1940	/*
1941	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1942	*/
1943	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1944	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1945	}
1946	return VINF_EM_RESCHEDULE_REM;
1947
1948	/* Force continued patch exection; usually due to write monitored stack. */
1949	case VINF_PATCH_CONTINUE:
1950	return VINF_SUCCESS;
1951
1952	/*
1953	* Anything else is fatal.
1954	*/
1955	default:
1956	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
1957	return VERR_IPE_UNEXPECTED_STATUS;
1958	}
1959	}
1960	return VINF_SUCCESS;
1961	}
1962
1963
1964	/**
1965	* Handle a privileged instruction.
1966	*
1967	* @returns VBox status code suitable for EM.
1968	* @param pVM VM handle.
1969	* @param pVCpu VMCPU handle;
1970	*/
1971	int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
1972	{
1973	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
1974	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1975
1976	Assert(!pCtx->eflags.Bits.u1VM);
1977
1978	if (PATMIsEnabled(pVM))
1979	{
1980	/*
1981	* Check if in patch code.
1982	*/
1983	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1984	{
1985	#ifdef LOG_ENABLED
1986	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1987	#endif
1988	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1989	return VERR_EM_RAW_PATCH_CONFLICT;
1990	}
1991	if ( (pCtx->ss & X86_SEL_RPL) == 0
1992	&& !pCtx->eflags.Bits.u1VM
1993	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1994	{
1995	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1996	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1997	if (RT_SUCCESS(rc))
1998	{
1999	#ifdef LOG_ENABLED
2000	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2001	#endif
2002	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
2003	return VINF_SUCCESS;
2004	}
2005	}
2006	}
2007
2008	#ifdef LOG_ENABLED
2009	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
2010	{
2011	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2012	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2013	}
2014	#endif
2015
2016	/*
2017	* Instruction statistics and logging.
2018	*/
2019	DISCPUSTATE Cpu;
2020	int rc;
2021
2022	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
2023	if (RT_SUCCESS(rc))
2024	{
2025	#ifdef VBOX_WITH_STATISTICS
2026	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
2027	switch (Cpu.pCurInstr->opcode)
2028	{
2029	case OP_INVLPG:
2030	STAM_COUNTER_INC(&pStats->StatInvlpg);
2031	break;
2032	case OP_IRET:
2033	STAM_COUNTER_INC(&pStats->StatIret);
2034	break;
2035	case OP_CLI:
2036	STAM_COUNTER_INC(&pStats->StatCli);
2037	emR3RecordCli(pVM, pVCpu, pCtx->rip);
2038	break;
2039	case OP_STI:
2040	STAM_COUNTER_INC(&pStats->StatSti);
2041	break;
2042	case OP_INSB:
2043	case OP_INSWD:
2044	case OP_IN:
2045	case OP_OUTSB:
2046	case OP_OUTSWD:
2047	case OP_OUT:
2048	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
2049	break;
2050
2051	case OP_MOV_CR:
2052	if (Cpu.param1.flags & USE_REG_GEN32)
2053	{
2054	//read
2055	Assert(Cpu.param2.flags & USE_REG_CR);
2056	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
2057	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
2058	}
2059	else
2060	{
2061	//write
2062	Assert(Cpu.param1.flags & USE_REG_CR);
2063	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
2064	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
2065	}
2066	break;
2067
2068	case OP_MOV_DR:
2069	STAM_COUNTER_INC(&pStats->StatMovDRx);
2070	break;
2071	case OP_LLDT:
2072	STAM_COUNTER_INC(&pStats->StatMovLldt);
2073	break;
2074	case OP_LIDT:
2075	STAM_COUNTER_INC(&pStats->StatMovLidt);
2076	break;
2077	case OP_LGDT:
2078	STAM_COUNTER_INC(&pStats->StatMovLgdt);
2079	break;
2080	case OP_SYSENTER:
2081	STAM_COUNTER_INC(&pStats->StatSysEnter);
2082	break;
2083	case OP_SYSEXIT:
2084	STAM_COUNTER_INC(&pStats->StatSysExit);
2085	break;
2086	case OP_SYSCALL:
2087	STAM_COUNTER_INC(&pStats->StatSysCall);
2088	break;
2089	case OP_SYSRET:
2090	STAM_COUNTER_INC(&pStats->StatSysRet);
2091	break;
2092	case OP_HLT:
2093	STAM_COUNTER_INC(&pStats->StatHlt);
2094	break;
2095	default:
2096	STAM_COUNTER_INC(&pStats->StatMisc);
2097	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
2098	break;
2099	}
2100	#endif /* VBOX_WITH_STATISTICS */
2101	if ( (pCtx->ss & X86_SEL_RPL) == 0
2102	&& !pCtx->eflags.Bits.u1VM
2103	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
2104	{
2105	uint32_t size;
2106
2107	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
2108	switch (Cpu.pCurInstr->opcode)
2109	{
2110	case OP_CLI:
2111	pCtx->eflags.u32 &= ~X86_EFL_IF;
2112	Assert(Cpu.opsize == 1);
2113	pCtx->rip += Cpu.opsize;
2114	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2115	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
2116
2117	case OP_STI:
2118	pCtx->eflags.u32 \|= X86_EFL_IF;
2119	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.opsize);
2120	Assert(Cpu.opsize == 1);
2121	pCtx->rip += Cpu.opsize;
2122	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2123	return VINF_SUCCESS;
2124
2125	case OP_HLT:
2126	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
2127	{
2128	PATMTRANSSTATE enmState;
2129	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
2130
2131	if (enmState == PATMTRANS_OVERWRITTEN)
2132	{
2133	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2134	Assert(rc == VERR_PATCH_DISABLED);
2135	/* Conflict detected, patch disabled */
2136	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
2137
2138	enmState = PATMTRANS_SAFE;
2139	}
2140
2141	/* The translation had better be successful. Otherwise we can't recover. */
2142	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
2143	if (enmState != PATMTRANS_OVERWRITTEN)
2144	pCtx->eip = pOrgInstrGC;
2145	}
2146	/* no break; we could just return VINF_EM_HALT here */
2147
2148	case OP_MOV_CR:
2149	case OP_MOV_DR:
2150	#ifdef LOG_ENABLED
2151	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2152	{
2153	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2154	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2155	}
2156	#endif
2157
2158	rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2159	if (RT_SUCCESS(rc))
2160	{
2161	pCtx->rip += Cpu.opsize;
2162	#ifdef EM_NOTIFY_HWACCM
2163	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
2164	HWACCMR3NotifyEmulated(pVCpu);
2165	#endif
2166	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2167
2168	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2169	&& Cpu.param1.flags == USE_REG_CR /* write */
2170	)
2171	{
2172	/* Deal with CR0 updates inside patch code that force
2173	* us to go to the recompiler.
2174	*/
2175	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
2176	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
2177	{
2178	PATMTRANSSTATE enmState;
2179	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
2180
2181	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
2182	if (enmState == PATMTRANS_OVERWRITTEN)
2183	{
2184	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2185	Assert(rc == VERR_PATCH_DISABLED);
2186	/* Conflict detected, patch disabled */
2187	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
2188	enmState = PATMTRANS_SAFE;
2189	}
2190	/* The translation had better be successful. Otherwise we can't recover. */
2191	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
2192	if (enmState != PATMTRANS_OVERWRITTEN)
2193	pCtx->rip = pOrgInstrGC;
2194	}
2195
2196	/* Reschedule is necessary as the execution/paging mode might have changed. */
2197	return VINF_EM_RESCHEDULE;
2198	}
2199	return rc; /* can return VINF_EM_HALT as well. */
2200	}
2201	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
2202	break; /* fall back to the recompiler */
2203	}
2204	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2205	}
2206	}
2207
2208	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2209	return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
2210
2211	return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV");
2212	}
2213
2214
2215	/**
2216	* Update the forced rawmode execution modifier.
2217	*
2218	* This function is called when we're returning from the raw-mode loop(s). If we're
2219	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2220	* if not in patch code, the flag will be cleared.
2221	*
2222	* We should never interrupt patch code while it's being executed. Cli patches can
2223	* contain big code blocks, but they are always executed with IF=0. Other patches
2224	* replace single instructions and should be atomic.
2225	*
2226	* @returns Updated rc.
2227	*
2228	* @param pVM The VM handle.
2229	* @param pVCpu The VMCPU handle.
2230	* @param pCtx The guest CPU context.
2231	* @param rc The result code.
2232	*/
2233	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
2234	{
2235	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2236	{
2237	/* ignore reschedule attempts. */
2238	switch (rc)
2239	{
2240	case VINF_EM_RESCHEDULE:
2241	case VINF_EM_RESCHEDULE_REM:
2242	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
2243	rc = VINF_SUCCESS;
2244	break;
2245	}
2246	pVCpu->em.s.fForceRAW = true;
2247	}
2248	else
2249	pVCpu->em.s.fForceRAW = false;
2250	return rc;
2251	}
2252
2253
2254	/**
2255	* Process a subset of the raw-mode return code.
2256	*
2257	* Since we have to share this with raw-mode single stepping, this inline
2258	* function has been created to avoid code duplication.
2259	*
2260	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2261	* @returns VBox status code to return to the EM main loop.
2262	*
2263	* @param pVM The VM handle
2264	* @param pVCpu The VMCPU handle
2265	* @param rc The return code.
2266	* @param pCtx The guest cpu context.
2267	*/
2268	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
2269	{
2270	switch (rc)
2271	{
2272	/*
2273	* Common & simple ones.
2274	*/
2275	case VINF_SUCCESS:
2276	break;
2277	case VINF_EM_RESCHEDULE_RAW:
2278	case VINF_EM_RESCHEDULE_HWACC:
2279	case VINF_EM_RAW_INTERRUPT:
2280	case VINF_EM_RAW_TO_R3:
2281	case VINF_EM_RAW_TIMER_PENDING:
2282	case VINF_EM_PENDING_REQUEST:
2283	rc = VINF_SUCCESS;
2284	break;
2285
2286	/*
2287	* Privileged instruction.
2288	*/
2289	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2290	case VINF_PATM_PATCH_TRAP_GP:
2291	rc = emR3RawPrivileged(pVM, pVCpu);
2292	break;
2293
2294	/*
2295	* Got a trap which needs dispatching.
2296	*/
2297	case VINF_EM_RAW_GUEST_TRAP:
2298	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2299	{
2300	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
2301	rc = VERR_EM_RAW_PATCH_CONFLICT;
2302	break;
2303	}
2304	rc = emR3RawGuestTrap(pVM, pVCpu);
2305	break;
2306
2307	/*
2308	* Trap in patch code.
2309	*/
2310	case VINF_PATM_PATCH_TRAP_PF:
2311	case VINF_PATM_PATCH_INT3:
2312	rc = emR3PatchTrap(pVM, pVCpu, pCtx, rc);
2313	break;
2314
2315	case VINF_PATM_DUPLICATE_FUNCTION:
2316	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2317	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2318	AssertRC(rc);
2319	rc = VINF_SUCCESS;
2320	break;
2321
2322	case VINF_PATM_CHECK_PATCH_PAGE:
2323	rc = PATMR3HandleMonitoredPage(pVM);
2324	AssertRC(rc);
2325	rc = VINF_SUCCESS;
2326	break;
2327
2328	/*
2329	* Patch manager.
2330	*/
2331	case VERR_EM_RAW_PATCH_CONFLICT:
2332	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
2333	break;
2334
2335	#ifdef VBOX_WITH_VMI
2336	/*
2337	* PARAV function.
2338	*/
2339	case VINF_EM_RESCHEDULE_PARAV:
2340	rc = PARAVCallFunction(pVM);
2341	break;
2342	#endif
2343
2344	/*
2345	* Memory mapped I/O access - attempt to patch the instruction
2346	*/
2347	case VINF_PATM_HC_MMIO_PATCH_READ:
2348	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2349	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2350	if (RT_FAILURE(rc))
2351	rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
2352	break;
2353
2354	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2355	AssertFailed(); /* not yet implemented. */
2356	rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
2357	break;
2358
2359	/*
2360	* Conflict or out of page tables.
2361	*
2362	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2363	* do here is to execute the pending forced actions.
2364	*/
2365	case VINF_PGM_SYNC_CR3:
2366	AssertMsg(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
2367	("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
2368	rc = VINF_SUCCESS;
2369	break;
2370
2371	/*
2372	* Paging mode change.
2373	*/
2374	case VINF_PGM_CHANGE_MODE:
2375	rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2376	if (rc == VINF_SUCCESS)
2377	rc = VINF_EM_RESCHEDULE;
2378	AssertMsg(RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
2379	break;
2380
2381	/*
2382	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2383	*/
2384	case VINF_CSAM_PENDING_ACTION:
2385	rc = VINF_SUCCESS;
2386	break;
2387
2388	/*
2389	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2390	*/
2391	case VINF_EM_RAW_INTERRUPT_PENDING:
2392	case VINF_EM_RAW_RING_SWITCH_INT:
2393	Assert(TRPMHasTrap(pVCpu));
2394	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2395
2396	if (TRPMHasTrap(pVCpu))
2397	{
2398	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2399	uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
2400	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2401	{
2402	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2403	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2404	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2405	}
2406	}
2407	rc = VINF_EM_RESCHEDULE_REM;
2408	break;
2409
2410	/*
2411	* Other ring switch types.
2412	*/
2413	case VINF_EM_RAW_RING_SWITCH:
2414	rc = emR3RawRingSwitch(pVM, pVCpu);
2415	break;
2416
2417	/*
2418	* REMGCNotifyInvalidatePage() failed because of overflow.
2419	*/
2420	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2421	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2422	REMR3ReplayInvalidatedPages(pVM, pVCpu);
2423	rc = VINF_SUCCESS;
2424	break;
2425
2426	/*
2427	* I/O Port access - emulate the instruction.
2428	*/
2429	case VINF_IOM_HC_IOPORT_READ:
2430	case VINF_IOM_HC_IOPORT_WRITE:
2431	rc = emR3RawExecuteIOInstruction(pVM, pVCpu);
2432	break;
2433
2434	/*
2435	* Memory mapped I/O access - emulate the instruction.
2436	*/
2437	case VINF_IOM_HC_MMIO_READ:
2438	case VINF_IOM_HC_MMIO_WRITE:
2439	case VINF_IOM_HC_MMIO_READ_WRITE:
2440	rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
2441	break;
2442
2443	/*
2444	* (MM)IO intensive code block detected; fall back to the recompiler for better performance
2445	*/
2446	case VINF_EM_RAW_EMULATE_IO_BLOCK:
2447	rc = HWACCMR3EmulateIoBlock(pVM, pCtx);
2448	break;
2449
2450	/*
2451	* Execute instruction.
2452	*/
2453	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2454	rc = emR3RawExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
2455	break;
2456	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2457	rc = emR3RawExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
2458	break;
2459	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2460	rc = emR3RawExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
2461	break;
2462	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2463	rc = emR3RawExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
2464	break;
2465	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2466	rc = emR3RawExecuteInstruction(pVM, pVCpu, "PD FAULT: ");
2467	break;
2468
2469	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2470	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2471	rc = emR3RawPrivileged(pVM, pVCpu);
2472	break;
2473
2474	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2475	rc = emR3RawExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2476	break;
2477
2478	case VINF_EM_RAW_EMULATE_INSTR:
2479	case VINF_PATCH_EMULATE_INSTR:
2480	rc = emR3RawExecuteInstruction(pVM, pVCpu, "EMUL: ");
2481	break;
2482
2483	/*
2484	* Stale selector and iret traps => REM.
2485	*/
2486	case VINF_EM_RAW_STALE_SELECTOR:
2487	case VINF_EM_RAW_IRET_TRAP:
2488	/* We will not go to the recompiler if EIP points to patch code. */
2489	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2490	{
2491	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2492	}
2493	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
2494	rc = VINF_EM_RESCHEDULE_REM;
2495	break;
2496
2497	/*
2498	* Up a level.
2499	*/
2500	case VINF_EM_TERMINATE:
2501	case VINF_EM_OFF:
2502	case VINF_EM_RESET:
2503	case VINF_EM_SUSPEND:
2504	case VINF_EM_HALT:
2505	case VINF_EM_RESUME:
2506	case VINF_EM_NO_MEMORY:
2507	case VINF_EM_RESCHEDULE:
2508	case VINF_EM_RESCHEDULE_REM:
2509	break;
2510
2511	/*
2512	* Up a level and invoke the debugger.
2513	*/
2514	case VINF_EM_DBG_STEPPED:
2515	case VINF_EM_DBG_BREAKPOINT:
2516	case VINF_EM_DBG_STEP:
2517	case VINF_EM_DBG_HYPER_BREAKPOINT:
2518	case VINF_EM_DBG_HYPER_STEPPED:
2519	case VINF_EM_DBG_HYPER_ASSERTION:
2520	case VINF_EM_DBG_STOP:
2521	break;
2522
2523	/*
2524	* Up a level, dump and debug.
2525	*/
2526	case VERR_TRPM_DONT_PANIC:
2527	case VERR_TRPM_PANIC:
2528	case VERR_VMM_RING0_ASSERTION:
2529	break;
2530
2531	/*
2532	* Up a level, after HwAccM have done some release logging.
2533	*/
2534	case VERR_VMX_INVALID_VMCS_FIELD:
2535	case VERR_VMX_INVALID_VMCS_PTR:
2536	case VERR_VMX_INVALID_VMXON_PTR:
2537	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2538	case VERR_VMX_UNEXPECTED_EXCEPTION:
2539	case VERR_VMX_UNEXPECTED_EXIT_CODE:
2540	case VERR_VMX_INVALID_GUEST_STATE:
2541	case VERR_VMX_UNABLE_TO_START_VM:
2542	case VERR_VMX_UNABLE_TO_RESUME_VM:
2543	HWACCMR3CheckError(pVM, rc);
2544	break;
2545	/*
2546	* Anything which is not known to us means an internal error
2547	* and the termination of the VM!
2548	*/
2549	default:
2550	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
2551	break;
2552	}
2553	return rc;
2554	}
2555
2556
2557	/**
2558	* Check for pending raw actions
2559	*
2560	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
2561	* EM statuses.
2562	* @param pVM The VM to operate on.
2563	* @param pVCpu The VMCPU handle.
2564	*/
2565	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
2566	{
2567	return emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
2568	}
2569
2570
2571	/**
2572	* Process raw-mode specific forced actions.
2573	*
2574	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2575	*
2576	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
2577	* EM statuses.
2578	* @param pVM The VM handle.
2579	* @param pVCpu The VMCPU handle.
2580	* @param pCtx The guest CPUM register context.
2581	*/
2582	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2583	{
2584	/*
2585	* Note that the order is vitally important!
2586	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2587	*/
2588
2589
2590	/*
2591	* Sync selector tables.
2592	*/
2593	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
2594	{
2595	int rc = SELMR3UpdateFromCPUM(pVM, pVCpu);
2596	if (RT_FAILURE(rc))
2597	return rc;
2598	}
2599
2600	/*
2601	* Sync IDT.
2602	*
2603	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
2604	* and PGMShwModifyPage, so we're in for trouble if for instance a
2605	* PGMSyncCR3+pgmPoolClearAll is pending.
2606	*/
2607	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
2608	{
2609	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
2610	&& EMIsRawRing0Enabled(pVM)
2611	&& CSAMIsEnabled(pVM))
2612	{
2613	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2614	if (RT_FAILURE(rc))
2615	return rc;
2616	}
2617
2618	int rc = TRPMR3SyncIDT(pVM, pVCpu);
2619	if (RT_FAILURE(rc))
2620	return rc;
2621	}
2622
2623	/*
2624	* Sync TSS.
2625	*/
2626	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
2627	{
2628	int rc = SELMR3SyncTSS(pVM, pVCpu);
2629	if (RT_FAILURE(rc))
2630	return rc;
2631	}
2632
2633	/*
2634	* Sync page directory.
2635	*/
2636	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2637	{
2638	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2639	if (RT_FAILURE(rc))
2640	return rc;
2641
2642	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
2643
2644	/* Prefetch pages for EIP and ESP. */
2645	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2646	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2647	if (rc == VINF_SUCCESS)
2648	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2649	if (rc != VINF_SUCCESS)
2650	{
2651	if (rc != VINF_PGM_SYNC_CR3)
2652	{
2653	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
2654	return rc;
2655	}
2656	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2657	if (RT_FAILURE(rc))
2658	return rc;
2659	}
2660	/** @todo maybe prefetch the supervisor stack page as well */
2661	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
2662	}
2663
2664	/*
2665	* Allocate handy pages (just in case the above actions have consumed some pages).
2666	*/
2667	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
2668	{
2669	int rc = PGMR3PhysAllocateHandyPages(pVM);
2670	if (RT_FAILURE(rc))
2671	return rc;
2672	}
2673
2674	/*
2675	* Check whether we're out of memory now.
2676	*
2677	* This may stem from some of the above actions or operations that has been executed
2678	* since we ran FFs. The allocate handy pages must for instance always be followed by
2679	* this check.
2680	*/
2681	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2682	return VINF_EM_NO_MEMORY;
2683
2684	return VINF_SUCCESS;
2685	}
2686
2687
2688	/**
2689	* Executes raw code.
2690	*
2691	* This function contains the raw-mode version of the inner
2692	* execution loop (the outer loop being in EMR3ExecuteVM()).
2693	*
2694	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2695	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2696	*
2697	* @param pVM VM handle.
2698	* @param pVCpu VMCPU handle.
2699	* @param pfFFDone Where to store an indicator telling whether or not
2700	* FFs were done before returning.
2701	*/
2702	static int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
2703	{
2704	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
2705
2706	int rc = VERR_INTERNAL_ERROR;
2707	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
2708	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2709	pVCpu->em.s.fForceRAW = false;
2710	*pfFFDone = false;
2711
2712
2713	/*
2714	*
2715	* Spin till we get a forced action or raw mode status code resulting in
2716	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2717	*
2718	*/
2719	for (;;)
2720	{
2721	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
2722
2723	/*
2724	* Check various preconditions.
2725	*/
2726	#ifdef VBOX_STRICT
2727	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
2728	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2729	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2730	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2731	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2732	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
2733	&& PGMMapHasConflicts(pVM))
2734	{
2735	PGMMapCheck(pVM);
2736	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2737	return VERR_INTERNAL_ERROR;
2738	}
2739	#endif /* VBOX_STRICT */
2740
2741	/*
2742	* Process high priority pre-execution raw-mode FFs.
2743	*/
2744	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
2745	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2746	{
2747	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
2748	if (rc != VINF_SUCCESS)
2749	break;
2750	}
2751
2752	/*
2753	* If we're going to execute ring-0 code, the guest state needs to
2754	* be modified a bit and some of the state components (IF, SS/CS RPL,
2755	* and perhaps EIP) needs to be stored with PATM.
2756	*/
2757	rc = CPUMRawEnter(pVCpu, NULL);
2758	if (rc != VINF_SUCCESS)
2759	{
2760	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
2761	break;
2762	}
2763
2764	/*
2765	* Scan code before executing it. Don't bother with user mode or V86 code
2766	*/
2767	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2768	&& !pCtx->eflags.Bits.u1VM
2769	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2770	{
2771	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
2772	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2773	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
2774	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
2775	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2776	{
2777	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
2778	if (rc != VINF_SUCCESS)
2779	{
2780	rc = CPUMRawLeave(pVCpu, NULL, rc);
2781	break;
2782	}
2783	}
2784	}
2785
2786	#ifdef LOG_ENABLED
2787	/*
2788	* Log important stuff before entering GC.
2789	*/
2790	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2791	if (pCtx->eflags.Bits.u1VM)
2792	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2793	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2794	{
2795	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2796	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2797	}
2798	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2799	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2800	#endif /* LOG_ENABLED */
2801
2802
2803
2804	/*
2805	* Execute the code.
2806	*/
2807	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
2808	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
2809	VMMR3Unlock(pVM);
2810	rc = VMMR3RawRunGC(pVM, pVCpu);
2811	VMMR3Lock(pVM);
2812	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
2813	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
2814
2815	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2816	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
2817
2818
2819
2820	/*
2821	* Restore the real CPU state and deal with high priority post
2822	* execution FFs before doing anything else.
2823	*/
2824	rc = CPUMRawLeave(pVCpu, NULL, rc);
2825	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
2826	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
2827	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
2828	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
2829
2830	#ifdef VBOX_STRICT
2831	/*
2832	* Assert TSS consistency & rc vs patch code.
2833	*/
2834	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2835	&& EMIsRawRing0Enabled(pVM))
2836	SELMR3CheckTSS(pVM);
2837	switch (rc)
2838	{
2839	case VINF_SUCCESS:
2840	case VINF_EM_RAW_INTERRUPT:
2841	case VINF_PATM_PATCH_TRAP_PF:
2842	case VINF_PATM_PATCH_TRAP_GP:
2843	case VINF_PATM_PATCH_INT3:
2844	case VINF_PATM_CHECK_PATCH_PAGE:
2845	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2846	case VINF_EM_RAW_GUEST_TRAP:
2847	case VINF_EM_RESCHEDULE_RAW:
2848	break;
2849
2850	default:
2851	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2852	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
2853	break;
2854	}
2855	/*
2856	* Let's go paranoid!
2857	*/
2858	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
2859	&& PGMMapHasConflicts(pVM))
2860	{
2861	PGMMapCheck(pVM);
2862	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
2863	return VERR_INTERNAL_ERROR;
2864	}
2865	#endif /* VBOX_STRICT */
2866
2867	/*
2868	* Process the returned status code.
2869	*/
2870	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2871	{
2872	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
2873	break;
2874	}
2875	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
2876	if (rc != VINF_SUCCESS)
2877	{
2878	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
2879	if (rc != VINF_SUCCESS)
2880	{
2881	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
2882	break;
2883	}
2884	}
2885
2886	/*
2887	* Check and execute forced actions.
2888	*/
2889	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2890	TMTimerPoll(pVM);
2891	#endif
2892	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
2893	if ( VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
2894	\|\| VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2895	{
2896	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2897
2898	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
2899	rc = emR3ForcedActions(pVM, pVCpu, rc);
2900	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
2901	if ( rc != VINF_SUCCESS
2902	&& rc != VINF_EM_RESCHEDULE_RAW)
2903	{
2904	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
2905	if (rc != VINF_SUCCESS)
2906	{
2907	*pfFFDone = true;
2908	break;
2909	}
2910	}
2911	}
2912	}
2913
2914	/*
2915	* Return to outer loop.
2916	*/
2917	#if defined(LOG_ENABLED) && defined(DEBUG)
2918	RTLogFlush(NULL);
2919	#endif
2920	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
2921	return rc;
2922	}
2923
2924
2925	/**
2926	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2927	*
2928	* This function contains the raw-mode version of the inner
2929	* execution loop (the outer loop being in EMR3ExecuteVM()).
2930	*
2931	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2932	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2933	*
2934	* @param pVM VM handle.
2935	* @param pVCpu VMCPU handle.
2936	* @param pfFFDone Where to store an indicator telling whether or not
2937	* FFs were done before returning.
2938	*/
2939	static int emR3HwAccExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
2940	{
2941	int rc = VERR_INTERNAL_ERROR;
2942	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
2943
2944	LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
2945	*pfFFDone = false;
2946
2947	STAM_COUNTER_INC(&pVCpu->em.s.StatHwAccExecuteEntry);
2948
2949	#ifdef EM_NOTIFY_HWACCM
2950	HWACCMR3NotifyScheduled(pVCpu);
2951	#endif
2952
2953	/*
2954	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2955	*/
2956	for (;;)
2957	{
2958	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHwAccEntry, a);
2959
2960	/*
2961	* Process high priority pre-execution raw-mode FFs.
2962	*/
2963	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
2964	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
2965	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2966	{
2967	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
2968	if (rc != VINF_SUCCESS)
2969	break;
2970	}
2971
2972	#ifdef LOG_ENABLED
2973	/*
2974	* Log important stuff before entering GC.
2975	*/
2976	if (TRPMHasTrap(pVCpu))
2977	Log(("Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
2978
2979	uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
2980	if (pCtx->eflags.Bits.u1VM)
2981	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2982	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
2983	Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2984	else
2985	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2986	#endif /* LOG_ENABLED */
2987
2988	/*
2989	* Execute the code.
2990	*/
2991	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHwAccEntry, a);
2992	STAM_PROFILE_START(&pVCpu->em.s.StatHwAccExec, x);
2993	VMMR3Unlock(pVM);
2994	rc = VMMR3HwAccRunGC(pVM, pVCpu);
2995	VMMR3Lock(pVM);
2996	STAM_PROFILE_STOP(&pVCpu->em.s.StatHwAccExec, x);
2997
2998	/*
2999	* Deal with high priority post execution FFs before doing anything else.
3000	*/
3001	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
3002	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
3003	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
3004	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
3005
3006	/*
3007	* Process the returned status code.
3008	*/
3009	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
3010	break;
3011
3012	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
3013	if (rc != VINF_SUCCESS)
3014	break;
3015
3016	/*
3017	* Check and execute forced actions.
3018	*/
3019	#ifdef VBOX_HIGH_RES_TIMERS_HACK
3020	TMTimerPoll(pVM);
3021	#endif
3022	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
3023	{
3024	rc = emR3ForcedActions(pVM, pVCpu, rc);
3025	if ( rc != VINF_SUCCESS
3026	&& rc != VINF_EM_RESCHEDULE_HWACC)
3027	{
3028	*pfFFDone = true;
3029	break;
3030	}
3031	}
3032	}
3033
3034	/*
3035	* Return to outer loop.
3036	*/
3037	#if defined(LOG_ENABLED) && defined(DEBUG)
3038	RTLogFlush(NULL);
3039	#endif
3040	return rc;
3041	}
3042
3043
3044	/**
3045	* Decides whether to execute RAW, HWACC or REM.
3046	*
3047	* @returns new EM state
3048	* @param pVM The VM.
3049	* @param pVCpu The VMCPU handle.
3050	* @param pCtx The CPU context.
3051	*/
3052	static EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3053	{
3054	/*
3055	* When forcing raw-mode execution, things are simple.
3056	*/
3057	if (pVCpu->em.s.fForceRAW)
3058	return EMSTATE_RAW;
3059
3060	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
3061	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
3062	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
3063
3064	X86EFLAGS EFlags = pCtx->eflags;
3065	if (HWACCMIsEnabled(pVM))
3066	{
3067	/* Hardware accelerated raw-mode:
3068	*
3069	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
3070	*/
3071	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
3072	return EMSTATE_HWACC;
3073
3074	/* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
3075	* off monitoring features essential for raw mode! */
3076	return EMSTATE_REM;
3077	}
3078
3079	/*
3080	* Standard raw-mode:
3081	*
3082	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
3083	* or 32 bits protected mode ring 0 code
3084	*
3085	* The tests are ordered by the likelyhood of being true during normal execution.
3086	*/
3087	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
3088	{
3089	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
3090	return EMSTATE_REM;
3091	}
3092
3093	#ifndef VBOX_RAW_V86
3094	if (EFlags.u32 & X86_EFL_VM) {
3095	Log2(("raw mode refused: VM_MASK\n"));
3096	return EMSTATE_REM;
3097	}
3098	#endif
3099
3100	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
3101	uint32_t u32CR0 = pCtx->cr0;
3102	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
3103	{
3104	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
3105	return EMSTATE_REM;
3106	}
3107
3108	if (pCtx->cr4 & X86_CR4_PAE)
3109	{
3110	uint32_t u32Dummy, u32Features;
3111
3112	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3113	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3114	return EMSTATE_REM;
3115	}
3116
3117	unsigned uSS = pCtx->ss;
3118	if ( pCtx->eflags.Bits.u1VM
3119	\|\| (uSS & X86_SEL_RPL) == 3)
3120	{
3121	if (!EMIsRawRing3Enabled(pVM))
3122	return EMSTATE_REM;
3123
3124	if (!(EFlags.u32 & X86_EFL_IF))
3125	{
3126	Log2(("raw mode refused: IF (RawR3)\n"));
3127	return EMSTATE_REM;
3128	}
3129
3130	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
3131	{
3132	Log2(("raw mode refused: CR0.WP + RawR0\n"));
3133	return EMSTATE_REM;
3134	}
3135	}
3136	else
3137	{
3138	if (!EMIsRawRing0Enabled(pVM))
3139	return EMSTATE_REM;
3140
3141	/* Only ring 0 supervisor code. */
3142	if ((uSS & X86_SEL_RPL) != 0)
3143	{
3144	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
3145	return EMSTATE_REM;
3146	}
3147
3148	// Let's start with pure 32 bits ring 0 code first
3149	/** @todo What's pure 32-bit mode? flat? */
3150	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
3151	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
3152	{
3153	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
3154	return EMSTATE_REM;
3155	}
3156
3157	/* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
3158	if (!(u32CR0 & X86_CR0_WP))
3159	{
3160	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
3161	return EMSTATE_REM;
3162	}
3163
3164	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
3165	{
3166	Log2(("raw r0 mode forced: patch code\n"));
3167	return EMSTATE_RAW;
3168	}
3169
3170	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
3171	if (!(EFlags.u32 & X86_EFL_IF))
3172	{
3173	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
3174	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
3175	return EMSTATE_REM;
3176	}
3177	#endif
3178
3179	/** @todo still necessary??? */
3180	if (EFlags.Bits.u2IOPL != 0)
3181	{
3182	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
3183	return EMSTATE_REM;
3184	}
3185	}
3186
3187	Assert(PGMPhysIsA20Enabled(pVCpu));
3188	return EMSTATE_RAW;
3189	}
3190
3191
3192	/**
3193	* Executes all high priority post execution force actions.
3194	*
3195	* @returns rc or a fatal status code.
3196	*
3197	* @param pVM VM handle.
3198	* @param pVCpu VMCPU handle.
3199	* @param rc The current rc.
3200	*/
3201	static int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
3202	{
3203	if (VM_FF_ISPENDING(pVM, VM_FF_PDM_CRITSECT))
3204	PDMR3CritSectFF(pVM);
3205
3206	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
3207	CSAMR3DoPendingAction(pVM, pVCpu);
3208
3209	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3210	{
3211	if ( rc > VINF_EM_NO_MEMORY
3212	&& rc <= VINF_EM_LAST)
3213	rc = VINF_EM_NO_MEMORY;
3214	}
3215
3216	return rc;
3217	}
3218
3219
3220	/**
3221	* Executes all pending forced actions.
3222	*
3223	* Forced actions can cause execution delays and execution
3224	* rescheduling. The first we deal with using action priority, so
3225	* that for instance pending timers aren't scheduled and ran until
3226	* right before execution. The rescheduling we deal with using
3227	* return codes. The same goes for VM termination, only in that case
3228	* we exit everything.
3229	*
3230	* @returns VBox status code of equal or greater importance/severity than rc.
3231	* The most important ones are: VINF_EM_RESCHEDULE,
3232	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3233	*
3234	* @param pVM VM handle.
3235	* @param pVCpu VMCPU handle.
3236	* @param rc The current rc.
3237	*
3238	*/
3239	static int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
3240	{
3241	STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
3242	#ifdef VBOX_STRICT
3243	int rcIrq = VINF_SUCCESS;
3244	#endif
3245	int rc2;
3246	#define UPDATE_RC() \
3247	do { \
3248	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
3249	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
3250	break; \
3251	if (!rc \|\| rc2 < rc) \
3252	rc = rc2; \
3253	} while (0)
3254
3255	/*
3256	* Post execution chunk first.
3257	*/
3258	if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
3259	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
3260	{
3261	/*
3262	* Termination request.
3263	*/
3264	if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
3265	{
3266	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3267	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3268	return VINF_EM_TERMINATE;
3269	}
3270
3271	/*
3272	* Debugger Facility polling.
3273	*/
3274	if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
3275	{
3276	rc2 = DBGFR3VMMForcedAction(pVM);
3277	UPDATE_RC();
3278	}
3279
3280	/*
3281	* Postponed reset request.
3282	*/
3283	if (VM_FF_ISPENDING(pVM, VM_FF_RESET))
3284	{
3285	rc2 = VMR3Reset(pVM);
3286	UPDATE_RC();
3287	VM_FF_CLEAR(pVM, VM_FF_RESET);
3288	}
3289
3290	/*
3291	* CSAM page scanning.
3292	*/
3293	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3294	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
3295	{
3296	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
3297
3298	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3299	Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
3300
3301	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3302	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
3303	}
3304
3305	/*
3306	* Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
3307	*/
3308	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3309	{
3310	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3311	UPDATE_RC();
3312	if (rc == VINF_EM_NO_MEMORY)
3313	return rc;
3314	}
3315
3316	/* check that we got them all */
3317	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_PGM_NO_MEMORY)));
3318	Assert(!(VMCPU_FF_NORMAL_PRIORITY_POST_MASK & ~(VMCPU_FF_CSAM_SCAN_PAGE)));
3319	}
3320
3321	/*
3322	* Normal priority then.
3323	* (Executed in no particular order.)
3324	*/
3325	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
3326	{
3327	/*
3328	* PDM Queues are pending.
3329	*/
3330	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
3331	PDMR3QueueFlushAll(pVM);
3332
3333	/*
3334	* PDM DMA transfers are pending.
3335	*/
3336	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
3337	PDMR3DmaRun(pVM);
3338
3339	/*
3340	* Requests from other threads.
3341	*/
3342	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
3343	{
3344	rc2 = VMR3ReqProcessU(pVM->pUVM, VMREQDEST_ANY);
3345	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3346	{
3347	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
3348	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3349	return rc2;
3350	}
3351	UPDATE_RC();
3352	}
3353
3354	/* Replay the handler notification changes. */
3355	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
3356	REMR3ReplayHandlerNotifications(pVM);
3357
3358	/* check that we got them all */
3359	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY)));
3360	}
3361
3362	/*
3363	* Normal priority then. (per-VCPU)
3364	* (Executed in no particular order.)
3365	*/
3366	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3367	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
3368	{
3369	/*
3370	* Requests from other threads.
3371	*/
3372	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
3373	{
3374	rc2 = VMR3ReqProcessU(pVM->pUVM, (VMREQDEST)pVCpu->idCpu);
3375	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3376	{
3377	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
3378	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3379	return rc2;
3380	}
3381	UPDATE_RC();
3382	}
3383
3384	/* check that we got them all */
3385	Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
3386	}
3387
3388	/*
3389	* High priority pre execution chunk last.
3390	* (Executed in ascending priority order.)
3391	*/
3392	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
3393	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
3394	{
3395	/*
3396	* Timers before interrupts.
3397	*/
3398	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_TIMER, VM_FF_PGM_NO_MEMORY))
3399	TMR3TimerQueuesDo(pVM);
3400
3401	/*
3402	* The instruction following an emulated STI should always be executed!
3403	*/
3404	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3405	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3406	{
3407	Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
3408	if (CPUMGetGuestEIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
3409	{
3410	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3411	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3412	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3413	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3414	*/
3415	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3416	}
3417	if (HWACCMR3IsActive(pVM))
3418	rc2 = VINF_EM_RESCHEDULE_HWACC;
3419	else
3420	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3421
3422	UPDATE_RC();
3423	}
3424
3425	/*
3426	* Interrupts.
3427	*/
3428	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3429	&& !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
3430	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_HWACC)
3431	&& !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3432	&& PATMAreInterruptsEnabled(pVM)
3433	&& !HWACCMR3IsEventPending(pVM))
3434	{
3435	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC))
3436	{
3437	/* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3438	/** @todo this really isn't nice, should properly handle this */
3439	rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
3440	#ifdef VBOX_STRICT
3441	rcIrq = rc2;
3442	#endif
3443	UPDATE_RC();
3444	}
3445	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3446	else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
3447	{
3448	rc2 = VINF_EM_RESCHEDULE_REM;
3449	UPDATE_RC();
3450	}
3451	}
3452
3453	/*
3454	* Allocate handy pages.
3455	*/
3456	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
3457	{
3458	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3459	UPDATE_RC();
3460	}
3461
3462	/*
3463	* Debugger Facility request.
3464	*/
3465	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
3466	{
3467	rc2 = DBGFR3VMMForcedAction(pVM);
3468	UPDATE_RC();
3469	}
3470
3471	/*
3472	* Termination request.
3473	*/
3474	if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
3475	{
3476	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3477	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3478	return VINF_EM_TERMINATE;
3479	}
3480
3481	/*
3482	* Out of memory? Since most of our fellow high priority actions may cause us
3483	* to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
3484	* at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
3485	* than us since we can terminate without allocating more memory.
3486	*/
3487	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3488	{
3489	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3490	UPDATE_RC();
3491	if (rc == VINF_EM_NO_MEMORY)
3492	return rc;
3493	}
3494
3495	#ifdef DEBUG
3496	/*
3497	* Debug, pause the VM.
3498	*/
3499	if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
3500	{
3501	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3502	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3503	return VINF_EM_SUSPEND;
3504	}
3505
3506	#endif
3507	/* check that we got them all */
3508	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)));
3509	Assert(!(VMCPU_FF_HIGH_PRIORITY_PRE_MASK & ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_INHIBIT_INTERRUPTS)));
3510	}
3511
3512	#undef UPDATE_RC
3513	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
3514	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3515	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3516	return rc;
3517	}
3518
3519
3520	/**
3521	* Execute VM.
3522	*
3523	* This function is the main loop of the VM. The emulation thread
3524	* calls this function when the VM has been successfully constructed
3525	* and we're ready for executing the VM.
3526	*
3527	* Returning from this function means that the VM is turned off or
3528	* suspended (state already saved) and deconstruction in next in line.
3529	*
3530	* All interaction from other thread are done using forced actions
3531	* and signaling of the wait object.
3532	*
3533	* @returns VBox status code, informational status codes may indicate failure.
3534	* @param pVM The VM to operate on.
3535	* @param pVCpu The VMCPU to operate on.
3536	*/
3537	VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
3538	{
3539	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3540	pVCpu->em.s.enmState, EMR3GetStateName(pVCpu->em.s.enmState), pVCpu->em.s.fForceRAW));
3541	VM_ASSERT_EMT(pVM);
3542	Assert(pVCpu->em.s.enmState == EMSTATE_NONE \|\| pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
3543
3544	VMMR3Lock(pVM);
3545
3546	int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
3547	if (rc == 0)
3548	{
3549	/*
3550	* Start the virtual time.
3551	*/
3552	rc = TMVirtualResume(pVM);
3553	Assert(rc == VINF_SUCCESS);
3554	rc = TMCpuTickResume(pVCpu);
3555	Assert(rc == VINF_SUCCESS);
3556
3557	/*
3558	* The Outer Main Loop.
3559	*/
3560	bool fFFDone = false;
3561
3562	/* Reschedule right away to start in the right state. */
3563	rc = VINF_SUCCESS;
3564	pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
3565
3566	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
3567	for (;;)
3568	{
3569	/*
3570	* Before we can schedule anything (we're here because
3571	* scheduling is required) we must service any pending
3572	* forced actions to avoid any pending action causing
3573	* immediate rescheduling upon entering an inner loop
3574	*
3575	* Do forced actions.
3576	*/
3577	if ( !fFFDone
3578	&& rc != VINF_EM_TERMINATE
3579	&& rc != VINF_EM_OFF
3580	&& ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
3581	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK)))
3582	{
3583	rc = emR3ForcedActions(pVM, pVCpu, rc);
3584	if ( ( rc == VINF_EM_RESCHEDULE_REM
3585	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3586	&& pVCpu->em.s.fForceRAW)
3587	rc = VINF_EM_RESCHEDULE_RAW;
3588	}
3589	else if (fFFDone)
3590	fFFDone = false;
3591
3592	/*
3593	* Now what to do?
3594	*/
3595	Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
3596	switch (rc)
3597	{
3598	/*
3599	* Keep doing what we're currently doing.
3600	*/
3601	case VINF_SUCCESS:
3602	break;
3603
3604	/*
3605	* Reschedule - to raw-mode execution.
3606	*/
3607	case VINF_EM_RESCHEDULE_RAW:
3608	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVCpu->em.s.enmState, EMSTATE_RAW));
3609	pVCpu->em.s.enmState = EMSTATE_RAW;
3610	break;
3611
3612	/*
3613	* Reschedule - to hardware accelerated raw-mode execution.
3614	*/
3615	case VINF_EM_RESCHEDULE_HWACC:
3616	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVCpu->em.s.enmState, EMSTATE_HWACC));
3617	Assert(!pVCpu->em.s.fForceRAW);
3618	pVCpu->em.s.enmState = EMSTATE_HWACC;
3619	break;
3620
3621	/*
3622	* Reschedule - to recompiled execution.
3623	*/
3624	case VINF_EM_RESCHEDULE_REM:
3625	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVCpu->em.s.enmState, EMSTATE_REM));
3626	pVCpu->em.s.enmState = EMSTATE_REM;
3627	break;
3628
3629	#ifdef VBOX_WITH_VMI
3630	/*
3631	* Reschedule - parav call.
3632	*/
3633	case VINF_EM_RESCHEDULE_PARAV:
3634	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVCpu->em.s.enmState, EMSTATE_PARAV));
3635	pVCpu->em.s.enmState = EMSTATE_PARAV;
3636	break;
3637	#endif
3638
3639	/*
3640	* Resume.
3641	*/
3642	case VINF_EM_RESUME:
3643	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVCpu->em.s.enmState));
3644	/* fall through and get scheduled. */
3645
3646	/*
3647	* Reschedule.
3648	*/
3649	case VINF_EM_RESCHEDULE:
3650	{
3651	EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
3652	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3653	pVCpu->em.s.enmState = enmState;
3654	break;
3655	}
3656
3657	/*
3658	* Halted.
3659	*/
3660	case VINF_EM_HALT:
3661	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_HALTED));
3662	pVCpu->em.s.enmState = EMSTATE_HALTED;
3663	break;
3664
3665	/*
3666	* Suspend.
3667	*/
3668	case VINF_EM_SUSPEND:
3669	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
3670	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
3671	break;
3672
3673	/*
3674	* Reset.
3675	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3676	*/
3677	case VINF_EM_RESET:
3678	{
3679	EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
3680	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3681	pVCpu->em.s.enmState = enmState;
3682	break;
3683	}
3684
3685	/*
3686	* Power Off.
3687	*/
3688	case VINF_EM_OFF:
3689	pVCpu->em.s.enmState = EMSTATE_TERMINATING;
3690	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
3691	TMVirtualPause(pVM);
3692	TMCpuTickPause(pVCpu);
3693	VMMR3Unlock(pVM);
3694	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3695	return rc;
3696
3697	/*
3698	* Terminate the VM.
3699	*/
3700	case VINF_EM_TERMINATE:
3701	pVCpu->em.s.enmState = EMSTATE_TERMINATING;
3702	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
3703	TMVirtualPause(pVM);
3704	TMCpuTickPause(pVCpu);
3705	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3706	return rc;
3707
3708
3709	/*
3710	* Out of memory, suspend the VM and stuff.
3711	*/
3712	case VINF_EM_NO_MEMORY:
3713	Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
3714	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
3715	TMVirtualPause(pVM);
3716	TMCpuTickPause(pVCpu);
3717	VMMR3Unlock(pVM);
3718	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3719
3720	rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
3721	N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
3722	if (rc != VINF_EM_SUSPEND)
3723	{
3724	if (RT_SUCCESS_NP(rc))
3725	{
3726	AssertLogRelMsgFailed(("%Rrc\n", rc));
3727	rc = VERR_EM_INTERNAL_ERROR;
3728	}
3729	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3730	}
3731	return rc;
3732
3733	/*
3734	* Guest debug events.
3735	*/
3736	case VINF_EM_DBG_STEPPED:
3737	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3738	case VINF_EM_DBG_STOP:
3739	case VINF_EM_DBG_BREAKPOINT:
3740	case VINF_EM_DBG_STEP:
3741	if (pVCpu->em.s.enmState == EMSTATE_RAW)
3742	{
3743	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3744	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3745	}
3746	else
3747	{
3748	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3749	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3750	}
3751	break;
3752
3753	/*
3754	* Hypervisor debug events.
3755	*/
3756	case VINF_EM_DBG_HYPER_STEPPED:
3757	case VINF_EM_DBG_HYPER_BREAKPOINT:
3758	case VINF_EM_DBG_HYPER_ASSERTION:
3759	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_HYPER));
3760	pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
3761	break;
3762
3763	/*
3764	* Guru mediations.
3765	*/
3766	case VERR_VMM_RING0_ASSERTION:
3767	Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
3768	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3769	break;
3770
3771	/*
3772	* Any error code showing up here other than the ones we
3773	* know and process above are considered to be FATAL.
3774	*
3775	* Unknown warnings and informational status codes are also
3776	* included in this.
3777	*/
3778	default:
3779	if (RT_SUCCESS_NP(rc))
3780	{
3781	AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
3782	rc = VERR_EM_INTERNAL_ERROR;
3783	}
3784	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3785	Log(("EMR3ExecuteVM returns %d\n", rc));
3786	break;
3787	}
3788
3789
3790	/*
3791	* Any waiters can now be woken up
3792	*/
3793	VMMR3Unlock(pVM);
3794	VMMR3Lock(pVM);
3795
3796	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
3797	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
3798
3799	/*
3800	* Act on the state.
3801	*/
3802	switch (pVCpu->em.s.enmState)
3803	{
3804	/*
3805	* Execute raw.
3806	*/
3807	case EMSTATE_RAW:
3808	rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
3809	break;
3810
3811	/*
3812	* Execute hardware accelerated raw.
3813	*/
3814	case EMSTATE_HWACC:
3815	rc = emR3HwAccExecute(pVM, pVCpu, &fFFDone);
3816	break;
3817
3818	/*
3819	* Execute recompiled.
3820	*/
3821	case EMSTATE_REM:
3822	rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
3823	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
3824	break;
3825
3826	#ifdef VBOX_WITH_VMI
3827	/*
3828	* Execute PARAV function.
3829	*/
3830	case EMSTATE_PARAV:
3831	rc = PARAVCallFunction(pVM);
3832	pVCpu->em.s.enmState = EMSTATE_REM;
3833	break;
3834	#endif
3835
3836	/*
3837	* hlt - execution halted until interrupt.
3838	*/
3839	case EMSTATE_HALTED:
3840	{
3841	STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
3842	rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
3843	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
3844	break;
3845	}
3846
3847	/*
3848	* Suspended - return to VM.cpp.
3849	*/
3850	case EMSTATE_SUSPENDED:
3851	TMVirtualPause(pVM);
3852	TMCpuTickPause(pVCpu);
3853	VMMR3Unlock(pVM);
3854	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3855	return VINF_EM_SUSPEND;
3856
3857	/*
3858	* Debugging in the guest.
3859	*/
3860	case EMSTATE_DEBUG_GUEST_REM:
3861	case EMSTATE_DEBUG_GUEST_RAW:
3862	TMVirtualPause(pVM);
3863	TMCpuTickPause(pVCpu);
3864	rc = emR3Debug(pVM, pVCpu, rc);
3865	TMVirtualResume(pVM);
3866	TMCpuTickResume(pVCpu);
3867	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
3868	break;
3869
3870	/*
3871	* Debugging in the hypervisor.
3872	*/
3873	case EMSTATE_DEBUG_HYPER:
3874	{
3875	TMVirtualPause(pVM);
3876	TMCpuTickPause(pVCpu);
3877	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3878
3879	rc = emR3Debug(pVM, pVCpu, rc);
3880	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
3881	if (rc != VINF_SUCCESS)
3882	{
3883	/* switch to guru meditation mode */
3884	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3885	VMMR3FatalDump(pVM, pVCpu, rc);
3886	return rc;
3887	}
3888
3889	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
3890	TMVirtualResume(pVM);
3891	TMCpuTickResume(pVCpu);
3892	break;
3893	}
3894
3895	/*
3896	* Guru meditation takes place in the debugger.
3897	*/
3898	case EMSTATE_GURU_MEDITATION:
3899	{
3900	TMVirtualPause(pVM);
3901	TMCpuTickPause(pVCpu);
3902	VMMR3FatalDump(pVM, pVCpu, rc);
3903	emR3Debug(pVM, pVCpu, rc);
3904	VMMR3Unlock(pVM);
3905	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3906	return rc;
3907	}
3908
3909	/*
3910	* The states we don't expect here.
3911	*/
3912	case EMSTATE_NONE:
3913	case EMSTATE_TERMINATING:
3914	default:
3915	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
3916	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3917	TMVirtualPause(pVM);
3918	TMCpuTickPause(pVCpu);
3919	VMMR3Unlock(pVM);
3920	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3921	return VERR_EM_INTERNAL_ERROR;
3922	}
3923	} /* The Outer Main Loop */
3924	}
3925	else
3926	{
3927	/*
3928	* Fatal error.
3929	*/
3930	LogFlow(("EMR3ExecuteVM: returns %Rrc (longjmp / fatal error)\n", rc));
3931	TMVirtualPause(pVM);
3932	TMCpuTickPause(pVCpu);
3933	VMMR3FatalDump(pVM, pVCpu, rc);
3934	emR3Debug(pVM, pVCpu, rc);
3935	VMMR3Unlock(pVM);
3936	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3937	/** @todo change the VM state! */
3938	return rc;
3939	}
3940
3941	/* (won't ever get here). */
3942	AssertFailed();
3943	}
3944

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 19253

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