EM.cpp@ 19322

Last change on this file since 19322 was 19322, checked in by vboxsync, 16 years ago
Deal with reset, suspend, resume, poweroff for SMP guests.
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1	/* $Id: EM.cpp 19322 2009-05-04 11:54:21Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_em EM - The Execution Monitor / Manager
23	*
24	* The Execution Monitor/Manager is responsible for running the VM, scheduling
25	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26	* Interpreted), and keeping the CPU states in sync. The function
27	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29	* emR3RemExecute).
30	*
31	* The interpreted execution is only used to avoid switching between
32	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33	* The interpretation is thus implemented as part of EM.
34	*
35	* @see grp_em
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_EM
42	#include <VBox/em.h>
43	#include <VBox/vmm.h>
44	#ifdef VBOX_WITH_VMI
45	# include <VBox/parav.h>
46	#endif
47	#include <VBox/patm.h>
48	#include <VBox/csam.h>
49	#include <VBox/selm.h>
50	#include <VBox/trpm.h>
51	#include <VBox/iom.h>
52	#include <VBox/dbgf.h>
53	#include <VBox/pgm.h>
54	#include <VBox/rem.h>
55	#include <VBox/tm.h>
56	#include <VBox/mm.h>
57	#include <VBox/ssm.h>
58	#include <VBox/pdmapi.h>
59	#include <VBox/pdmcritsect.h>
60	#include <VBox/pdmqueue.h>
61	#include <VBox/hwaccm.h>
62	#include <VBox/patm.h>
63	#include "EMInternal.h"
64	#include <VBox/vm.h>
65	#include <VBox/cpumdis.h>
66	#include <VBox/dis.h>
67	#include <VBox/disopcode.h>
68	#include <VBox/dbgf.h>
69
70	#include <VBox/log.h>
71	#include <iprt/thread.h>
72	#include <iprt/assert.h>
73	#include <iprt/asm.h>
74	#include <iprt/semaphore.h>
75	#include <iprt/string.h>
76	#include <iprt/avl.h>
77	#include <iprt/stream.h>
78	#include <VBox/param.h>
79	#include <VBox/err.h>
80
81
82	/*******************************************************************************
83	* Defined Constants And Macros *
84	*******************************************************************************/
85	#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
86	#define EM_NOTIFY_HWACCM
87	#endif
88
89
90	/*******************************************************************************
91	* Internal Functions *
92	*******************************************************************************/
93	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
94	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
95	static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
96	static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
97	static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
98	static int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu);
99	static int emR3RawStep(PVM pVM, PVMCPU pVCpu);
100	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
101	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
102	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
103	static int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
104	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
105	static int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
106	static int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
107	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
108	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
109	static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations);
110	static EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
111	static void emR3RemLock(PVM pVM);
112	static void emR3RemUnlock(PVM pVM);
113
114	/**
115	* Initializes the EM.
116	*
117	* @returns VBox status code.
118	* @param pVM The VM to operate on.
119	*/
120	VMMR3DECL(int) EMR3Init(PVM pVM)
121	{
122	LogFlow(("EMR3Init\n"));
123	/*
124	* Assert alignment and sizes.
125	*/
126	AssertCompileMemberAlignment(VM, em.s, 32);
127	AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
128	AssertReleaseMsg(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump),
129	("%d bytes, padding %d\n", sizeof(pVM->aCpus[0].em.s.u.FatalLongJump), sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump)));
130
131	/*
132	* Init the structure.
133	*/
134	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
135	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
136	if (RT_FAILURE(rc))
137	pVM->fRawR3Enabled = true;
138	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
139	if (RT_FAILURE(rc))
140	pVM->fRawR0Enabled = true;
141	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
142
143	/*
144	* Initialize the REM critical section.
145	*/
146	rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, "EM-REM");
147	AssertRCReturn(rc, rc);
148
149	/*
150	* Saved state.
151	*/
152	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
153	NULL, emR3Save, NULL,
154	NULL, emR3Load, NULL);
155	if (RT_FAILURE(rc))
156	return rc;
157
158	for (unsigned i=0;i<pVM->cCPUs;i++)
159	{
160	PVMCPU pVCpu = &pVM->aCpus[i];
161
162	pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
163
164	pVCpu->em.s.enmState = EMSTATE_NONE;
165	pVCpu->em.s.fForceRAW = false;
166
167	pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
168	pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
169	AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
170
171	# define EM_REG_COUNTER(a, b, c) \
172	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
173	AssertRC(rc);
174
175	# define EM_REG_COUNTER_USED(a, b, c) \
176	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
177	AssertRC(rc);
178
179	# define EM_REG_PROFILE(a, b, c) \
180	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
181	AssertRC(rc);
182
183	# define EM_REG_PROFILE_ADV(a, b, c) \
184	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
185	AssertRC(rc);
186
187	/*
188	* Statistics.
189	*/
190	#ifdef VBOX_WITH_STATISTICS
191	PEMSTATS pStats;
192	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
193	if (RT_FAILURE(rc))
194	return rc;
195
196	pVCpu->em.s.pStatsR3 = pStats;
197	pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
198	pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
199
200	EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
201	EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
202
203	EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
204	EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
205
206	EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
207	EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
208	EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
209	EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
210	EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
211	EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
212	EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
213	EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
214	EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
215	EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
216	EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
217	EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
218	EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
219	EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
220	EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
221	EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
222	EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
223	EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
224	EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
225	EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
226	EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
227	EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
228	EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
229	EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
230	EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
231	EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
232	EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
233	EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
234	EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
235	EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
236	EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
237	EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
238	EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
239	EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
240	EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
241	EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
242	EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
243	EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
244	EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
245	EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
246	EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
247	EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
248	EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
249	EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
250	EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
251	EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
252	EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
253	EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
254	EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
255	EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
256	EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
257	EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
258	EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
259	EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
260	EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
261	EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
262	EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
263	EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
264	EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
265	EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
266	EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
267	EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
268	EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
269	EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
270	EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
271	EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
272	EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
273	EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
274	EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
275	EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
276	EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
277	EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
278
279	EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
280	EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
281
282	EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
283	EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
284	EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
285	EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
286	EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
287	EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
288	EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
289	EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
290	EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
291	EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
292	EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
293	EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
294	EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
295	EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
296	EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
297	EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
298	EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
299	EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
300	EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
301	EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
302	EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
303	EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
304	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
305	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
306	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
307	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
308	EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
309	EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
310	EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
311	EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
312	EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
313	EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
314	EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
315	EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
316	EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
317	EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
318	EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
319	EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
320	EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
321	EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
322	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
323	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
324	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
325	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
326	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
327	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
328	EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
329	EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
330	EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
331	EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
332
333	EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
334	EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
335	EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
336	EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
337	EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
338	EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
339	EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
340	EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
341	EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
342	EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
343	EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
344	EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
345	EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
346	EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
347	EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
348	EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
349	EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
350	EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
351	EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
352	EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
353	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
354	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
355	EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
356	EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
357	EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
358	EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
359	EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
360	EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
361
362	EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
363	EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
364	EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
365	EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
366
367	EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
368	EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
369	EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
370	EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
371	EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
372	EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
373	EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
374	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 read instructions.");
375	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 read instructions.");
376	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 read instructions.");
377	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 read instructions.");
378	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 read instructions.");
379	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 write instructions.");
380	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 write instructions.");
381	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 write instructions.");
382	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 write instructions.");
383	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 write instructions.");
384	EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
385	EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
386	EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
387	EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
388	EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
389	EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
390	EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
391	EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
392	EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
393
394	EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
395	pVCpu->em.s.pCliStatTree = 0;
396
397	/* these should be considered for release statistics. */
398	EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
399	EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
400	EM_REG_COUNTER(&pVCpu->em.s.StatMiscEmu, "/PROF/CPU%d/EM/Emulation/Misc", "Profiling of emR3RawExecuteInstruction.");
401	EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
402	EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
403	EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
404	EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
405	EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
406	EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
407	EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
408	EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
409
410	#endif /* VBOX_WITH_STATISTICS */
411
412	EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
413	EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
414	EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
415	EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
416
417	EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
418	}
419
420	return VINF_SUCCESS;
421	}
422
423
424	/**
425	* Initializes the per-VCPU EM.
426	*
427	* @returns VBox status code.
428	* @param pVM The VM to operate on.
429	*/
430	VMMR3DECL(int) EMR3InitCPU(PVM pVM)
431	{
432	LogFlow(("EMR3InitCPU\n"));
433	return VINF_SUCCESS;
434	}
435
436
437	/**
438	* Applies relocations to data and code managed by this
439	* component. This function will be called at init and
440	* whenever the VMM need to relocate it self inside the GC.
441	*
442	* @param pVM The VM.
443	*/
444	VMMR3DECL(void) EMR3Relocate(PVM pVM)
445	{
446	LogFlow(("EMR3Relocate\n"));
447	for (unsigned i=0;i<pVM->cCPUs;i++)
448	{
449	PVMCPU pVCpu = &pVM->aCpus[i];
450
451	if (pVCpu->em.s.pStatsR3)
452	pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
453	}
454	}
455
456
457	/**
458	* Reset notification.
459	*
460	* @param pVM
461	*/
462	VMMR3DECL(void) EMR3Reset(PVM pVM)
463	{
464	LogFlow(("EMR3Reset: \n"));
465	for (unsigned i=0;i<pVM->cCPUs;i++)
466	{
467	PVMCPU pVCpu = &pVM->aCpus[i];
468
469	pVCpu->em.s.fForceRAW = false;
470	}
471	}
472
473
474	/**
475	* Terminates the EM.
476	*
477	* Termination means cleaning up and freeing all resources,
478	* the VM it self is at this point powered off or suspended.
479	*
480	* @returns VBox status code.
481	* @param pVM The VM to operate on.
482	*/
483	VMMR3DECL(int) EMR3Term(PVM pVM)
484	{
485	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
486
487	PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
488	return VINF_SUCCESS;
489	}
490
491	/**
492	* Terminates the per-VCPU EM.
493	*
494	* Termination means cleaning up and freeing all resources,
495	* the VM it self is at this point powered off or suspended.
496	*
497	* @returns VBox status code.
498	* @param pVM The VM to operate on.
499	*/
500	VMMR3DECL(int) EMR3TermCPU(PVM pVM)
501	{
502	return 0;
503	}
504
505	/**
506	* Execute state save operation.
507	*
508	* @returns VBox status code.
509	* @param pVM VM Handle.
510	* @param pSSM SSM operation handle.
511	*/
512	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
513	{
514	for (unsigned i=0;i<pVM->cCPUs;i++)
515	{
516	PVMCPU pVCpu = &pVM->aCpus[i];
517
518	int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
519	AssertRCReturn(rc, rc);
520	}
521	return VINF_SUCCESS;
522	}
523
524
525	/**
526	* Execute state load operation.
527	*
528	* @returns VBox status code.
529	* @param pVM VM Handle.
530	* @param pSSM SSM operation handle.
531	* @param u32Version Data layout version.
532	*/
533	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
534	{
535	int rc = VINF_SUCCESS;
536
537	/*
538	* Validate version.
539	*/
540	if (u32Version != EM_SAVED_STATE_VERSION)
541	{
542	AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
543	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
544	}
545
546	/*
547	* Load the saved state.
548	*/
549	for (unsigned i=0;i<pVM->cCPUs;i++)
550	{
551	PVMCPU pVCpu = &pVM->aCpus[i];
552
553	rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
554	if (RT_FAILURE(rc))
555	pVCpu->em.s.fForceRAW = false;
556
557	Assert(!pVCpu->em.s.pCliStatTree);
558	}
559	return rc;
560	}
561
562
563	/**
564	* Enables or disables a set of raw-mode execution modes.
565	*
566	* @returns VINF_SUCCESS on success.
567	* @returns VINF_RESCHEDULE if a rescheduling might be required.
568	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
569	*
570	* @param pVM The VM to operate on.
571	* @param enmMode The execution mode change.
572	* @thread The emulation thread.
573	*/
574	VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
575	{
576	switch (enmMode)
577	{
578	case EMRAW_NONE:
579	pVM->fRawR3Enabled = false;
580	pVM->fRawR0Enabled = false;
581	break;
582	case EMRAW_RING3_ENABLE:
583	pVM->fRawR3Enabled = true;
584	break;
585	case EMRAW_RING3_DISABLE:
586	pVM->fRawR3Enabled = false;
587	break;
588	case EMRAW_RING0_ENABLE:
589	pVM->fRawR0Enabled = true;
590	break;
591	case EMRAW_RING0_DISABLE:
592	pVM->fRawR0Enabled = false;
593	break;
594	default:
595	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
596	return VERR_INVALID_PARAMETER;
597	}
598	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
599	pVM->fRawR3Enabled, pVM->fRawR0Enabled));
600	return pVM->aCpus[0].em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
601	}
602
603
604	/**
605	* Raise a fatal error.
606	*
607	* Safely terminate the VM with full state report and stuff. This function
608	* will naturally never return.
609	*
610	* @param pVCpu VMCPU handle.
611	* @param rc VBox status code.
612	*/
613	VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
614	{
615	longjmp(pVCpu->em.s.u.FatalLongJump, rc);
616	AssertReleaseMsgFailed(("longjmp returned!\n"));
617	}
618
619
620	/**
621	* Gets the EM state name.
622	*
623	* @returns pointer to read only state name,
624	* @param enmState The state.
625	*/
626	VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
627	{
628	switch (enmState)
629	{
630	case EMSTATE_NONE: return "EMSTATE_NONE";
631	case EMSTATE_RAW: return "EMSTATE_RAW";
632	case EMSTATE_HWACC: return "EMSTATE_HWACC";
633	case EMSTATE_REM: return "EMSTATE_REM";
634	case EMSTATE_PARAV: return "EMSTATE_PARAV";
635	case EMSTATE_HALTED: return "EMSTATE_HALTED";
636	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
637	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
638	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
639	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
640	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
641	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
642	default: return "Unknown!";
643	}
644	}
645
646
647	#ifdef VBOX_WITH_STATISTICS
648	/**
649	* Just a braindead function to keep track of cli addresses.
650	* @param pVM VM handle.
651	* @param pVMCPU VMCPU handle.
652	* @param GCPtrInstr The EIP of the cli instruction.
653	*/
654	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
655	{
656	PCLISTAT pRec;
657
658	pRec = (PCLISTAT)RTAvlPVGet(&pVCpu->em.s.pCliStatTree, (AVLPVKEY)GCPtrInstr);
659	if (!pRec)
660	{
661	/* New cli instruction; insert into the tree. */
662	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
663	Assert(pRec);
664	if (!pRec)
665	return;
666	pRec->Core.Key = (AVLPVKEY)GCPtrInstr;
667
668	char szCliStatName[32];
669	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
670	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
671
672	bool fRc = RTAvlPVInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
673	Assert(fRc); NOREF(fRc);
674	}
675	STAM_COUNTER_INC(&pRec->Counter);
676	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
677	}
678	#endif /* VBOX_WITH_STATISTICS */
679
680
681	/**
682	* Debug loop.
683	*
684	* @returns VBox status code for EM.
685	* @param pVM VM handle.
686	* @param pVCpu VMCPU handle.
687	* @param rc Current EM VBox status code..
688	*/
689	static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
690	{
691	for (;;)
692	{
693	Log(("emR3Debug: rc=%Rrc\n", rc));
694	const int rcLast = rc;
695
696	/*
697	* Debug related RC.
698	*/
699	switch (rc)
700	{
701	/*
702	* Single step an instruction.
703	*/
704	case VINF_EM_DBG_STEP:
705	if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
706	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
707	\|\| pVCpu->em.s.fForceRAW /* paranoia */)
708	rc = emR3RawStep(pVM, pVCpu);
709	else
710	{
711	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
712	rc = emR3RemStep(pVM, pVCpu);
713	}
714	break;
715
716	/*
717	* Simple events: stepped, breakpoint, stop/assertion.
718	*/
719	case VINF_EM_DBG_STEPPED:
720	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
721	break;
722
723	case VINF_EM_DBG_BREAKPOINT:
724	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
725	break;
726
727	case VINF_EM_DBG_STOP:
728	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
729	break;
730
731	case VINF_EM_DBG_HYPER_STEPPED:
732	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
733	break;
734
735	case VINF_EM_DBG_HYPER_BREAKPOINT:
736	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
737	break;
738
739	case VINF_EM_DBG_HYPER_ASSERTION:
740	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
741	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
742	break;
743
744	/*
745	* Guru meditation.
746	*/
747	case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
748	rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
749	break;
750	case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
751	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
752	break;
753
754	default: /** @todo don't use default for guru, but make special errors code! */
755	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
756	break;
757	}
758
759	/*
760	* Process the result.
761	*/
762	do
763	{
764	switch (rc)
765	{
766	/*
767	* Continue the debugging loop.
768	*/
769	case VINF_EM_DBG_STEP:
770	case VINF_EM_DBG_STOP:
771	case VINF_EM_DBG_STEPPED:
772	case VINF_EM_DBG_BREAKPOINT:
773	case VINF_EM_DBG_HYPER_STEPPED:
774	case VINF_EM_DBG_HYPER_BREAKPOINT:
775	case VINF_EM_DBG_HYPER_ASSERTION:
776	break;
777
778	/*
779	* Resuming execution (in some form) has to be done here if we got
780	* a hypervisor debug event.
781	*/
782	case VINF_SUCCESS:
783	case VINF_EM_RESUME:
784	case VINF_EM_SUSPEND:
785	case VINF_EM_RESCHEDULE:
786	case VINF_EM_RESCHEDULE_RAW:
787	case VINF_EM_RESCHEDULE_REM:
788	case VINF_EM_HALT:
789	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
790	{
791	rc = emR3RawResumeHyper(pVM, pVCpu);
792	if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
793	continue;
794	}
795	if (rc == VINF_SUCCESS)
796	rc = VINF_EM_RESCHEDULE;
797	return rc;
798
799	/*
800	* The debugger isn't attached.
801	* We'll simply turn the thing off since that's the easiest thing to do.
802	*/
803	case VERR_DBGF_NOT_ATTACHED:
804	switch (rcLast)
805	{
806	case VINF_EM_DBG_HYPER_STEPPED:
807	case VINF_EM_DBG_HYPER_BREAKPOINT:
808	case VINF_EM_DBG_HYPER_ASSERTION:
809	case VERR_TRPM_PANIC:
810	case VERR_TRPM_DONT_PANIC:
811	case VERR_VMM_RING0_ASSERTION:
812	return rcLast;
813	}
814	return VINF_EM_OFF;
815
816	/*
817	* Status codes terminating the VM in one or another sense.
818	*/
819	case VINF_EM_TERMINATE:
820	case VINF_EM_OFF:
821	case VINF_EM_RESET:
822	case VINF_EM_NO_MEMORY:
823	case VINF_EM_RAW_STALE_SELECTOR:
824	case VINF_EM_RAW_IRET_TRAP:
825	case VERR_TRPM_PANIC:
826	case VERR_TRPM_DONT_PANIC:
827	case VERR_VMM_RING0_ASSERTION:
828	case VERR_INTERNAL_ERROR:
829	case VERR_INTERNAL_ERROR_2:
830	case VERR_INTERNAL_ERROR_3:
831	case VERR_INTERNAL_ERROR_4:
832	case VERR_INTERNAL_ERROR_5:
833	case VERR_IPE_UNEXPECTED_STATUS:
834	case VERR_IPE_UNEXPECTED_INFO_STATUS:
835	case VERR_IPE_UNEXPECTED_ERROR_STATUS:
836	return rc;
837
838	/*
839	* The rest is unexpected, and will keep us here.
840	*/
841	default:
842	AssertMsgFailed(("Unxpected rc %Rrc!\n", rc));
843	break;
844	}
845	} while (false);
846	} /* debug for ever */
847	}
848
849	/**
850	* Locks REM execution to a single VCpu
851	*
852	* @param pVM VM handle.
853	*/
854	static void emR3RemLock(PVM pVM)
855	{
856	int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
857	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
858	}
859
860	/**
861	* Unlocks REM execution
862	*
863	* @param pVM VM handle.
864	*/
865	static void emR3RemUnlock(PVM pVM)
866	{
867	PDMCritSectLeave(&pVM->em.s.CritSectREM);
868	}
869
870	/**
871	* Steps recompiled code.
872	*
873	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
874	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
875	*
876	* @param pVM VM handle.
877	* @param pVCpu VMCPU handle.
878	*/
879	static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
880	{
881	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
882
883	emR3RemLock(pVM);
884
885	/*
886	* Switch to REM, step instruction, switch back.
887	*/
888	int rc = REMR3State(pVM, pVCpu);
889	if (RT_SUCCESS(rc))
890	{
891	rc = REMR3Step(pVM, pVCpu);
892	REMR3StateBack(pVM, pVCpu);
893	}
894	emR3RemUnlock(pVM);
895
896	LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
897	return rc;
898	}
899
900
901	/**
902	* Executes recompiled code.
903	*
904	* This function contains the recompiler version of the inner
905	* execution loop (the outer loop being in EMR3ExecuteVM()).
906	*
907	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
908	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
909	*
910	* @param pVM VM handle.
911	* @param pVCpu VMCPU handle.
912	* @param pfFFDone Where to store an indicator telling wheter or not
913	* FFs were done before returning.
914	*
915	*/
916	static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
917	{
918	#ifdef LOG_ENABLED
919	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
920	uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
921
922	if (pCtx->eflags.Bits.u1VM)
923	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
924	else
925	Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
926	#endif
927	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
928
929	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
930	AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
931	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo #1419 - get flat address. */
932	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
933	#endif
934
935	/* Big lock, but you are not supposed to own any lock when coming in here. */
936	emR3RemLock(pVM);
937
938	/*
939	* Spin till we get a forced action which returns anything but VINF_SUCCESS
940	* or the REM suggests raw-mode execution.
941	*/
942	*pfFFDone = false;
943	bool fInREMState = false;
944	int rc = VINF_SUCCESS;
945
946	/* Flush the recompiler TLB if the VCPU has changed. */
947	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
948	REMFlushTBs(pVM);
949	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
950
951	for (;;)
952	{
953	/*
954	* Update REM state if not already in sync.
955	*/
956	if (!fInREMState)
957	{
958	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
959	rc = REMR3State(pVM, pVCpu);
960	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
961	if (RT_FAILURE(rc))
962	break;
963	fInREMState = true;
964
965	/*
966	* We might have missed the raising of VMREQ, TIMER and some other
967	* imporant FFs while we were busy switching the state. So, check again.
968	*/
969	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
970	{
971	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
972	goto l_REMDoForcedActions;
973	}
974	}
975
976
977	/*
978	* Execute REM.
979	*/
980	STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
981	rc = REMR3Run(pVM, pVCpu);
982	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
983
984
985	/*
986	* Deal with high priority post execution FFs before doing anything else.
987	*/
988	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
989	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
990	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
991
992	/*
993	* Process the returned status code.
994	* (Try keep this short! Call functions!)
995	*/
996	if (rc != VINF_SUCCESS)
997	{
998	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
999	break;
1000	if (rc != VINF_REM_INTERRUPED_FF)
1001	{
1002	/*
1003	* Anything which is not known to us means an internal error
1004	* and the termination of the VM!
1005	*/
1006	AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1007	break;
1008	}
1009	}
1010
1011
1012	/*
1013	* Check and execute forced actions.
1014	* Sync back the VM state before calling any of these.
1015	*/
1016	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1017	TMTimerPoll(pVM);
1018	#endif
1019	if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
1020	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE)))
1021	{
1022	l_REMDoForcedActions:
1023	if (fInREMState)
1024	{
1025	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, d);
1026	REMR3StateBack(pVM, pVCpu);
1027	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, d);
1028	fInREMState = false;
1029	}
1030	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1031	rc = emR3ForcedActions(pVM, pVCpu, rc);
1032	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1033	if ( rc != VINF_SUCCESS
1034	&& rc != VINF_EM_RESCHEDULE_REM)
1035	{
1036	*pfFFDone = true;
1037	break;
1038	}
1039	}
1040
1041	} /* The Inner Loop, recompiled execution mode version. */
1042
1043
1044	/*
1045	* Returning. Sync back the VM state if required.
1046	*/
1047	if (fInREMState)
1048	{
1049	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, e);
1050	REMR3StateBack(pVM, pVCpu);
1051	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, e);
1052	}
1053	emR3RemUnlock(pVM);
1054
1055	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1056	return rc;
1057	}
1058
1059
1060	/**
1061	* Resumes executing hypervisor after a debug event.
1062	*
1063	* This is kind of special since our current guest state is
1064	* potentially out of sync.
1065	*
1066	* @returns VBox status code.
1067	* @param pVM The VM handle.
1068	* @param pVCpu The VMCPU handle.
1069	*/
1070	static int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
1071	{
1072	int rc;
1073	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1074	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
1075	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
1076
1077	/*
1078	* Resume execution.
1079	*/
1080	CPUMRawEnter(pVCpu, NULL);
1081	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
1082	rc = VMMR3ResumeHyper(pVM, pVCpu);
1083	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
1084	rc = CPUMRawLeave(pVCpu, NULL, rc);
1085	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1086
1087	/*
1088	* Deal with the return code.
1089	*/
1090	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1091	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1092	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1093	return rc;
1094	}
1095
1096
1097	/**
1098	* Steps rawmode.
1099	*
1100	* @returns VBox status code.
1101	* @param pVM The VM handle.
1102	* @param pVCpu The VMCPU handle.
1103	*/
1104	static int emR3RawStep(PVM pVM, PVMCPU pVCpu)
1105	{
1106	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
1107	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
1108	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
1109	int rc;
1110	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1111	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
1112	#ifndef DEBUG_sandervl
1113	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
1114	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
1115	#endif
1116	if (fGuest)
1117	{
1118	/*
1119	* Check vital forced actions, but ignore pending interrupts and timers.
1120	*/
1121	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1122	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1123	{
1124	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1125	if (rc != VINF_SUCCESS)
1126	return rc;
1127	}
1128
1129	/*
1130	* Set flags for single stepping.
1131	*/
1132	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
1133	}
1134	else
1135	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
1136
1137	/*
1138	* Single step.
1139	* We do not start time or anything, if anything we should just do a few nanoseconds.
1140	*/
1141	CPUMRawEnter(pVCpu, NULL);
1142	do
1143	{
1144	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
1145	rc = VMMR3ResumeHyper(pVM, pVCpu);
1146	else
1147	rc = VMMR3RawRunGC(pVM, pVCpu);
1148	#ifndef DEBUG_sandervl
1149	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
1150	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
1151	#endif
1152	} while ( rc == VINF_SUCCESS
1153	\|\| rc == VINF_EM_RAW_INTERRUPT);
1154	rc = CPUMRawLeave(pVCpu, NULL, rc);
1155	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1156
1157	/*
1158	* Make sure the trap flag is cleared.
1159	* (Too bad if the guest is trying to single step too.)
1160	*/
1161	if (fGuest)
1162	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1163	else
1164	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
1165
1166	/*
1167	* Deal with the return codes.
1168	*/
1169	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1170	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1171	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1172	return rc;
1173	}
1174
1175
1176	#ifdef DEBUG
1177
1178	/**
1179	* Steps hardware accelerated mode.
1180	*
1181	* @returns VBox status code.
1182	* @param pVM The VM handle.
1183	* @param pVCpu The VMCPU handle.
1184	*/
1185	static int emR3HwAccStep(PVM pVM, PVMCPU pVCpu)
1186	{
1187	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1188
1189	int rc;
1190	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1191	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1192
1193	/*
1194	* Check vital forced actions, but ignore pending interrupts and timers.
1195	*/
1196	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1197	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1198	{
1199	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1200	if (rc != VINF_SUCCESS)
1201	return rc;
1202	}
1203	/*
1204	* Set flags for single stepping.
1205	*/
1206	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
1207
1208	/*
1209	* Single step.
1210	* We do not start time or anything, if anything we should just do a few nanoseconds.
1211	*/
1212	do
1213	{
1214	rc = VMMR3HwAccRunGC(pVM, pVCpu);
1215	} while ( rc == VINF_SUCCESS
1216	\|\| rc == VINF_EM_RAW_INTERRUPT);
1217	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1218
1219	/*
1220	* Make sure the trap flag is cleared.
1221	* (Too bad if the guest is trying to single step too.)
1222	*/
1223	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1224
1225	/*
1226	* Deal with the return codes.
1227	*/
1228	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1229	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1230	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1231	return rc;
1232	}
1233
1234
1235	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1236	{
1237	int rc = VINF_SUCCESS;
1238	EMSTATE enmOldState = pVCpu->em.s.enmState;
1239	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1240
1241	Log(("Single step BEGIN:\n"));
1242	for (uint32_t i = 0; i < cIterations; i++)
1243	{
1244	DBGFR3PrgStep(pVCpu);
1245	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1246	rc = emR3RawStep(pVM, pVCpu);
1247	if (rc != VINF_SUCCESS)
1248	break;
1249	}
1250	Log(("Single step END: rc=%Rrc\n", rc));
1251	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1252	pVCpu->em.s.enmState = enmOldState;
1253	return rc;
1254	}
1255
1256
1257	static int emR3SingleStepExecHwAcc(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1258	{
1259	int rc = VINF_SUCCESS;
1260	EMSTATE enmOldState = pVCpu->em.s.enmState;
1261	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1262
1263	Log(("Single step BEGIN:\n"));
1264	for (uint32_t i = 0; i < cIterations; i++)
1265	{
1266	DBGFR3PrgStep(pVCpu);
1267	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1268	rc = emR3HwAccStep(pVM, pVCpu);
1269	if ( rc != VINF_SUCCESS
1270	\|\| !HWACCMR3CanExecuteGuest(pVM, pVCpu->em.s.pCtx))
1271	break;
1272	}
1273	Log(("Single step END: rc=%Rrc\n", rc));
1274	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1275	pVCpu->em.s.enmState = enmOldState;
1276	return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
1277	}
1278
1279
1280	static int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1281	{
1282	EMSTATE enmOldState = pVCpu->em.s.enmState;
1283
1284	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1285
1286	Log(("Single step BEGIN:\n"));
1287	for (uint32_t i = 0; i < cIterations; i++)
1288	{
1289	DBGFR3PrgStep(pVCpu);
1290	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1291	emR3RemStep(pVM, pVCpu);
1292	if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1293	break;
1294	}
1295	Log(("Single step END:\n"));
1296	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1297	pVCpu->em.s.enmState = enmOldState;
1298	return VINF_EM_RESCHEDULE;
1299	}
1300
1301	#endif /* DEBUG */
1302
1303
1304	/**
1305	* Executes one (or perhaps a few more) instruction(s).
1306	*
1307	* @returns VBox status code suitable for EM.
1308	*
1309	* @param pVM VM handle.
1310	* @param pVCpu VMCPU handle
1311	* @param rcGC GC return code
1312	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1313	* instruction and prefix the log output with this text.
1314	*/
1315	#ifdef LOG_ENABLED
1316	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
1317	#else
1318	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
1319	#endif
1320	{
1321	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1322	int rc;
1323
1324	/*
1325	*
1326	* The simple solution is to use the recompiler.
1327	* The better solution is to disassemble the current instruction and
1328	* try handle as many as possible without using REM.
1329	*
1330	*/
1331
1332	#ifdef LOG_ENABLED
1333	/*
1334	* Disassemble the instruction if requested.
1335	*/
1336	if (pszPrefix)
1337	{
1338	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1339	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1340	}
1341	#endif /* LOG_ENABLED */
1342
1343	/*
1344	* PATM is making life more interesting.
1345	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1346	* tell PATM there is a trap in this code and have it take the appropriate actions
1347	* to allow us execute the code in REM.
1348	*/
1349	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1350	{
1351	Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
1352
1353	RTGCPTR pNewEip;
1354	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1355	switch (rc)
1356	{
1357	/*
1358	* It's not very useful to emulate a single instruction and then go back to raw
1359	* mode; just execute the whole block until IF is set again.
1360	*/
1361	case VINF_SUCCESS:
1362	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
1363	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1364	pCtx->eip = pNewEip;
1365	Assert(pCtx->eip);
1366
1367	if (pCtx->eflags.Bits.u1IF)
1368	{
1369	/*
1370	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1371	*/
1372	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1373	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1374	}
1375	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1376	{
1377	/* special case: iret, that sets IF, detected a pending irq/event */
1378	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET");
1379	}
1380	return VINF_EM_RESCHEDULE_REM;
1381
1382	/*
1383	* One instruction.
1384	*/
1385	case VINF_PATCH_EMULATE_INSTR:
1386	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1387	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1388	pCtx->eip = pNewEip;
1389	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1390
1391	/*
1392	* The patch was disabled, hand it to the REM.
1393	*/
1394	case VERR_PATCH_DISABLED:
1395	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
1396	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1397	pCtx->eip = pNewEip;
1398	if (pCtx->eflags.Bits.u1IF)
1399	{
1400	/*
1401	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1402	*/
1403	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1404	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1405	}
1406	return VINF_EM_RESCHEDULE_REM;
1407
1408	/* Force continued patch exection; usually due to write monitored stack. */
1409	case VINF_PATCH_CONTINUE:
1410	return VINF_SUCCESS;
1411
1412	default:
1413	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
1414	return VERR_IPE_UNEXPECTED_STATUS;
1415	}
1416	}
1417
1418	#if 0
1419	/* Try our own instruction emulator before falling back to the recompiler. */
1420	DISCPUSTATE Cpu;
1421	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1422	if (RT_SUCCESS(rc))
1423	{
1424	uint32_t size;
1425
1426	switch (Cpu.pCurInstr->opcode)
1427	{
1428	/* @todo we can do more now */
1429	case OP_MOV:
1430	case OP_AND:
1431	case OP_OR:
1432	case OP_XOR:
1433	case OP_POP:
1434	case OP_INC:
1435	case OP_DEC:
1436	case OP_XCHG:
1437	STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
1438	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1439	if (RT_SUCCESS(rc))
1440	{
1441	pCtx->rip += Cpu.opsize;
1442	#ifdef EM_NOTIFY_HWACCM
1443	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1444	HWACCMR3NotifyEmulated(pVCpu);
1445	#endif
1446	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
1447	return rc;
1448	}
1449	if (rc != VERR_EM_INTERPRETER)
1450	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
1451	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
1452	break;
1453	}
1454	}
1455	#endif /* 0 */
1456	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
1457	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
1458	emR3RemLock(pVM);
1459	rc = REMR3EmulateInstruction(pVM, pVCpu);
1460	emR3RemUnlock(pVM);
1461	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
1462
1463	#ifdef EM_NOTIFY_HWACCM
1464	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1465	HWACCMR3NotifyEmulated(pVCpu);
1466	#endif
1467	return rc;
1468	}
1469
1470
1471	/**
1472	* Executes one (or perhaps a few more) instruction(s).
1473	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1474	*
1475	* @returns VBox status code suitable for EM.
1476	* @param pVM VM handle.
1477	* @param pVCpu VMCPU handle.
1478	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1479	* instruction and prefix the log output with this text.
1480	* @param rcGC GC return code
1481	*/
1482	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
1483	{
1484	#ifdef LOG_ENABLED
1485	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
1486	#else
1487	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
1488	#endif
1489	}
1490
1491	/**
1492	* Executes one (or perhaps a few more) IO instruction(s).
1493	*
1494	* @returns VBox status code suitable for EM.
1495	* @param pVM VM handle.
1496	* @param pVCpu VMCPU handle.
1497	*/
1498	int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
1499	{
1500	int rc;
1501	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1502
1503	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
1504
1505	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1506	* as io instructions tend to come in packages of more than one
1507	*/
1508	DISCPUSTATE Cpu;
1509	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
1510	if (RT_SUCCESS(rc))
1511	{
1512	rc = VINF_EM_RAW_EMULATE_INSTR;
1513
1514	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1515	{
1516	switch (Cpu.pCurInstr->opcode)
1517	{
1518	case OP_IN:
1519	{
1520	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
1521	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1522	break;
1523	}
1524
1525	case OP_OUT:
1526	{
1527	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
1528	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1529	break;
1530	}
1531	}
1532	}
1533	else if (Cpu.prefix & PREFIX_REP)
1534	{
1535	switch (Cpu.pCurInstr->opcode)
1536	{
1537	case OP_INSB:
1538	case OP_INSWD:
1539	{
1540	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
1541	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1542	break;
1543	}
1544
1545	case OP_OUTSB:
1546	case OP_OUTSWD:
1547	{
1548	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
1549	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1550	break;
1551	}
1552	}
1553	}
1554
1555	/*
1556	* Handled the I/O return codes.
1557	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1558	*/
1559	if (IOM_SUCCESS(rc))
1560	{
1561	pCtx->rip += Cpu.opsize;
1562	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1563	return rc;
1564	}
1565
1566	if (rc == VINF_EM_RAW_GUEST_TRAP)
1567	{
1568	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1569	rc = emR3RawGuestTrap(pVM, pVCpu);
1570	return rc;
1571	}
1572	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1573
1574	if (RT_FAILURE(rc))
1575	{
1576	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1577	return rc;
1578	}
1579	AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc=%Rrc\n", rc));
1580	}
1581	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1582	return emR3RawExecuteInstruction(pVM, pVCpu, "IO: ");
1583	}
1584
1585
1586	/**
1587	* Handle a guest context trap.
1588	*
1589	* @returns VBox status code suitable for EM.
1590	* @param pVM VM handle.
1591	* @param pVCpu VMCPU handle.
1592	*/
1593	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
1594	{
1595	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1596
1597	/*
1598	* Get the trap info.
1599	*/
1600	uint8_t u8TrapNo;
1601	TRPMEVENT enmType;
1602	RTGCUINT uErrorCode;
1603	RTGCUINTPTR uCR2;
1604	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1605	if (RT_FAILURE(rc))
1606	{
1607	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
1608	return rc;
1609	}
1610
1611	/*
1612	* Traps can be directly forwarded in hardware accelerated mode.
1613	*/
1614	if (HWACCMR3IsActive(pVM))
1615	{
1616	#ifdef LOGGING_ENABLED
1617	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1618	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1619	#endif
1620	return VINF_EM_RESCHEDULE_HWACC;
1621	}
1622
1623	#if 1 /* Experimental: Review, disable if it causes trouble. */
1624	/*
1625	* Handle traps in patch code first.
1626	*
1627	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
1628	* but several traps isn't handled specially by TRPM in RC and we end up here
1629	* instead. One example is #DE.
1630	*/
1631	uint32_t uCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
1632	if ( uCpl == 0
1633	&& PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1634	{
1635	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
1636	return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
1637	}
1638	#endif
1639
1640	/*
1641	* If the guest gate is marked unpatched, then we will check again if we can patch it.
1642	* (This assumes that we've already tried and failed to dispatch the trap in
1643	* RC for the gates that already has been patched. Which is true for most high
1644	* volume traps, because these are handled specially, but not for odd ones like #DE.)
1645	*/
1646	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
1647	{
1648	CSAMR3CheckGates(pVM, u8TrapNo, 1);
1649	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
1650
1651	/* If it was successful, then we could go back to raw mode. */
1652	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
1653	{
1654	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
1655	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1656	AssertRCReturn(rc, rc);
1657
1658	TRPMERRORCODE enmError = uErrorCode != ~0U
1659	? TRPM_TRAP_HAS_ERRORCODE
1660	: TRPM_TRAP_NO_ERRORCODE;
1661	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
1662	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1663	{
1664	TRPMResetTrap(pVCpu);
1665	return VINF_EM_RESCHEDULE_RAW;
1666	}
1667	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
1668	}
1669	}
1670
1671	/*
1672	* Scan kernel code that traps; we might not get another chance.
1673	*/
1674	/** @todo move this up before the dispatching? */
1675	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1676	&& !pCtx->eflags.Bits.u1VM)
1677	{
1678	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1679	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1680	}
1681
1682	/*
1683	* Trap specific handling.
1684	*/
1685	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1686	{
1687	/*
1688	* If MONITOR & MWAIT are supported, then interpret them here.
1689	*/
1690	DISCPUSTATE cpu;
1691	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1692	if ( RT_SUCCESS(rc)
1693	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1694	{
1695	uint32_t u32Dummy, u32Features, u32ExtFeatures;
1696	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1697	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1698	{
1699	rc = TRPMResetTrap(pVCpu);
1700	AssertRC(rc);
1701
1702	uint32_t opsize;
1703	rc = EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
1704	if (RT_SUCCESS(rc))
1705	{
1706	pCtx->rip += cpu.opsize;
1707	#ifdef EM_NOTIFY_HWACCM
1708	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1709	HWACCMR3NotifyEmulated(pVCpu);
1710	#endif
1711	return rc;
1712	}
1713	return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: ");
1714	}
1715	}
1716	}
1717	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1718	{
1719	/*
1720	* Handle I/O bitmap?
1721	*/
1722	/** @todo We're not supposed to be here with a false guest trap concerning
1723	* I/O access. We can easily handle those in RC. */
1724	DISCPUSTATE cpu;
1725	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1726	if ( RT_SUCCESS(rc)
1727	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1728	{
1729	/*
1730	* We should really check the TSS for the IO bitmap, but it's not like this
1731	* lazy approach really makes things worse.
1732	*/
1733	rc = TRPMResetTrap(pVCpu);
1734	AssertRC(rc);
1735	return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
1736	}
1737	}
1738
1739	#ifdef LOG_ENABLED
1740	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1741	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1742
1743	/* Get guest page information. */
1744	uint64_t fFlags = 0;
1745	RTGCPHYS GCPhys = 0;
1746	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
1747	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1748	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1749	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1750	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1751	#endif
1752
1753	/*
1754	* #PG has CR2.
1755	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1756	*/
1757	if (u8TrapNo == 14 /* #PG */)
1758	pCtx->cr2 = uCR2;
1759
1760	return VINF_EM_RESCHEDULE_REM;
1761	}
1762
1763
1764	/**
1765	* Handle a ring switch trap.
1766	* Need to do statistics and to install patches. The result is going to REM.
1767	*
1768	* @returns VBox status code suitable for EM.
1769	* @param pVM VM handle.
1770	* @param pVCpu VMCPU handle.
1771	*/
1772	int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
1773	{
1774	int rc;
1775	DISCPUSTATE Cpu;
1776	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1777
1778	/*
1779	* sysenter, syscall & callgate
1780	*/
1781	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1782	if (RT_SUCCESS(rc))
1783	{
1784	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1785	{
1786	if (pCtx->SysEnter.cs != 0)
1787	{
1788	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1789	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1790	if (RT_SUCCESS(rc))
1791	{
1792	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1793	return VINF_EM_RESCHEDULE_RAW;
1794	}
1795	}
1796	}
1797
1798	#ifdef VBOX_WITH_STATISTICS
1799	switch (Cpu.pCurInstr->opcode)
1800	{
1801	case OP_SYSENTER:
1802	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
1803	break;
1804	case OP_SYSEXIT:
1805	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
1806	break;
1807	case OP_SYSCALL:
1808	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
1809	break;
1810	case OP_SYSRET:
1811	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
1812	break;
1813	}
1814	#endif
1815	}
1816	else
1817	AssertRC(rc);
1818
1819	/* go to the REM to emulate a single instruction */
1820	return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
1821	}
1822
1823
1824	/**
1825	* Handle a trap (\#PF or \#GP) in patch code
1826	*
1827	* @returns VBox status code suitable for EM.
1828	* @param pVM VM handle.
1829	* @param pVCpu VMCPU handle.
1830	* @param pCtx CPU context
1831	* @param gcret GC return code
1832	*/
1833	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
1834	{
1835	uint8_t u8TrapNo;
1836	int rc;
1837	TRPMEVENT enmType;
1838	RTGCUINT uErrorCode;
1839	RTGCUINTPTR uCR2;
1840
1841	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1842
1843	if (gcret == VINF_PATM_PATCH_INT3)
1844	{
1845	u8TrapNo = 3;
1846	uCR2 = 0;
1847	uErrorCode = 0;
1848	}
1849	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
1850	{
1851	/* No active trap in this case. Kind of ugly. */
1852	u8TrapNo = X86_XCPT_GP;
1853	uCR2 = 0;
1854	uErrorCode = 0;
1855	}
1856	else
1857	{
1858	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1859	if (RT_FAILURE(rc))
1860	{
1861	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
1862	return rc;
1863	}
1864	/* Reset the trap as we'll execute the original instruction again. */
1865	TRPMResetTrap(pVCpu);
1866	}
1867
1868	/*
1869	* Deal with traps inside patch code.
1870	* (This code won't run outside GC.)
1871	*/
1872	if (u8TrapNo != 1)
1873	{
1874	#ifdef LOG_ENABLED
1875	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1876	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1877
1878	DISCPUSTATE Cpu;
1879	int rc;
1880
1881	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1882	if ( RT_SUCCESS(rc)
1883	&& Cpu.pCurInstr->opcode == OP_IRET)
1884	{
1885	uint32_t eip, selCS, uEFlags;
1886
1887	/* Iret crashes are bad as we have already changed the flags on the stack */
1888	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
1889	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
1890	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
1891	if (rc == VINF_SUCCESS)
1892	{
1893	if ( (uEFlags & X86_EFL_VM)
1894	\|\| (selCS & X86_SEL_RPL) == 3)
1895	{
1896	uint32_t selSS, esp;
1897
1898	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
1899	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
1900
1901	if (uEFlags & X86_EFL_VM)
1902	{
1903	uint32_t selDS, selES, selFS, selGS;
1904	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
1905	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
1906	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
1907	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
1908	if (rc == VINF_SUCCESS)
1909	{
1910	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1911	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1912	}
1913	}
1914	else
1915	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1916	}
1917	else
1918	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
1919	}
1920	}
1921	#endif /* LOG_ENABLED */
1922	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1923	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1924
1925	RTGCPTR pNewEip;
1926	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1927	switch (rc)
1928	{
1929	/*
1930	* Execute the faulting instruction.
1931	*/
1932	case VINF_SUCCESS:
1933	{
1934	/** @todo execute a whole block */
1935	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
1936	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1937	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1938
1939	pCtx->eip = pNewEip;
1940	AssertRelease(pCtx->eip);
1941
1942	if (pCtx->eflags.Bits.u1IF)
1943	{
1944	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1945	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1946	*/
1947	if ( u8TrapNo == X86_XCPT_GP
1948	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1949	{
1950	/** @todo move to PATMR3HandleTrap */
1951	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
1952	PATMR3RemovePatch(pVM, pCtx->eip);
1953	}
1954
1955	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1956	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
1957
1958	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1959	/* Interrupts are enabled; just go back to the original instruction.
1960	return VINF_SUCCESS; */
1961	}
1962	return VINF_EM_RESCHEDULE_REM;
1963	}
1964
1965	/*
1966	* One instruction.
1967	*/
1968	case VINF_PATCH_EMULATE_INSTR:
1969	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1970	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1971	pCtx->eip = pNewEip;
1972	AssertRelease(pCtx->eip);
1973	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
1974
1975	/*
1976	* The patch was disabled, hand it to the REM.
1977	*/
1978	case VERR_PATCH_DISABLED:
1979	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1980	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1981	pCtx->eip = pNewEip;
1982	AssertRelease(pCtx->eip);
1983
1984	if (pCtx->eflags.Bits.u1IF)
1985	{
1986	/*
1987	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1988	*/
1989	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1990	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1991	}
1992	return VINF_EM_RESCHEDULE_REM;
1993
1994	/* Force continued patch exection; usually due to write monitored stack. */
1995	case VINF_PATCH_CONTINUE:
1996	return VINF_SUCCESS;
1997
1998	/*
1999	* Anything else is fatal.
2000	*/
2001	default:
2002	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
2003	return VERR_IPE_UNEXPECTED_STATUS;
2004	}
2005	}
2006	return VINF_SUCCESS;
2007	}
2008
2009
2010	/**
2011	* Handle a privileged instruction.
2012	*
2013	* @returns VBox status code suitable for EM.
2014	* @param pVM VM handle.
2015	* @param pVCpu VMCPU handle;
2016	*/
2017	int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
2018	{
2019	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
2020	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
2021
2022	Assert(!pCtx->eflags.Bits.u1VM);
2023
2024	if (PATMIsEnabled(pVM))
2025	{
2026	/*
2027	* Check if in patch code.
2028	*/
2029	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2030	{
2031	#ifdef LOG_ENABLED
2032	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2033	#endif
2034	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
2035	return VERR_EM_RAW_PATCH_CONFLICT;
2036	}
2037	if ( (pCtx->ss & X86_SEL_RPL) == 0
2038	&& !pCtx->eflags.Bits.u1VM
2039	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2040	{
2041	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2042	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
2043	if (RT_SUCCESS(rc))
2044	{
2045	#ifdef LOG_ENABLED
2046	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2047	#endif
2048	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
2049	return VINF_SUCCESS;
2050	}
2051	}
2052	}
2053
2054	#ifdef LOG_ENABLED
2055	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
2056	{
2057	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2058	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2059	}
2060	#endif
2061
2062	/*
2063	* Instruction statistics and logging.
2064	*/
2065	DISCPUSTATE Cpu;
2066	int rc;
2067
2068	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
2069	if (RT_SUCCESS(rc))
2070	{
2071	#ifdef VBOX_WITH_STATISTICS
2072	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
2073	switch (Cpu.pCurInstr->opcode)
2074	{
2075	case OP_INVLPG:
2076	STAM_COUNTER_INC(&pStats->StatInvlpg);
2077	break;
2078	case OP_IRET:
2079	STAM_COUNTER_INC(&pStats->StatIret);
2080	break;
2081	case OP_CLI:
2082	STAM_COUNTER_INC(&pStats->StatCli);
2083	emR3RecordCli(pVM, pVCpu, pCtx->rip);
2084	break;
2085	case OP_STI:
2086	STAM_COUNTER_INC(&pStats->StatSti);
2087	break;
2088	case OP_INSB:
2089	case OP_INSWD:
2090	case OP_IN:
2091	case OP_OUTSB:
2092	case OP_OUTSWD:
2093	case OP_OUT:
2094	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
2095	break;
2096
2097	case OP_MOV_CR:
2098	if (Cpu.param1.flags & USE_REG_GEN32)
2099	{
2100	//read
2101	Assert(Cpu.param2.flags & USE_REG_CR);
2102	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
2103	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
2104	}
2105	else
2106	{
2107	//write
2108	Assert(Cpu.param1.flags & USE_REG_CR);
2109	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
2110	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
2111	}
2112	break;
2113
2114	case OP_MOV_DR:
2115	STAM_COUNTER_INC(&pStats->StatMovDRx);
2116	break;
2117	case OP_LLDT:
2118	STAM_COUNTER_INC(&pStats->StatMovLldt);
2119	break;
2120	case OP_LIDT:
2121	STAM_COUNTER_INC(&pStats->StatMovLidt);
2122	break;
2123	case OP_LGDT:
2124	STAM_COUNTER_INC(&pStats->StatMovLgdt);
2125	break;
2126	case OP_SYSENTER:
2127	STAM_COUNTER_INC(&pStats->StatSysEnter);
2128	break;
2129	case OP_SYSEXIT:
2130	STAM_COUNTER_INC(&pStats->StatSysExit);
2131	break;
2132	case OP_SYSCALL:
2133	STAM_COUNTER_INC(&pStats->StatSysCall);
2134	break;
2135	case OP_SYSRET:
2136	STAM_COUNTER_INC(&pStats->StatSysRet);
2137	break;
2138	case OP_HLT:
2139	STAM_COUNTER_INC(&pStats->StatHlt);
2140	break;
2141	default:
2142	STAM_COUNTER_INC(&pStats->StatMisc);
2143	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
2144	break;
2145	}
2146	#endif /* VBOX_WITH_STATISTICS */
2147	if ( (pCtx->ss & X86_SEL_RPL) == 0
2148	&& !pCtx->eflags.Bits.u1VM
2149	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
2150	{
2151	uint32_t size;
2152
2153	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
2154	switch (Cpu.pCurInstr->opcode)
2155	{
2156	case OP_CLI:
2157	pCtx->eflags.u32 &= ~X86_EFL_IF;
2158	Assert(Cpu.opsize == 1);
2159	pCtx->rip += Cpu.opsize;
2160	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2161	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
2162
2163	case OP_STI:
2164	pCtx->eflags.u32 \|= X86_EFL_IF;
2165	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.opsize);
2166	Assert(Cpu.opsize == 1);
2167	pCtx->rip += Cpu.opsize;
2168	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2169	return VINF_SUCCESS;
2170
2171	case OP_HLT:
2172	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
2173	{
2174	PATMTRANSSTATE enmState;
2175	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
2176
2177	if (enmState == PATMTRANS_OVERWRITTEN)
2178	{
2179	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2180	Assert(rc == VERR_PATCH_DISABLED);
2181	/* Conflict detected, patch disabled */
2182	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
2183
2184	enmState = PATMTRANS_SAFE;
2185	}
2186
2187	/* The translation had better be successful. Otherwise we can't recover. */
2188	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
2189	if (enmState != PATMTRANS_OVERWRITTEN)
2190	pCtx->eip = pOrgInstrGC;
2191	}
2192	/* no break; we could just return VINF_EM_HALT here */
2193
2194	case OP_MOV_CR:
2195	case OP_MOV_DR:
2196	#ifdef LOG_ENABLED
2197	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2198	{
2199	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2200	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2201	}
2202	#endif
2203
2204	rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2205	if (RT_SUCCESS(rc))
2206	{
2207	pCtx->rip += Cpu.opsize;
2208	#ifdef EM_NOTIFY_HWACCM
2209	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
2210	HWACCMR3NotifyEmulated(pVCpu);
2211	#endif
2212	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2213
2214	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2215	&& Cpu.param1.flags == USE_REG_CR /* write */
2216	)
2217	{
2218	/* Deal with CR0 updates inside patch code that force
2219	* us to go to the recompiler.
2220	*/
2221	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
2222	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
2223	{
2224	PATMTRANSSTATE enmState;
2225	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
2226
2227	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
2228	if (enmState == PATMTRANS_OVERWRITTEN)
2229	{
2230	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2231	Assert(rc == VERR_PATCH_DISABLED);
2232	/* Conflict detected, patch disabled */
2233	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
2234	enmState = PATMTRANS_SAFE;
2235	}
2236	/* The translation had better be successful. Otherwise we can't recover. */
2237	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
2238	if (enmState != PATMTRANS_OVERWRITTEN)
2239	pCtx->rip = pOrgInstrGC;
2240	}
2241
2242	/* Reschedule is necessary as the execution/paging mode might have changed. */
2243	return VINF_EM_RESCHEDULE;
2244	}
2245	return rc; /* can return VINF_EM_HALT as well. */
2246	}
2247	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
2248	break; /* fall back to the recompiler */
2249	}
2250	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2251	}
2252	}
2253
2254	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2255	return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
2256
2257	return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV");
2258	}
2259
2260
2261	/**
2262	* Update the forced rawmode execution modifier.
2263	*
2264	* This function is called when we're returning from the raw-mode loop(s). If we're
2265	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2266	* if not in patch code, the flag will be cleared.
2267	*
2268	* We should never interrupt patch code while it's being executed. Cli patches can
2269	* contain big code blocks, but they are always executed with IF=0. Other patches
2270	* replace single instructions and should be atomic.
2271	*
2272	* @returns Updated rc.
2273	*
2274	* @param pVM The VM handle.
2275	* @param pVCpu The VMCPU handle.
2276	* @param pCtx The guest CPU context.
2277	* @param rc The result code.
2278	*/
2279	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
2280	{
2281	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2282	{
2283	/* ignore reschedule attempts. */
2284	switch (rc)
2285	{
2286	case VINF_EM_RESCHEDULE:
2287	case VINF_EM_RESCHEDULE_REM:
2288	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
2289	rc = VINF_SUCCESS;
2290	break;
2291	}
2292	pVCpu->em.s.fForceRAW = true;
2293	}
2294	else
2295	pVCpu->em.s.fForceRAW = false;
2296	return rc;
2297	}
2298
2299
2300	/**
2301	* Process a subset of the raw-mode return code.
2302	*
2303	* Since we have to share this with raw-mode single stepping, this inline
2304	* function has been created to avoid code duplication.
2305	*
2306	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2307	* @returns VBox status code to return to the EM main loop.
2308	*
2309	* @param pVM The VM handle
2310	* @param pVCpu The VMCPU handle
2311	* @param rc The return code.
2312	* @param pCtx The guest cpu context.
2313	*/
2314	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
2315	{
2316	switch (rc)
2317	{
2318	/*
2319	* Common & simple ones.
2320	*/
2321	case VINF_SUCCESS:
2322	break;
2323	case VINF_EM_RESCHEDULE_RAW:
2324	case VINF_EM_RESCHEDULE_HWACC:
2325	case VINF_EM_RAW_INTERRUPT:
2326	case VINF_EM_RAW_TO_R3:
2327	case VINF_EM_RAW_TIMER_PENDING:
2328	case VINF_EM_PENDING_REQUEST:
2329	rc = VINF_SUCCESS;
2330	break;
2331
2332	/*
2333	* Privileged instruction.
2334	*/
2335	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2336	case VINF_PATM_PATCH_TRAP_GP:
2337	rc = emR3RawPrivileged(pVM, pVCpu);
2338	break;
2339
2340	/*
2341	* Got a trap which needs dispatching.
2342	*/
2343	case VINF_EM_RAW_GUEST_TRAP:
2344	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2345	{
2346	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
2347	rc = VERR_EM_RAW_PATCH_CONFLICT;
2348	break;
2349	}
2350	rc = emR3RawGuestTrap(pVM, pVCpu);
2351	break;
2352
2353	/*
2354	* Trap in patch code.
2355	*/
2356	case VINF_PATM_PATCH_TRAP_PF:
2357	case VINF_PATM_PATCH_INT3:
2358	rc = emR3PatchTrap(pVM, pVCpu, pCtx, rc);
2359	break;
2360
2361	case VINF_PATM_DUPLICATE_FUNCTION:
2362	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2363	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2364	AssertRC(rc);
2365	rc = VINF_SUCCESS;
2366	break;
2367
2368	case VINF_PATM_CHECK_PATCH_PAGE:
2369	rc = PATMR3HandleMonitoredPage(pVM);
2370	AssertRC(rc);
2371	rc = VINF_SUCCESS;
2372	break;
2373
2374	/*
2375	* Patch manager.
2376	*/
2377	case VERR_EM_RAW_PATCH_CONFLICT:
2378	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
2379	break;
2380
2381	#ifdef VBOX_WITH_VMI
2382	/*
2383	* PARAV function.
2384	*/
2385	case VINF_EM_RESCHEDULE_PARAV:
2386	rc = PARAVCallFunction(pVM);
2387	break;
2388	#endif
2389
2390	/*
2391	* Memory mapped I/O access - attempt to patch the instruction
2392	*/
2393	case VINF_PATM_HC_MMIO_PATCH_READ:
2394	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2395	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2396	if (RT_FAILURE(rc))
2397	rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
2398	break;
2399
2400	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2401	AssertFailed(); /* not yet implemented. */
2402	rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
2403	break;
2404
2405	/*
2406	* Conflict or out of page tables.
2407	*
2408	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2409	* do here is to execute the pending forced actions.
2410	*/
2411	case VINF_PGM_SYNC_CR3:
2412	AssertMsg(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
2413	("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
2414	rc = VINF_SUCCESS;
2415	break;
2416
2417	/*
2418	* Paging mode change.
2419	*/
2420	case VINF_PGM_CHANGE_MODE:
2421	rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2422	if (rc == VINF_SUCCESS)
2423	rc = VINF_EM_RESCHEDULE;
2424	AssertMsg(RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
2425	break;
2426
2427	/*
2428	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2429	*/
2430	case VINF_CSAM_PENDING_ACTION:
2431	rc = VINF_SUCCESS;
2432	break;
2433
2434	/*
2435	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2436	*/
2437	case VINF_EM_RAW_INTERRUPT_PENDING:
2438	case VINF_EM_RAW_RING_SWITCH_INT:
2439	Assert(TRPMHasTrap(pVCpu));
2440	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2441
2442	if (TRPMHasTrap(pVCpu))
2443	{
2444	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2445	uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
2446	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2447	{
2448	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2449	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2450	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2451	}
2452	}
2453	rc = VINF_EM_RESCHEDULE_REM;
2454	break;
2455
2456	/*
2457	* Other ring switch types.
2458	*/
2459	case VINF_EM_RAW_RING_SWITCH:
2460	rc = emR3RawRingSwitch(pVM, pVCpu);
2461	break;
2462
2463	/*
2464	* REMGCNotifyInvalidatePage() failed because of overflow.
2465	*/
2466	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2467	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2468	emR3RemLock(pVM);
2469	REMR3ReplayInvalidatedPages(pVM, pVCpu);
2470	emR3RemUnlock(pVM);
2471	rc = VINF_SUCCESS;
2472	break;
2473
2474	/*
2475	* I/O Port access - emulate the instruction.
2476	*/
2477	case VINF_IOM_HC_IOPORT_READ:
2478	case VINF_IOM_HC_IOPORT_WRITE:
2479	rc = emR3RawExecuteIOInstruction(pVM, pVCpu);
2480	break;
2481
2482	/*
2483	* Memory mapped I/O access - emulate the instruction.
2484	*/
2485	case VINF_IOM_HC_MMIO_READ:
2486	case VINF_IOM_HC_MMIO_WRITE:
2487	case VINF_IOM_HC_MMIO_READ_WRITE:
2488	rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
2489	break;
2490
2491	/*
2492	* (MM)IO intensive code block detected; fall back to the recompiler for better performance
2493	*/
2494	case VINF_EM_RAW_EMULATE_IO_BLOCK:
2495	rc = HWACCMR3EmulateIoBlock(pVM, pCtx);
2496	break;
2497
2498	/*
2499	* Execute instruction.
2500	*/
2501	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2502	rc = emR3RawExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
2503	break;
2504	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2505	rc = emR3RawExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
2506	break;
2507	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2508	rc = emR3RawExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
2509	break;
2510	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2511	rc = emR3RawExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
2512	break;
2513	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2514	rc = emR3RawExecuteInstruction(pVM, pVCpu, "PD FAULT: ");
2515	break;
2516
2517	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2518	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2519	rc = emR3RawPrivileged(pVM, pVCpu);
2520	break;
2521
2522	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2523	rc = emR3RawExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2524	break;
2525
2526	case VINF_EM_RAW_EMULATE_INSTR:
2527	case VINF_PATCH_EMULATE_INSTR:
2528	rc = emR3RawExecuteInstruction(pVM, pVCpu, "EMUL: ");
2529	break;
2530
2531	/*
2532	* Stale selector and iret traps => REM.
2533	*/
2534	case VINF_EM_RAW_STALE_SELECTOR:
2535	case VINF_EM_RAW_IRET_TRAP:
2536	/* We will not go to the recompiler if EIP points to patch code. */
2537	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2538	{
2539	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2540	}
2541	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
2542	rc = VINF_EM_RESCHEDULE_REM;
2543	break;
2544
2545	/*
2546	* Up a level.
2547	*/
2548	case VINF_EM_TERMINATE:
2549	case VINF_EM_OFF:
2550	case VINF_EM_RESET:
2551	case VINF_EM_SUSPEND:
2552	case VINF_EM_HALT:
2553	case VINF_EM_RESUME:
2554	case VINF_EM_NO_MEMORY:
2555	case VINF_EM_RESCHEDULE:
2556	case VINF_EM_RESCHEDULE_REM:
2557	break;
2558
2559	/*
2560	* Up a level and invoke the debugger.
2561	*/
2562	case VINF_EM_DBG_STEPPED:
2563	case VINF_EM_DBG_BREAKPOINT:
2564	case VINF_EM_DBG_STEP:
2565	case VINF_EM_DBG_HYPER_BREAKPOINT:
2566	case VINF_EM_DBG_HYPER_STEPPED:
2567	case VINF_EM_DBG_HYPER_ASSERTION:
2568	case VINF_EM_DBG_STOP:
2569	break;
2570
2571	/*
2572	* Up a level, dump and debug.
2573	*/
2574	case VERR_TRPM_DONT_PANIC:
2575	case VERR_TRPM_PANIC:
2576	case VERR_VMM_RING0_ASSERTION:
2577	break;
2578
2579	/*
2580	* Up a level, after HwAccM have done some release logging.
2581	*/
2582	case VERR_VMX_INVALID_VMCS_FIELD:
2583	case VERR_VMX_INVALID_VMCS_PTR:
2584	case VERR_VMX_INVALID_VMXON_PTR:
2585	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2586	case VERR_VMX_UNEXPECTED_EXCEPTION:
2587	case VERR_VMX_UNEXPECTED_EXIT_CODE:
2588	case VERR_VMX_INVALID_GUEST_STATE:
2589	case VERR_VMX_UNABLE_TO_START_VM:
2590	case VERR_VMX_UNABLE_TO_RESUME_VM:
2591	HWACCMR3CheckError(pVM, rc);
2592	break;
2593	/*
2594	* Anything which is not known to us means an internal error
2595	* and the termination of the VM!
2596	*/
2597	default:
2598	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
2599	break;
2600	}
2601	return rc;
2602	}
2603
2604
2605	/**
2606	* Check for pending raw actions
2607	*
2608	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
2609	* EM statuses.
2610	* @param pVM The VM to operate on.
2611	* @param pVCpu The VMCPU handle.
2612	*/
2613	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
2614	{
2615	return emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
2616	}
2617
2618
2619	/**
2620	* Process raw-mode specific forced actions.
2621	*
2622	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2623	*
2624	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
2625	* EM statuses.
2626	* @param pVM The VM handle.
2627	* @param pVCpu The VMCPU handle.
2628	* @param pCtx The guest CPUM register context.
2629	*/
2630	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2631	{
2632	/*
2633	* Note that the order is vitally important!
2634	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2635	*/
2636
2637
2638	/*
2639	* Sync selector tables.
2640	*/
2641	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
2642	{
2643	int rc = SELMR3UpdateFromCPUM(pVM, pVCpu);
2644	if (RT_FAILURE(rc))
2645	return rc;
2646	}
2647
2648	/*
2649	* Sync IDT.
2650	*
2651	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
2652	* and PGMShwModifyPage, so we're in for trouble if for instance a
2653	* PGMSyncCR3+pgmPoolClearAll is pending.
2654	*/
2655	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
2656	{
2657	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
2658	&& EMIsRawRing0Enabled(pVM)
2659	&& CSAMIsEnabled(pVM))
2660	{
2661	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2662	if (RT_FAILURE(rc))
2663	return rc;
2664	}
2665
2666	int rc = TRPMR3SyncIDT(pVM, pVCpu);
2667	if (RT_FAILURE(rc))
2668	return rc;
2669	}
2670
2671	/*
2672	* Sync TSS.
2673	*/
2674	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
2675	{
2676	int rc = SELMR3SyncTSS(pVM, pVCpu);
2677	if (RT_FAILURE(rc))
2678	return rc;
2679	}
2680
2681	/*
2682	* Sync page directory.
2683	*/
2684	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2685	{
2686	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2687	if (RT_FAILURE(rc))
2688	return rc;
2689
2690	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
2691
2692	/* Prefetch pages for EIP and ESP. */
2693	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2694	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2695	if (rc == VINF_SUCCESS)
2696	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2697	if (rc != VINF_SUCCESS)
2698	{
2699	if (rc != VINF_PGM_SYNC_CR3)
2700	{
2701	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
2702	return rc;
2703	}
2704	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2705	if (RT_FAILURE(rc))
2706	return rc;
2707	}
2708	/** @todo maybe prefetch the supervisor stack page as well */
2709	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
2710	}
2711
2712	/*
2713	* Allocate handy pages (just in case the above actions have consumed some pages).
2714	*/
2715	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
2716	{
2717	int rc = PGMR3PhysAllocateHandyPages(pVM);
2718	if (RT_FAILURE(rc))
2719	return rc;
2720	}
2721
2722	/*
2723	* Check whether we're out of memory now.
2724	*
2725	* This may stem from some of the above actions or operations that has been executed
2726	* since we ran FFs. The allocate handy pages must for instance always be followed by
2727	* this check.
2728	*/
2729	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2730	return VINF_EM_NO_MEMORY;
2731
2732	return VINF_SUCCESS;
2733	}
2734
2735
2736	/**
2737	* Executes raw code.
2738	*
2739	* This function contains the raw-mode version of the inner
2740	* execution loop (the outer loop being in EMR3ExecuteVM()).
2741	*
2742	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2743	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2744	*
2745	* @param pVM VM handle.
2746	* @param pVCpu VMCPU handle.
2747	* @param pfFFDone Where to store an indicator telling whether or not
2748	* FFs were done before returning.
2749	*/
2750	static int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
2751	{
2752	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
2753
2754	int rc = VERR_INTERNAL_ERROR;
2755	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
2756	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2757	pVCpu->em.s.fForceRAW = false;
2758	*pfFFDone = false;
2759
2760
2761	/*
2762	*
2763	* Spin till we get a forced action or raw mode status code resulting in
2764	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2765	*
2766	*/
2767	for (;;)
2768	{
2769	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
2770
2771	/*
2772	* Check various preconditions.
2773	*/
2774	#ifdef VBOX_STRICT
2775	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
2776	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2777	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2778	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2779	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2780	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
2781	&& PGMMapHasConflicts(pVM))
2782	{
2783	PGMMapCheck(pVM);
2784	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2785	return VERR_INTERNAL_ERROR;
2786	}
2787	#endif /* VBOX_STRICT */
2788
2789	/*
2790	* Process high priority pre-execution raw-mode FFs.
2791	*/
2792	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
2793	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2794	{
2795	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
2796	if (rc != VINF_SUCCESS)
2797	break;
2798	}
2799
2800	/*
2801	* If we're going to execute ring-0 code, the guest state needs to
2802	* be modified a bit and some of the state components (IF, SS/CS RPL,
2803	* and perhaps EIP) needs to be stored with PATM.
2804	*/
2805	rc = CPUMRawEnter(pVCpu, NULL);
2806	if (rc != VINF_SUCCESS)
2807	{
2808	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
2809	break;
2810	}
2811
2812	/*
2813	* Scan code before executing it. Don't bother with user mode or V86 code
2814	*/
2815	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2816	&& !pCtx->eflags.Bits.u1VM
2817	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2818	{
2819	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
2820	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2821	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
2822	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
2823	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2824	{
2825	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
2826	if (rc != VINF_SUCCESS)
2827	{
2828	rc = CPUMRawLeave(pVCpu, NULL, rc);
2829	break;
2830	}
2831	}
2832	}
2833
2834	#ifdef LOG_ENABLED
2835	/*
2836	* Log important stuff before entering GC.
2837	*/
2838	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2839	if (pCtx->eflags.Bits.u1VM)
2840	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2841	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2842	{
2843	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2844	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2845	}
2846	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2847	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2848	#endif /* LOG_ENABLED */
2849
2850
2851
2852	/*
2853	* Execute the code.
2854	*/
2855	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
2856	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
2857	VMMR3Unlock(pVM);
2858	rc = VMMR3RawRunGC(pVM, pVCpu);
2859	VMMR3Lock(pVM);
2860	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
2861	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
2862
2863	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2864	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
2865
2866
2867
2868	/*
2869	* Restore the real CPU state and deal with high priority post
2870	* execution FFs before doing anything else.
2871	*/
2872	rc = CPUMRawLeave(pVCpu, NULL, rc);
2873	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
2874	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
2875	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
2876	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
2877
2878	#ifdef VBOX_STRICT
2879	/*
2880	* Assert TSS consistency & rc vs patch code.
2881	*/
2882	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2883	&& EMIsRawRing0Enabled(pVM))
2884	SELMR3CheckTSS(pVM);
2885	switch (rc)
2886	{
2887	case VINF_SUCCESS:
2888	case VINF_EM_RAW_INTERRUPT:
2889	case VINF_PATM_PATCH_TRAP_PF:
2890	case VINF_PATM_PATCH_TRAP_GP:
2891	case VINF_PATM_PATCH_INT3:
2892	case VINF_PATM_CHECK_PATCH_PAGE:
2893	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2894	case VINF_EM_RAW_GUEST_TRAP:
2895	case VINF_EM_RESCHEDULE_RAW:
2896	break;
2897
2898	default:
2899	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2900	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
2901	break;
2902	}
2903	/*
2904	* Let's go paranoid!
2905	*/
2906	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
2907	&& PGMMapHasConflicts(pVM))
2908	{
2909	PGMMapCheck(pVM);
2910	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
2911	return VERR_INTERNAL_ERROR;
2912	}
2913	#endif /* VBOX_STRICT */
2914
2915	/*
2916	* Process the returned status code.
2917	*/
2918	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2919	{
2920	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
2921	break;
2922	}
2923	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
2924	if (rc != VINF_SUCCESS)
2925	{
2926	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
2927	if (rc != VINF_SUCCESS)
2928	{
2929	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
2930	break;
2931	}
2932	}
2933
2934	/*
2935	* Check and execute forced actions.
2936	*/
2937	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2938	TMTimerPoll(pVM);
2939	#endif
2940	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
2941	if ( VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
2942	\|\| VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2943	{
2944	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2945
2946	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
2947	rc = emR3ForcedActions(pVM, pVCpu, rc);
2948	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
2949	if ( rc != VINF_SUCCESS
2950	&& rc != VINF_EM_RESCHEDULE_RAW)
2951	{
2952	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
2953	if (rc != VINF_SUCCESS)
2954	{
2955	*pfFFDone = true;
2956	break;
2957	}
2958	}
2959	}
2960	}
2961
2962	/*
2963	* Return to outer loop.
2964	*/
2965	#if defined(LOG_ENABLED) && defined(DEBUG)
2966	RTLogFlush(NULL);
2967	#endif
2968	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
2969	return rc;
2970	}
2971
2972
2973	/**
2974	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2975	*
2976	* This function contains the raw-mode version of the inner
2977	* execution loop (the outer loop being in EMR3ExecuteVM()).
2978	*
2979	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2980	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2981	*
2982	* @param pVM VM handle.
2983	* @param pVCpu VMCPU handle.
2984	* @param pfFFDone Where to store an indicator telling whether or not
2985	* FFs were done before returning.
2986	*/
2987	static int emR3HwAccExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
2988	{
2989	int rc = VERR_INTERNAL_ERROR;
2990	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
2991
2992	LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
2993	*pfFFDone = false;
2994
2995	STAM_COUNTER_INC(&pVCpu->em.s.StatHwAccExecuteEntry);
2996
2997	#ifdef EM_NOTIFY_HWACCM
2998	HWACCMR3NotifyScheduled(pVCpu);
2999	#endif
3000
3001	/*
3002	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
3003	*/
3004	for (;;)
3005	{
3006	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHwAccEntry, a);
3007
3008	/*
3009	* Process high priority pre-execution raw-mode FFs.
3010	*/
3011	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
3012	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
3013	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
3014	{
3015	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
3016	if (rc != VINF_SUCCESS)
3017	break;
3018	}
3019
3020	#ifdef LOG_ENABLED
3021	/*
3022	* Log important stuff before entering GC.
3023	*/
3024	if (TRPMHasTrap(pVCpu))
3025	Log(("Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
3026
3027	uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
3028	if (pCtx->eflags.Bits.u1VM)
3029	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
3030	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
3031	Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
3032	else
3033	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
3034	#endif /* LOG_ENABLED */
3035
3036	/*
3037	* Execute the code.
3038	*/
3039	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHwAccEntry, a);
3040	STAM_PROFILE_START(&pVCpu->em.s.StatHwAccExec, x);
3041	VMMR3Unlock(pVM);
3042	rc = VMMR3HwAccRunGC(pVM, pVCpu);
3043	VMMR3Lock(pVM);
3044	STAM_PROFILE_STOP(&pVCpu->em.s.StatHwAccExec, x);
3045
3046	/*
3047	* Deal with high priority post execution FFs before doing anything else.
3048	*/
3049	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
3050	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
3051	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
3052	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
3053
3054	/*
3055	* Process the returned status code.
3056	*/
3057	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
3058	break;
3059
3060	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
3061	if (rc != VINF_SUCCESS)
3062	break;
3063
3064	/*
3065	* Check and execute forced actions.
3066	*/
3067	#ifdef VBOX_HIGH_RES_TIMERS_HACK
3068	TMTimerPoll(pVM);
3069	#endif
3070	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
3071	{
3072	rc = emR3ForcedActions(pVM, pVCpu, rc);
3073	if ( rc != VINF_SUCCESS
3074	&& rc != VINF_EM_RESCHEDULE_HWACC)
3075	{
3076	*pfFFDone = true;
3077	break;
3078	}
3079	}
3080	}
3081
3082	/*
3083	* Return to outer loop.
3084	*/
3085	#if defined(LOG_ENABLED) && defined(DEBUG)
3086	RTLogFlush(NULL);
3087	#endif
3088	return rc;
3089	}
3090
3091
3092	/**
3093	* Decides whether to execute RAW, HWACC or REM.
3094	*
3095	* @returns new EM state
3096	* @param pVM The VM.
3097	* @param pVCpu The VMCPU handle.
3098	* @param pCtx The CPU context.
3099	*/
3100	static EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3101	{
3102	/*
3103	* When forcing raw-mode execution, things are simple.
3104	*/
3105	if (pVCpu->em.s.fForceRAW)
3106	return EMSTATE_RAW;
3107
3108	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
3109	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
3110	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
3111
3112	X86EFLAGS EFlags = pCtx->eflags;
3113	if (HWACCMIsEnabled(pVM))
3114	{
3115	/* Hardware accelerated raw-mode:
3116	*
3117	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
3118	*/
3119	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
3120	return EMSTATE_HWACC;
3121
3122	/* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
3123	* off monitoring features essential for raw mode! */
3124	return EMSTATE_REM;
3125	}
3126
3127	/*
3128	* Standard raw-mode:
3129	*
3130	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
3131	* or 32 bits protected mode ring 0 code
3132	*
3133	* The tests are ordered by the likelyhood of being true during normal execution.
3134	*/
3135	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
3136	{
3137	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
3138	return EMSTATE_REM;
3139	}
3140
3141	#ifndef VBOX_RAW_V86
3142	if (EFlags.u32 & X86_EFL_VM) {
3143	Log2(("raw mode refused: VM_MASK\n"));
3144	return EMSTATE_REM;
3145	}
3146	#endif
3147
3148	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
3149	uint32_t u32CR0 = pCtx->cr0;
3150	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
3151	{
3152	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
3153	return EMSTATE_REM;
3154	}
3155
3156	if (pCtx->cr4 & X86_CR4_PAE)
3157	{
3158	uint32_t u32Dummy, u32Features;
3159
3160	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3161	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3162	return EMSTATE_REM;
3163	}
3164
3165	unsigned uSS = pCtx->ss;
3166	if ( pCtx->eflags.Bits.u1VM
3167	\|\| (uSS & X86_SEL_RPL) == 3)
3168	{
3169	if (!EMIsRawRing3Enabled(pVM))
3170	return EMSTATE_REM;
3171
3172	if (!(EFlags.u32 & X86_EFL_IF))
3173	{
3174	Log2(("raw mode refused: IF (RawR3)\n"));
3175	return EMSTATE_REM;
3176	}
3177
3178	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
3179	{
3180	Log2(("raw mode refused: CR0.WP + RawR0\n"));
3181	return EMSTATE_REM;
3182	}
3183	}
3184	else
3185	{
3186	if (!EMIsRawRing0Enabled(pVM))
3187	return EMSTATE_REM;
3188
3189	/* Only ring 0 supervisor code. */
3190	if ((uSS & X86_SEL_RPL) != 0)
3191	{
3192	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
3193	return EMSTATE_REM;
3194	}
3195
3196	// Let's start with pure 32 bits ring 0 code first
3197	/** @todo What's pure 32-bit mode? flat? */
3198	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
3199	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
3200	{
3201	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
3202	return EMSTATE_REM;
3203	}
3204
3205	/* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
3206	if (!(u32CR0 & X86_CR0_WP))
3207	{
3208	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
3209	return EMSTATE_REM;
3210	}
3211
3212	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
3213	{
3214	Log2(("raw r0 mode forced: patch code\n"));
3215	return EMSTATE_RAW;
3216	}
3217
3218	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
3219	if (!(EFlags.u32 & X86_EFL_IF))
3220	{
3221	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
3222	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
3223	return EMSTATE_REM;
3224	}
3225	#endif
3226
3227	/** @todo still necessary??? */
3228	if (EFlags.Bits.u2IOPL != 0)
3229	{
3230	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
3231	return EMSTATE_REM;
3232	}
3233	}
3234
3235	Assert(PGMPhysIsA20Enabled(pVCpu));
3236	return EMSTATE_RAW;
3237	}
3238
3239
3240	/**
3241	* Executes all high priority post execution force actions.
3242	*
3243	* @returns rc or a fatal status code.
3244	*
3245	* @param pVM VM handle.
3246	* @param pVCpu VMCPU handle.
3247	* @param rc The current rc.
3248	*/
3249	static int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
3250	{
3251	if (VM_FF_ISPENDING(pVM, VM_FF_PDM_CRITSECT))
3252	PDMR3CritSectFF(pVM);
3253
3254	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
3255	CSAMR3DoPendingAction(pVM, pVCpu);
3256
3257	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3258	{
3259	if ( rc > VINF_EM_NO_MEMORY
3260	&& rc <= VINF_EM_LAST)
3261	rc = VINF_EM_NO_MEMORY;
3262	}
3263
3264	return rc;
3265	}
3266
3267
3268	/**
3269	* Executes all pending forced actions.
3270	*
3271	* Forced actions can cause execution delays and execution
3272	* rescheduling. The first we deal with using action priority, so
3273	* that for instance pending timers aren't scheduled and ran until
3274	* right before execution. The rescheduling we deal with using
3275	* return codes. The same goes for VM termination, only in that case
3276	* we exit everything.
3277	*
3278	* @returns VBox status code of equal or greater importance/severity than rc.
3279	* The most important ones are: VINF_EM_RESCHEDULE,
3280	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3281	*
3282	* @param pVM VM handle.
3283	* @param pVCpu VMCPU handle.
3284	* @param rc The current rc.
3285	*
3286	*/
3287	static int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
3288	{
3289	STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
3290	#ifdef VBOX_STRICT
3291	int rcIrq = VINF_SUCCESS;
3292	#endif
3293	int rc2;
3294	#define UPDATE_RC() \
3295	do { \
3296	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
3297	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
3298	break; \
3299	if (!rc \|\| rc2 < rc) \
3300	rc = rc2; \
3301	} while (0)
3302
3303	/*
3304	* Post execution chunk first.
3305	*/
3306	if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
3307	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
3308	{
3309	/*
3310	* Termination request.
3311	*/
3312	if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
3313	{
3314	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3315	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3316	return VINF_EM_TERMINATE;
3317	}
3318
3319	/*
3320	* Debugger Facility polling.
3321	*/
3322	if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
3323	{
3324	rc2 = DBGFR3VMMForcedAction(pVM);
3325	UPDATE_RC();
3326	}
3327
3328	/*
3329	* Postponed reset request.
3330	*/
3331	if (VM_FF_ISPENDING(pVM, VM_FF_RESET))
3332	{
3333	rc2 = VMR3Reset(pVM);
3334	UPDATE_RC();
3335	VM_FF_CLEAR(pVM, VM_FF_RESET);
3336	}
3337
3338	/*
3339	* CSAM page scanning.
3340	*/
3341	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3342	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
3343	{
3344	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
3345
3346	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3347	Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
3348
3349	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3350	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
3351	}
3352
3353	/*
3354	* Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
3355	*/
3356	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3357	{
3358	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3359	UPDATE_RC();
3360	if (rc == VINF_EM_NO_MEMORY)
3361	return rc;
3362	}
3363
3364	/* check that we got them all */
3365	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_PGM_NO_MEMORY)));
3366	Assert(!(VMCPU_FF_NORMAL_PRIORITY_POST_MASK & ~(VMCPU_FF_CSAM_SCAN_PAGE)));
3367	}
3368
3369	/*
3370	* Normal priority then.
3371	* (Executed in no particular order.)
3372	*/
3373	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
3374	{
3375	/*
3376	* PDM Queues are pending.
3377	*/
3378	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
3379	PDMR3QueueFlushAll(pVM);
3380
3381	/*
3382	* PDM DMA transfers are pending.
3383	*/
3384	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
3385	PDMR3DmaRun(pVM);
3386
3387	/*
3388	* Requests from other threads.
3389	*/
3390	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
3391	{
3392	rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY);
3393	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3394	{
3395	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
3396	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3397	return rc2;
3398	}
3399	UPDATE_RC();
3400	}
3401
3402	/* Replay the handler notification changes. */
3403	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
3404	{
3405	emR3RemLock(pVM);
3406	REMR3ReplayHandlerNotifications(pVM);
3407	emR3RemUnlock(pVM);
3408	}
3409
3410	/* check that we got them all */
3411	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY)));
3412	}
3413
3414	/*
3415	* Normal priority then. (per-VCPU)
3416	* (Executed in no particular order.)
3417	*/
3418	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3419	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
3420	{
3421	/*
3422	* Requests from other threads.
3423	*/
3424	if (VMCPU_FF_IS_PENDING_EXCEPT(pVCpu, VMCPU_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
3425	{
3426	rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu);
3427	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3428	{
3429	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
3430	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3431	return rc2;
3432	}
3433	UPDATE_RC();
3434	}
3435
3436	/* check that we got them all */
3437	Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
3438	}
3439
3440	/*
3441	* High priority pre execution chunk last.
3442	* (Executed in ascending priority order.)
3443	*/
3444	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
3445	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
3446	{
3447	/*
3448	* Timers before interrupts.
3449	*/
3450	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_TIMER, VM_FF_PGM_NO_MEMORY))
3451	TMR3TimerQueuesDo(pVM);
3452
3453	/*
3454	* The instruction following an emulated STI should always be executed!
3455	*/
3456	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3457	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3458	{
3459	Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
3460	if (CPUMGetGuestEIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
3461	{
3462	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3463	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3464	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3465	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3466	*/
3467	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3468	}
3469	if (HWACCMR3IsActive(pVM))
3470	rc2 = VINF_EM_RESCHEDULE_HWACC;
3471	else
3472	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3473
3474	UPDATE_RC();
3475	}
3476
3477	/*
3478	* Interrupts.
3479	*/
3480	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3481	&& !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
3482	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_HWACC)
3483	&& !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3484	&& PATMAreInterruptsEnabled(pVM)
3485	&& !HWACCMR3IsEventPending(pVM))
3486	{
3487	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC))
3488	{
3489	/* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3490	/** @todo this really isn't nice, should properly handle this */
3491	rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
3492	#ifdef VBOX_STRICT
3493	rcIrq = rc2;
3494	#endif
3495	UPDATE_RC();
3496	}
3497	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3498	else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
3499	{
3500	rc2 = VINF_EM_RESCHEDULE_REM;
3501	UPDATE_RC();
3502	}
3503	}
3504
3505	/*
3506	* Allocate handy pages.
3507	*/
3508	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
3509	{
3510	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3511	UPDATE_RC();
3512	}
3513
3514	/*
3515	* Debugger Facility request.
3516	*/
3517	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
3518	{
3519	rc2 = DBGFR3VMMForcedAction(pVM);
3520	UPDATE_RC();
3521	}
3522
3523	/*
3524	* Termination request.
3525	*/
3526	if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
3527	{
3528	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3529	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3530	return VINF_EM_TERMINATE;
3531	}
3532
3533	/*
3534	* Out of memory? Since most of our fellow high priority actions may cause us
3535	* to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
3536	* at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
3537	* than us since we can terminate without allocating more memory.
3538	*/
3539	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3540	{
3541	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3542	UPDATE_RC();
3543	if (rc == VINF_EM_NO_MEMORY)
3544	return rc;
3545	}
3546
3547	#ifdef DEBUG
3548	/*
3549	* Debug, pause the VM.
3550	*/
3551	if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
3552	{
3553	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3554	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3555	return VINF_EM_SUSPEND;
3556	}
3557
3558	#endif
3559	/* check that we got them all */
3560	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)));
3561	Assert(!(VMCPU_FF_HIGH_PRIORITY_PRE_MASK & ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_INHIBIT_INTERRUPTS)));
3562	}
3563
3564	#undef UPDATE_RC
3565	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
3566	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3567	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3568	return rc;
3569	}
3570
3571
3572	/**
3573	* Execute VM.
3574	*
3575	* This function is the main loop of the VM. The emulation thread
3576	* calls this function when the VM has been successfully constructed
3577	* and we're ready for executing the VM.
3578	*
3579	* Returning from this function means that the VM is turned off or
3580	* suspended (state already saved) and deconstruction in next in line.
3581	*
3582	* All interaction from other thread are done using forced actions
3583	* and signaling of the wait object.
3584	*
3585	* @returns VBox status code, informational status codes may indicate failure.
3586	* @param pVM The VM to operate on.
3587	* @param pVCpu The VMCPU to operate on.
3588	*/
3589	VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
3590	{
3591	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3592	pVCpu->em.s.enmState, EMR3GetStateName(pVCpu->em.s.enmState), pVCpu->em.s.fForceRAW));
3593	VM_ASSERT_EMT(pVM);
3594	Assert(pVCpu->em.s.enmState == EMSTATE_NONE \|\| pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
3595
3596	VMMR3Lock(pVM);
3597
3598	int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
3599	if (rc == 0)
3600	{
3601	/*
3602	* Start the virtual time.
3603	*/
3604	rc = TMVirtualResume(pVM);
3605	Assert(rc == VINF_SUCCESS);
3606	rc = TMCpuTickResume(pVCpu);
3607	Assert(rc == VINF_SUCCESS);
3608
3609	/*
3610	* The Outer Main Loop.
3611	*/
3612	bool fFFDone = false;
3613
3614	/* Reschedule right away to start in the right state. */
3615	rc = VINF_SUCCESS;
3616	pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
3617
3618	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
3619	for (;;)
3620	{
3621	/*
3622	* Before we can schedule anything (we're here because
3623	* scheduling is required) we must service any pending
3624	* forced actions to avoid any pending action causing
3625	* immediate rescheduling upon entering an inner loop
3626	*
3627	* Do forced actions.
3628	*/
3629	if ( !fFFDone
3630	&& rc != VINF_EM_TERMINATE
3631	&& rc != VINF_EM_OFF
3632	&& ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
3633	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK)))
3634	{
3635	rc = emR3ForcedActions(pVM, pVCpu, rc);
3636	if ( ( rc == VINF_EM_RESCHEDULE_REM
3637	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3638	&& pVCpu->em.s.fForceRAW)
3639	rc = VINF_EM_RESCHEDULE_RAW;
3640	}
3641	else if (fFFDone)
3642	fFFDone = false;
3643
3644	/*
3645	* Now what to do?
3646	*/
3647	Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
3648	switch (rc)
3649	{
3650	/*
3651	* Keep doing what we're currently doing.
3652	*/
3653	case VINF_SUCCESS:
3654	break;
3655
3656	/*
3657	* Reschedule - to raw-mode execution.
3658	*/
3659	case VINF_EM_RESCHEDULE_RAW:
3660	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVCpu->em.s.enmState, EMSTATE_RAW));
3661	pVCpu->em.s.enmState = EMSTATE_RAW;
3662	break;
3663
3664	/*
3665	* Reschedule - to hardware accelerated raw-mode execution.
3666	*/
3667	case VINF_EM_RESCHEDULE_HWACC:
3668	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVCpu->em.s.enmState, EMSTATE_HWACC));
3669	Assert(!pVCpu->em.s.fForceRAW);
3670	pVCpu->em.s.enmState = EMSTATE_HWACC;
3671	break;
3672
3673	/*
3674	* Reschedule - to recompiled execution.
3675	*/
3676	case VINF_EM_RESCHEDULE_REM:
3677	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVCpu->em.s.enmState, EMSTATE_REM));
3678	pVCpu->em.s.enmState = EMSTATE_REM;
3679	break;
3680
3681	#ifdef VBOX_WITH_VMI
3682	/*
3683	* Reschedule - parav call.
3684	*/
3685	case VINF_EM_RESCHEDULE_PARAV:
3686	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVCpu->em.s.enmState, EMSTATE_PARAV));
3687	pVCpu->em.s.enmState = EMSTATE_PARAV;
3688	break;
3689	#endif
3690
3691	/*
3692	* Resume.
3693	*/
3694	case VINF_EM_RESUME:
3695	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVCpu->em.s.enmState));
3696	/* fall through and get scheduled. */
3697
3698	/*
3699	* Reschedule.
3700	*/
3701	case VINF_EM_RESCHEDULE:
3702	{
3703	EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
3704	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3705	pVCpu->em.s.enmState = enmState;
3706	break;
3707	}
3708
3709	/*
3710	* Halted.
3711	*/
3712	case VINF_EM_HALT:
3713	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_HALTED));
3714	pVCpu->em.s.enmState = EMSTATE_HALTED;
3715	break;
3716
3717	/*
3718	* Suspend.
3719	*/
3720	case VINF_EM_SUSPEND:
3721	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
3722	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
3723	break;
3724
3725	/*
3726	* Reset.
3727	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3728	*/
3729	case VINF_EM_RESET:
3730	{
3731	if (pVCpu->idCpu == 0)
3732	{
3733	EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
3734	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3735	pVCpu->em.s.enmState = enmState;
3736	}
3737	else
3738	{
3739	/* All other VCPUs go into the halted state until woken up again. */
3740	pVCpu->em.s.enmState = EMSTATE_HALTED;
3741	}
3742	break;
3743	}
3744
3745	/*
3746	* Power Off.
3747	*/
3748	case VINF_EM_OFF:
3749	pVCpu->em.s.enmState = EMSTATE_TERMINATING;
3750	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
3751	TMVirtualPause(pVM);
3752	TMCpuTickPause(pVCpu);
3753	VMMR3Unlock(pVM);
3754	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3755	return rc;
3756
3757	/*
3758	* Terminate the VM.
3759	*/
3760	case VINF_EM_TERMINATE:
3761	pVCpu->em.s.enmState = EMSTATE_TERMINATING;
3762	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
3763	TMVirtualPause(pVM);
3764	TMCpuTickPause(pVCpu);
3765	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3766	return rc;
3767
3768
3769	/*
3770	* Out of memory, suspend the VM and stuff.
3771	*/
3772	case VINF_EM_NO_MEMORY:
3773	Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
3774	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
3775	TMVirtualPause(pVM);
3776	TMCpuTickPause(pVCpu);
3777	VMMR3Unlock(pVM);
3778	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3779
3780	rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
3781	N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
3782	if (rc != VINF_EM_SUSPEND)
3783	{
3784	if (RT_SUCCESS_NP(rc))
3785	{
3786	AssertLogRelMsgFailed(("%Rrc\n", rc));
3787	rc = VERR_EM_INTERNAL_ERROR;
3788	}
3789	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3790	}
3791	return rc;
3792
3793	/*
3794	* Guest debug events.
3795	*/
3796	case VINF_EM_DBG_STEPPED:
3797	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3798	case VINF_EM_DBG_STOP:
3799	case VINF_EM_DBG_BREAKPOINT:
3800	case VINF_EM_DBG_STEP:
3801	if (pVCpu->em.s.enmState == EMSTATE_RAW)
3802	{
3803	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3804	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3805	}
3806	else
3807	{
3808	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3809	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3810	}
3811	break;
3812
3813	/*
3814	* Hypervisor debug events.
3815	*/
3816	case VINF_EM_DBG_HYPER_STEPPED:
3817	case VINF_EM_DBG_HYPER_BREAKPOINT:
3818	case VINF_EM_DBG_HYPER_ASSERTION:
3819	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_HYPER));
3820	pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
3821	break;
3822
3823	/*
3824	* Guru mediations.
3825	*/
3826	case VERR_VMM_RING0_ASSERTION:
3827	Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
3828	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3829	break;
3830
3831	/*
3832	* Any error code showing up here other than the ones we
3833	* know and process above are considered to be FATAL.
3834	*
3835	* Unknown warnings and informational status codes are also
3836	* included in this.
3837	*/
3838	default:
3839	if (RT_SUCCESS_NP(rc))
3840	{
3841	AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
3842	rc = VERR_EM_INTERNAL_ERROR;
3843	}
3844	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3845	Log(("EMR3ExecuteVM returns %d\n", rc));
3846	break;
3847	}
3848
3849
3850	/*
3851	* Any waiters can now be woken up
3852	*/
3853	VMMR3Unlock(pVM);
3854	VMMR3Lock(pVM);
3855
3856	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
3857	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
3858
3859	/*
3860	* Act on the state.
3861	*/
3862	switch (pVCpu->em.s.enmState)
3863	{
3864	/*
3865	* Execute raw.
3866	*/
3867	case EMSTATE_RAW:
3868	rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
3869	break;
3870
3871	/*
3872	* Execute hardware accelerated raw.
3873	*/
3874	case EMSTATE_HWACC:
3875	rc = emR3HwAccExecute(pVM, pVCpu, &fFFDone);
3876	break;
3877
3878	/*
3879	* Execute recompiled.
3880	*/
3881	case EMSTATE_REM:
3882	rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
3883	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
3884	break;
3885
3886	#ifdef VBOX_WITH_VMI
3887	/*
3888	* Execute PARAV function.
3889	*/
3890	case EMSTATE_PARAV:
3891	rc = PARAVCallFunction(pVM);
3892	pVCpu->em.s.enmState = EMSTATE_REM;
3893	break;
3894	#endif
3895
3896	/*
3897	* hlt - execution halted until interrupt.
3898	*/
3899	case EMSTATE_HALTED:
3900	{
3901	STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
3902	rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
3903	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
3904	break;
3905	}
3906
3907	/*
3908	* Suspended - return to VM.cpp.
3909	*/
3910	case EMSTATE_SUSPENDED:
3911	TMVirtualPause(pVM);
3912	TMCpuTickPause(pVCpu);
3913	VMMR3Unlock(pVM);
3914	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3915	return VINF_EM_SUSPEND;
3916
3917	/*
3918	* Debugging in the guest.
3919	*/
3920	case EMSTATE_DEBUG_GUEST_REM:
3921	case EMSTATE_DEBUG_GUEST_RAW:
3922	TMVirtualPause(pVM);
3923	TMCpuTickPause(pVCpu);
3924	rc = emR3Debug(pVM, pVCpu, rc);
3925	TMVirtualResume(pVM);
3926	TMCpuTickResume(pVCpu);
3927	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
3928	break;
3929
3930	/*
3931	* Debugging in the hypervisor.
3932	*/
3933	case EMSTATE_DEBUG_HYPER:
3934	{
3935	TMVirtualPause(pVM);
3936	TMCpuTickPause(pVCpu);
3937	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3938
3939	rc = emR3Debug(pVM, pVCpu, rc);
3940	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
3941	if (rc != VINF_SUCCESS)
3942	{
3943	/* switch to guru meditation mode */
3944	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3945	VMMR3FatalDump(pVM, pVCpu, rc);
3946	return rc;
3947	}
3948
3949	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
3950	TMVirtualResume(pVM);
3951	TMCpuTickResume(pVCpu);
3952	break;
3953	}
3954
3955	/*
3956	* Guru meditation takes place in the debugger.
3957	*/
3958	case EMSTATE_GURU_MEDITATION:
3959	{
3960	TMVirtualPause(pVM);
3961	TMCpuTickPause(pVCpu);
3962	VMMR3FatalDump(pVM, pVCpu, rc);
3963	emR3Debug(pVM, pVCpu, rc);
3964	VMMR3Unlock(pVM);
3965	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3966	return rc;
3967	}
3968
3969	/*
3970	* The states we don't expect here.
3971	*/
3972	case EMSTATE_NONE:
3973	case EMSTATE_TERMINATING:
3974	default:
3975	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
3976	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3977	TMVirtualPause(pVM);
3978	TMCpuTickPause(pVCpu);
3979	VMMR3Unlock(pVM);
3980	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3981	return VERR_EM_INTERNAL_ERROR;
3982	}
3983	} /* The Outer Main Loop */
3984	}
3985	else
3986	{
3987	/*
3988	* Fatal error.
3989	*/
3990	LogFlow(("EMR3ExecuteVM: returns %Rrc (longjmp / fatal error)\n", rc));
3991	TMVirtualPause(pVM);
3992	TMCpuTickPause(pVCpu);
3993	VMMR3FatalDump(pVM, pVCpu, rc);
3994	emR3Debug(pVM, pVCpu, rc);
3995	VMMR3Unlock(pVM);
3996	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3997	/** @todo change the VM state! */
3998	return rc;
3999	}
4000
4001	/* (won't ever get here). */
4002	AssertFailed();
4003	}
4004

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 19322

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