EM.cpp@ 1939

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1	/* $Id: EM.cpp 1913 2007-04-04 08:26:18Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor/Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_em EM - The Execution Monitor/Manager
24	*
25	* The Execution Monitor/Manager is responsible for running the VM, scheduling
26	* the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27	* the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28	* the VM.
29	*
30	*/
31
32	/*******************************************************************************
33	* Header Files *
34	*******************************************************************************/
35	#define LOG_GROUP LOG_GROUP_EM
36	#include <VBox/em.h>
37	#include <VBox/vmm.h>
38	#include <VBox/patm.h>
39	#include <VBox/csam.h>
40	#include <VBox/selm.h>
41	#include <VBox/trpm.h>
42	#include <VBox/iom.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/pgm.h>
45	#include <VBox/rem.h>
46	#include <VBox/tm.h>
47	#include <VBox/mm.h>
48	#include <VBox/pdm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/patm.h>
51	#include "EMInternal.h"
52	#include <VBox/vm.h>
53	#include <VBox/cpumdis.h>
54	#include <VBox/dis.h>
55	#include <VBox/disopcode.h>
56	#include <VBox/dbgf.h>
57
58	#include <VBox/log.h>
59	#include <iprt/thread.h>
60	#include <iprt/assert.h>
61	#include <iprt/asm.h>
62	#include <iprt/semaphore.h>
63	#include <iprt/string.h>
64	#include <iprt/avl.h>
65	#include <iprt/stream.h>
66	#include <VBox/param.h>
67	#include <VBox/err.h>
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
74	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
75	static int emR3Debug(PVM pVM, int rc);
76	static int emR3RemStep(PVM pVM);
77	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
78	static int emR3RawResumeHyper(PVM pVM);
79	static int emR3RawStep(PVM pVM);
80	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
81	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
82	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
83	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
84	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
85	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
86	static int emR3ForcedActions(PVM pVM, int rc);
87	static int emR3RawGuestTrap(PVM pVM);
88
89
90	/**
91	* Initializes the EM.
92	*
93	* @returns VBox status code.
94	* @param pVM The VM to operate on.
95	*/
96	EMR3DECL(int) EMR3Init(PVM pVM)
97	{
98	LogFlow(("EMR3Init\n"));
99	/*
100	* Assert alignment and sizes.
101	*/
102	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
103	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
104	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
105	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
106
107	/*
108	* Init the structure.
109	*/
110	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
111	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
112	if (VBOX_FAILURE(rc))
113	pVM->fRawR3Enabled = true;
114	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
115	if (VBOX_FAILURE(rc))
116	pVM->fRawR0Enabled = true;
117	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
118	pVM->em.s.enmState = EMSTATE_NONE;
119	pVM->em.s.fForceRAW = false;
120
121	rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
122	AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
123	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
124	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
125
126	/*
127	* Saved state.
128	*/
129	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
130	NULL, emR3Save, NULL,
131	NULL, emR3Load, NULL);
132	if (VBOX_FAILURE(rc))
133	return rc;
134
135	/*
136	* Statistics.
137	*/
138	#ifdef VBOX_WITH_STATISTICS
139	PEMSTATS pStats;
140	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
141	if (VBOX_FAILURE(rc))
142	return rc;
143	pVM->em.s.pStatsHC = pStats;
144	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
145
146	STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
147	STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
148
149	STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
150	STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
151
152	STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
153	STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
154	STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
155	STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
156	STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
157	STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
158	STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
159	STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
160	STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
161	STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
162	STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
163	STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
164	STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
165	STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
185	//STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
196
197	STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
198	STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
199
200	STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
204	STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
205	STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
206	STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
207	STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
208	STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
237	//STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
238
239	STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
240	STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
241	STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
246	STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
247	STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
248	STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
249	STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
261
262	STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
263	STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
264	STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
265	STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
266
267	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
268	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
269	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
270	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
271	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
272	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
273	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
274	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
275	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
276	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
277	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
278	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
279	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
280	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
281	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
282	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
283	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
284	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
285	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
286	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
287	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
288	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
289	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
290	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
291	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
292	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
293
294	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
295	pVM->em.s.pCliStatTree = 0;
296	#endif /* VBOX_WITH_STATISTICS */
297
298	/* these should be considered for release statistics. */
299	STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
300	STAM_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
301	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
302	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
303	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
304	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
305	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
306	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
307	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
308	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
309	STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
310	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
311	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
312	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
313	STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
314	STAM_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
315
316
317	return VINF_SUCCESS;
318	}
319
320
321
322	/**
323	* Applies relocations to data and code managed by this
324	* component. This function will be called at init and
325	* whenever the VMM need to relocate it self inside the GC.
326	*
327	* @param pVM The VM.
328	*/
329	EMR3DECL(void) EMR3Relocate(PVM pVM)
330	{
331	LogFlow(("EMR3Relocate\n"));
332	if (pVM->em.s.pStatsHC)
333	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
334	}
335
336
337	/**
338	* Reset notification.
339	*
340	* @param pVM
341	*/
342	EMR3DECL(void) EMR3Reset(PVM pVM)
343	{
344	LogFlow(("EMR3Reset: \n"));
345	pVM->em.s.fForceRAW = false;
346	}
347
348
349	/**
350	* Terminates the EM.
351	*
352	* Termination means cleaning up and freeing all resources,
353	* the VM it self is at this point powered off or suspended.
354	*
355	* @returns VBox status code.
356	* @param pVM The VM to operate on.
357	*/
358	EMR3DECL(int) EMR3Term(PVM pVM)
359	{
360	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
361
362	return VINF_SUCCESS;
363	}
364
365
366	/**
367	* Execute state save operation.
368	*
369	* @returns VBox status code.
370	* @param pVM VM Handle.
371	* @param pSSM SSM operation handle.
372	*/
373	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
374	{
375	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
376	}
377
378
379	/**
380	* Execute state load operation.
381	*
382	* @returns VBox status code.
383	* @param pVM VM Handle.
384	* @param pSSM SSM operation handle.
385	* @param u32Version Data layout version.
386	*/
387	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
388	{
389	/*
390	* Validate version.
391	*/
392	if (u32Version != EM_SAVED_STATE_VERSION)
393	{
394	Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
395	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
396	}
397
398	/*
399	* Load the saved state.
400	*/
401	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
402	if (VBOX_FAILURE(rc))
403	pVM->em.s.fForceRAW = false;
404
405	Assert(pVM->em.s.pCliStatTree == 0);
406	return rc;
407	}
408
409
410	/**
411	* Enables or disables a set of raw-mode execution modes.
412	*
413	* @returns VINF_SUCCESS on success.
414	* @returns VINF_RESCHEDULE if a rescheduling might be required.
415	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
416	*
417	* @param pVM The VM to operate on.
418	* @param enmMode The execution mode change.
419	* @thread The emulation thread.
420	*/
421	EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
422	{
423	switch (enmMode)
424	{
425	case EMRAW_NONE:
426	pVM->fRawR3Enabled = false;
427	pVM->fRawR0Enabled = false;
428	break;
429	case EMRAW_RING3_ENABLE:
430	pVM->fRawR3Enabled = true;
431	break;
432	case EMRAW_RING3_DISABLE:
433	pVM->fRawR3Enabled = false;
434	break;
435	case EMRAW_RING0_ENABLE:
436	pVM->fRawR0Enabled = true;
437	break;
438	case EMRAW_RING0_DISABLE:
439	pVM->fRawR0Enabled = false;
440	break;
441	default:
442	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
443	return VERR_INVALID_PARAMETER;
444	}
445	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
446	pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
447	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
448	}
449
450
451	/**
452	* Raise a fatal error.
453	*
454	* Safely terminate the VM with full state report and stuff. This function
455	* will naturally never return.
456	*
457	* @param pVM VM handle.
458	* @param rc VBox status code.
459	*/
460	EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
461	{
462	longjmp(pVM->em.s.u.FatalLongJump, rc);
463	AssertReleaseMsgFailed(("longjmp returned!\n"));
464	}
465
466
467	/**
468	* Gets the EM state name.
469	*
470	* @returns pointer to read only state name,
471	* @param enmState The state.
472	*/
473	EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
474	{
475	switch (enmState)
476	{
477	case EMSTATE_RAW: return "EMSTATE_RAW";
478	case EMSTATE_HWACC: return "EMSTATE_HWACC";
479	case EMSTATE_REM: return "EMSTATE_REM";
480	case EMSTATE_HALTED: return "EMSTATE_HALTED";
481	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
482	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
483	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
484	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
485	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
486	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
487	default: return "Unknown!";
488	}
489	}
490
491
492	#ifdef VBOX_WITH_STATISTICS
493	/**
494	* Just a braindead function to keep track of cli addresses.
495	* @param pVM VM handle.
496	* @param pInstrGC The EIP of the cli instruction.
497	*/
498	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
499	{
500	PCLISTAT pRec;
501
502	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
503	if (!pRec)
504	{
505	/* New cli instruction; insert into the tree. */
506	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
507	Assert(pRec);
508	if (!pRec)
509	return;
510	pRec->Core.Key = (AVLPVKEY)pInstrGC;
511
512	char szCliStatName[32];
513	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
514	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
515
516	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
517	Assert(fRc); NOREF(fRc);
518	}
519	STAM_COUNTER_INC(&pRec->Counter);
520	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
521	}
522	#endif /* VBOX_WITH_STATISTICS */
523
524
525	/**
526	* Debug loop.
527	*
528	* @returns VBox status code for EM.
529	* @param pVM VM handle.
530	* @param rc Current EM VBox status code..
531	*/
532	static int emR3Debug(PVM pVM, int rc)
533	{
534	for (;;)
535	{
536	Log(("emR3Debug: rc=%Vrc\n", rc));
537	const int rcLast = rc;
538
539	/*
540	* Debug related RC.
541	*/
542	switch (rc)
543	{
544	/*
545	* Single step an instruction.
546	*/
547	case VINF_EM_DBG_STEP:
548	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
549	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
550	\|\| pVM->em.s.fForceRAW /* paranoia */)
551	rc = emR3RawStep(pVM);
552	else
553	{
554	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
555	rc = emR3RemStep(pVM);
556	}
557	break;
558
559	/*
560	* Simple events: stepped, breakpoint, stop/assertion.
561	*/
562	case VINF_EM_DBG_STEPPED:
563	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
564	break;
565
566	case VINF_EM_DBG_BREAKPOINT:
567	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
568	break;
569
570	case VINF_EM_DBG_STOP:
571	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
572	break;
573
574	case VINF_EM_DBG_HYPER_STEPPED:
575	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
576	break;
577
578	case VINF_EM_DBG_HYPER_BREAKPOINT:
579	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
580	break;
581
582	case VINF_EM_DBG_HYPER_ASSERTION:
583	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
584	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
585	break;
586
587	/*
588	* Guru meditation.
589	*/
590	default: /** @todo don't use default for guru, but make special errors code! */
591	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
592	break;
593	}
594
595	/*
596	* Process the result.
597	*/
598	do
599	{
600	switch (rc)
601	{
602	/*
603	* Continue the debugging loop.
604	*/
605	case VINF_EM_DBG_STEP:
606	case VINF_EM_DBG_STOP:
607	case VINF_EM_DBG_STEPPED:
608	case VINF_EM_DBG_BREAKPOINT:
609	case VINF_EM_DBG_HYPER_STEPPED:
610	case VINF_EM_DBG_HYPER_BREAKPOINT:
611	case VINF_EM_DBG_HYPER_ASSERTION:
612	break;
613
614	/*
615	* Resuming execution (in some form) has to be done here if we got
616	* a hypervisor debug event.
617	*/
618	case VINF_SUCCESS:
619	case VINF_EM_RESUME:
620	case VINF_EM_SUSPEND:
621	case VINF_EM_RESCHEDULE:
622	case VINF_EM_RESCHEDULE_RAW:
623	case VINF_EM_RESCHEDULE_REM:
624	case VINF_EM_HALT:
625	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
626	{
627	rc = emR3RawResumeHyper(pVM);
628	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
629	continue;
630	}
631	if (rc == VINF_SUCCESS)
632	rc = VINF_EM_RESCHEDULE;
633	return rc;
634
635	/*
636	* The debugger isn't attached.
637	* We'll simply turn the thing off since that's the easiest thing to do.
638	*/
639	case VERR_DBGF_NOT_ATTACHED:
640	switch (rcLast)
641	{
642	case VINF_EM_DBG_HYPER_ASSERTION:
643	case VINF_EM_DBG_HYPER_STEPPED:
644	case VINF_EM_DBG_HYPER_BREAKPOINT:
645	return rcLast;
646	}
647	return VINF_EM_OFF;
648
649	/*
650	* Status codes terminating the VM in one or another sense.
651	*/
652	case VINF_EM_TERMINATE:
653	case VINF_EM_OFF:
654	case VINF_EM_RESET:
655	case VINF_EM_RAW_STALE_SELECTOR:
656	case VINF_EM_RAW_IRET_TRAP:
657	case VERR_TRPM_PANIC:
658	case VERR_TRPM_DONT_PANIC:
659	case VERR_INTERNAL_ERROR:
660	return rc;
661
662	/*
663	* The rest is unexpected, and will keep us here.
664	*/
665	default:
666	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
667	break;
668	}
669	} while (false);
670	} /* debug for ever */
671	}
672
673
674	/**
675	* Steps recompiled code.
676	*
677	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
678	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
679	*
680	* @param pVM VM handle.
681	*/
682	static int emR3RemStep(PVM pVM)
683	{
684	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
685
686	/*
687	* Switch to REM, step instruction, switch back.
688	*/
689	int rc = REMR3State(pVM);
690	if (VBOX_SUCCESS(rc))
691	{
692	rc = REMR3Step(pVM);
693	REMR3StateBack(pVM);
694	}
695	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
696	return rc;
697	}
698
699	/**
700	* Executes recompiled code.
701	*
702	* This function contains the recompiler version of the inner
703	* execution loop (the outer loop being in EMR3ExecuteVM()).
704	*
705	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
706	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
707	*
708	* @param pVM VM handle.
709	* @param pfFFDone Where to store an indicator telling wheter or not
710	* FFs were done before returning.
711	*
712	*/
713	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
714	{
715	#ifdef LOG_ENABLED
716	PCPUMCTX pCtx = pVM->em.s.pCtx;
717	if (pCtx->eflags.Bits.u1VM)
718	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
719	else if ((pCtx->ss & X86_SEL_RPL) == 0)
720	Log(("EMR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
721	else if ((pCtx->ss & X86_SEL_RPL) == 3)
722	Log(("EMR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
723	#endif
724	STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
725
726	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
727	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
728	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
729	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
730	#endif
731
732	/*
733	* Spin till we get a forced action which returns anything but VINF_SUCCESS
734	* or the REM suggests raw-mode execution.
735	*/
736	*pfFFDone = false;
737	bool fInREMState = false;
738	int rc = VINF_SUCCESS;
739	for (;;)
740	{
741	/*
742	* Update REM state if not already in sync.
743	*/
744	if (!fInREMState)
745	{
746	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
747	rc = REMR3State(pVM);
748	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
749	if (VBOX_FAILURE(rc))
750	break;
751	fInREMState = true;
752
753	/*
754	* We might have missed the raising of VMREQ, TIMER and some other
755	* imporant FFs while we were busy switching the state. So, check again.
756	*/
757	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
758	{
759	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
760	goto l_REMDoForcedActions;
761	}
762	}
763
764
765	/*
766	* Execute REM.
767	*/
768	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
769	rc = REMR3Run(pVM);
770	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
771
772
773	/*
774	* Deal with high priority post execution FFs before doing anything else.
775	*/
776	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
777	rc = emR3HighPriorityPostForcedActions(pVM, rc);
778
779	/*
780	* Process the returned status code.
781	* (Try keep this short! Call functions!)
782	*/
783	if (rc != VINF_SUCCESS)
784	{
785	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
786	break;
787	if (rc != VINF_REM_INTERRUPED_FF)
788	{
789	/*
790	* Anything which is not known to us means an internal error
791	* and the termination of the VM!
792	*/
793	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
794	break;
795	}
796	}
797
798
799	/*
800	* Check and execute forced actions.
801	* Sync back the VM state before calling any of these.
802	*/
803	#ifdef VBOX_HIGH_RES_TIMERS_HACK
804	TMTimerPoll(pVM);
805	#endif
806	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
807	{
808	l_REMDoForcedActions:
809	if (fInREMState)
810	{
811	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
812	REMR3StateBack(pVM);
813	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
814	fInREMState = false;
815	}
816	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
817	rc = emR3ForcedActions(pVM, rc);
818	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
819	if ( rc != VINF_SUCCESS
820	&& rc != VINF_EM_RESCHEDULE_REM)
821	{
822	*pfFFDone = true;
823	break;
824	}
825	}
826
827	} /* The Inner Loop, recompiled execution mode version. */
828
829
830	/*
831	* Returning. Sync back the VM state if required.
832	*/
833	if (fInREMState)
834	{
835	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
836	REMR3StateBack(pVM);
837	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
838	}
839
840	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
841	return rc;
842	}
843
844
845	/**
846	* Resumes executing hypervisor after a debug event.
847	*
848	* This is kind of special since our current guest state is
849	* potentially out of sync.
850	*
851	* @returns VBox status code.
852	* @param pVM The VM handle.
853	*/
854	static int emR3RawResumeHyper(PVM pVM)
855	{
856	int rc;
857	PCPUMCTX pCtx = pVM->em.s.pCtx;
858	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
859	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
860
861	/*
862	* Resume execution.
863	*/
864	CPUMRawEnter(pVM, NULL);
865	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
866	rc = VMMR3ResumeHyper(pVM);
867	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
868	rc = CPUMRawLeave(pVM, NULL, rc);
869	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
870
871	/*
872	* Deal with the return code.
873	*/
874	rc = emR3HighPriorityPostForcedActions(pVM, rc);
875	rc = emR3RawHandleRC(pVM, pCtx, rc);
876	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
877	return rc;
878	}
879
880
881	/**
882	* Steps rawmode.
883	*
884	* @returns VBox status code.
885	* @param pVM The VM handle.
886	*/
887	static int emR3RawStep(PVM pVM)
888	{
889	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
890	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
891	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
892	int rc;
893	PCPUMCTX pCtx = pVM->em.s.pCtx;
894	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
895	#ifndef DEBUG_sandervl
896	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
897	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
898	#endif
899	if (fGuest)
900	{
901	/*
902	* Check vital forced actions, but ignore pending interrupts and timers.
903	*/
904	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
905	{
906	rc = emR3RawForcedActions(pVM, pCtx);
907	if (VBOX_FAILURE(rc))
908	return rc;
909	}
910
911	/*
912	* Set flags for single stepping.
913	*/
914	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
915	}
916	else
917	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
918
919	/*
920	* Single step.
921	* We do not start time or anything, if anything we should just do a few nanoseconds.
922	*/
923	CPUMRawEnter(pVM, NULL);
924	do
925	{
926	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
927	rc = VMMR3ResumeHyper(pVM);
928	else
929	rc = VMMR3RawRunGC(pVM);
930	#ifndef DEBUG_sandervl
931	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
932	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
933	#endif
934	} while ( rc == VINF_SUCCESS
935	\|\| rc == VINF_EM_RAW_INTERRUPT);
936	rc = CPUMRawLeave(pVM, NULL, rc);
937	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
938
939	/*
940	* Make sure the trap flag is cleared.
941	* (Too bad if the guest is trying to single step too.)
942	*/
943	if (fGuest)
944	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
945	else
946	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
947
948	/*
949	* Deal with the return codes.
950	*/
951	rc = emR3HighPriorityPostForcedActions(pVM, rc);
952	rc = emR3RawHandleRC(pVM, pCtx, rc);
953	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
954	return rc;
955	}
956
957	#ifdef DEBUG_sandervl
958	void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
959	{
960	EMSTATE enmOldState = pVM->em.s.enmState;
961	PCPUMCTX pCtx = pVM->em.s.pCtx;
962
963	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
964
965	Log(("Single step BEGIN:\n"));
966	for(uint32_t i=0;i<cIterations;i++)
967	{
968	DBGFR3PrgStep(pVM);
969	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
970	emR3RawStep(pVM);
971	}
972	Log(("Single step END:\n"));
973	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
974	pVM->em.s.enmState = enmOldState;
975	}
976
977	void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
978	{
979	EMSTATE enmOldState = pVM->em.s.enmState;
980	PCPUMCTX pCtx = pVM->em.s.pCtx;
981
982	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
983
984	Log(("Single step BEGIN:\n"));
985	for(uint32_t i=0;i<cIterations;i++)
986	{
987	DBGFR3PrgStep(pVM);
988	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
989	emR3RemStep(pVM);
990	}
991	Log(("Single step END:\n"));
992	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
993	pVM->em.s.enmState = enmOldState;
994	}
995	#endif
996
997	/**
998	* Executes one (or perhaps a few more) instruction(s).
999	*
1000	* @returns VBox status code suitable for EM.
1001	*
1002	* @param pVM VM handle.
1003	* @param rcGC GC return code
1004	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1005	* instruction and prefix the log output with this text.
1006	*/
1007	#ifdef LOG_ENABLED
1008	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1009	#else
1010	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1011	#endif
1012	{
1013	PCPUMCTX pCtx = pVM->em.s.pCtx;
1014	int rc;
1015
1016	/*
1017	*
1018	* The simple solution is to use the recompiler.
1019	* The better solution is to disassemble the current instruction and
1020	* try handle as many as possible without using REM.
1021	*
1022	*/
1023
1024	#ifdef LOG_ENABLED
1025	/*
1026	* Disassemble the instruction if requested.
1027	*/
1028	if (pszPrefix)
1029	{
1030	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1031	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1032	}
1033	#endif /* LOG_ENABLED */
1034
1035
1036	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
1037
1038	/*
1039	* PATM is making life more interesting.
1040	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1041	* tell PATM there is a trap in this code and have it take the appropriate actions
1042	* to allow us execute the code in REM.
1043	*/
1044	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1045	{
1046	Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
1047
1048	RTGCPTR pNewEip;
1049	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1050	switch (rc)
1051	{
1052	/*
1053	* It's not very useful to emulate a single instruction and then go back to raw
1054	* mode; just execute the whole block until IF is set again.
1055	*/
1056	case VINF_SUCCESS:
1057	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1058	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1059	pCtx->eip = pNewEip;
1060	Assert(pCtx->eip);
1061
1062	if (pCtx->eflags.Bits.u1IF)
1063	{
1064	/*
1065	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1066	*/
1067	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1068	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1069	}
1070	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1071	{
1072	/* special case: iret, that sets IF, detected a pending irq/event */
1073	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1074	}
1075	return VINF_EM_RESCHEDULE_REM;
1076
1077	/*
1078	* One instruction.
1079	*/
1080	case VINF_PATCH_EMULATE_INSTR:
1081	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1082	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1083	pCtx->eip = pNewEip;
1084	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1085
1086	/*
1087	* The patch was disabled, hand it to the REM.
1088	*/
1089	case VERR_PATCH_DISABLED:
1090	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1091	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1092	pCtx->eip = pNewEip;
1093	if (pCtx->eflags.Bits.u1IF)
1094	{
1095	/*
1096	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1097	*/
1098	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1099	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1100	}
1101	return VINF_EM_RESCHEDULE_REM;
1102
1103	/* Force continued patch exection; usually due to write monitored stack. */
1104	case VINF_PATCH_CONTINUE:
1105	return VINF_SUCCESS;
1106
1107	default:
1108	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1109	return VERR_INTERNAL_ERROR;
1110	}
1111	}
1112
1113	#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1114	DISCPUSTATE Cpu;
1115	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1116	if (VBOX_SUCCESS(rc))
1117	{
1118	uint32_t size;
1119
1120	switch (Cpu.pCurInstr->opcode)
1121	{
1122	case OP_MOV:
1123	case OP_AND:
1124	case OP_OR:
1125	case OP_XOR:
1126	case OP_POP:
1127	case OP_INC:
1128	case OP_DEC:
1129	case OP_XCHG:
1130	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1131	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1132	if (VBOX_SUCCESS(rc))
1133	{
1134	pCtx->eip += Cpu.opsize;
1135	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1136	return rc;
1137	}
1138	if (rc != VERR_EM_INTERPRETER)
1139	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1140	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1141	break;
1142	}
1143	}
1144	#endif
1145	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1146	rc = REMR3EmulateInstruction(pVM);
1147	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1148
1149	return rc;
1150	}
1151
1152
1153	/**
1154	* Executes one (or perhaps a few more) instruction(s).
1155	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1156	*
1157	* @returns VBox status code suitable for EM.
1158	* @param pVM VM handle.
1159	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1160	* instruction and prefix the log output with this text.
1161	* @param rcGC GC return code
1162	*/
1163	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1164	{
1165	#ifdef LOG_ENABLED
1166	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1167	#else
1168	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1169	#endif
1170	}
1171
1172	/**
1173	* Executes one (or perhaps a few more) IO instruction(s).
1174	*
1175	* @returns VBox status code suitable for EM.
1176	* @param pVM VM handle.
1177	*/
1178	int emR3RawExecuteIOInstruction(PVM pVM)
1179	{
1180	int rc;
1181	PCPUMCTX pCtx = pVM->em.s.pCtx;
1182
1183	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1184
1185	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1186	* as io instructions tend to come in packages of more than one
1187	*/
1188	DISCPUSTATE Cpu;
1189	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1190	if (VBOX_SUCCESS(rc))
1191	{
1192	#ifdef VBOX_WITH_STATISTICS
1193	switch (Cpu.pCurInstr->opcode)
1194	{
1195	case OP_INSB:
1196	case OP_INSWD:
1197	case OP_IN:
1198	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1199	break;
1200
1201	case OP_OUTSB:
1202	case OP_OUTSWD:
1203	case OP_OUT:
1204	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1205	break;
1206	}
1207	#endif
1208
1209	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1210	{
1211	OP_PARAMVAL ParmVal;
1212	int rc;
1213	switch (Cpu.pCurInstr->opcode)
1214	{
1215	case OP_IN:
1216	{
1217	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal, PARAM_SOURCE);
1218	if ( VBOX_FAILURE(rc)
1219	\|\| ParmVal.type != PARMTYPE_IMMEDIATE)
1220	break;
1221
1222	if (!(Cpu.param1.flags & (USE_REG_GEN8 \| USE_REG_GEN16 \| USE_REG_GEN32)))
1223	break;
1224
1225	/* Make sure port access is allowed */
1226	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1227	if (rc != VINF_SUCCESS)
1228	{
1229	if (rc == VINF_EM_RAW_GUEST_TRAP)
1230	rc = emR3RawGuestTrap(pVM);
1231
1232	return rc;
1233	}
1234
1235	uint32_t u32Value = 0;
1236	switch (Cpu.param1.size)
1237	{
1238	case 1:
1239	Assert(Cpu.param1.base.reg_gen8 == USE_REG_AL);
1240	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint8_t));
1241	if (VBOX_SUCCESS(rc))
1242	{
1243	pCtx->eax = (pCtx->eax & ~0xFF) \| (uint8_t)u32Value;
1244	Log(("EMU: in8 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFF));
1245	pCtx->eip += Cpu.opsize;
1246	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1247	return rc;
1248	}
1249	AssertRC(rc);
1250	break;
1251
1252	case 2:
1253	Assert(Cpu.param1.base.reg_gen16 == USE_REG_AX);
1254	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint16_t));
1255	if (VBOX_SUCCESS(rc))
1256	{
1257	pCtx->eax = (pCtx->eax & ~0xFFFF) \| (uint16_t)u32Value;
1258	Log(("EMU: in16 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFFFF));
1259	pCtx->eip += Cpu.opsize;
1260	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1261	return rc;
1262	}
1263	AssertRC(rc);
1264	break;
1265
1266	case 4:
1267	Assert(Cpu.param1.base.reg_gen32 == USE_REG_EAX);
1268	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint32_t));
1269	if (VBOX_SUCCESS(rc))
1270	{
1271	pCtx->eax = u32Value;
1272	Log(("EMU: in32 %x, %x\n", ParmVal.val.val16, pCtx->eax));
1273	pCtx->eip += Cpu.opsize;
1274	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1275	return rc;
1276	}
1277	AssertRC(rc);
1278	break;
1279
1280	default:
1281	AssertMsgFailed(("Unexpected port size %d\n", ParmVal.size));
1282	break;
1283	}
1284	break;
1285	}
1286
1287	case OP_OUT:
1288	{
1289	// it really is the destination, but we're interested in the destination value. hence we specify PARAM_SOURCE (bit of a hack)
1290	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &ParmVal, PARAM_SOURCE);
1291	if ( VBOX_FAILURE(rc)
1292	\|\| ParmVal.type != PARMTYPE_IMMEDIATE)
1293	break;
1294	OP_PARAMVAL ParmVal2;
1295	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal2, PARAM_SOURCE);
1296	if ( VBOX_FAILURE(rc)
1297	\|\| ParmVal2.type != PARMTYPE_IMMEDIATE)
1298	break;
1299
1300	/* Make sure port access is allowed */
1301	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1302	if (rc != VINF_SUCCESS)
1303	{
1304	if (rc == VINF_EM_RAW_GUEST_TRAP)
1305	rc = emR3RawGuestTrap(pVM);
1306
1307	return rc;
1308	}
1309
1310	AssertMsg(Cpu.param2.size == ParmVal2.size, ("size %d vs %d\n", Cpu.param2.size, ParmVal2.size));
1311	switch (ParmVal2.size)
1312	{
1313	case 1:
1314	Log(("EMU: out8 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val8));
1315	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val8, sizeof(ParmVal2.val.val8));
1316	if (VBOX_SUCCESS(rc))
1317	{
1318	pCtx->eip += Cpu.opsize;
1319	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1320	return rc;
1321	}
1322	AssertRC(rc);
1323	break;
1324
1325	case 2:
1326	Log(("EMU: out16 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val16));
1327	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val16, sizeof(ParmVal2.val.val16));
1328	if (VBOX_SUCCESS(rc))
1329	{
1330	pCtx->eip += Cpu.opsize;
1331	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1332	return rc;
1333	}
1334	AssertRC(rc);
1335	break;
1336
1337	case 4:
1338	Log(("EMU: out32 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val32));
1339	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val32, sizeof(ParmVal2.val.val32));
1340	if (VBOX_SUCCESS(rc))
1341	{
1342	pCtx->eip += Cpu.opsize;
1343	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1344	return rc;
1345	}
1346	AssertRC(rc);
1347	break;
1348
1349	default:
1350	AssertMsgFailed(("Unexpected port size %d\n", ParmVal2.size));
1351	break;
1352	}
1353	break;
1354	}
1355
1356	default:
1357	break;
1358	}
1359	}//if(!(Cpu.prefix & (PREFIX_REP\|PREFIX_REPNE))
1360	else if (Cpu.prefix & PREFIX_REP)
1361	{
1362	switch (Cpu.pCurInstr->opcode)
1363	{
1364	case OP_INSB:
1365	case OP_INSWD:
1366	{
1367	/*
1368	* Do not optimize the destination address decrement case (not worth the effort)
1369	* and likewise for 16 bit address size (would need to use and update only cx/di).
1370	*/
1371	if (pCtx->eflags.Bits.u1DF \|\| Cpu.addrmode != CPUMODE_32BIT)
1372	break;
1373	/*
1374	* Get port number and transfer count directly from the registers (no need to bother the
1375	* disassembler). And get the I/O register size from the opcode / prefix.
1376	*/
1377	uint32_t uPort = pCtx->edx & 0xffff;
1378	RTGCUINTREG cTransfers = pCtx->ecx;
1379	unsigned cbUnit;
1380	if (Cpu.pCurInstr->opcode == OP_INSB)
1381	cbUnit = 1;
1382	else
1383	cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1384
1385	RTGCPTR GCPtrDst = pCtx->edi;
1386	uint32_t cpl = (pCtx->eflags.Bits.u1VM) ? 3 : (pCtx->ss & X86_SEL_RPL);
1387
1388	/* Access verification first; we can't recover from traps inside this instruction, as the port read cannot be repeated. */
1389	rc = PGMVerifyAccess(pVM, GCPtrDst, cTransfers * cbUnit,
1390	X86_PTE_RW \| ((cpl == 3) ? X86_PTE_US : 0));
1391	if (rc != VINF_SUCCESS)
1392	{
1393	Log(("EMU: rep ins%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1394	break;
1395	}
1396
1397	Log(("EMU: rep ins%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1398
1399	/* Make sure port access is allowed */
1400	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1401	if (rc != VINF_SUCCESS)
1402	{
1403	if (rc == VINF_EM_RAW_GUEST_TRAP)
1404	rc = emR3RawGuestTrap(pVM);
1405
1406	return rc;
1407	}
1408
1409	/*
1410	* If the device supports string transfers, ask it to do as
1411	* much as it wants. The rest is done with single-word transfers.
1412	*/
1413	rc = IOMIOPortReadString(pVM, uPort, &GCPtrDst, &cTransfers, cbUnit);
1414	AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1415
1416	while (cTransfers && rc == VINF_SUCCESS)
1417	{
1418	uint32_t u32Value;
1419	rc = IOMIOPortRead(pVM, uPort, &u32Value, cbUnit);
1420	AssertRC(rc);
1421	int rc2 = PGMPhysWriteGCPtrDirty(pVM, GCPtrDst, &u32Value, cbUnit);
1422	AssertRC(rc2);
1423	GCPtrDst += cbUnit;
1424	cTransfers--;
1425	}
1426	pCtx->edi += (pCtx->ecx - cTransfers) * cbUnit;
1427	pCtx->ecx = cTransfers;
1428	if (!cTransfers && VBOX_SUCCESS(rc))
1429	pCtx->eip += Cpu.opsize;
1430	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1431	return rc;
1432	}
1433	case OP_OUTSB:
1434	case OP_OUTSWD:
1435	{
1436	/*
1437	* Do not optimize the source address decrement case (not worth the effort)
1438	* and likewise for 16 bit address size (would need to use and update only cx/si).
1439	*/
1440	if (pCtx->eflags.Bits.u1DF \|\| Cpu.addrmode != CPUMODE_32BIT)
1441	break;
1442	/*
1443	* Get port number and transfer count directly from the registers (no need to bother the
1444	* disassembler). And get the I/O register size from the opcode / prefix.
1445	*/
1446	uint32_t uPort = pCtx->edx & 0xffff;
1447	RTGCUINTREG cTransfers = pCtx->ecx;
1448	unsigned cbUnit;
1449	if (Cpu.pCurInstr->opcode == OP_OUTSB)
1450	cbUnit = 1;
1451	else
1452	cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1453
1454	RTGCPTR GCPtrSrc = pCtx->esi;
1455	uint32_t cpl = (pCtx->eflags.Bits.u1VM) ? 3 : (pCtx->ss & X86_SEL_RPL);
1456
1457	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1458	rc = PGMVerifyAccess(pVM, GCPtrSrc, cTransfers * cbUnit, ((cpl == 3) ? X86_PTE_US : 0));
1459	if (rc != VINF_SUCCESS)
1460	{
1461	Log(("EMU: rep outs%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1462	break;
1463	}
1464
1465	Log(("EMU: rep outs%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1466
1467	/* Make sure port access is allowed */
1468	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1469	if (rc != VINF_SUCCESS)
1470	{
1471	if (rc == VINF_EM_RAW_GUEST_TRAP)
1472	rc = emR3RawGuestTrap(pVM);
1473
1474	return rc;
1475	}
1476
1477	/*
1478	* If the device supports string transfers, ask it to do as
1479	* much as it wants. The rest is done with single-word transfers.
1480	*/
1481	rc = IOMIOPortWriteString(pVM, uPort, &GCPtrSrc, &cTransfers, cbUnit);
1482	AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1483
1484	while (cTransfers && rc == VINF_SUCCESS)
1485	{
1486	uint32_t u32Value;
1487	rc = PGMPhysReadGCPtr(pVM, &u32Value, GCPtrSrc, cbUnit);
1488	Assert(rc == VINF_SUCCESS);
1489	rc = IOMIOPortWrite(pVM, uPort, u32Value, cbUnit);
1490	AssertRC(rc);
1491	GCPtrSrc += cbUnit;
1492	cTransfers--;
1493	}
1494	pCtx->esi += (pCtx->ecx - cTransfers) * cbUnit;
1495	pCtx->ecx = cTransfers;
1496	if (!cTransfers && VBOX_SUCCESS(rc))
1497	pCtx->eip += Cpu.opsize;
1498	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1499	return rc;
1500	}
1501	}
1502	}//if(Cpu.prefix & PREFIX_REP)
1503	}
1504
1505	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1506	return emR3RawExecuteInstruction(pVM, "IO: ");
1507	}
1508
1509
1510	/**
1511	* Handle a guest context trap.
1512	*
1513	* @returns VBox status code suitable for EM.
1514	* @param pVM VM handle.
1515	*/
1516	static int emR3RawGuestTrap(PVM pVM)
1517	{
1518	PCPUMCTX pCtx = pVM->em.s.pCtx;
1519
1520	/*
1521	* Get the trap info.
1522	*/
1523	uint8_t u8TrapNo;
1524	bool fSoftwareInterrupt;
1525	RTGCUINT uErrorCode;
1526	RTGCUINTPTR uCR2;
1527	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
1528	if (VBOX_FAILURE(rc))
1529	{
1530	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1531	return rc;
1532	}
1533
1534	/* Traps can be directly forwarded in hardware accelerated mode. */
1535	if (HWACCMR3IsActive(pVM))
1536	{
1537	#ifdef LOGGING_ENABLED
1538	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1539	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1540	#endif
1541	return VINF_EM_RESCHEDULE_HWACC;
1542	}
1543
1544	/** Scan kernel code that traps; we might not get another chance. */
1545	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1546	&& !pCtx->eflags.Bits.u1VM)
1547	{
1548	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1549	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
1550	}
1551
1552	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1553	{
1554	DISCPUSTATE cpu;
1555
1556	/* If MONITOR & MWAIT are supported, then interpret them here. */
1557	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1558	if ( VBOX_SUCCESS(rc)
1559	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1560	{
1561	uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1562
1563	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1564
1565	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1566	{
1567	rc = TRPMResetTrap(pVM);
1568	AssertRC(rc);
1569
1570	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1571	if (VBOX_SUCCESS(rc))
1572	{
1573	pCtx->eip += cpu.opsize;
1574	return rc;
1575	}
1576	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1577	}
1578	}
1579	}
1580	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1581	{
1582	DISCPUSTATE cpu;
1583
1584	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1585	if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1586	{
1587	/*
1588	* We should really check the TSS for the IO bitmap, but it's not like this
1589	* lazy approach really makes things worse.
1590	*/
1591	rc = TRPMResetTrap(pVM);
1592	AssertRC(rc);
1593	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1594	}
1595	}
1596
1597	#ifdef LOG_ENABLED
1598	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1599	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1600
1601	/* Get guest page information. */
1602	uint64_t fFlags = 0;
1603	RTGCPHYS GCPhys = 0;
1604	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1605	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1606	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, fSoftwareInterrupt ? " software" : "", GCPhys, fFlags,
1607	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1608	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1609	#endif
1610
1611	/*
1612	* #PG has CR2.
1613	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1614	*/
1615	if (u8TrapNo == 14 /* #PG */)
1616	pCtx->cr2 = uCR2;
1617
1618	return VINF_EM_RESCHEDULE_REM;
1619	}
1620
1621
1622	/**
1623	* Handle a ring switch trap.
1624	* Need to do statistics and to install patches. The result is going to REM.
1625	*
1626	* @returns VBox status code suitable for EM.
1627	* @param pVM VM handle.
1628	*/
1629	int emR3RawRingSwitch(PVM pVM)
1630	{
1631	int rc;
1632	DISCPUSTATE Cpu;
1633	PCPUMCTX pCtx = pVM->em.s.pCtx;
1634
1635	/*
1636	* sysenter, syscall & callgate
1637	*/
1638	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1639	if (VBOX_SUCCESS(rc))
1640	{
1641	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1642	{
1643	if (pCtx->SysEnter.cs != 0)
1644	{
1645	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1646	SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1647	if (VBOX_SUCCESS(rc))
1648	{
1649	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1650	return VINF_EM_RESCHEDULE_RAW;
1651	}
1652	}
1653	}
1654
1655	#ifdef VBOX_WITH_STATISTICS
1656	switch (Cpu.pCurInstr->opcode)
1657	{
1658	case OP_SYSENTER:
1659	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1660	break;
1661	case OP_SYSEXIT:
1662	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1663	break;
1664	case OP_SYSCALL:
1665	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1666	break;
1667	case OP_SYSRET:
1668	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1669	break;
1670	}
1671	#endif
1672	}
1673	else
1674	AssertRC(rc);
1675
1676	/* go to the REM to emulate a single instruction */
1677	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1678	}
1679
1680	/**
1681	* Handle a trap (#PF or #GP) in patch code
1682	*
1683	* @returns VBox status code suitable for EM.
1684	* @param pVM VM handle.
1685	* @param pCtx CPU context
1686	* @param gcret GC return code
1687	*/
1688	int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1689	{
1690	uint8_t u8TrapNo;
1691	int rc;
1692	bool fSoftwareInterrupt;
1693	RTGCUINT uErrorCode;
1694	RTGCUINTPTR uCR2;
1695
1696	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1697
1698	if (gcret == VINF_PATM_PATCH_INT3)
1699	{
1700	u8TrapNo = 3;
1701	uCR2 = 0;
1702	uErrorCode = 0;
1703	}
1704	else
1705	if (gcret == VINF_PATM_PATCH_TRAP_GP)
1706	{
1707	/* No active trap in this case. Kind of ugly. */
1708	u8TrapNo = X86_XCPT_GP;
1709	uCR2 = 0;
1710	uErrorCode = 0;
1711	}
1712	else
1713	{
1714	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
1715	if (VBOX_FAILURE(rc))
1716	{
1717	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1718	return rc;
1719	}
1720	/* Reset the trap as we'll execute the original instruction again. */
1721	TRPMResetTrap(pVM);
1722	}
1723
1724	/*
1725	* Deal with traps inside patch code.
1726	* (This code won't run outside GC.)
1727	*/
1728	if (u8TrapNo != 1)
1729	{
1730	#ifdef LOG_ENABLED
1731	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1732	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1733
1734	DISCPUSTATE Cpu;
1735	int rc;
1736
1737	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1738	if ( VBOX_SUCCESS(rc)
1739	&& Cpu.pCurInstr->opcode == OP_IRET)
1740	{
1741	uint32_t eip, selCS, uEFlags;
1742
1743	/* Iret crashes are bad as we have already changed the flags on the stack */
1744	rc = PGMPhysReadGCPtr(pVM, &eip, pCtx->esp, 4);
1745	rc \|= PGMPhysReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1746	rc \|= PGMPhysReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1747	if (rc == VINF_SUCCESS)
1748	{
1749	if ( (uEFlags & X86_EFL_VM)
1750	\|\| (selCS & X86_SEL_RPL) == 3)
1751	{
1752	uint32_t selSS, esp;
1753
1754	rc \|= PGMPhysReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1755	rc \|= PGMPhysReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1756
1757	if (uEFlags & X86_EFL_VM)
1758	{
1759	uint32_t selDS, selES, selFS, selGS;
1760	rc = PGMPhysReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1761	rc \|= PGMPhysReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1762	rc \|= PGMPhysReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1763	rc \|= PGMPhysReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1764	if (rc == VINF_SUCCESS)
1765	{
1766	Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1767	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1768	}
1769	}
1770	else
1771	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1772	}
1773	else
1774	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1775	}
1776	}
1777	#endif
1778	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1779	pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1780
1781	RTGCPTR pNewEip;
1782	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1783	switch (rc)
1784	{
1785	/*
1786	* Execute the faulting instruction.
1787	*/
1788	case VINF_SUCCESS:
1789	{
1790	/** @todo execute a whole block */
1791	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1792	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1793	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1794
1795	pCtx->eip = pNewEip;
1796	AssertRelease(pCtx->eip);
1797
1798	if (pCtx->eflags.Bits.u1IF)
1799	{
1800	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1801	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1802	*/
1803	if ( u8TrapNo == X86_XCPT_GP
1804	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1805	{
1806	/** @todo move to PATMR3HandleTrap */
1807	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1808	PATMR3RemovePatch(pVM, pCtx->eip);
1809	}
1810
1811	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1812	/** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1813
1814	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1815	/* Interrupts are enabled; just go back to the original instruction.
1816	return VINF_SUCCESS; */
1817	}
1818	return VINF_EM_RESCHEDULE_REM;
1819	}
1820
1821	/*
1822	* One instruction.
1823	*/
1824	case VINF_PATCH_EMULATE_INSTR:
1825	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1826	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1827	pCtx->eip = pNewEip;
1828	AssertRelease(pCtx->eip);
1829	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1830
1831	/*
1832	* The patch was disabled, hand it to the REM.
1833	*/
1834	case VERR_PATCH_DISABLED:
1835	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1836	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1837	pCtx->eip = pNewEip;
1838	AssertRelease(pCtx->eip);
1839
1840	if (pCtx->eflags.Bits.u1IF)
1841	{
1842	/*
1843	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1844	*/
1845	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1846	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1847	}
1848	return VINF_EM_RESCHEDULE_REM;
1849
1850	/* Force continued patch exection; usually due to write monitored stack. */
1851	case VINF_PATCH_CONTINUE:
1852	return VINF_SUCCESS;
1853
1854	/*
1855	* Anything else is fatal.
1856	*/
1857	default:
1858	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1859	return VERR_INTERNAL_ERROR;
1860	}
1861	}
1862	return VINF_SUCCESS;
1863	}
1864
1865
1866	/**
1867	* Handle a privileged instruction.
1868	*
1869	* @returns VBox status code suitable for EM.
1870	* @param pVM VM handle.
1871	*/
1872	int emR3RawPrivileged(PVM pVM)
1873	{
1874	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1875	PCPUMCTX pCtx = pVM->em.s.pCtx;
1876
1877	Assert(!pCtx->eflags.Bits.u1VM);
1878
1879	if (PATMIsEnabled(pVM))
1880	{
1881	/*
1882	* Check if in patch code.
1883	*/
1884	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1885	{
1886	#ifdef LOG_ENABLED
1887	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1888	#endif
1889	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1890	return VERR_EM_RAW_PATCH_CONFLICT;
1891	}
1892	if ( (pCtx->ss & X86_SEL_RPL) == 0
1893	&& !pCtx->eflags.Bits.u1VM
1894	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1895	{
1896	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1897	SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1898	if (VBOX_SUCCESS(rc))
1899	{
1900	#ifdef LOG_ENABLED
1901	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1902	#endif
1903	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1904	return VINF_SUCCESS;
1905	}
1906	}
1907	}
1908
1909	#ifdef LOG_ENABLED
1910	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1911	{
1912	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1913	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1914	}
1915	#endif
1916
1917	/*
1918	* Instruction statistics and logging.
1919	*/
1920	DISCPUSTATE Cpu;
1921	int rc;
1922
1923	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1924	if (VBOX_SUCCESS(rc))
1925	{
1926	#ifdef VBOX_WITH_STATISTICS
1927	PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1928	switch (Cpu.pCurInstr->opcode)
1929	{
1930	case OP_INVLPG:
1931	STAM_COUNTER_INC(&pStats->StatInvlpg);
1932	break;
1933	case OP_IRET:
1934	STAM_COUNTER_INC(&pStats->StatIret);
1935	break;
1936	case OP_CLI:
1937	STAM_COUNTER_INC(&pStats->StatCli);
1938	emR3RecordCli(pVM, pCtx->eip);
1939	break;
1940	case OP_STI:
1941	STAM_COUNTER_INC(&pStats->StatSti);
1942	break;
1943	case OP_INSB:
1944	case OP_INSWD:
1945	case OP_IN:
1946	case OP_OUTSB:
1947	case OP_OUTSWD:
1948	case OP_OUT:
1949	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1950	break;
1951
1952	case OP_MOV_CR:
1953	if (Cpu.param1.flags & USE_REG_GEN32)
1954	{
1955	//read
1956	Assert(Cpu.param2.flags & USE_REG_CR);
1957	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1958	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1959	}
1960	else
1961	{
1962	//write
1963	Assert(Cpu.param1.flags & USE_REG_CR);
1964	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1965	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1966	}
1967	break;
1968
1969	case OP_MOV_DR:
1970	STAM_COUNTER_INC(&pStats->StatMovDRx);
1971	break;
1972	case OP_LLDT:
1973	STAM_COUNTER_INC(&pStats->StatMovLldt);
1974	break;
1975	case OP_LIDT:
1976	STAM_COUNTER_INC(&pStats->StatMovLidt);
1977	break;
1978	case OP_LGDT:
1979	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1980	break;
1981	case OP_SYSENTER:
1982	STAM_COUNTER_INC(&pStats->StatSysEnter);
1983	break;
1984	case OP_SYSEXIT:
1985	STAM_COUNTER_INC(&pStats->StatSysExit);
1986	break;
1987	case OP_SYSCALL:
1988	STAM_COUNTER_INC(&pStats->StatSysCall);
1989	break;
1990	case OP_SYSRET:
1991	STAM_COUNTER_INC(&pStats->StatSysRet);
1992	break;
1993	case OP_HLT:
1994	STAM_COUNTER_INC(&pStats->StatHlt);
1995	break;
1996	default:
1997	STAM_COUNTER_INC(&pStats->StatMisc);
1998	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1999	break;
2000	}
2001	#endif
2002	if ( (pCtx->ss & X86_SEL_RPL) == 0
2003	&& !pCtx->eflags.Bits.u1VM
2004	&& SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid))
2005	{
2006	uint32_t size;
2007
2008	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
2009	switch (Cpu.pCurInstr->opcode)
2010	{
2011	case OP_CLI:
2012	pCtx->eflags.u32 &= ~X86_EFL_IF;
2013	Assert(Cpu.opsize == 1);
2014	pCtx->eip += Cpu.opsize;
2015	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2016	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
2017
2018	case OP_STI:
2019	pCtx->eflags.u32 \|= X86_EFL_IF;
2020	EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
2021	Assert(Cpu.opsize == 1);
2022	pCtx->eip += Cpu.opsize;
2023	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2024	return VINF_SUCCESS;
2025
2026	case OP_HLT:
2027	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
2028	{
2029	PATMTRANSSTATE enmState;
2030	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
2031
2032	if (enmState == PATMTRANS_OVERWRITTEN)
2033	{
2034	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2035	Assert(rc == VERR_PATCH_DISABLED);
2036	/* Conflict detected, patch disabled */
2037	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
2038
2039	enmState = PATMTRANS_SAFE;
2040	}
2041
2042	/* The translation had better be successful. Otherwise we can't recover. */
2043	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
2044	if (enmState != PATMTRANS_OVERWRITTEN)
2045	pCtx->eip = pOrgInstrGC;
2046	}
2047	/* no break; we could just return VINF_EM_HALT here */
2048
2049	case OP_MOV_CR:
2050	case OP_MOV_DR:
2051	#ifdef LOG_ENABLED
2052	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2053	{
2054	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2055	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2056	}
2057	#endif
2058
2059	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2060	if (VBOX_SUCCESS(rc))
2061	{
2062	pCtx->eip += Cpu.opsize;
2063	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2064
2065	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2066	&& Cpu.param1.flags == USE_REG_CR /* write */
2067	)
2068	{
2069	/* Reschedule is necessary as the execution/paging mode might have changed. */
2070	return VINF_EM_RESCHEDULE;
2071	}
2072	return rc; /* can return VINF_EM_HALT as well. */
2073	}
2074	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
2075	break; /* fall back to the recompiler */
2076	}
2077	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2078	}
2079	}
2080
2081	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2082	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
2083
2084	return emR3RawExecuteInstruction(pVM, "PRIV");
2085	}
2086
2087
2088	/**
2089	* Update the forced rawmode execution modifier.
2090	*
2091	* This function is called when we're returning from the raw-mode loop(s). If we're
2092	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2093	* if not in patch code, the flag will be cleared.
2094	*
2095	* We should never interrupt patch code while it's being executed. Cli patches can
2096	* contain big code blocks, but they are always executed with IF=0. Other patches
2097	* replace single instructions and should be atomic.
2098	*
2099	* @returns Updated rc.
2100	*
2101	* @param pVM The VM handle.
2102	* @param pCtx The guest CPU context.
2103	* @param rc The result code.
2104	*/
2105	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2106	{
2107	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2108	{
2109	/* ignore reschedule attempts. */
2110	switch (rc)
2111	{
2112	case VINF_EM_RESCHEDULE:
2113	case VINF_EM_RESCHEDULE_REM:
2114	rc = VINF_SUCCESS;
2115	break;
2116	}
2117	pVM->em.s.fForceRAW = true;
2118	}
2119	else
2120	pVM->em.s.fForceRAW = false;
2121	return rc;
2122	}
2123
2124
2125	/**
2126	* Process a subset of the raw-mode return code.
2127	*
2128	* Since we have to share this with raw-mode single stepping, this inline
2129	* function has been created to avoid code duplication.
2130	*
2131	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2132	* @returns VBox status code to return to the EM main loop.
2133	*
2134	* @param pVM The VM handle
2135	* @param rc The return code.
2136	* @param pCtx The guest cpu context.
2137	*/
2138	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2139	{
2140	switch (rc)
2141	{
2142	/*
2143	* Common & simple ones.
2144	*/
2145	case VINF_SUCCESS:
2146	break;
2147	case VINF_EM_RESCHEDULE_RAW:
2148	case VINF_EM_RESCHEDULE_HWACC:
2149	case VINF_EM_RAW_INTERRUPT:
2150	case VINF_EM_RAW_TO_R3:
2151	case VINF_EM_RAW_TIMER_PENDING:
2152	case VINF_EM_PENDING_REQUEST:
2153	rc = VINF_SUCCESS;
2154	break;
2155
2156	/*
2157	* Privileged instruction.
2158	*/
2159	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2160	case VINF_PATM_PATCH_TRAP_GP:
2161	rc = emR3RawPrivileged(pVM);
2162	break;
2163
2164	/*
2165	* Got a trap which needs dispatching.
2166	*/
2167	case VINF_EM_RAW_GUEST_TRAP:
2168	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2169	{
2170	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2171	rc = VERR_EM_RAW_PATCH_CONFLICT;
2172	break;
2173	}
2174
2175	Assert(TRPMHasTrap(pVM));
2176	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2177
2178	if (TRPMHasTrap(pVM))
2179	{
2180	uint8_t u8Interrupt;
2181	uint32_t uErrorCode;
2182	TRPMERRORCODE enmError = TRPM_TRAP_NO_ERRORCODE;
2183
2184	rc = TRPMQueryTrapAll(pVM, &u8Interrupt, NULL, &uErrorCode, NULL);
2185	AssertRC(rc);
2186
2187	if (uErrorCode != ~0U)
2188	enmError = TRPM_TRAP_HAS_ERRORCODE;
2189
2190	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2191	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2192	{
2193	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2194	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2195
2196	/** If it was successful, then we could go back to raw mode. */
2197	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER)
2198	{
2199	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8Interrupt, uErrorCode, enmError, TRPM_TRAP);
2200	if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
2201	{
2202	TRPMResetTrap(pVM);
2203	return VINF_EM_RESCHEDULE_RAW;
2204	}
2205	}
2206	}
2207	}
2208	rc = emR3RawGuestTrap(pVM);
2209	break;
2210
2211	/*
2212	* Trap in patch code.
2213	*/
2214	case VINF_PATM_PATCH_TRAP_PF:
2215	case VINF_PATM_PATCH_INT3:
2216	rc = emR3PatchTrap(pVM, pCtx, rc);
2217	break;
2218
2219	case VINF_PATM_DUPLICATE_FUNCTION:
2220	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2221	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2222	AssertRC(rc);
2223	rc = VINF_SUCCESS;
2224	break;
2225
2226	case VINF_PATM_CHECK_PATCH_PAGE:
2227	rc = PATMR3HandleMonitoredPage(pVM);
2228	AssertRC(rc);
2229	rc = VINF_SUCCESS;
2230	break;
2231
2232	/*
2233	* Patch manager.
2234	*/
2235	case VERR_EM_RAW_PATCH_CONFLICT:
2236	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2237	break;
2238
2239	/*
2240	* Memory mapped I/O access - attempt to patch the instruction
2241	*/
2242	case VINF_PATM_HC_MMIO_PATCH_READ:
2243	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
2244	PATMFL_MMIO_ACCESS \| (SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2245	if (VBOX_FAILURE(rc))
2246	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2247	break;
2248
2249	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2250	AssertFailed(); /* not yet implemented. */
2251	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2252	break;
2253
2254	/*
2255	* Conflict or out of page tables.
2256	*
2257	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2258	* do here is to execute the pending forced actions.
2259	*/
2260	case VINF_PGM_SYNC_CR3:
2261	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2262	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2263	rc = VINF_SUCCESS;
2264	break;
2265
2266	/*
2267	* Paging mode change.
2268	*/
2269	case VINF_PGM_CHANGE_MODE:
2270	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2271	if (VBOX_SUCCESS(rc))
2272	rc = VINF_EM_RESCHEDULE;
2273	break;
2274
2275	/*
2276	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2277	*/
2278	case VINF_CSAM_PENDING_ACTION:
2279	rc = VINF_SUCCESS;
2280	break;
2281
2282	/*
2283	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2284	*/
2285	case VINF_EM_RAW_INTERRUPT_PENDING:
2286	case VINF_EM_RAW_RING_SWITCH_INT:
2287	{
2288	uint8_t u8Interrupt;
2289
2290	Assert(TRPMHasTrap(pVM));
2291	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2292
2293	if (TRPMHasTrap(pVM))
2294	{
2295	u8Interrupt = TRPMGetTrapNo(pVM);
2296
2297	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2298	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2299	{
2300	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2301	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2302	/** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2303	}
2304	}
2305	rc = VINF_EM_RESCHEDULE_REM;
2306	break;
2307	}
2308
2309	/*
2310	* Other ring switch types.
2311	*/
2312	case VINF_EM_RAW_RING_SWITCH:
2313	rc = emR3RawRingSwitch(pVM);
2314	break;
2315
2316	/*
2317	* REMGCNotifyInvalidatePage() failed because of overflow.
2318	*/
2319	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2320	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2321	REMR3ReplayInvalidatedPages(pVM);
2322	break;
2323
2324	/*
2325	* I/O Port access - emulate the instruction.
2326	*/
2327	case VINF_IOM_HC_IOPORT_READ:
2328	case VINF_IOM_HC_IOPORT_WRITE:
2329	case VINF_IOM_HC_IOPORT_READWRITE:
2330	rc = emR3RawExecuteIOInstruction(pVM);
2331	break;
2332
2333	/*
2334	* Memory mapped I/O access - emulate the instruction.
2335	*/
2336	case VINF_IOM_HC_MMIO_READ:
2337	case VINF_IOM_HC_MMIO_WRITE:
2338	case VINF_IOM_HC_MMIO_READ_WRITE:
2339	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2340	break;
2341
2342	/*
2343	* Execute instruction.
2344	*/
2345	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2346	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2347	break;
2348	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2349	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2350	break;
2351	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2352	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2353	break;
2354	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2355	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2356	break;
2357	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2358	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2359	break;
2360
2361	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2362	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2363	rc = emR3RawPrivileged(pVM);
2364	break;
2365
2366	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2367	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2368	break;
2369
2370	case VINF_EM_RAW_EMULATE_INSTR:
2371	case VINF_PATCH_EMULATE_INSTR:
2372	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2373	break;
2374
2375	/*
2376	* Stale selector and iret traps => REM.
2377	*/
2378	case VINF_EM_RAW_STALE_SELECTOR:
2379	case VINF_EM_RAW_IRET_TRAP:
2380	/* We will not go to the recompiler if EIP points to patch code. */
2381	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2382	{
2383	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2384	}
2385	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2386	rc = VINF_EM_RESCHEDULE_REM;
2387	break;
2388
2389	/*
2390	* Up a level.
2391	*/
2392	case VINF_EM_TERMINATE:
2393	case VINF_EM_OFF:
2394	case VINF_EM_RESET:
2395	case VINF_EM_SUSPEND:
2396	case VINF_EM_HALT:
2397	case VINF_EM_RESUME:
2398	case VINF_EM_RESCHEDULE:
2399	case VINF_EM_RESCHEDULE_REM:
2400	break;
2401
2402	/*
2403	* Up a level and invoke the debugger.
2404	*/
2405	case VINF_EM_DBG_STEPPED:
2406	case VINF_EM_DBG_BREAKPOINT:
2407	case VINF_EM_DBG_STEP:
2408	case VINF_EM_DBG_HYPER_ASSERTION:
2409	case VINF_EM_DBG_HYPER_BREAKPOINT:
2410	case VINF_EM_DBG_HYPER_STEPPED:
2411	case VINF_EM_DBG_STOP:
2412	break;
2413
2414	/*
2415	* Up a level, dump and debug.
2416	*/
2417	case VERR_TRPM_DONT_PANIC:
2418	case VERR_TRPM_PANIC:
2419	break;
2420
2421	/*
2422	* Anything which is not known to us means an internal error
2423	* and the termination of the VM!
2424	*/
2425	default:
2426	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2427	break;
2428	}
2429	return rc;
2430	}
2431
2432
2433	/**
2434	* Process raw-mode specific forced actions.
2435	*
2436	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2437	*
2438	* @returns VBox status code.
2439	* Only the normal success/failure stuff, no VINF_EM_*.
2440	* @param pVM The VM handle.
2441	* @param pCtx The guest CPUM register context.
2442	*/
2443	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2444	{
2445	/*
2446	* Note that the order is vitally important!
2447	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2448	*/
2449
2450
2451	/*
2452	* Sync selector tables.
2453	*/
2454	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2455	{
2456	int rc = SELMR3UpdateFromCPUM(pVM);
2457	if (VBOX_FAILURE(rc))
2458	return rc;
2459	}
2460
2461	/*
2462	* Sync IDT.
2463	*/
2464	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2465	{
2466	int rc = TRPMR3SyncIDT(pVM);
2467	if (VBOX_FAILURE(rc))
2468	return rc;
2469	}
2470
2471	/*
2472	* Sync TSS.
2473	*/
2474	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2475	{
2476	int rc = SELMR3SyncTSS(pVM);
2477	if (VBOX_FAILURE(rc))
2478	return rc;
2479	}
2480
2481	/*
2482	* Sync page directory.
2483	*/
2484	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2485	{
2486	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2487	if (VBOX_FAILURE(rc))
2488	return rc;
2489
2490	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2491
2492	/* Prefetch pages for EIP and ESP */
2493	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2494	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip));
2495	if (rc == VINF_SUCCESS)
2496	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2497	if (rc != VINF_SUCCESS)
2498	{
2499	if (rc != VINF_PGM_SYNC_CR3)
2500	return rc;
2501	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2502	if (VBOX_FAILURE(rc))
2503	return rc;
2504	}
2505	/** @todo maybe prefetch the supervisor stack page as well */
2506	}
2507
2508	return VINF_SUCCESS;
2509	}
2510
2511
2512	/**
2513	* Executes raw code.
2514	*
2515	* This function contains the raw-mode version of the inner
2516	* execution loop (the outer loop being in EMR3ExecuteVM()).
2517	*
2518	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2519	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2520	*
2521	* @param pVM VM handle.
2522	* @param pfFFDone Where to store an indicator telling whether or not
2523	* FFs were done before returning.
2524	*/
2525	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2526	{
2527	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2528
2529	int rc = VERR_INTERNAL_ERROR;
2530	PCPUMCTX pCtx = pVM->em.s.pCtx;
2531	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2532	pVM->em.s.fForceRAW = false;
2533	*pfFFDone = false;
2534
2535
2536	/*
2537	*
2538	* Spin till we get a forced action or raw mode status code resulting in
2539	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2540	*
2541	*/
2542	for (;;)
2543	{
2544	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2545
2546	/*
2547	* Check various preconditions.
2548	*/
2549	#ifdef VBOX_STRICT
2550	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2551	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2552	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2553	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2554	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2555	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2556	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2557	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2558	{
2559	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2560	return VERR_INTERNAL_ERROR;
2561	}
2562	#endif /* VBOX_STRICT */
2563
2564	/*
2565	* Process high priority pre-execution raw-mode FFs.
2566	*/
2567	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2568	{
2569	rc = emR3RawForcedActions(pVM, pCtx);
2570	if (VBOX_FAILURE(rc))
2571	break;
2572	}
2573
2574	/*
2575	* If we're going to execute ring-0 code, the guest state needs to
2576	* be modified a bit and some of the state components (IF, SS/CS RPL,
2577	* and perhaps EIP) needs to be stored with PATM.
2578	*/
2579	rc = CPUMRawEnter(pVM, NULL);
2580	if (rc != VINF_SUCCESS)
2581	{
2582	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2583	break;
2584	}
2585
2586	/*
2587	* Scan code before executing it. Don't bother with user mode or V86 code
2588	*/
2589	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2590	&& !pCtx->eflags.Bits.u1VM
2591	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2592	{
2593	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2594	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2595	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2596	}
2597
2598	#ifdef LOG_ENABLED
2599	/*
2600	* Log important stuff before entering GC.
2601	*/
2602	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2603	if (pCtx->eflags.Bits.u1VM)
2604	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2605	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2606	{
2607	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2608	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2609	}
2610	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2611	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2612	#endif /* LOG_ENABLED */
2613
2614
2615
2616	/*
2617	* Execute the code.
2618	*/
2619	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2620	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2621	VMMR3Unlock(pVM);
2622	rc = VMMR3RawRunGC(pVM);
2623	VMMR3Lock(pVM);
2624	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2625	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2626
2627	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2628	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2629
2630
2631	/*
2632	* Restore the real CPU state and deal with high priority post
2633	* execution FFs before doing anything else.
2634	*/
2635	rc = CPUMRawLeave(pVM, NULL, rc);
2636	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2637	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2638	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2639
2640	#ifdef PGM_CACHE_VERY_STRICT
2641	/*
2642	* Page manager cache checks.
2643	*/
2644	if ( rc == VINF_EM_RAW_INTERRUPT
2645	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2646	\|\| rc == VINF_IOM_HC_IOPORT_READ
2647	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2648	\|\| rc == VINF_IOM_HC_IOPORT_READWRITE
2649	//\|\| rc == VINF_PATM_PATCH_INT3
2650	)
2651	pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2652	#endif
2653
2654	#ifdef VBOX_STRICT
2655	/*
2656	* Assert TSS consistency & rc vs patch code.
2657	*/
2658	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2659	&& EMIsRawRing0Enabled(pVM))
2660	SELMR3CheckTSS(pVM);
2661	switch (rc)
2662	{
2663	case VINF_SUCCESS:
2664	case VINF_EM_RAW_INTERRUPT:
2665	case VINF_PATM_PATCH_TRAP_PF:
2666	case VINF_PATM_PATCH_TRAP_GP:
2667	case VINF_PATM_PATCH_INT3:
2668	case VINF_PATM_CHECK_PATCH_PAGE:
2669	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2670	case VINF_EM_RAW_GUEST_TRAP:
2671	case VINF_EM_RESCHEDULE_RAW:
2672	break;
2673
2674	default:
2675	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2676	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2677	break;
2678	}
2679	/*
2680	* Let's go paranoid!
2681	*/
2682	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2683	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2684	{
2685	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2686	return VERR_INTERNAL_ERROR;
2687	}
2688	#endif /* VBOX_STRICT */
2689
2690	/*
2691	* Process the returned status code.
2692	*/
2693	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2694	{
2695	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2696	break;
2697	}
2698	rc = emR3RawHandleRC(pVM, pCtx, rc);
2699	if (rc != VINF_SUCCESS)
2700	{
2701	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2702	if (rc != VINF_SUCCESS)
2703	{
2704	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2705	break;
2706	}
2707	}
2708
2709	/*
2710	* Check and execute forced actions.
2711	*/
2712	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2713	TMTimerPoll(pVM);
2714	#endif
2715	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2716	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2717	{
2718	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2719
2720	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2721	rc = emR3ForcedActions(pVM, rc);
2722	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2723	if ( rc != VINF_SUCCESS
2724	&& rc != VINF_EM_RESCHEDULE_RAW)
2725	{
2726	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2727	if (rc != VINF_SUCCESS)
2728	{
2729	*pfFFDone = true;
2730	break;
2731	}
2732	}
2733	}
2734	}
2735
2736	/*
2737	* Return to outer loop.
2738	*/
2739	#if defined(LOG_ENABLED) && defined(DEBUG)
2740	RTLogFlush(NULL);
2741	#endif
2742	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2743	return rc;
2744	}
2745
2746
2747	/**
2748	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2749	*
2750	* This function contains the raw-mode version of the inner
2751	* execution loop (the outer loop being in EMR3ExecuteVM()).
2752	*
2753	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2754	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2755	*
2756	* @param pVM VM handle.
2757	* @param pfFFDone Where to store an indicator telling whether or not
2758	* FFs were done before returning.
2759	*/
2760	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2761	{
2762	int rc = VERR_INTERNAL_ERROR;
2763	PCPUMCTX pCtx = pVM->em.s.pCtx;
2764
2765	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2766	*pfFFDone = false;
2767
2768	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2769
2770	/*
2771	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2772	*/
2773	for (;;)
2774	{
2775	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2776
2777	/*
2778	* Check various preconditions.
2779	*/
2780	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2781
2782	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2783
2784	/*
2785	* Sync page directory.
2786	*/
2787	if (VM_FF_ISPENDING(pVM, (VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)))
2788	{
2789	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2790	if (VBOX_FAILURE(rc))
2791	return rc;
2792
2793	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2794
2795	/* Prefetch pages for EIP and ESP */
2796	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip));
2797	if (rc == VINF_SUCCESS)
2798	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2799	if (rc != VINF_SUCCESS)
2800	{
2801	if (rc != VINF_PGM_SYNC_CR3)
2802	return rc;
2803	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2804	if (VBOX_FAILURE(rc))
2805	return rc;
2806	}
2807
2808	/** @todo maybe prefetch the supervisor stack page as well */
2809	}
2810
2811	#ifdef LOG_ENABLED
2812	uint8_t u8Vector;
2813
2814	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2815	if (rc == VINF_SUCCESS)
2816	{
2817	Log(("Pending hardware interrupt %d\n", u8Vector));
2818	}
2819	/*
2820	* Log important stuff before entering GC.
2821	*/
2822	if (pCtx->eflags.Bits.u1VM)
2823	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2824	else if ((pCtx->ss & X86_SEL_RPL) == 0)
2825	Log(("HWR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
2826	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2827	Log(("HWR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
2828	#endif
2829
2830
2831	/*
2832	* Execute the code.
2833	*/
2834	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2835	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2836	VMMR3Unlock(pVM);
2837	rc = VMMR3HwAccRunGC(pVM);
2838	VMMR3Lock(pVM);
2839	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2840
2841
2842	/*
2843	* Deal with high priority post execution FFs before doing anything else.
2844	*/
2845	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2846	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2847	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2848
2849	/*
2850	* Process the returned status code.
2851	*/
2852	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2853	break;
2854
2855	rc = emR3RawHandleRC(pVM, pCtx, rc);
2856	if (rc != VINF_SUCCESS)
2857	break;
2858
2859	/*
2860	* Check and execute forced actions.
2861	*/
2862	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2863	TMTimerPoll(pVM);
2864	#endif
2865	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2866	{
2867	rc = emR3ForcedActions(pVM, rc);
2868	if ( rc != VINF_SUCCESS
2869	&& rc != VINF_EM_RESCHEDULE_HWACC)
2870	{
2871	*pfFFDone = true;
2872	break;
2873	}
2874	}
2875	}
2876	/*
2877	* Return to outer loop.
2878	*/
2879	#if defined(LOG_ENABLED) && defined(DEBUG)
2880	RTLogFlush(NULL);
2881	#endif
2882	return rc;
2883	}
2884
2885
2886	/**
2887	* Decides whether to execute RAW, HWACC or REM.
2888	*
2889	* @returns new EM state
2890	* @param pVM The VM.
2891	* @param pCtx The CPU context.
2892	*/
2893	inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2894	{
2895	/*
2896	* When forcing raw-mode execution, things are simple.
2897	*/
2898	if (pVM->em.s.fForceRAW)
2899	return EMSTATE_RAW;
2900
2901	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2902	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2903	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2904
2905	X86EFLAGS EFlags = pCtx->eflags;
2906	if (HWACCMIsEnabled(pVM))
2907	{
2908	/* Hardware accelerated raw-mode:
2909	*
2910	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2911	*/
2912	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2913	return EMSTATE_HWACC;
2914
2915	/** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2916	return EMSTATE_REM;
2917	}
2918
2919	/* Standard raw-mode:
2920	*
2921	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2922	* or 32 bits protected mode ring 0 code
2923	*
2924	* The tests are ordered by the likelyhood of being true during normal execution.
2925	*/
2926	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2927	{
2928	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2929	return EMSTATE_REM;
2930	}
2931
2932	#ifndef VBOX_RAW_V86
2933	if (EFlags.u32 & X86_EFL_VM) {
2934	Log2(("raw mode refused: VM_MASK\n"));
2935	return EMSTATE_REM;
2936	}
2937	#endif
2938
2939	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2940	uint32_t u32CR0 = pCtx->cr0;
2941	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2942	{
2943	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2944	return EMSTATE_REM;
2945	}
2946
2947	if (pCtx->cr4 & X86_CR4_PAE)
2948	{
2949	//Log2(("raw mode refused: PAE\n"));
2950	return EMSTATE_REM;
2951	}
2952
2953	unsigned uSS = pCtx->ss;
2954	if ( pCtx->eflags.Bits.u1VM
2955	\|\| (uSS & X86_SEL_RPL) == 3)
2956	{
2957	if (!EMIsRawRing3Enabled(pVM))
2958	return EMSTATE_REM;
2959
2960	if (!(EFlags.u32 & X86_EFL_IF))
2961	{
2962	Log2(("raw mode refused: IF (RawR3)\n"));
2963	return EMSTATE_REM;
2964	}
2965
2966	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2967	{
2968	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2969	return EMSTATE_REM;
2970	}
2971	}
2972	else
2973	{
2974	if (!EMIsRawRing0Enabled(pVM))
2975	return EMSTATE_REM;
2976
2977	/* Only ring 0 supervisor code. */
2978	if ((uSS & X86_SEL_RPL) != 0)
2979	{
2980	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2981	return EMSTATE_REM;
2982	}
2983
2984	// Let's start with pure 32 bits ring 0 code first
2985	/** @todo What's pure 32-bit mode? flat? */
2986	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2987	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
2988	{
2989	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2990	return EMSTATE_REM;
2991	}
2992
2993	/* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2994	if (!(u32CR0 & X86_CR0_WP))
2995	{
2996	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2997	return EMSTATE_REM;
2998	}
2999
3000	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
3001	{
3002	Log2(("raw r0 mode forced: patch code\n"));
3003	return EMSTATE_RAW;
3004	}
3005
3006	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
3007	if (!(EFlags.u32 & X86_EFL_IF))
3008	{
3009	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
3010	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
3011	return EMSTATE_REM;
3012	}
3013	#endif
3014
3015	/** @todo still necessary??? */
3016	if (EFlags.Bits.u2IOPL != 0)
3017	{
3018	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
3019	return EMSTATE_REM;
3020	}
3021	}
3022
3023	Assert(PGMPhysIsA20Enabled(pVM));
3024	return EMSTATE_RAW;
3025	}
3026
3027
3028	/**
3029	* Executes all high priority post execution force actions.
3030	*
3031	* @returns rc or a fatal status code.
3032	*
3033	* @param pVM VM handle.
3034	* @param rc The current rc.
3035	*/
3036	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
3037	{
3038	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
3039	PDMR3CritSectFF(pVM);
3040
3041	if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
3042	CSAMR3DoPendingAction(pVM);
3043
3044	return rc;
3045	}
3046
3047
3048	/**
3049	* Executes all pending forced actions.
3050	*
3051	* Forced actions can cause execution delays and execution
3052	* rescheduling. The first we deal with using action priority, so
3053	* that for instance pending timers aren't scheduled and ran until
3054	* right before execution. The rescheduling we deal with using
3055	* return codes. The same goes for VM termination, only in that case
3056	* we exit everything.
3057	*
3058	* @returns VBox status code of equal or greater importance/severity than rc.
3059	* The most important ones are: VINF_EM_RESCHEDULE,
3060	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3061	*
3062	* @param pVM VM handle.
3063	* @param rc The current rc.
3064	*
3065	*/
3066	static int emR3ForcedActions(PVM pVM, int rc)
3067	{
3068	#ifdef VBOX_STRICT
3069	int rcIrq = VINF_SUCCESS;
3070	#endif
3071	STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
3072
3073	#define UPDATE_RC() \
3074	do { \
3075	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
3076	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
3077	break; \
3078	if (!rc \|\| rc2 < rc) \
3079	rc = rc2; \
3080	} while (0)
3081
3082	int rc2;
3083
3084	/*
3085	* Post execution chunk first.
3086	*/
3087	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
3088	{
3089	/*
3090	* Termination request.
3091	*/
3092	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3093	{
3094	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3095	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3096	return VINF_EM_TERMINATE;
3097	}
3098
3099	/*
3100	* Debugger Facility polling.
3101	*/
3102	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3103	{
3104	rc2 = DBGFR3VMMForcedAction(pVM);
3105	UPDATE_RC();
3106	}
3107
3108	/*
3109	* Postponed reset request.
3110	*/
3111	if (VM_FF_ISSET(pVM, VM_FF_RESET))
3112	{
3113	rc2 = VMR3Reset(pVM);
3114	UPDATE_RC();
3115	VM_FF_CLEAR(pVM, VM_FF_RESET);
3116	}
3117
3118	/*
3119	* CSAM page scanning.
3120	*/
3121	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
3122	{
3123	PCPUMCTX pCtx = pVM->em.s.pCtx;
3124
3125	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3126	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3127
3128	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
3129	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3130	}
3131
3132	/* check that we got them all */
3133	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
3134	}
3135
3136	/*
3137	* Normal priority then.
3138	* (Executed in no particular order.)
3139	*/
3140	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3141	{
3142	/*
3143	* PDM Queues are pending.
3144	*/
3145	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3146	PDMR3QueueFlushAll(pVM);
3147
3148	/*
3149	* PDM DMA transfers are pending.
3150	*/
3151	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3152	PDMR3DmaRun(pVM);
3153
3154	/*
3155	* Requests from other threads.
3156	*/
3157	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3158	{
3159	rc2 = VMR3ReqProcess(pVM);
3160	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3161	{
3162	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3163	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3164	return rc2;
3165	}
3166	UPDATE_RC();
3167	}
3168
3169	/* check that we got them all */
3170	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA)));
3171	}
3172
3173	/*
3174	* Execute polling function ever so often.
3175	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING SOON!
3176	*/
3177	static unsigned cLast = 0;
3178	if (!((++cLast) % 4))
3179	PDMR3Poll(pVM);
3180
3181	/*
3182	* High priority pre execution chunk last.
3183	* (Executed in ascending priority order.)
3184	*/
3185	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3186	{
3187	/*
3188	* Timers before interrupts.
3189	*/
3190	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3191	TMR3TimerQueuesDo(pVM);
3192
3193	/*
3194	* The instruction following an emulated STI should always be executed!
3195	*/
3196	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3197	{
3198	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3199	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3200	{
3201	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3202	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3203	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3204	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3205	*/
3206	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3207	}
3208	if (HWACCMR3IsActive(pVM))
3209	rc2 = VINF_EM_RESCHEDULE_HWACC;
3210	else
3211	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3212
3213	UPDATE_RC();
3214	}
3215
3216	/*
3217	* Interrupts.
3218	*/
3219	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3220	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3221	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3222	&& PATMAreInterruptsEnabled(pVM)
3223	&& !HWACCMR3IsEventPending(pVM))
3224	{
3225	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3226	{
3227	/** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3228	/** @todo this really isn't nice, should properly handle this */
3229	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3230	#ifdef VBOX_STRICT
3231	rcIrq = rc2;
3232	#endif
3233	UPDATE_RC();
3234	}
3235	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3236	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3237	{
3238	rc2 = VINF_EM_RESCHEDULE_REM;
3239	UPDATE_RC();
3240	}
3241	}
3242
3243	/*
3244	* Debugger Facility request.
3245	*/
3246	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3247	{
3248	rc2 = DBGFR3VMMForcedAction(pVM);
3249	UPDATE_RC();
3250	}
3251
3252	/*
3253	* Termination request.
3254	*/
3255	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3256	{
3257	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3258	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3259	return VINF_EM_TERMINATE;
3260	}
3261
3262	#ifdef DEBUG
3263	/*
3264	* Debug, pause the VM.
3265	*/
3266	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3267	{
3268	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3269	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3270	return VINF_EM_SUSPEND;
3271	}
3272
3273	#endif
3274	/* check that we got them all */
3275	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS)));
3276	}
3277
3278	#undef UPDATE_RC
3279	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3280	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3281	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3282	return rc;
3283	}
3284
3285
3286	/**
3287	* Execute VM.
3288	*
3289	* This function is the main loop of the VM. The emulation thread
3290	* calls this function when the VM has been successfully constructed
3291	* and we're ready for executing the VM.
3292	*
3293	* Returning from this function means that the VM is turned off or
3294	* suspended (state already saved) and deconstruction in next in line.
3295	*
3296	* All interaction from other thread are done using forced actions
3297	* and signaling of the wait object.
3298	*
3299	* @returns VBox status code.
3300	* @param pVM The VM to operate on.
3301	*/
3302	EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3303	{
3304	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3305	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3306	VM_ASSERT_EMT(pVM);
3307	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3308
3309	VMMR3Lock(pVM);
3310
3311	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3312	if (rc == 0)
3313	{
3314	/*
3315	* Start the virtual time.
3316	*/
3317	rc = TMVirtualResume(pVM);
3318	Assert(rc == VINF_SUCCESS);
3319	rc = TMCpuTickResume(pVM);
3320	Assert(rc == VINF_SUCCESS);
3321
3322	/*
3323	* The Outer Main Loop.
3324	*/
3325	bool fFFDone = false;
3326	rc = VINF_EM_RESCHEDULE;
3327	pVM->em.s.enmState = EMSTATE_REM;
3328	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3329	for (;;)
3330	{
3331	/*
3332	* Before we can schedule anything (we're here because
3333	* scheduling is required) we must service any pending
3334	* forced actions to avoid any pending action causing
3335	* immidate rescheduling upon entering an inner loop
3336	*
3337	* Do forced actions.
3338	*/
3339	if ( !fFFDone
3340	&& rc != VINF_EM_TERMINATE
3341	&& rc != VINF_EM_OFF
3342	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3343	{
3344	rc = emR3ForcedActions(pVM, rc);
3345	if ( ( rc == VINF_EM_RESCHEDULE_REM
3346	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3347	&& pVM->em.s.fForceRAW)
3348	rc = VINF_EM_RESCHEDULE_RAW;
3349	}
3350	else if (fFFDone)
3351	fFFDone = false;
3352
3353	/*
3354	* Now what to do?
3355	*/
3356	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3357	switch (rc)
3358	{
3359	/*
3360	* Keep doing what we're currently doing.
3361	*/
3362	case VINF_SUCCESS:
3363	break;
3364
3365	/*
3366	* Reschedule - to raw-mode execution.
3367	*/
3368	case VINF_EM_RESCHEDULE_RAW:
3369	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3370	pVM->em.s.enmState = EMSTATE_RAW;
3371	break;
3372
3373	/*
3374	* Reschedule - to hardware accelerated raw-mode execution.
3375	*/
3376	case VINF_EM_RESCHEDULE_HWACC:
3377	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3378	Assert(!pVM->em.s.fForceRAW);
3379	pVM->em.s.enmState = EMSTATE_HWACC;
3380	break;
3381
3382	/*
3383	* Reschedule - to recompiled execution.
3384	*/
3385	case VINF_EM_RESCHEDULE_REM:
3386	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3387	pVM->em.s.enmState = EMSTATE_REM;
3388	break;
3389
3390	/*
3391	* Resume.
3392	*/
3393	case VINF_EM_RESUME:
3394	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3395	/* fall through and get scheduled. */
3396
3397	/*
3398	* Reschedule.
3399	*/
3400	case VINF_EM_RESCHEDULE:
3401	{
3402	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3403	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3404	pVM->em.s.enmState = enmState;
3405	break;
3406	}
3407
3408	/*
3409	* Halted.
3410	*/
3411	case VINF_EM_HALT:
3412	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3413	pVM->em.s.enmState = EMSTATE_HALTED;
3414	break;
3415
3416	/*
3417	* Suspend.
3418	*/
3419	case VINF_EM_SUSPEND:
3420	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3421	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3422	break;
3423
3424	/*
3425	* Reset.
3426	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3427	*/
3428	case VINF_EM_RESET:
3429	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3430	pVM->em.s.enmState = EMSTATE_REM;
3431	break;
3432
3433	/*
3434	* Power Off.
3435	*/
3436	case VINF_EM_OFF:
3437	pVM->em.s.enmState = EMSTATE_TERMINATING;
3438	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3439	TMVirtualPause(pVM);
3440	TMCpuTickPause(pVM);
3441	VMMR3Unlock(pVM);
3442	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3443	return rc;
3444
3445	/*
3446	* Terminate the VM.
3447	*/
3448	case VINF_EM_TERMINATE:
3449	pVM->em.s.enmState = EMSTATE_TERMINATING;
3450	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3451	TMVirtualPause(pVM);
3452	TMCpuTickPause(pVM);
3453	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3454	return rc;
3455
3456	/*
3457	* Guest debug events.
3458	*/
3459	case VINF_EM_DBG_STEPPED:
3460	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3461	case VINF_EM_DBG_STOP:
3462	case VINF_EM_DBG_BREAKPOINT:
3463	case VINF_EM_DBG_STEP:
3464	if (pVM->em.s.enmState == EMSTATE_RAW)
3465	{
3466	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3467	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3468	}
3469	else
3470	{
3471	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3472	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3473	}
3474	break;
3475
3476	/*
3477	* Hypervisor debug events.
3478	*/
3479	case VINF_EM_DBG_HYPER_STEPPED:
3480	case VINF_EM_DBG_HYPER_BREAKPOINT:
3481	case VINF_EM_DBG_HYPER_ASSERTION:
3482	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3483	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3484	break;
3485
3486	/*
3487	* Any error code showing up here other than the ones we
3488	* know and process above are considered to be FATAL.
3489	*
3490	* Unknown warnings and informational status codes are also
3491	* included in this.
3492	*/
3493	default:
3494	if (VBOX_SUCCESS(rc))
3495	{
3496	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3497	rc = VERR_EM_INTERNAL_ERROR;
3498	}
3499	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3500	Log(("EMR3ExecuteVM returns %d\n", rc));
3501	break;
3502	}
3503
3504
3505	/*
3506	* Any waiters can now be woken up
3507	*/
3508	VMMR3Unlock(pVM);
3509	VMMR3Lock(pVM);
3510
3511	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3512	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3513
3514	/*
3515	* Act on the state.
3516	*/
3517	switch (pVM->em.s.enmState)
3518	{
3519	/*
3520	* Execute raw.
3521	*/
3522	case EMSTATE_RAW:
3523	rc = emR3RawExecute(pVM, &fFFDone);
3524	break;
3525
3526	/*
3527	* Execute hardware accelerated raw.
3528	*/
3529	case EMSTATE_HWACC:
3530	rc = emR3HwAccExecute(pVM, &fFFDone);
3531	break;
3532
3533	/*
3534	* Execute recompiled.
3535	*/
3536	case EMSTATE_REM:
3537	rc = emR3RemExecute(pVM, &fFFDone);
3538	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3539	break;
3540
3541	/*
3542	* hlt - execution halted until interrupt.
3543	*/
3544	case EMSTATE_HALTED:
3545	{
3546	STAM_PROFILE_START(&pVM->em.s.StatHalted, y);
3547	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3548	STAM_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3549	break;
3550	}
3551
3552	/*
3553	* Suspended - return to VM.cpp.
3554	*/
3555	case EMSTATE_SUSPENDED:
3556	TMVirtualPause(pVM);
3557	TMCpuTickPause(pVM);
3558	VMMR3Unlock(pVM);
3559	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3560	return VINF_EM_SUSPEND;
3561
3562	/*
3563	* Debugging in the guest.
3564	*/
3565	case EMSTATE_DEBUG_GUEST_REM:
3566	case EMSTATE_DEBUG_GUEST_RAW:
3567	TMVirtualPause(pVM);
3568	TMCpuTickPause(pVM);
3569	rc = emR3Debug(pVM, rc);
3570	TMVirtualResume(pVM);
3571	TMCpuTickResume(pVM);
3572	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3573	break;
3574
3575	/*
3576	* Debugging in the hypervisor.
3577	*/
3578	case EMSTATE_DEBUG_HYPER:
3579	{
3580	TMVirtualPause(pVM);
3581	TMCpuTickPause(pVM);
3582	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3583
3584	rc = emR3Debug(pVM, rc);
3585	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3586	if (rc != VINF_SUCCESS)
3587	{
3588	/* switch to guru meditation mode */
3589	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3590	VMMR3FatalDump(pVM, rc);
3591	return rc;
3592	}
3593
3594	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3595	TMVirtualResume(pVM);
3596	TMCpuTickResume(pVM);
3597	break;
3598	}
3599
3600	/*
3601	* Guru meditation takes place in the debugger.
3602	*/
3603	case EMSTATE_GURU_MEDITATION:
3604	{
3605	/** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3606	TMVirtualPause(pVM);
3607	TMCpuTickPause(pVM);
3608	VMMR3FatalDump(pVM, rc);
3609	int rc2 = emR3Debug(pVM, rc);
3610	if (rc2 == VERR_DBGF_NOT_ATTACHED)
3611	{
3612	VMMR3Unlock(pVM);
3613	/** @todo change the VM state! */
3614	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3615	return rc;
3616	}
3617	TMVirtualResume(pVM);
3618	TMCpuTickResume(pVM);
3619	rc = rc2;
3620	/** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3621	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3622	break;
3623	}
3624
3625	/*
3626	* The states we don't expect here.
3627	*/
3628	case EMSTATE_NONE:
3629	case EMSTATE_TERMINATING:
3630	default:
3631	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3632	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3633	TMVirtualPause(pVM);
3634	TMCpuTickPause(pVM);
3635	VMMR3Unlock(pVM);
3636	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3637	return VERR_EM_INTERNAL_ERROR;
3638	}
3639	} /* The Outer Main Loop */
3640	}
3641	else
3642	{
3643	/*
3644	* Fatal error.
3645	*/
3646	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3647	TMVirtualPause(pVM);
3648	TMCpuTickPause(pVM);
3649	VMMR3FatalDump(pVM, rc);
3650	emR3Debug(pVM, rc);
3651	VMMR3Unlock(pVM);
3652	/** @todo change the VM state! */
3653	return rc;
3654	}
3655
3656	/* (won't ever get here). */
3657	AssertFailed();
3658	}
3659

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 1939

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