EM.cpp@ 19793

Last change on this file since 19793 was 19793, checked in by vboxsync, 16 years ago
Deal with critical section nesting when trying to clean up after a guru meditation.
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1	/* $Id: EM.cpp 19793 2009-05-18 14:30:15Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_em EM - The Execution Monitor / Manager
23	*
24	* The Execution Monitor/Manager is responsible for running the VM, scheduling
25	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26	* Interpreted), and keeping the CPU states in sync. The function
27	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29	* emR3RemExecute).
30	*
31	* The interpreted execution is only used to avoid switching between
32	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33	* The interpretation is thus implemented as part of EM.
34	*
35	* @see grp_em
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_EM
42	#include <VBox/em.h>
43	#include <VBox/vmm.h>
44	#ifdef VBOX_WITH_VMI
45	# include <VBox/parav.h>
46	#endif
47	#include <VBox/patm.h>
48	#include <VBox/csam.h>
49	#include <VBox/selm.h>
50	#include <VBox/trpm.h>
51	#include <VBox/iom.h>
52	#include <VBox/dbgf.h>
53	#include <VBox/pgm.h>
54	#include <VBox/rem.h>
55	#include <VBox/tm.h>
56	#include <VBox/mm.h>
57	#include <VBox/ssm.h>
58	#include <VBox/pdmapi.h>
59	#include <VBox/pdmcritsect.h>
60	#include <VBox/pdmqueue.h>
61	#include <VBox/hwaccm.h>
62	#include <VBox/patm.h>
63	#include "EMInternal.h"
64	#include <VBox/vm.h>
65	#include <VBox/cpumdis.h>
66	#include <VBox/dis.h>
67	#include <VBox/disopcode.h>
68	#include <VBox/dbgf.h>
69
70	#include <VBox/log.h>
71	#include <iprt/thread.h>
72	#include <iprt/assert.h>
73	#include <iprt/asm.h>
74	#include <iprt/semaphore.h>
75	#include <iprt/string.h>
76	#include <iprt/avl.h>
77	#include <iprt/stream.h>
78	#include <VBox/param.h>
79	#include <VBox/err.h>
80
81
82	/*******************************************************************************
83	* Defined Constants And Macros *
84	*******************************************************************************/
85	#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
86	#define EM_NOTIFY_HWACCM
87	#endif
88
89
90	/*******************************************************************************
91	* Internal Functions *
92	*******************************************************************************/
93	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
94	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
95	static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
96	static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
97	static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
98	static int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu);
99	static int emR3RawStep(PVM pVM, PVMCPU pVCpu);
100	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
101	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
102	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
103	static int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
104	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
105	static int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
106	static int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
107	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
108	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
109	static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations);
110	static EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
111	static void emR3RemLock(PVM pVM);
112	static void emR3RemUnlock(PVM pVM);
113
114	/**
115	* Initializes the EM.
116	*
117	* @returns VBox status code.
118	* @param pVM The VM to operate on.
119	*/
120	VMMR3DECL(int) EMR3Init(PVM pVM)
121	{
122	LogFlow(("EMR3Init\n"));
123	/*
124	* Assert alignment and sizes.
125	*/
126	AssertCompileMemberAlignment(VM, em.s, 32);
127	AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
128	AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
129	AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
130
131	/*
132	* Init the structure.
133	*/
134	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
135	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
136	if (RT_FAILURE(rc))
137	pVM->fRawR3Enabled = true;
138	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
139	if (RT_FAILURE(rc))
140	pVM->fRawR0Enabled = true;
141	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
142
143	/*
144	* Initialize the REM critical section.
145	*/
146	rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, "EM-REM");
147	AssertRCReturn(rc, rc);
148
149	/*
150	* Saved state.
151	*/
152	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
153	NULL, emR3Save, NULL,
154	NULL, emR3Load, NULL);
155	if (RT_FAILURE(rc))
156	return rc;
157
158	for (unsigned i=0;i<pVM->cCPUs;i++)
159	{
160	PVMCPU pVCpu = &pVM->aCpus[i];
161
162	pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
163
164	pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
165	pVCpu->em.s.enmPrevState = EMSTATE_NONE;
166	pVCpu->em.s.fForceRAW = false;
167
168	pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
169	pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
170	AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
171
172	# define EM_REG_COUNTER(a, b, c) \
173	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
174	AssertRC(rc);
175
176	# define EM_REG_COUNTER_USED(a, b, c) \
177	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
178	AssertRC(rc);
179
180	# define EM_REG_PROFILE(a, b, c) \
181	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
182	AssertRC(rc);
183
184	# define EM_REG_PROFILE_ADV(a, b, c) \
185	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
186	AssertRC(rc);
187
188	/*
189	* Statistics.
190	*/
191	#ifdef VBOX_WITH_STATISTICS
192	PEMSTATS pStats;
193	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
194	if (RT_FAILURE(rc))
195	return rc;
196
197	pVCpu->em.s.pStatsR3 = pStats;
198	pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
199	pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
200
201	EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
202	EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
203
204	EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
205	EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
206
207	EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
208	EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
209	EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
210	EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
211	EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
212	EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
213	EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
214	EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
215	EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
216	EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
217	EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
218	EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
219	EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
220	EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
221	EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
222	EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
223	EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
224	EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
225	EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
226	EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
227	EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
228	EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
229	EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
230	EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
231	EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
232	EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
233	EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
234	EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
235	EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
236	EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
237	EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
238	EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
239	EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
240	EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
241	EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
242	EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
243	EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
244	EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
245	EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
246	EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
247	EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
248	EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
249	EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
250	EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
251	EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
252	EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
253	EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
254	EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
255	EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
256	EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
257	EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
258	EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
259	EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
260	EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
261	EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
262	EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
263	EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
264	EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
265	EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
266	EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
267	EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
268	EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
269	EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
270	EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
271	EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
272	EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
273	EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
274	EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
275	EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
276	EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
277	EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
278	EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
279
280	EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
281	EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
282
283	EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
284	EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
285	EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
286	EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
287	EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
288	EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
289	EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
290	EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
291	EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
292	EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
293	EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
294	EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
295	EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
296	EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
297	EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
298	EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
299	EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
300	EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
301	EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
302	EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
303	EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
304	EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
305	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
306	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
307	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
308	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
309	EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
310	EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
311	EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
312	EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
313	EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
314	EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
315	EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
316	EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
317	EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
318	EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
319	EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
320	EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
321	EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
322	EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
323	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
324	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
325	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
326	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
327	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
328	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
329	EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
330	EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
331	EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
332	EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
333
334	EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
335	EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
336	EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
337	EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
338	EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
339	EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
340	EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
341	EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
342	EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
343	EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
344	EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
345	EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
346	EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
347	EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
348	EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
349	EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
350	EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
351	EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
352	EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
353	EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
354	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
355	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
356	EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
357	EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
358	EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
359	EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
360	EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
361	EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
362
363	EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
364	EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
365	EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
366	EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
367
368	EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
369	EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
370	EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
371	EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
372	EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
373	EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
374	EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
375	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 read instructions.");
376	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 read instructions.");
377	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 read instructions.");
378	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 read instructions.");
379	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 read instructions.");
380	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 write instructions.");
381	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 write instructions.");
382	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 write instructions.");
383	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 write instructions.");
384	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 write instructions.");
385	EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
386	EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
387	EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
388	EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
389	EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
390	EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
391	EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
392	EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
393	EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
394
395	EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
396	pVCpu->em.s.pCliStatTree = 0;
397
398	/* these should be considered for release statistics. */
399	EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
400	EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
401	EM_REG_COUNTER(&pVCpu->em.s.StatMiscEmu, "/PROF/CPU%d/EM/Emulation/Misc", "Profiling of emR3RawExecuteInstruction.");
402	EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
403	EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
404	EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
405	EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
406	EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
407	EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
408	EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
409	EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
410
411	#endif /* VBOX_WITH_STATISTICS */
412
413	EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
414	EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
415	EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
416	EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
417
418	EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
419	}
420
421	return VINF_SUCCESS;
422	}
423
424
425	/**
426	* Initializes the per-VCPU EM.
427	*
428	* @returns VBox status code.
429	* @param pVM The VM to operate on.
430	*/
431	VMMR3DECL(int) EMR3InitCPU(PVM pVM)
432	{
433	LogFlow(("EMR3InitCPU\n"));
434	return VINF_SUCCESS;
435	}
436
437
438	/**
439	* Applies relocations to data and code managed by this
440	* component. This function will be called at init and
441	* whenever the VMM need to relocate it self inside the GC.
442	*
443	* @param pVM The VM.
444	*/
445	VMMR3DECL(void) EMR3Relocate(PVM pVM)
446	{
447	LogFlow(("EMR3Relocate\n"));
448	for (unsigned i=0;i<pVM->cCPUs;i++)
449	{
450	PVMCPU pVCpu = &pVM->aCpus[i];
451
452	if (pVCpu->em.s.pStatsR3)
453	pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
454	}
455	}
456
457
458	/**
459	* Reset notification.
460	*
461	* @param pVM
462	*/
463	VMMR3DECL(void) EMR3Reset(PVM pVM)
464	{
465	LogFlow(("EMR3Reset: \n"));
466	for (unsigned i=0;i<pVM->cCPUs;i++)
467	{
468	PVMCPU pVCpu = &pVM->aCpus[i];
469
470	pVCpu->em.s.fForceRAW = false;
471	}
472	}
473
474
475	/**
476	* Terminates the EM.
477	*
478	* Termination means cleaning up and freeing all resources,
479	* the VM it self is at this point powered off or suspended.
480	*
481	* @returns VBox status code.
482	* @param pVM The VM to operate on.
483	*/
484	VMMR3DECL(int) EMR3Term(PVM pVM)
485	{
486	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
487
488	PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
489	return VINF_SUCCESS;
490	}
491
492	/**
493	* Terminates the per-VCPU EM.
494	*
495	* Termination means cleaning up and freeing all resources,
496	* the VM it self is at this point powered off or suspended.
497	*
498	* @returns VBox status code.
499	* @param pVM The VM to operate on.
500	*/
501	VMMR3DECL(int) EMR3TermCPU(PVM pVM)
502	{
503	return 0;
504	}
505
506	/**
507	* Execute state save operation.
508	*
509	* @returns VBox status code.
510	* @param pVM VM Handle.
511	* @param pSSM SSM operation handle.
512	*/
513	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
514	{
515	for (unsigned i=0;i<pVM->cCPUs;i++)
516	{
517	PVMCPU pVCpu = &pVM->aCpus[i];
518
519	int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
520	AssertRCReturn(rc, rc);
521	}
522	return VINF_SUCCESS;
523	}
524
525
526	/**
527	* Execute state load operation.
528	*
529	* @returns VBox status code.
530	* @param pVM VM Handle.
531	* @param pSSM SSM operation handle.
532	* @param u32Version Data layout version.
533	*/
534	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
535	{
536	int rc = VINF_SUCCESS;
537
538	/*
539	* Validate version.
540	*/
541	if (u32Version != EM_SAVED_STATE_VERSION)
542	{
543	AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
544	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
545	}
546
547	/*
548	* Load the saved state.
549	*/
550	for (unsigned i=0;i<pVM->cCPUs;i++)
551	{
552	PVMCPU pVCpu = &pVM->aCpus[i];
553
554	rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
555	if (RT_FAILURE(rc))
556	pVCpu->em.s.fForceRAW = false;
557
558	Assert(!pVCpu->em.s.pCliStatTree);
559	}
560	return rc;
561	}
562
563
564	/**
565	* Enables or disables a set of raw-mode execution modes.
566	*
567	* @returns VINF_SUCCESS on success.
568	* @returns VINF_RESCHEDULE if a rescheduling might be required.
569	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
570	*
571	* @param pVM The VM to operate on.
572	* @param enmMode The execution mode change.
573	* @thread The emulation thread.
574	*/
575	VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
576	{
577	switch (enmMode)
578	{
579	case EMRAW_NONE:
580	pVM->fRawR3Enabled = false;
581	pVM->fRawR0Enabled = false;
582	break;
583	case EMRAW_RING3_ENABLE:
584	pVM->fRawR3Enabled = true;
585	break;
586	case EMRAW_RING3_DISABLE:
587	pVM->fRawR3Enabled = false;
588	break;
589	case EMRAW_RING0_ENABLE:
590	pVM->fRawR0Enabled = true;
591	break;
592	case EMRAW_RING0_DISABLE:
593	pVM->fRawR0Enabled = false;
594	break;
595	default:
596	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
597	return VERR_INVALID_PARAMETER;
598	}
599	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
600	pVM->fRawR3Enabled, pVM->fRawR0Enabled));
601	return pVM->aCpus[0].em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
602	}
603
604
605	/**
606	* Raise a fatal error.
607	*
608	* Safely terminate the VM with full state report and stuff. This function
609	* will naturally never return.
610	*
611	* @param pVCpu VMCPU handle.
612	* @param rc VBox status code.
613	*/
614	VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
615	{
616	longjmp(pVCpu->em.s.u.FatalLongJump, rc);
617	AssertReleaseMsgFailed(("longjmp returned!\n"));
618	}
619
620
621	/**
622	* Gets the EM state name.
623	*
624	* @returns pointer to read only state name,
625	* @param enmState The state.
626	*/
627	VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
628	{
629	switch (enmState)
630	{
631	case EMSTATE_NONE: return "EMSTATE_NONE";
632	case EMSTATE_RAW: return "EMSTATE_RAW";
633	case EMSTATE_HWACC: return "EMSTATE_HWACC";
634	case EMSTATE_REM: return "EMSTATE_REM";
635	case EMSTATE_PARAV: return "EMSTATE_PARAV";
636	case EMSTATE_HALTED: return "EMSTATE_HALTED";
637	case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
638	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
639	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
640	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
641	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
642	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
643	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
644	default: return "Unknown!";
645	}
646	}
647
648
649	#ifdef VBOX_WITH_STATISTICS
650	/**
651	* Just a braindead function to keep track of cli addresses.
652	* @param pVM VM handle.
653	* @param pVMCPU VMCPU handle.
654	* @param GCPtrInstr The EIP of the cli instruction.
655	*/
656	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
657	{
658	PCLISTAT pRec;
659
660	pRec = (PCLISTAT)RTAvlPVGet(&pVCpu->em.s.pCliStatTree, (AVLPVKEY)GCPtrInstr);
661	if (!pRec)
662	{
663	/* New cli instruction; insert into the tree. */
664	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
665	Assert(pRec);
666	if (!pRec)
667	return;
668	pRec->Core.Key = (AVLPVKEY)GCPtrInstr;
669
670	char szCliStatName[32];
671	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
672	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
673
674	bool fRc = RTAvlPVInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
675	Assert(fRc); NOREF(fRc);
676	}
677	STAM_COUNTER_INC(&pRec->Counter);
678	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
679	}
680	#endif /* VBOX_WITH_STATISTICS */
681
682
683	/**
684	* Debug loop.
685	*
686	* @returns VBox status code for EM.
687	* @param pVM VM handle.
688	* @param pVCpu VMCPU handle.
689	* @param rc Current EM VBox status code..
690	*/
691	static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
692	{
693	for (;;)
694	{
695	Log(("emR3Debug: rc=%Rrc\n", rc));
696	const int rcLast = rc;
697
698	/*
699	* Debug related RC.
700	*/
701	switch (rc)
702	{
703	/*
704	* Single step an instruction.
705	*/
706	case VINF_EM_DBG_STEP:
707	if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
708	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
709	\|\| pVCpu->em.s.fForceRAW /* paranoia */)
710	rc = emR3RawStep(pVM, pVCpu);
711	else
712	{
713	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
714	rc = emR3RemStep(pVM, pVCpu);
715	}
716	break;
717
718	/*
719	* Simple events: stepped, breakpoint, stop/assertion.
720	*/
721	case VINF_EM_DBG_STEPPED:
722	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
723	break;
724
725	case VINF_EM_DBG_BREAKPOINT:
726	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
727	break;
728
729	case VINF_EM_DBG_STOP:
730	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
731	break;
732
733	case VINF_EM_DBG_HYPER_STEPPED:
734	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
735	break;
736
737	case VINF_EM_DBG_HYPER_BREAKPOINT:
738	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
739	break;
740
741	case VINF_EM_DBG_HYPER_ASSERTION:
742	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
743	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
744	break;
745
746	/*
747	* Guru meditation.
748	*/
749	case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
750	rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
751	break;
752	case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
753	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
754	break;
755
756	default: /** @todo don't use default for guru, but make special errors code! */
757	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
758	break;
759	}
760
761	/*
762	* Process the result.
763	*/
764	do
765	{
766	switch (rc)
767	{
768	/*
769	* Continue the debugging loop.
770	*/
771	case VINF_EM_DBG_STEP:
772	case VINF_EM_DBG_STOP:
773	case VINF_EM_DBG_STEPPED:
774	case VINF_EM_DBG_BREAKPOINT:
775	case VINF_EM_DBG_HYPER_STEPPED:
776	case VINF_EM_DBG_HYPER_BREAKPOINT:
777	case VINF_EM_DBG_HYPER_ASSERTION:
778	break;
779
780	/*
781	* Resuming execution (in some form) has to be done here if we got
782	* a hypervisor debug event.
783	*/
784	case VINF_SUCCESS:
785	case VINF_EM_RESUME:
786	case VINF_EM_SUSPEND:
787	case VINF_EM_RESCHEDULE:
788	case VINF_EM_RESCHEDULE_RAW:
789	case VINF_EM_RESCHEDULE_REM:
790	case VINF_EM_HALT:
791	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
792	{
793	rc = emR3RawResumeHyper(pVM, pVCpu);
794	if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
795	continue;
796	}
797	if (rc == VINF_SUCCESS)
798	rc = VINF_EM_RESCHEDULE;
799	return rc;
800
801	/*
802	* The debugger isn't attached.
803	* We'll simply turn the thing off since that's the easiest thing to do.
804	*/
805	case VERR_DBGF_NOT_ATTACHED:
806	switch (rcLast)
807	{
808	case VINF_EM_DBG_HYPER_STEPPED:
809	case VINF_EM_DBG_HYPER_BREAKPOINT:
810	case VINF_EM_DBG_HYPER_ASSERTION:
811	case VERR_TRPM_PANIC:
812	case VERR_TRPM_DONT_PANIC:
813	case VERR_VMM_RING0_ASSERTION:
814	return rcLast;
815	}
816	return VINF_EM_OFF;
817
818	/*
819	* Status codes terminating the VM in one or another sense.
820	*/
821	case VINF_EM_TERMINATE:
822	case VINF_EM_OFF:
823	case VINF_EM_RESET:
824	case VINF_EM_NO_MEMORY:
825	case VINF_EM_RAW_STALE_SELECTOR:
826	case VINF_EM_RAW_IRET_TRAP:
827	case VERR_TRPM_PANIC:
828	case VERR_TRPM_DONT_PANIC:
829	case VERR_VMM_RING0_ASSERTION:
830	case VERR_INTERNAL_ERROR:
831	case VERR_INTERNAL_ERROR_2:
832	case VERR_INTERNAL_ERROR_3:
833	case VERR_INTERNAL_ERROR_4:
834	case VERR_INTERNAL_ERROR_5:
835	case VERR_IPE_UNEXPECTED_STATUS:
836	case VERR_IPE_UNEXPECTED_INFO_STATUS:
837	case VERR_IPE_UNEXPECTED_ERROR_STATUS:
838	return rc;
839
840	/*
841	* The rest is unexpected, and will keep us here.
842	*/
843	default:
844	AssertMsgFailed(("Unxpected rc %Rrc!\n", rc));
845	break;
846	}
847	} while (false);
848	} /* debug for ever */
849	}
850
851	/**
852	* Locks REM execution to a single VCpu
853	*
854	* @param pVM VM handle.
855	*/
856	static void emR3RemLock(PVM pVM)
857	{
858	int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
859	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
860	}
861
862	/**
863	* Unlocks REM execution
864	*
865	* @param pVM VM handle.
866	*/
867	static void emR3RemUnlock(PVM pVM)
868	{
869	PDMCritSectLeave(&pVM->em.s.CritSectREM);
870	}
871
872	/**
873	* Steps recompiled code.
874	*
875	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
876	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
877	*
878	* @param pVM VM handle.
879	* @param pVCpu VMCPU handle.
880	*/
881	static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
882	{
883	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
884
885	emR3RemLock(pVM);
886
887	/*
888	* Switch to REM, step instruction, switch back.
889	*/
890	int rc = REMR3State(pVM, pVCpu);
891	if (RT_SUCCESS(rc))
892	{
893	rc = REMR3Step(pVM, pVCpu);
894	REMR3StateBack(pVM, pVCpu);
895	}
896	emR3RemUnlock(pVM);
897
898	LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
899	return rc;
900	}
901
902
903	/**
904	* Executes recompiled code.
905	*
906	* This function contains the recompiler version of the inner
907	* execution loop (the outer loop being in EMR3ExecuteVM()).
908	*
909	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
910	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
911	*
912	* @param pVM VM handle.
913	* @param pVCpu VMCPU handle.
914	* @param pfFFDone Where to store an indicator telling wheter or not
915	* FFs were done before returning.
916	*
917	*/
918	static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
919	{
920	#ifdef LOG_ENABLED
921	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
922	uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
923
924	if (pCtx->eflags.Bits.u1VM)
925	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
926	else
927	Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
928	#endif
929	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
930
931	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
932	AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
933	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo #1419 - get flat address. */
934	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
935	#endif
936
937	/* Big lock, but you are not supposed to own any lock when coming in here. */
938	emR3RemLock(pVM);
939
940	/*
941	* Spin till we get a forced action which returns anything but VINF_SUCCESS
942	* or the REM suggests raw-mode execution.
943	*/
944	*pfFFDone = false;
945	bool fInREMState = false;
946	int rc = VINF_SUCCESS;
947
948	/* Flush the recompiler TLB if the VCPU has changed. */
949	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
950	{
951	REMFlushTBs(pVM);
952	/* Also sync the entire state. */
953	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
954	}
955	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
956
957	for (;;)
958	{
959	/*
960	* Update REM state if not already in sync.
961	*/
962	if (!fInREMState)
963	{
964	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
965	rc = REMR3State(pVM, pVCpu);
966	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
967	if (RT_FAILURE(rc))
968	break;
969	fInREMState = true;
970
971	/*
972	* We might have missed the raising of VMREQ, TIMER and some other
973	* imporant FFs while we were busy switching the state. So, check again.
974	*/
975	if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET)
976	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER \| VMCPU_FF_REQUEST))
977	{
978	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
979	goto l_REMDoForcedActions;
980	}
981	}
982
983
984	/*
985	* Execute REM.
986	*/
987	STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
988	rc = REMR3Run(pVM, pVCpu);
989	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
990
991
992	/*
993	* Deal with high priority post execution FFs before doing anything else.
994	*/
995	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
996	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
997	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
998
999	/*
1000	* Process the returned status code.
1001	* (Try keep this short! Call functions!)
1002	*/
1003	if (rc != VINF_SUCCESS)
1004	{
1005	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1006	break;
1007	if (rc != VINF_REM_INTERRUPED_FF)
1008	{
1009	/*
1010	* Anything which is not known to us means an internal error
1011	* and the termination of the VM!
1012	*/
1013	AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1014	break;
1015	}
1016	}
1017
1018
1019	/*
1020	* Check and execute forced actions.
1021	* Sync back the VM state before calling any of these.
1022	*/
1023	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1024	TMTimerPoll(pVM, pVCpu);
1025	#endif
1026	AssertCompile((VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
1027	if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
1028	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE)))
1029	{
1030	l_REMDoForcedActions:
1031	if (fInREMState)
1032	{
1033	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, d);
1034	REMR3StateBack(pVM, pVCpu);
1035	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, d);
1036	fInREMState = false;
1037	}
1038	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1039	rc = emR3ForcedActions(pVM, pVCpu, rc);
1040	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1041	if ( rc != VINF_SUCCESS
1042	&& rc != VINF_EM_RESCHEDULE_REM)
1043	{
1044	*pfFFDone = true;
1045	break;
1046	}
1047	}
1048
1049	} /* The Inner Loop, recompiled execution mode version. */
1050
1051
1052	/*
1053	* Returning. Sync back the VM state if required.
1054	*/
1055	if (fInREMState)
1056	{
1057	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, e);
1058	REMR3StateBack(pVM, pVCpu);
1059	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, e);
1060	}
1061	emR3RemUnlock(pVM);
1062
1063	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1064	return rc;
1065	}
1066
1067
1068	/**
1069	* Resumes executing hypervisor after a debug event.
1070	*
1071	* This is kind of special since our current guest state is
1072	* potentially out of sync.
1073	*
1074	* @returns VBox status code.
1075	* @param pVM The VM handle.
1076	* @param pVCpu The VMCPU handle.
1077	*/
1078	static int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
1079	{
1080	int rc;
1081	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1082	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
1083	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
1084
1085	/*
1086	* Resume execution.
1087	*/
1088	CPUMRawEnter(pVCpu, NULL);
1089	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
1090	rc = VMMR3ResumeHyper(pVM, pVCpu);
1091	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
1092	rc = CPUMRawLeave(pVCpu, NULL, rc);
1093	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1094
1095	/*
1096	* Deal with the return code.
1097	*/
1098	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1099	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1100	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1101	return rc;
1102	}
1103
1104
1105	/**
1106	* Steps rawmode.
1107	*
1108	* @returns VBox status code.
1109	* @param pVM The VM handle.
1110	* @param pVCpu The VMCPU handle.
1111	*/
1112	static int emR3RawStep(PVM pVM, PVMCPU pVCpu)
1113	{
1114	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
1115	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
1116	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
1117	int rc;
1118	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1119	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
1120	#ifndef DEBUG_sandervl
1121	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
1122	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
1123	#endif
1124	if (fGuest)
1125	{
1126	/*
1127	* Check vital forced actions, but ignore pending interrupts and timers.
1128	*/
1129	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1130	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1131	{
1132	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1133	if (rc != VINF_SUCCESS)
1134	return rc;
1135	}
1136
1137	/*
1138	* Set flags for single stepping.
1139	*/
1140	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
1141	}
1142	else
1143	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
1144
1145	/*
1146	* Single step.
1147	* We do not start time or anything, if anything we should just do a few nanoseconds.
1148	*/
1149	CPUMRawEnter(pVCpu, NULL);
1150	do
1151	{
1152	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
1153	rc = VMMR3ResumeHyper(pVM, pVCpu);
1154	else
1155	rc = VMMR3RawRunGC(pVM, pVCpu);
1156	#ifndef DEBUG_sandervl
1157	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
1158	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
1159	#endif
1160	} while ( rc == VINF_SUCCESS
1161	\|\| rc == VINF_EM_RAW_INTERRUPT);
1162	rc = CPUMRawLeave(pVCpu, NULL, rc);
1163	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1164
1165	/*
1166	* Make sure the trap flag is cleared.
1167	* (Too bad if the guest is trying to single step too.)
1168	*/
1169	if (fGuest)
1170	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1171	else
1172	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
1173
1174	/*
1175	* Deal with the return codes.
1176	*/
1177	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1178	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1179	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1180	return rc;
1181	}
1182
1183
1184	#ifdef DEBUG
1185
1186	/**
1187	* Steps hardware accelerated mode.
1188	*
1189	* @returns VBox status code.
1190	* @param pVM The VM handle.
1191	* @param pVCpu The VMCPU handle.
1192	*/
1193	static int emR3HwAccStep(PVM pVM, PVMCPU pVCpu)
1194	{
1195	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1196
1197	int rc;
1198	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1199	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1200
1201	/*
1202	* Check vital forced actions, but ignore pending interrupts and timers.
1203	*/
1204	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1205	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1206	{
1207	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1208	if (rc != VINF_SUCCESS)
1209	return rc;
1210	}
1211	/*
1212	* Set flags for single stepping.
1213	*/
1214	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
1215
1216	/*
1217	* Single step.
1218	* We do not start time or anything, if anything we should just do a few nanoseconds.
1219	*/
1220	do
1221	{
1222	rc = VMMR3HwAccRunGC(pVM, pVCpu);
1223	} while ( rc == VINF_SUCCESS
1224	\|\| rc == VINF_EM_RAW_INTERRUPT);
1225	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1226
1227	/*
1228	* Make sure the trap flag is cleared.
1229	* (Too bad if the guest is trying to single step too.)
1230	*/
1231	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1232
1233	/*
1234	* Deal with the return codes.
1235	*/
1236	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1237	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1238	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1239	return rc;
1240	}
1241
1242
1243	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1244	{
1245	int rc = VINF_SUCCESS;
1246	EMSTATE enmOldState = pVCpu->em.s.enmState;
1247	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1248
1249	Log(("Single step BEGIN:\n"));
1250	for (uint32_t i = 0; i < cIterations; i++)
1251	{
1252	DBGFR3PrgStep(pVCpu);
1253	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1254	rc = emR3RawStep(pVM, pVCpu);
1255	if (rc != VINF_SUCCESS)
1256	break;
1257	}
1258	Log(("Single step END: rc=%Rrc\n", rc));
1259	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1260	pVCpu->em.s.enmState = enmOldState;
1261	return rc;
1262	}
1263
1264
1265	static int emR3SingleStepExecHwAcc(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1266	{
1267	int rc = VINF_SUCCESS;
1268	EMSTATE enmOldState = pVCpu->em.s.enmState;
1269	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1270
1271	Log(("Single step BEGIN:\n"));
1272	for (uint32_t i = 0; i < cIterations; i++)
1273	{
1274	DBGFR3PrgStep(pVCpu);
1275	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1276	rc = emR3HwAccStep(pVM, pVCpu);
1277	if ( rc != VINF_SUCCESS
1278	\|\| !HWACCMR3CanExecuteGuest(pVM, pVCpu->em.s.pCtx))
1279	break;
1280	}
1281	Log(("Single step END: rc=%Rrc\n", rc));
1282	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1283	pVCpu->em.s.enmState = enmOldState;
1284	return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
1285	}
1286
1287
1288	static int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1289	{
1290	EMSTATE enmOldState = pVCpu->em.s.enmState;
1291
1292	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1293
1294	Log(("Single step BEGIN:\n"));
1295	for (uint32_t i = 0; i < cIterations; i++)
1296	{
1297	DBGFR3PrgStep(pVCpu);
1298	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1299	emR3RemStep(pVM, pVCpu);
1300	if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1301	break;
1302	}
1303	Log(("Single step END:\n"));
1304	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1305	pVCpu->em.s.enmState = enmOldState;
1306	return VINF_EM_RESCHEDULE;
1307	}
1308
1309	#endif /* DEBUG */
1310
1311
1312	/**
1313	* Executes one (or perhaps a few more) instruction(s).
1314	*
1315	* @returns VBox status code suitable for EM.
1316	*
1317	* @param pVM VM handle.
1318	* @param pVCpu VMCPU handle
1319	* @param rcGC GC return code
1320	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1321	* instruction and prefix the log output with this text.
1322	*/
1323	#ifdef LOG_ENABLED
1324	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
1325	#else
1326	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
1327	#endif
1328	{
1329	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1330	int rc;
1331
1332	/*
1333	*
1334	* The simple solution is to use the recompiler.
1335	* The better solution is to disassemble the current instruction and
1336	* try handle as many as possible without using REM.
1337	*
1338	*/
1339
1340	#ifdef LOG_ENABLED
1341	/*
1342	* Disassemble the instruction if requested.
1343	*/
1344	if (pszPrefix)
1345	{
1346	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1347	DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
1348	}
1349	#endif /* LOG_ENABLED */
1350
1351	/*
1352	* PATM is making life more interesting.
1353	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1354	* tell PATM there is a trap in this code and have it take the appropriate actions
1355	* to allow us execute the code in REM.
1356	*/
1357	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1358	{
1359	Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
1360
1361	RTGCPTR pNewEip;
1362	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1363	switch (rc)
1364	{
1365	/*
1366	* It's not very useful to emulate a single instruction and then go back to raw
1367	* mode; just execute the whole block until IF is set again.
1368	*/
1369	case VINF_SUCCESS:
1370	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
1371	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1372	pCtx->eip = pNewEip;
1373	Assert(pCtx->eip);
1374
1375	if (pCtx->eflags.Bits.u1IF)
1376	{
1377	/*
1378	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1379	*/
1380	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1381	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1382	}
1383	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1384	{
1385	/* special case: iret, that sets IF, detected a pending irq/event */
1386	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET");
1387	}
1388	return VINF_EM_RESCHEDULE_REM;
1389
1390	/*
1391	* One instruction.
1392	*/
1393	case VINF_PATCH_EMULATE_INSTR:
1394	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1395	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1396	pCtx->eip = pNewEip;
1397	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1398
1399	/*
1400	* The patch was disabled, hand it to the REM.
1401	*/
1402	case VERR_PATCH_DISABLED:
1403	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
1404	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1405	pCtx->eip = pNewEip;
1406	if (pCtx->eflags.Bits.u1IF)
1407	{
1408	/*
1409	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1410	*/
1411	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1412	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1413	}
1414	return VINF_EM_RESCHEDULE_REM;
1415
1416	/* Force continued patch exection; usually due to write monitored stack. */
1417	case VINF_PATCH_CONTINUE:
1418	return VINF_SUCCESS;
1419
1420	default:
1421	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
1422	return VERR_IPE_UNEXPECTED_STATUS;
1423	}
1424	}
1425
1426	#if 0
1427	/* Try our own instruction emulator before falling back to the recompiler. */
1428	DISCPUSTATE Cpu;
1429	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1430	if (RT_SUCCESS(rc))
1431	{
1432	uint32_t size;
1433
1434	switch (Cpu.pCurInstr->opcode)
1435	{
1436	/* @todo we can do more now */
1437	case OP_MOV:
1438	case OP_AND:
1439	case OP_OR:
1440	case OP_XOR:
1441	case OP_POP:
1442	case OP_INC:
1443	case OP_DEC:
1444	case OP_XCHG:
1445	STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
1446	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1447	if (RT_SUCCESS(rc))
1448	{
1449	pCtx->rip += Cpu.opsize;
1450	#ifdef EM_NOTIFY_HWACCM
1451	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1452	HWACCMR3NotifyEmulated(pVCpu);
1453	#endif
1454	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
1455	return rc;
1456	}
1457	if (rc != VERR_EM_INTERPRETER)
1458	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
1459	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
1460	break;
1461	}
1462	}
1463	#endif /* 0 */
1464	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
1465	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
1466	emR3RemLock(pVM);
1467	/* Flush the recompiler TLB if the VCPU has changed. */
1468	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
1469	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1470	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
1471
1472	rc = REMR3EmulateInstruction(pVM, pVCpu);
1473	emR3RemUnlock(pVM);
1474	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
1475
1476	#ifdef EM_NOTIFY_HWACCM
1477	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1478	HWACCMR3NotifyEmulated(pVCpu);
1479	#endif
1480	return rc;
1481	}
1482
1483
1484	/**
1485	* Executes one (or perhaps a few more) instruction(s).
1486	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1487	*
1488	* @returns VBox status code suitable for EM.
1489	* @param pVM VM handle.
1490	* @param pVCpu VMCPU handle.
1491	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1492	* instruction and prefix the log output with this text.
1493	* @param rcGC GC return code
1494	*/
1495	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
1496	{
1497	#ifdef LOG_ENABLED
1498	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
1499	#else
1500	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
1501	#endif
1502	}
1503
1504	/**
1505	* Executes one (or perhaps a few more) IO instruction(s).
1506	*
1507	* @returns VBox status code suitable for EM.
1508	* @param pVM VM handle.
1509	* @param pVCpu VMCPU handle.
1510	*/
1511	int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
1512	{
1513	int rc;
1514	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1515
1516	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
1517
1518	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1519	* as io instructions tend to come in packages of more than one
1520	*/
1521	DISCPUSTATE Cpu;
1522	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
1523	if (RT_SUCCESS(rc))
1524	{
1525	rc = VINF_EM_RAW_EMULATE_INSTR;
1526
1527	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1528	{
1529	switch (Cpu.pCurInstr->opcode)
1530	{
1531	case OP_IN:
1532	{
1533	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
1534	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1535	break;
1536	}
1537
1538	case OP_OUT:
1539	{
1540	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
1541	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1542	break;
1543	}
1544	}
1545	}
1546	else if (Cpu.prefix & PREFIX_REP)
1547	{
1548	switch (Cpu.pCurInstr->opcode)
1549	{
1550	case OP_INSB:
1551	case OP_INSWD:
1552	{
1553	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
1554	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1555	break;
1556	}
1557
1558	case OP_OUTSB:
1559	case OP_OUTSWD:
1560	{
1561	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
1562	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1563	break;
1564	}
1565	}
1566	}
1567
1568	/*
1569	* Handled the I/O return codes.
1570	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1571	*/
1572	if (IOM_SUCCESS(rc))
1573	{
1574	pCtx->rip += Cpu.opsize;
1575	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1576	return rc;
1577	}
1578
1579	if (rc == VINF_EM_RAW_GUEST_TRAP)
1580	{
1581	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1582	rc = emR3RawGuestTrap(pVM, pVCpu);
1583	return rc;
1584	}
1585	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1586
1587	if (RT_FAILURE(rc))
1588	{
1589	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1590	return rc;
1591	}
1592	AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc=%Rrc\n", rc));
1593	}
1594	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1595	return emR3RawExecuteInstruction(pVM, pVCpu, "IO: ");
1596	}
1597
1598
1599	/**
1600	* Handle a guest context trap.
1601	*
1602	* @returns VBox status code suitable for EM.
1603	* @param pVM VM handle.
1604	* @param pVCpu VMCPU handle.
1605	*/
1606	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
1607	{
1608	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1609
1610	/*
1611	* Get the trap info.
1612	*/
1613	uint8_t u8TrapNo;
1614	TRPMEVENT enmType;
1615	RTGCUINT uErrorCode;
1616	RTGCUINTPTR uCR2;
1617	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1618	if (RT_FAILURE(rc))
1619	{
1620	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
1621	return rc;
1622	}
1623
1624	/*
1625	* Traps can be directly forwarded in hardware accelerated mode.
1626	*/
1627	if (HWACCMIsEnabled(pVM))
1628	{
1629	#ifdef LOGGING_ENABLED
1630	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1631	DBGFR3DisasInstrCurrentLog(pVCpu, "Guest trap");
1632	#endif
1633	return VINF_EM_RESCHEDULE_HWACC;
1634	}
1635
1636	#if 1 /* Experimental: Review, disable if it causes trouble. */
1637	/*
1638	* Handle traps in patch code first.
1639	*
1640	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
1641	* but several traps isn't handled specially by TRPM in RC and we end up here
1642	* instead. One example is #DE.
1643	*/
1644	uint32_t uCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
1645	if ( uCpl == 0
1646	&& PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1647	{
1648	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
1649	return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
1650	}
1651	#endif
1652
1653	/*
1654	* If the guest gate is marked unpatched, then we will check again if we can patch it.
1655	* (This assumes that we've already tried and failed to dispatch the trap in
1656	* RC for the gates that already has been patched. Which is true for most high
1657	* volume traps, because these are handled specially, but not for odd ones like #DE.)
1658	*/
1659	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
1660	{
1661	CSAMR3CheckGates(pVM, u8TrapNo, 1);
1662	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
1663
1664	/* If it was successful, then we could go back to raw mode. */
1665	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
1666	{
1667	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
1668	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1669	AssertRCReturn(rc, rc);
1670
1671	TRPMERRORCODE enmError = uErrorCode != ~0U
1672	? TRPM_TRAP_HAS_ERRORCODE
1673	: TRPM_TRAP_NO_ERRORCODE;
1674	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
1675	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1676	{
1677	TRPMResetTrap(pVCpu);
1678	return VINF_EM_RESCHEDULE_RAW;
1679	}
1680	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
1681	}
1682	}
1683
1684	/*
1685	* Scan kernel code that traps; we might not get another chance.
1686	*/
1687	/** @todo move this up before the dispatching? */
1688	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1689	&& !pCtx->eflags.Bits.u1VM)
1690	{
1691	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1692	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1693	}
1694
1695	/*
1696	* Trap specific handling.
1697	*/
1698	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1699	{
1700	/*
1701	* If MONITOR & MWAIT are supported, then interpret them here.
1702	*/
1703	DISCPUSTATE cpu;
1704	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1705	if ( RT_SUCCESS(rc)
1706	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1707	{
1708	uint32_t u32Dummy, u32Features, u32ExtFeatures;
1709	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1710	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1711	{
1712	rc = TRPMResetTrap(pVCpu);
1713	AssertRC(rc);
1714
1715	uint32_t opsize;
1716	rc = EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
1717	if (RT_SUCCESS(rc))
1718	{
1719	pCtx->rip += cpu.opsize;
1720	#ifdef EM_NOTIFY_HWACCM
1721	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1722	HWACCMR3NotifyEmulated(pVCpu);
1723	#endif
1724	return rc;
1725	}
1726	return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: ");
1727	}
1728	}
1729	}
1730	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1731	{
1732	/*
1733	* Handle I/O bitmap?
1734	*/
1735	/** @todo We're not supposed to be here with a false guest trap concerning
1736	* I/O access. We can easily handle those in RC. */
1737	DISCPUSTATE cpu;
1738	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1739	if ( RT_SUCCESS(rc)
1740	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1741	{
1742	/*
1743	* We should really check the TSS for the IO bitmap, but it's not like this
1744	* lazy approach really makes things worse.
1745	*/
1746	rc = TRPMResetTrap(pVCpu);
1747	AssertRC(rc);
1748	return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
1749	}
1750	}
1751
1752	#ifdef LOG_ENABLED
1753	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1754	DBGFR3DisasInstrCurrentLog(pVCpu, "Guest trap");
1755
1756	/* Get guest page information. */
1757	uint64_t fFlags = 0;
1758	RTGCPHYS GCPhys = 0;
1759	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
1760	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1761	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1762	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1763	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1764	#endif
1765
1766	/*
1767	* #PG has CR2.
1768	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1769	*/
1770	if (u8TrapNo == 14 /* #PG */)
1771	pCtx->cr2 = uCR2;
1772
1773	return VINF_EM_RESCHEDULE_REM;
1774	}
1775
1776
1777	/**
1778	* Handle a ring switch trap.
1779	* Need to do statistics and to install patches. The result is going to REM.
1780	*
1781	* @returns VBox status code suitable for EM.
1782	* @param pVM VM handle.
1783	* @param pVCpu VMCPU handle.
1784	*/
1785	int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
1786	{
1787	int rc;
1788	DISCPUSTATE Cpu;
1789	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1790
1791	/*
1792	* sysenter, syscall & callgate
1793	*/
1794	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1795	if (RT_SUCCESS(rc))
1796	{
1797	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1798	{
1799	if (pCtx->SysEnter.cs != 0)
1800	{
1801	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1802	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1803	if (RT_SUCCESS(rc))
1804	{
1805	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched sysenter instruction");
1806	return VINF_EM_RESCHEDULE_RAW;
1807	}
1808	}
1809	}
1810
1811	#ifdef VBOX_WITH_STATISTICS
1812	switch (Cpu.pCurInstr->opcode)
1813	{
1814	case OP_SYSENTER:
1815	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
1816	break;
1817	case OP_SYSEXIT:
1818	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
1819	break;
1820	case OP_SYSCALL:
1821	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
1822	break;
1823	case OP_SYSRET:
1824	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
1825	break;
1826	}
1827	#endif
1828	}
1829	else
1830	AssertRC(rc);
1831
1832	/* go to the REM to emulate a single instruction */
1833	return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
1834	}
1835
1836
1837	/**
1838	* Handle a trap (\#PF or \#GP) in patch code
1839	*
1840	* @returns VBox status code suitable for EM.
1841	* @param pVM VM handle.
1842	* @param pVCpu VMCPU handle.
1843	* @param pCtx CPU context
1844	* @param gcret GC return code
1845	*/
1846	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
1847	{
1848	uint8_t u8TrapNo;
1849	int rc;
1850	TRPMEVENT enmType;
1851	RTGCUINT uErrorCode;
1852	RTGCUINTPTR uCR2;
1853
1854	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1855
1856	if (gcret == VINF_PATM_PATCH_INT3)
1857	{
1858	u8TrapNo = 3;
1859	uCR2 = 0;
1860	uErrorCode = 0;
1861	}
1862	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
1863	{
1864	/* No active trap in this case. Kind of ugly. */
1865	u8TrapNo = X86_XCPT_GP;
1866	uCR2 = 0;
1867	uErrorCode = 0;
1868	}
1869	else
1870	{
1871	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1872	if (RT_FAILURE(rc))
1873	{
1874	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
1875	return rc;
1876	}
1877	/* Reset the trap as we'll execute the original instruction again. */
1878	TRPMResetTrap(pVCpu);
1879	}
1880
1881	/*
1882	* Deal with traps inside patch code.
1883	* (This code won't run outside GC.)
1884	*/
1885	if (u8TrapNo != 1)
1886	{
1887	#ifdef LOG_ENABLED
1888	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1889	DBGFR3DisasInstrCurrentLog(pVCpu, "Patch code");
1890
1891	DISCPUSTATE Cpu;
1892	int rc;
1893
1894	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1895	if ( RT_SUCCESS(rc)
1896	&& Cpu.pCurInstr->opcode == OP_IRET)
1897	{
1898	uint32_t eip, selCS, uEFlags;
1899
1900	/* Iret crashes are bad as we have already changed the flags on the stack */
1901	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
1902	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
1903	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
1904	if (rc == VINF_SUCCESS)
1905	{
1906	if ( (uEFlags & X86_EFL_VM)
1907	\|\| (selCS & X86_SEL_RPL) == 3)
1908	{
1909	uint32_t selSS, esp;
1910
1911	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
1912	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
1913
1914	if (uEFlags & X86_EFL_VM)
1915	{
1916	uint32_t selDS, selES, selFS, selGS;
1917	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
1918	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
1919	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
1920	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
1921	if (rc == VINF_SUCCESS)
1922	{
1923	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1924	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1925	}
1926	}
1927	else
1928	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1929	}
1930	else
1931	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
1932	}
1933	}
1934	#endif /* LOG_ENABLED */
1935	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1936	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1937
1938	RTGCPTR pNewEip;
1939	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1940	switch (rc)
1941	{
1942	/*
1943	* Execute the faulting instruction.
1944	*/
1945	case VINF_SUCCESS:
1946	{
1947	/** @todo execute a whole block */
1948	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
1949	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1950	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1951
1952	pCtx->eip = pNewEip;
1953	AssertRelease(pCtx->eip);
1954
1955	if (pCtx->eflags.Bits.u1IF)
1956	{
1957	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1958	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1959	*/
1960	if ( u8TrapNo == X86_XCPT_GP
1961	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1962	{
1963	/** @todo move to PATMR3HandleTrap */
1964	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
1965	PATMR3RemovePatch(pVM, pCtx->eip);
1966	}
1967
1968	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1969	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
1970
1971	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1972	/* Interrupts are enabled; just go back to the original instruction.
1973	return VINF_SUCCESS; */
1974	}
1975	return VINF_EM_RESCHEDULE_REM;
1976	}
1977
1978	/*
1979	* One instruction.
1980	*/
1981	case VINF_PATCH_EMULATE_INSTR:
1982	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1983	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1984	pCtx->eip = pNewEip;
1985	AssertRelease(pCtx->eip);
1986	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
1987
1988	/*
1989	* The patch was disabled, hand it to the REM.
1990	*/
1991	case VERR_PATCH_DISABLED:
1992	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1993	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1994	pCtx->eip = pNewEip;
1995	AssertRelease(pCtx->eip);
1996
1997	if (pCtx->eflags.Bits.u1IF)
1998	{
1999	/*
2000	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
2001	*/
2002	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
2003	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
2004	}
2005	return VINF_EM_RESCHEDULE_REM;
2006
2007	/* Force continued patch exection; usually due to write monitored stack. */
2008	case VINF_PATCH_CONTINUE:
2009	return VINF_SUCCESS;
2010
2011	/*
2012	* Anything else is fatal.
2013	*/
2014	default:
2015	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
2016	return VERR_IPE_UNEXPECTED_STATUS;
2017	}
2018	}
2019	return VINF_SUCCESS;
2020	}
2021
2022
2023	/**
2024	* Handle a privileged instruction.
2025	*
2026	* @returns VBox status code suitable for EM.
2027	* @param pVM VM handle.
2028	* @param pVCpu VMCPU handle;
2029	*/
2030	int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
2031	{
2032	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
2033	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
2034
2035	Assert(!pCtx->eflags.Bits.u1VM);
2036
2037	if (PATMIsEnabled(pVM))
2038	{
2039	/*
2040	* Check if in patch code.
2041	*/
2042	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2043	{
2044	#ifdef LOG_ENABLED
2045	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2046	#endif
2047	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
2048	return VERR_EM_RAW_PATCH_CONFLICT;
2049	}
2050	if ( (pCtx->ss & X86_SEL_RPL) == 0
2051	&& !pCtx->eflags.Bits.u1VM
2052	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2053	{
2054	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2055	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
2056	if (RT_SUCCESS(rc))
2057	{
2058	#ifdef LOG_ENABLED
2059	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2060	#endif
2061	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched privileged instruction");
2062	return VINF_SUCCESS;
2063	}
2064	}
2065	}
2066
2067	#ifdef LOG_ENABLED
2068	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
2069	{
2070	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2071	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
2072	}
2073	#endif
2074
2075	/*
2076	* Instruction statistics and logging.
2077	*/
2078	DISCPUSTATE Cpu;
2079	int rc;
2080
2081	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
2082	if (RT_SUCCESS(rc))
2083	{
2084	#ifdef VBOX_WITH_STATISTICS
2085	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
2086	switch (Cpu.pCurInstr->opcode)
2087	{
2088	case OP_INVLPG:
2089	STAM_COUNTER_INC(&pStats->StatInvlpg);
2090	break;
2091	case OP_IRET:
2092	STAM_COUNTER_INC(&pStats->StatIret);
2093	break;
2094	case OP_CLI:
2095	STAM_COUNTER_INC(&pStats->StatCli);
2096	emR3RecordCli(pVM, pVCpu, pCtx->rip);
2097	break;
2098	case OP_STI:
2099	STAM_COUNTER_INC(&pStats->StatSti);
2100	break;
2101	case OP_INSB:
2102	case OP_INSWD:
2103	case OP_IN:
2104	case OP_OUTSB:
2105	case OP_OUTSWD:
2106	case OP_OUT:
2107	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
2108	break;
2109
2110	case OP_MOV_CR:
2111	if (Cpu.param1.flags & USE_REG_GEN32)
2112	{
2113	//read
2114	Assert(Cpu.param2.flags & USE_REG_CR);
2115	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
2116	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
2117	}
2118	else
2119	{
2120	//write
2121	Assert(Cpu.param1.flags & USE_REG_CR);
2122	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
2123	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
2124	}
2125	break;
2126
2127	case OP_MOV_DR:
2128	STAM_COUNTER_INC(&pStats->StatMovDRx);
2129	break;
2130	case OP_LLDT:
2131	STAM_COUNTER_INC(&pStats->StatMovLldt);
2132	break;
2133	case OP_LIDT:
2134	STAM_COUNTER_INC(&pStats->StatMovLidt);
2135	break;
2136	case OP_LGDT:
2137	STAM_COUNTER_INC(&pStats->StatMovLgdt);
2138	break;
2139	case OP_SYSENTER:
2140	STAM_COUNTER_INC(&pStats->StatSysEnter);
2141	break;
2142	case OP_SYSEXIT:
2143	STAM_COUNTER_INC(&pStats->StatSysExit);
2144	break;
2145	case OP_SYSCALL:
2146	STAM_COUNTER_INC(&pStats->StatSysCall);
2147	break;
2148	case OP_SYSRET:
2149	STAM_COUNTER_INC(&pStats->StatSysRet);
2150	break;
2151	case OP_HLT:
2152	STAM_COUNTER_INC(&pStats->StatHlt);
2153	break;
2154	default:
2155	STAM_COUNTER_INC(&pStats->StatMisc);
2156	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
2157	break;
2158	}
2159	#endif /* VBOX_WITH_STATISTICS */
2160	if ( (pCtx->ss & X86_SEL_RPL) == 0
2161	&& !pCtx->eflags.Bits.u1VM
2162	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
2163	{
2164	uint32_t size;
2165
2166	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
2167	switch (Cpu.pCurInstr->opcode)
2168	{
2169	case OP_CLI:
2170	pCtx->eflags.u32 &= ~X86_EFL_IF;
2171	Assert(Cpu.opsize == 1);
2172	pCtx->rip += Cpu.opsize;
2173	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2174	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
2175
2176	case OP_STI:
2177	pCtx->eflags.u32 \|= X86_EFL_IF;
2178	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.opsize);
2179	Assert(Cpu.opsize == 1);
2180	pCtx->rip += Cpu.opsize;
2181	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2182	return VINF_SUCCESS;
2183
2184	case OP_HLT:
2185	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
2186	{
2187	PATMTRANSSTATE enmState;
2188	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
2189
2190	if (enmState == PATMTRANS_OVERWRITTEN)
2191	{
2192	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2193	Assert(rc == VERR_PATCH_DISABLED);
2194	/* Conflict detected, patch disabled */
2195	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
2196
2197	enmState = PATMTRANS_SAFE;
2198	}
2199
2200	/* The translation had better be successful. Otherwise we can't recover. */
2201	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
2202	if (enmState != PATMTRANS_OVERWRITTEN)
2203	pCtx->eip = pOrgInstrGC;
2204	}
2205	/* no break; we could just return VINF_EM_HALT here */
2206
2207	case OP_MOV_CR:
2208	case OP_MOV_DR:
2209	#ifdef LOG_ENABLED
2210	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2211	{
2212	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2213	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
2214	}
2215	#endif
2216
2217	rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2218	if (RT_SUCCESS(rc))
2219	{
2220	pCtx->rip += Cpu.opsize;
2221	#ifdef EM_NOTIFY_HWACCM
2222	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
2223	HWACCMR3NotifyEmulated(pVCpu);
2224	#endif
2225	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2226
2227	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2228	&& Cpu.param1.flags == USE_REG_CR /* write */
2229	)
2230	{
2231	/* Deal with CR0 updates inside patch code that force
2232	* us to go to the recompiler.
2233	*/
2234	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
2235	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
2236	{
2237	PATMTRANSSTATE enmState;
2238	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
2239
2240	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
2241	if (enmState == PATMTRANS_OVERWRITTEN)
2242	{
2243	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2244	Assert(rc == VERR_PATCH_DISABLED);
2245	/* Conflict detected, patch disabled */
2246	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
2247	enmState = PATMTRANS_SAFE;
2248	}
2249	/* The translation had better be successful. Otherwise we can't recover. */
2250	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
2251	if (enmState != PATMTRANS_OVERWRITTEN)
2252	pCtx->rip = pOrgInstrGC;
2253	}
2254
2255	/* Reschedule is necessary as the execution/paging mode might have changed. */
2256	return VINF_EM_RESCHEDULE;
2257	}
2258	return rc; /* can return VINF_EM_HALT as well. */
2259	}
2260	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
2261	break; /* fall back to the recompiler */
2262	}
2263	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2264	}
2265	}
2266
2267	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2268	return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
2269
2270	return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV");
2271	}
2272
2273
2274	/**
2275	* Update the forced rawmode execution modifier.
2276	*
2277	* This function is called when we're returning from the raw-mode loop(s). If we're
2278	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2279	* if not in patch code, the flag will be cleared.
2280	*
2281	* We should never interrupt patch code while it's being executed. Cli patches can
2282	* contain big code blocks, but they are always executed with IF=0. Other patches
2283	* replace single instructions and should be atomic.
2284	*
2285	* @returns Updated rc.
2286	*
2287	* @param pVM The VM handle.
2288	* @param pVCpu The VMCPU handle.
2289	* @param pCtx The guest CPU context.
2290	* @param rc The result code.
2291	*/
2292	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
2293	{
2294	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2295	{
2296	/* ignore reschedule attempts. */
2297	switch (rc)
2298	{
2299	case VINF_EM_RESCHEDULE:
2300	case VINF_EM_RESCHEDULE_REM:
2301	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
2302	rc = VINF_SUCCESS;
2303	break;
2304	}
2305	pVCpu->em.s.fForceRAW = true;
2306	}
2307	else
2308	pVCpu->em.s.fForceRAW = false;
2309	return rc;
2310	}
2311
2312
2313	/**
2314	* Process a subset of the raw-mode return code.
2315	*
2316	* Since we have to share this with raw-mode single stepping, this inline
2317	* function has been created to avoid code duplication.
2318	*
2319	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2320	* @returns VBox status code to return to the EM main loop.
2321	*
2322	* @param pVM The VM handle
2323	* @param pVCpu The VMCPU handle
2324	* @param rc The return code.
2325	* @param pCtx The guest cpu context.
2326	*/
2327	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
2328	{
2329	switch (rc)
2330	{
2331	/*
2332	* Common & simple ones.
2333	*/
2334	case VINF_SUCCESS:
2335	break;
2336	case VINF_EM_RESCHEDULE_RAW:
2337	case VINF_EM_RESCHEDULE_HWACC:
2338	case VINF_EM_RAW_INTERRUPT:
2339	case VINF_EM_RAW_TO_R3:
2340	case VINF_EM_RAW_TIMER_PENDING:
2341	case VINF_EM_PENDING_REQUEST:
2342	rc = VINF_SUCCESS;
2343	break;
2344
2345	/*
2346	* Privileged instruction.
2347	*/
2348	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2349	case VINF_PATM_PATCH_TRAP_GP:
2350	rc = emR3RawPrivileged(pVM, pVCpu);
2351	break;
2352
2353	/*
2354	* Got a trap which needs dispatching.
2355	*/
2356	case VINF_EM_RAW_GUEST_TRAP:
2357	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2358	{
2359	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
2360	rc = VERR_EM_RAW_PATCH_CONFLICT;
2361	break;
2362	}
2363	rc = emR3RawGuestTrap(pVM, pVCpu);
2364	break;
2365
2366	/*
2367	* Trap in patch code.
2368	*/
2369	case VINF_PATM_PATCH_TRAP_PF:
2370	case VINF_PATM_PATCH_INT3:
2371	rc = emR3PatchTrap(pVM, pVCpu, pCtx, rc);
2372	break;
2373
2374	case VINF_PATM_DUPLICATE_FUNCTION:
2375	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2376	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2377	AssertRC(rc);
2378	rc = VINF_SUCCESS;
2379	break;
2380
2381	case VINF_PATM_CHECK_PATCH_PAGE:
2382	rc = PATMR3HandleMonitoredPage(pVM);
2383	AssertRC(rc);
2384	rc = VINF_SUCCESS;
2385	break;
2386
2387	/*
2388	* Patch manager.
2389	*/
2390	case VERR_EM_RAW_PATCH_CONFLICT:
2391	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
2392	break;
2393
2394	#ifdef VBOX_WITH_VMI
2395	/*
2396	* PARAV function.
2397	*/
2398	case VINF_EM_RESCHEDULE_PARAV:
2399	rc = PARAVCallFunction(pVM);
2400	break;
2401	#endif
2402
2403	/*
2404	* Memory mapped I/O access - attempt to patch the instruction
2405	*/
2406	case VINF_PATM_HC_MMIO_PATCH_READ:
2407	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2408	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2409	if (RT_FAILURE(rc))
2410	rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
2411	break;
2412
2413	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2414	AssertFailed(); /* not yet implemented. */
2415	rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
2416	break;
2417
2418	/*
2419	* Conflict or out of page tables.
2420	*
2421	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2422	* do here is to execute the pending forced actions.
2423	*/
2424	case VINF_PGM_SYNC_CR3:
2425	AssertMsg(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
2426	("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
2427	rc = VINF_SUCCESS;
2428	break;
2429
2430	/*
2431	* Paging mode change.
2432	*/
2433	case VINF_PGM_CHANGE_MODE:
2434	rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2435	if (rc == VINF_SUCCESS)
2436	rc = VINF_EM_RESCHEDULE;
2437	AssertMsg(RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
2438	break;
2439
2440	/*
2441	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2442	*/
2443	case VINF_CSAM_PENDING_ACTION:
2444	rc = VINF_SUCCESS;
2445	break;
2446
2447	/*
2448	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2449	*/
2450	case VINF_EM_RAW_INTERRUPT_PENDING:
2451	case VINF_EM_RAW_RING_SWITCH_INT:
2452	Assert(TRPMHasTrap(pVCpu));
2453	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2454
2455	if (TRPMHasTrap(pVCpu))
2456	{
2457	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2458	uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
2459	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2460	{
2461	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2462	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2463	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2464	}
2465	}
2466	rc = VINF_EM_RESCHEDULE_REM;
2467	break;
2468
2469	/*
2470	* Other ring switch types.
2471	*/
2472	case VINF_EM_RAW_RING_SWITCH:
2473	rc = emR3RawRingSwitch(pVM, pVCpu);
2474	break;
2475
2476	/*
2477	* REMGCNotifyInvalidatePage() failed because of overflow.
2478	*/
2479	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2480	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2481	emR3RemLock(pVM);
2482	REMR3ReplayInvalidatedPages(pVM, pVCpu);
2483	emR3RemUnlock(pVM);
2484	rc = VINF_SUCCESS;
2485	break;
2486
2487	/*
2488	* I/O Port access - emulate the instruction.
2489	*/
2490	case VINF_IOM_HC_IOPORT_READ:
2491	case VINF_IOM_HC_IOPORT_WRITE:
2492	rc = emR3RawExecuteIOInstruction(pVM, pVCpu);
2493	break;
2494
2495	/*
2496	* Memory mapped I/O access - emulate the instruction.
2497	*/
2498	case VINF_IOM_HC_MMIO_READ:
2499	case VINF_IOM_HC_MMIO_WRITE:
2500	case VINF_IOM_HC_MMIO_READ_WRITE:
2501	rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
2502	break;
2503
2504	/*
2505	* (MM)IO intensive code block detected; fall back to the recompiler for better performance
2506	*/
2507	case VINF_EM_RAW_EMULATE_IO_BLOCK:
2508	rc = HWACCMR3EmulateIoBlock(pVM, pCtx);
2509	break;
2510
2511	/*
2512	* Execute instruction.
2513	*/
2514	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2515	rc = emR3RawExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
2516	break;
2517	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2518	rc = emR3RawExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
2519	break;
2520	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2521	rc = emR3RawExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
2522	break;
2523	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2524	rc = emR3RawExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
2525	break;
2526	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2527	rc = emR3RawExecuteInstruction(pVM, pVCpu, "PD FAULT: ");
2528	break;
2529
2530	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2531	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2532	rc = emR3RawPrivileged(pVM, pVCpu);
2533	break;
2534
2535	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2536	rc = emR3RawExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2537	break;
2538
2539	case VINF_EM_RAW_EMULATE_INSTR:
2540	case VINF_PATCH_EMULATE_INSTR:
2541	rc = emR3RawExecuteInstruction(pVM, pVCpu, "EMUL: ");
2542	break;
2543
2544	/*
2545	* Stale selector and iret traps => REM.
2546	*/
2547	case VINF_EM_RAW_STALE_SELECTOR:
2548	case VINF_EM_RAW_IRET_TRAP:
2549	/* We will not go to the recompiler if EIP points to patch code. */
2550	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2551	{
2552	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2553	}
2554	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
2555	rc = VINF_EM_RESCHEDULE_REM;
2556	break;
2557
2558	/*
2559	* Up a level.
2560	*/
2561	case VINF_EM_TERMINATE:
2562	case VINF_EM_OFF:
2563	case VINF_EM_RESET:
2564	case VINF_EM_SUSPEND:
2565	case VINF_EM_HALT:
2566	case VINF_EM_RESUME:
2567	case VINF_EM_NO_MEMORY:
2568	case VINF_EM_RESCHEDULE:
2569	case VINF_EM_RESCHEDULE_REM:
2570	case VINF_EM_WAIT_SIPI:
2571	break;
2572
2573	/*
2574	* Up a level and invoke the debugger.
2575	*/
2576	case VINF_EM_DBG_STEPPED:
2577	case VINF_EM_DBG_BREAKPOINT:
2578	case VINF_EM_DBG_STEP:
2579	case VINF_EM_DBG_HYPER_BREAKPOINT:
2580	case VINF_EM_DBG_HYPER_STEPPED:
2581	case VINF_EM_DBG_HYPER_ASSERTION:
2582	case VINF_EM_DBG_STOP:
2583	break;
2584
2585	/*
2586	* Up a level, dump and debug.
2587	*/
2588	case VERR_TRPM_DONT_PANIC:
2589	case VERR_TRPM_PANIC:
2590	case VERR_VMM_RING0_ASSERTION:
2591	break;
2592
2593	/*
2594	* Up a level, after HwAccM have done some release logging.
2595	*/
2596	case VERR_VMX_INVALID_VMCS_FIELD:
2597	case VERR_VMX_INVALID_VMCS_PTR:
2598	case VERR_VMX_INVALID_VMXON_PTR:
2599	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2600	case VERR_VMX_UNEXPECTED_EXCEPTION:
2601	case VERR_VMX_UNEXPECTED_EXIT_CODE:
2602	case VERR_VMX_INVALID_GUEST_STATE:
2603	case VERR_VMX_UNABLE_TO_START_VM:
2604	case VERR_VMX_UNABLE_TO_RESUME_VM:
2605	HWACCMR3CheckError(pVM, rc);
2606	break;
2607	/*
2608	* Anything which is not known to us means an internal error
2609	* and the termination of the VM!
2610	*/
2611	default:
2612	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
2613	break;
2614	}
2615	return rc;
2616	}
2617
2618
2619	/**
2620	* Check for pending raw actions
2621	*
2622	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
2623	* EM statuses.
2624	* @param pVM The VM to operate on.
2625	* @param pVCpu The VMCPU handle.
2626	*/
2627	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
2628	{
2629	return emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
2630	}
2631
2632
2633	/**
2634	* Process raw-mode specific forced actions.
2635	*
2636	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2637	*
2638	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
2639	* EM statuses.
2640	* @param pVM The VM handle.
2641	* @param pVCpu The VMCPU handle.
2642	* @param pCtx The guest CPUM register context.
2643	*/
2644	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2645	{
2646	/*
2647	* Note that the order is vitally important!
2648	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2649	*/
2650
2651
2652	/*
2653	* Sync selector tables.
2654	*/
2655	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
2656	{
2657	int rc = SELMR3UpdateFromCPUM(pVM, pVCpu);
2658	if (RT_FAILURE(rc))
2659	return rc;
2660	}
2661
2662	/*
2663	* Sync IDT.
2664	*
2665	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
2666	* and PGMShwModifyPage, so we're in for trouble if for instance a
2667	* PGMSyncCR3+pgmPoolClearAll is pending.
2668	*/
2669	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
2670	{
2671	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
2672	&& EMIsRawRing0Enabled(pVM)
2673	&& CSAMIsEnabled(pVM))
2674	{
2675	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2676	if (RT_FAILURE(rc))
2677	return rc;
2678	}
2679
2680	int rc = TRPMR3SyncIDT(pVM, pVCpu);
2681	if (RT_FAILURE(rc))
2682	return rc;
2683	}
2684
2685	/*
2686	* Sync TSS.
2687	*/
2688	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
2689	{
2690	int rc = SELMR3SyncTSS(pVM, pVCpu);
2691	if (RT_FAILURE(rc))
2692	return rc;
2693	}
2694
2695	/*
2696	* Sync page directory.
2697	*/
2698	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2699	{
2700	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2701	if (RT_FAILURE(rc))
2702	return rc;
2703
2704	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
2705
2706	/* Prefetch pages for EIP and ESP. */
2707	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2708	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2709	if (rc == VINF_SUCCESS)
2710	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2711	if (rc != VINF_SUCCESS)
2712	{
2713	if (rc != VINF_PGM_SYNC_CR3)
2714	{
2715	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
2716	return rc;
2717	}
2718	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2719	if (RT_FAILURE(rc))
2720	return rc;
2721	}
2722	/** @todo maybe prefetch the supervisor stack page as well */
2723	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
2724	}
2725
2726	/*
2727	* Allocate handy pages (just in case the above actions have consumed some pages).
2728	*/
2729	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
2730	{
2731	int rc = PGMR3PhysAllocateHandyPages(pVM);
2732	if (RT_FAILURE(rc))
2733	return rc;
2734	}
2735
2736	/*
2737	* Check whether we're out of memory now.
2738	*
2739	* This may stem from some of the above actions or operations that has been executed
2740	* since we ran FFs. The allocate handy pages must for instance always be followed by
2741	* this check.
2742	*/
2743	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2744	return VINF_EM_NO_MEMORY;
2745
2746	return VINF_SUCCESS;
2747	}
2748
2749
2750	/**
2751	* Executes raw code.
2752	*
2753	* This function contains the raw-mode version of the inner
2754	* execution loop (the outer loop being in EMR3ExecuteVM()).
2755	*
2756	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2757	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2758	*
2759	* @param pVM VM handle.
2760	* @param pVCpu VMCPU handle.
2761	* @param pfFFDone Where to store an indicator telling whether or not
2762	* FFs were done before returning.
2763	*/
2764	static int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
2765	{
2766	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
2767
2768	int rc = VERR_INTERNAL_ERROR;
2769	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
2770	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2771	pVCpu->em.s.fForceRAW = false;
2772	*pfFFDone = false;
2773
2774
2775	/*
2776	*
2777	* Spin till we get a forced action or raw mode status code resulting in
2778	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2779	*
2780	*/
2781	for (;;)
2782	{
2783	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
2784
2785	/*
2786	* Check various preconditions.
2787	*/
2788	#ifdef VBOX_STRICT
2789	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
2790	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2791	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2792	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2793	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2794	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
2795	&& PGMMapHasConflicts(pVM))
2796	{
2797	PGMMapCheck(pVM);
2798	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2799	return VERR_INTERNAL_ERROR;
2800	}
2801	#endif /* VBOX_STRICT */
2802
2803	/*
2804	* Process high priority pre-execution raw-mode FFs.
2805	*/
2806	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
2807	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2808	{
2809	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
2810	if (rc != VINF_SUCCESS)
2811	break;
2812	}
2813
2814	/*
2815	* If we're going to execute ring-0 code, the guest state needs to
2816	* be modified a bit and some of the state components (IF, SS/CS RPL,
2817	* and perhaps EIP) needs to be stored with PATM.
2818	*/
2819	rc = CPUMRawEnter(pVCpu, NULL);
2820	if (rc != VINF_SUCCESS)
2821	{
2822	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
2823	break;
2824	}
2825
2826	/*
2827	* Scan code before executing it. Don't bother with user mode or V86 code
2828	*/
2829	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2830	&& !pCtx->eflags.Bits.u1VM
2831	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2832	{
2833	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
2834	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2835	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
2836	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
2837	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2838	{
2839	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
2840	if (rc != VINF_SUCCESS)
2841	{
2842	rc = CPUMRawLeave(pVCpu, NULL, rc);
2843	break;
2844	}
2845	}
2846	}
2847
2848	#ifdef LOG_ENABLED
2849	/*
2850	* Log important stuff before entering GC.
2851	*/
2852	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2853	if (pCtx->eflags.Bits.u1VM)
2854	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2855	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2856	{
2857	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2858	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2859	}
2860	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2861	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2862	#endif /* LOG_ENABLED */
2863
2864
2865
2866	/*
2867	* Execute the code.
2868	*/
2869	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
2870	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
2871	rc = VMMR3RawRunGC(pVM, pVCpu);
2872	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
2873	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
2874
2875	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2876	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
2877
2878
2879
2880	/*
2881	* Restore the real CPU state and deal with high priority post
2882	* execution FFs before doing anything else.
2883	*/
2884	rc = CPUMRawLeave(pVCpu, NULL, rc);
2885	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
2886	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
2887	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
2888	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
2889
2890	#ifdef VBOX_STRICT
2891	/*
2892	* Assert TSS consistency & rc vs patch code.
2893	*/
2894	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2895	&& EMIsRawRing0Enabled(pVM))
2896	SELMR3CheckTSS(pVM);
2897	switch (rc)
2898	{
2899	case VINF_SUCCESS:
2900	case VINF_EM_RAW_INTERRUPT:
2901	case VINF_PATM_PATCH_TRAP_PF:
2902	case VINF_PATM_PATCH_TRAP_GP:
2903	case VINF_PATM_PATCH_INT3:
2904	case VINF_PATM_CHECK_PATCH_PAGE:
2905	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2906	case VINF_EM_RAW_GUEST_TRAP:
2907	case VINF_EM_RESCHEDULE_RAW:
2908	break;
2909
2910	default:
2911	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2912	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
2913	break;
2914	}
2915	/*
2916	* Let's go paranoid!
2917	*/
2918	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
2919	&& PGMMapHasConflicts(pVM))
2920	{
2921	PGMMapCheck(pVM);
2922	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
2923	return VERR_INTERNAL_ERROR;
2924	}
2925	#endif /* VBOX_STRICT */
2926
2927	/*
2928	* Process the returned status code.
2929	*/
2930	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2931	{
2932	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
2933	break;
2934	}
2935	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
2936	if (rc != VINF_SUCCESS)
2937	{
2938	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
2939	if (rc != VINF_SUCCESS)
2940	{
2941	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
2942	break;
2943	}
2944	}
2945
2946	/*
2947	* Check and execute forced actions.
2948	*/
2949	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2950	TMTimerPoll(pVM, pVCpu);
2951	#endif
2952	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
2953	if ( VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
2954	\|\| VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2955	{
2956	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2957
2958	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
2959	rc = emR3ForcedActions(pVM, pVCpu, rc);
2960	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
2961	if ( rc != VINF_SUCCESS
2962	&& rc != VINF_EM_RESCHEDULE_RAW)
2963	{
2964	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
2965	if (rc != VINF_SUCCESS)
2966	{
2967	*pfFFDone = true;
2968	break;
2969	}
2970	}
2971	}
2972	}
2973
2974	/*
2975	* Return to outer loop.
2976	*/
2977	#if defined(LOG_ENABLED) && defined(DEBUG)
2978	RTLogFlush(NULL);
2979	#endif
2980	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
2981	return rc;
2982	}
2983
2984
2985	/**
2986	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2987	*
2988	* This function contains the raw-mode version of the inner
2989	* execution loop (the outer loop being in EMR3ExecuteVM()).
2990	*
2991	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2992	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2993	*
2994	* @param pVM VM handle.
2995	* @param pVCpu VMCPU handle.
2996	* @param pfFFDone Where to store an indicator telling whether or not
2997	* FFs were done before returning.
2998	*/
2999	static int emR3HwAccExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
3000	{
3001	int rc = VERR_INTERNAL_ERROR;
3002	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
3003
3004	LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
3005	*pfFFDone = false;
3006
3007	STAM_COUNTER_INC(&pVCpu->em.s.StatHwAccExecuteEntry);
3008
3009	#ifdef EM_NOTIFY_HWACCM
3010	HWACCMR3NotifyScheduled(pVCpu);
3011	#endif
3012
3013	/*
3014	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
3015	*/
3016	for (;;)
3017	{
3018	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHwAccEntry, a);
3019
3020	/*
3021	* Process high priority pre-execution raw-mode FFs.
3022	*/
3023	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
3024	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
3025	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
3026	{
3027	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
3028	if (rc != VINF_SUCCESS)
3029	break;
3030	}
3031
3032	#ifdef LOG_ENABLED
3033	/*
3034	* Log important stuff before entering GC.
3035	*/
3036	if (TRPMHasTrap(pVCpu))
3037	Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
3038
3039	uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
3040
3041	if (pVM->cCPUs == 1)
3042	{
3043	if (pCtx->eflags.Bits.u1VM)
3044	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
3045	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
3046	Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
3047	else
3048	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
3049	}
3050	else
3051	{
3052	if (pCtx->eflags.Bits.u1VM)
3053	Log(("HWV86-CPU%d: %08X IF=%d\n", pVCpu->idCpu, pCtx->eip, pCtx->eflags.Bits.u1IF));
3054	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
3055	Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
3056	else
3057	Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
3058	}
3059	#endif /* LOG_ENABLED */
3060
3061	/*
3062	* Execute the code.
3063	*/
3064	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHwAccEntry, a);
3065	STAM_PROFILE_START(&pVCpu->em.s.StatHwAccExec, x);
3066	rc = VMMR3HwAccRunGC(pVM, pVCpu);
3067	STAM_PROFILE_STOP(&pVCpu->em.s.StatHwAccExec, x);
3068
3069	/*
3070	* Deal with high priority post execution FFs before doing anything else.
3071	*/
3072	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
3073	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
3074	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
3075	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
3076
3077	/*
3078	* Process the returned status code.
3079	*/
3080	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
3081	break;
3082
3083	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
3084	if (rc != VINF_SUCCESS)
3085	break;
3086
3087	/*
3088	* Check and execute forced actions.
3089	*/
3090	#ifdef VBOX_HIGH_RES_TIMERS_HACK
3091	TMTimerPoll(pVM, pVCpu);
3092	#endif
3093	if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK)
3094	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_MASK))
3095	{
3096	rc = emR3ForcedActions(pVM, pVCpu, rc);
3097	if ( rc != VINF_SUCCESS
3098	&& rc != VINF_EM_RESCHEDULE_HWACC)
3099	{
3100	*pfFFDone = true;
3101	break;
3102	}
3103	}
3104	}
3105
3106	/*
3107	* Return to outer loop.
3108	*/
3109	#if defined(LOG_ENABLED) && defined(DEBUG)
3110	RTLogFlush(NULL);
3111	#endif
3112	return rc;
3113	}
3114
3115
3116	/**
3117	* Decides whether to execute RAW, HWACC or REM.
3118	*
3119	* @returns new EM state
3120	* @param pVM The VM.
3121	* @param pVCpu The VMCPU handle.
3122	* @param pCtx The CPU context.
3123	*/
3124	static EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3125	{
3126	/*
3127	* When forcing raw-mode execution, things are simple.
3128	*/
3129	if (pVCpu->em.s.fForceRAW)
3130	return EMSTATE_RAW;
3131
3132	/*
3133	* We stay in the wait for SIPI state unless explicitly told otherwise.
3134	*/
3135	if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
3136	return EMSTATE_WAIT_SIPI;
3137
3138	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
3139	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
3140	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
3141
3142	X86EFLAGS EFlags = pCtx->eflags;
3143	if (HWACCMIsEnabled(pVM))
3144	{
3145	/* Hardware accelerated raw-mode:
3146	*
3147	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
3148	*/
3149	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
3150	return EMSTATE_HWACC;
3151
3152	/* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
3153	* off monitoring features essential for raw mode! */
3154	return EMSTATE_REM;
3155	}
3156
3157	/*
3158	* Standard raw-mode:
3159	*
3160	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
3161	* or 32 bits protected mode ring 0 code
3162	*
3163	* The tests are ordered by the likelyhood of being true during normal execution.
3164	*/
3165	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
3166	{
3167	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
3168	return EMSTATE_REM;
3169	}
3170
3171	#ifndef VBOX_RAW_V86
3172	if (EFlags.u32 & X86_EFL_VM) {
3173	Log2(("raw mode refused: VM_MASK\n"));
3174	return EMSTATE_REM;
3175	}
3176	#endif
3177
3178	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
3179	uint32_t u32CR0 = pCtx->cr0;
3180	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
3181	{
3182	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
3183	return EMSTATE_REM;
3184	}
3185
3186	if (pCtx->cr4 & X86_CR4_PAE)
3187	{
3188	uint32_t u32Dummy, u32Features;
3189
3190	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3191	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3192	return EMSTATE_REM;
3193	}
3194
3195	unsigned uSS = pCtx->ss;
3196	if ( pCtx->eflags.Bits.u1VM
3197	\|\| (uSS & X86_SEL_RPL) == 3)
3198	{
3199	if (!EMIsRawRing3Enabled(pVM))
3200	return EMSTATE_REM;
3201
3202	if (!(EFlags.u32 & X86_EFL_IF))
3203	{
3204	Log2(("raw mode refused: IF (RawR3)\n"));
3205	return EMSTATE_REM;
3206	}
3207
3208	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
3209	{
3210	Log2(("raw mode refused: CR0.WP + RawR0\n"));
3211	return EMSTATE_REM;
3212	}
3213	}
3214	else
3215	{
3216	if (!EMIsRawRing0Enabled(pVM))
3217	return EMSTATE_REM;
3218
3219	/* Only ring 0 supervisor code. */
3220	if ((uSS & X86_SEL_RPL) != 0)
3221	{
3222	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
3223	return EMSTATE_REM;
3224	}
3225
3226	// Let's start with pure 32 bits ring 0 code first
3227	/** @todo What's pure 32-bit mode? flat? */
3228	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
3229	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
3230	{
3231	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
3232	return EMSTATE_REM;
3233	}
3234
3235	/* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
3236	if (!(u32CR0 & X86_CR0_WP))
3237	{
3238	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
3239	return EMSTATE_REM;
3240	}
3241
3242	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
3243	{
3244	Log2(("raw r0 mode forced: patch code\n"));
3245	return EMSTATE_RAW;
3246	}
3247
3248	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
3249	if (!(EFlags.u32 & X86_EFL_IF))
3250	{
3251	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
3252	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
3253	return EMSTATE_REM;
3254	}
3255	#endif
3256
3257	/** @todo still necessary??? */
3258	if (EFlags.Bits.u2IOPL != 0)
3259	{
3260	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
3261	return EMSTATE_REM;
3262	}
3263	}
3264
3265	Assert(PGMPhysIsA20Enabled(pVCpu));
3266	return EMSTATE_RAW;
3267	}
3268
3269
3270	/**
3271	* Executes all high priority post execution force actions.
3272	*
3273	* @returns rc or a fatal status code.
3274	*
3275	* @param pVM VM handle.
3276	* @param pVCpu VMCPU handle.
3277	* @param rc The current rc.
3278	*/
3279	static int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
3280	{
3281	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
3282	PDMR3CritSectFF(pVCpu);
3283
3284	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
3285	CSAMR3DoPendingAction(pVM, pVCpu);
3286
3287	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3288	{
3289	if ( rc > VINF_EM_NO_MEMORY
3290	&& rc <= VINF_EM_LAST)
3291	rc = VINF_EM_NO_MEMORY;
3292	}
3293
3294	return rc;
3295	}
3296
3297
3298	/**
3299	* Executes all pending forced actions.
3300	*
3301	* Forced actions can cause execution delays and execution
3302	* rescheduling. The first we deal with using action priority, so
3303	* that for instance pending timers aren't scheduled and ran until
3304	* right before execution. The rescheduling we deal with using
3305	* return codes. The same goes for VM termination, only in that case
3306	* we exit everything.
3307	*
3308	* @returns VBox status code of equal or greater importance/severity than rc.
3309	* The most important ones are: VINF_EM_RESCHEDULE,
3310	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3311	*
3312	* @param pVM VM handle.
3313	* @param pVCpu VMCPU handle.
3314	* @param rc The current rc.
3315	*
3316	*/
3317	static int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
3318	{
3319	STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
3320	#ifdef VBOX_STRICT
3321	int rcIrq = VINF_SUCCESS;
3322	#endif
3323	int rc2;
3324	#define UPDATE_RC() \
3325	do { \
3326	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
3327	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
3328	break; \
3329	if (!rc \|\| rc2 < rc) \
3330	rc = rc2; \
3331	} while (0)
3332
3333	/*
3334	* Post execution chunk first.
3335	*/
3336	if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
3337	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
3338	{
3339	/*
3340	* Termination request.
3341	*/
3342	if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
3343	{
3344	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3345	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3346	return VINF_EM_TERMINATE;
3347	}
3348
3349	/*
3350	* Debugger Facility polling.
3351	*/
3352	if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
3353	{
3354	rc2 = DBGFR3VMMForcedAction(pVM);
3355	UPDATE_RC();
3356	}
3357
3358	/*
3359	* Postponed reset request.
3360	*/
3361	if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET_BIT))
3362	{
3363	rc2 = VMR3Reset(pVM);
3364	UPDATE_RC();
3365	}
3366
3367	/*
3368	* CSAM page scanning.
3369	*/
3370	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3371	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
3372	{
3373	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
3374
3375	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3376	Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
3377
3378	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3379	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
3380	}
3381
3382	/*
3383	* Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
3384	*/
3385	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3386	{
3387	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3388	UPDATE_RC();
3389	if (rc == VINF_EM_NO_MEMORY)
3390	return rc;
3391	}
3392
3393	/* check that we got them all */
3394	AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_PGM_NO_MEMORY));
3395	AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_CSAM_SCAN_PAGE);
3396	}
3397
3398	/*
3399	* Normal priority then.
3400	* (Executed in no particular order.)
3401	*/
3402	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
3403	{
3404	/*
3405	* PDM Queues are pending.
3406	*/
3407	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
3408	PDMR3QueueFlushAll(pVM);
3409
3410	/*
3411	* PDM DMA transfers are pending.
3412	*/
3413	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
3414	PDMR3DmaRun(pVM);
3415
3416	/*
3417	* Requests from other threads.
3418	*/
3419	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
3420	{
3421	rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY);
3422	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3423	{
3424	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
3425	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3426	return rc2;
3427	}
3428	UPDATE_RC();
3429	}
3430
3431	/* Replay the handler notification changes. */
3432	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
3433	{
3434	emR3RemLock(pVM);
3435	REMR3ReplayHandlerNotifications(pVM);
3436	emR3RemUnlock(pVM);
3437	}
3438
3439	/* check that we got them all */
3440	AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY));
3441	}
3442
3443	/*
3444	* Normal priority then. (per-VCPU)
3445	* (Executed in no particular order.)
3446	*/
3447	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3448	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
3449	{
3450	/*
3451	* Requests from other threads.
3452	*/
3453	if (VMCPU_FF_IS_PENDING_EXCEPT(pVCpu, VMCPU_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
3454	{
3455	rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu);
3456	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3457	{
3458	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
3459	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3460	return rc2;
3461	}
3462	UPDATE_RC();
3463	}
3464
3465	/* check that we got them all */
3466	Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
3467	}
3468
3469	/*
3470	* High priority pre execution chunk last.
3471	* (Executed in ascending priority order.)
3472	*/
3473	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
3474	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
3475	{
3476	/*
3477	* Timers before interrupts.
3478	*/
3479	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
3480	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3481	TMR3TimerQueuesDo(pVM);
3482
3483	/*
3484	* The instruction following an emulated STI should always be executed!
3485	*/
3486	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
3487	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3488	{
3489	Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
3490	if (CPUMGetGuestEIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
3491	{
3492	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3493	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3494	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3495	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3496	*/
3497	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3498	}
3499	if (HWACCMR3IsActive(pVCpu))
3500	rc2 = VINF_EM_RESCHEDULE_HWACC;
3501	else
3502	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3503
3504	UPDATE_RC();
3505	}
3506
3507	/*
3508	* Interrupts.
3509	*/
3510	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3511	&& !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
3512	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_HWACC)
3513	&& !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3514	&& PATMAreInterruptsEnabled(pVM)
3515	&& !HWACCMR3IsEventPending(pVM))
3516	{
3517	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC))
3518	{
3519	/* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3520	/** @todo this really isn't nice, should properly handle this */
3521	rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
3522	#ifdef VBOX_STRICT
3523	rcIrq = rc2;
3524	#endif
3525	UPDATE_RC();
3526	}
3527	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3528	else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
3529	{
3530	rc2 = VINF_EM_RESCHEDULE_REM;
3531	UPDATE_RC();
3532	}
3533	}
3534
3535	/*
3536	* Allocate handy pages.
3537	*/
3538	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
3539	{
3540	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3541	UPDATE_RC();
3542	}
3543
3544	/*
3545	* Debugger Facility request.
3546	*/
3547	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
3548	{
3549	rc2 = DBGFR3VMMForcedAction(pVM);
3550	UPDATE_RC();
3551	}
3552
3553	/*
3554	* Termination request.
3555	*/
3556	if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
3557	{
3558	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3559	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3560	return VINF_EM_TERMINATE;
3561	}
3562
3563	/*
3564	* Out of memory? Since most of our fellow high priority actions may cause us
3565	* to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
3566	* at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
3567	* than us since we can terminate without allocating more memory.
3568	*/
3569	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3570	{
3571	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3572	UPDATE_RC();
3573	if (rc == VINF_EM_NO_MEMORY)
3574	return rc;
3575	}
3576
3577	/*
3578	* If the virtual sync clock is still stopped, make TM restart it.
3579	*/
3580	if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
3581	TMR3VirtualSyncFF(pVM, pVCpu);
3582
3583	#ifdef DEBUG
3584	/*
3585	* Debug, pause the VM.
3586	*/
3587	if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
3588	{
3589	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3590	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3591	return VINF_EM_SUSPEND;
3592	}
3593	#endif
3594
3595	/* check that we got them all */
3596	AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY));
3597	AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_INHIBIT_INTERRUPTS));
3598	}
3599
3600	#undef UPDATE_RC
3601	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
3602	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3603	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3604	return rc;
3605	}
3606
3607	/**
3608	* Release the IOM lock if owned by the current VCPU
3609	*
3610	* @param pVM The VM to operate on.
3611	*/
3612	VMMR3DECL(void) EMR3ReleaseOwnedLocks(PVM pVM)
3613	{
3614	while (PDMCritSectIsOwner(&pVM->em.s.CritSectREM))
3615	PDMCritSectLeave(&pVM->em.s.CritSectREM);
3616	}
3617
3618
3619	/**
3620	* Execute VM.
3621	*
3622	* This function is the main loop of the VM. The emulation thread
3623	* calls this function when the VM has been successfully constructed
3624	* and we're ready for executing the VM.
3625	*
3626	* Returning from this function means that the VM is turned off or
3627	* suspended (state already saved) and deconstruction in next in line.
3628	*
3629	* All interaction from other thread are done using forced actions
3630	* and signaling of the wait object.
3631	*
3632	* @returns VBox status code, informational status codes may indicate failure.
3633	* @param pVM The VM to operate on.
3634	* @param pVCpu The VMCPU to operate on.
3635	*/
3636	VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
3637	{
3638	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3639	pVCpu->em.s.enmState, EMR3GetStateName(pVCpu->em.s.enmState), pVCpu->em.s.fForceRAW));
3640	VM_ASSERT_EMT(pVM);
3641	Assert(pVCpu->em.s.enmState == EMSTATE_NONE \|\| pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI \|\| pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
3642
3643	int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
3644	if (rc == 0)
3645	{
3646	/*
3647	* Start the virtual time.
3648	*/
3649	TMR3NotifyResume(pVM, pVCpu);
3650
3651	/*
3652	* The Outer Main Loop.
3653	*/
3654	bool fFFDone = false;
3655
3656	/* Reschedule right away to start in the right state. */
3657	rc = VINF_SUCCESS;
3658
3659	/** @todo doesn't work for the save/restore case */
3660	if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
3661	&& ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
3662	\|\| pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
3663	{
3664	/* Pause->Resume: Restore the old wait state or else we'll start executing code. */
3665	pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
3666	}
3667	else
3668	pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
3669
3670	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
3671	for (;;)
3672	{
3673	/*
3674	* Before we can schedule anything (we're here because
3675	* scheduling is required) we must service any pending
3676	* forced actions to avoid any pending action causing
3677	* immediate rescheduling upon entering an inner loop
3678	*
3679	* Do forced actions.
3680	*/
3681	if ( !fFFDone
3682	&& rc != VINF_EM_TERMINATE
3683	&& rc != VINF_EM_OFF
3684	&& ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
3685	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK)))
3686	{
3687	rc = emR3ForcedActions(pVM, pVCpu, rc);
3688	if ( ( rc == VINF_EM_RESCHEDULE_REM
3689	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3690	&& pVCpu->em.s.fForceRAW)
3691	rc = VINF_EM_RESCHEDULE_RAW;
3692	}
3693	else if (fFFDone)
3694	fFFDone = false;
3695
3696	/*
3697	* Now what to do?
3698	*/
3699	Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
3700	switch (rc)
3701	{
3702	/*
3703	* Keep doing what we're currently doing.
3704	*/
3705	case VINF_SUCCESS:
3706	break;
3707
3708	/*
3709	* Reschedule - to raw-mode execution.
3710	*/
3711	case VINF_EM_RESCHEDULE_RAW:
3712	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVCpu->em.s.enmState, EMSTATE_RAW));
3713	pVCpu->em.s.enmState = EMSTATE_RAW;
3714	break;
3715
3716	/*
3717	* Reschedule - to hardware accelerated raw-mode execution.
3718	*/
3719	case VINF_EM_RESCHEDULE_HWACC:
3720	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVCpu->em.s.enmState, EMSTATE_HWACC));
3721	Assert(!pVCpu->em.s.fForceRAW);
3722	pVCpu->em.s.enmState = EMSTATE_HWACC;
3723	break;
3724
3725	/*
3726	* Reschedule - to recompiled execution.
3727	*/
3728	case VINF_EM_RESCHEDULE_REM:
3729	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVCpu->em.s.enmState, EMSTATE_REM));
3730	pVCpu->em.s.enmState = EMSTATE_REM;
3731	break;
3732
3733	#ifdef VBOX_WITH_VMI
3734	/*
3735	* Reschedule - parav call.
3736	*/
3737	case VINF_EM_RESCHEDULE_PARAV:
3738	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVCpu->em.s.enmState, EMSTATE_PARAV));
3739	pVCpu->em.s.enmState = EMSTATE_PARAV;
3740	break;
3741	#endif
3742
3743	/*
3744	* Resume.
3745	*/
3746	case VINF_EM_RESUME:
3747	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVCpu->em.s.enmState));
3748	/* Don't reschedule in the halted or wait for SIPI case. */
3749	if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
3750	\|\| pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
3751	break;
3752	/* fall through and get scheduled. */
3753
3754	/*
3755	* Reschedule.
3756	*/
3757	case VINF_EM_RESCHEDULE:
3758	{
3759	EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
3760	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3761	pVCpu->em.s.enmState = enmState;
3762	break;
3763	}
3764
3765	/*
3766	* Halted.
3767	*/
3768	case VINF_EM_HALT:
3769	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_HALTED));
3770	pVCpu->em.s.enmState = EMSTATE_HALTED;
3771	break;
3772
3773	/*
3774	* Switch to the wait for SIPI state (application processor only)
3775	*/
3776	case VINF_EM_WAIT_SIPI:
3777	Assert(pVCpu->idCpu != 0);
3778	Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_WAIT_SIPI));
3779	pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
3780	break;
3781
3782
3783	/*
3784	* Suspend.
3785	*/
3786	case VINF_EM_SUSPEND:
3787	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
3788	pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
3789	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
3790	break;
3791
3792	/*
3793	* Reset.
3794	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3795	*/
3796	case VINF_EM_RESET:
3797	{
3798	if (pVCpu->idCpu == 0)
3799	{
3800	EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
3801	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3802	pVCpu->em.s.enmState = enmState;
3803	}
3804	else
3805	{
3806	/* All other VCPUs go into the wait for SIPI state. */
3807	pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
3808	}
3809	break;
3810	}
3811
3812	/*
3813	* Power Off.
3814	*/
3815	case VINF_EM_OFF:
3816	pVCpu->em.s.enmState = EMSTATE_TERMINATING;
3817	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
3818	TMR3NotifySuspend(pVM, pVCpu);
3819	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3820	return rc;
3821
3822	/*
3823	* Terminate the VM.
3824	*/
3825	case VINF_EM_TERMINATE:
3826	pVCpu->em.s.enmState = EMSTATE_TERMINATING;
3827	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
3828	TMR3NotifySuspend(pVM, pVCpu);
3829	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3830	return rc;
3831
3832
3833	/*
3834	* Out of memory, suspend the VM and stuff.
3835	*/
3836	case VINF_EM_NO_MEMORY:
3837	Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
3838	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
3839	TMR3NotifySuspend(pVM, pVCpu);
3840	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3841
3842	rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
3843	N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
3844	if (rc != VINF_EM_SUSPEND)
3845	{
3846	if (RT_SUCCESS_NP(rc))
3847	{
3848	AssertLogRelMsgFailed(("%Rrc\n", rc));
3849	rc = VERR_EM_INTERNAL_ERROR;
3850	}
3851	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3852	}
3853	return rc;
3854
3855	/*
3856	* Guest debug events.
3857	*/
3858	case VINF_EM_DBG_STEPPED:
3859	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3860	case VINF_EM_DBG_STOP:
3861	case VINF_EM_DBG_BREAKPOINT:
3862	case VINF_EM_DBG_STEP:
3863	if (pVCpu->em.s.enmState == EMSTATE_RAW)
3864	{
3865	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3866	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3867	}
3868	else
3869	{
3870	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3871	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3872	}
3873	break;
3874
3875	/*
3876	* Hypervisor debug events.
3877	*/
3878	case VINF_EM_DBG_HYPER_STEPPED:
3879	case VINF_EM_DBG_HYPER_BREAKPOINT:
3880	case VINF_EM_DBG_HYPER_ASSERTION:
3881	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_HYPER));
3882	pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
3883	break;
3884
3885	/*
3886	* Guru mediations.
3887	*/
3888	case VERR_VMM_RING0_ASSERTION:
3889	Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
3890	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3891	break;
3892
3893	/*
3894	* Any error code showing up here other than the ones we
3895	* know and process above are considered to be FATAL.
3896	*
3897	* Unknown warnings and informational status codes are also
3898	* included in this.
3899	*/
3900	default:
3901	if (RT_SUCCESS_NP(rc))
3902	{
3903	AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
3904	rc = VERR_EM_INTERNAL_ERROR;
3905	}
3906	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3907	Log(("EMR3ExecuteVM returns %d\n", rc));
3908	break;
3909	}
3910
3911	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
3912	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
3913
3914	/*
3915	* Act on the state.
3916	*/
3917	switch (pVCpu->em.s.enmState)
3918	{
3919	/*
3920	* Execute raw.
3921	*/
3922	case EMSTATE_RAW:
3923	rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
3924	break;
3925
3926	/*
3927	* Execute hardware accelerated raw.
3928	*/
3929	case EMSTATE_HWACC:
3930	rc = emR3HwAccExecute(pVM, pVCpu, &fFFDone);
3931	break;
3932
3933	/*
3934	* Execute recompiled.
3935	*/
3936	case EMSTATE_REM:
3937	rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
3938	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
3939	break;
3940
3941	#ifdef VBOX_WITH_VMI
3942	/*
3943	* Execute PARAV function.
3944	*/
3945	case EMSTATE_PARAV:
3946	rc = PARAVCallFunction(pVM);
3947	pVCpu->em.s.enmState = EMSTATE_REM;
3948	break;
3949	#endif
3950
3951	/*
3952	* Application processor execution halted until SIPI.
3953	*/
3954	case EMSTATE_WAIT_SIPI:
3955	Assert(!(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
3956	/* no break */
3957	/*
3958	* hlt - execution halted until interrupt.
3959	*/
3960	case EMSTATE_HALTED:
3961	{
3962	STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
3963	rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
3964	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
3965	break;
3966	}
3967
3968	/*
3969	* Suspended - return to VM.cpp.
3970	*/
3971	case EMSTATE_SUSPENDED:
3972	TMR3NotifySuspend(pVM, pVCpu);
3973	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3974	return VINF_EM_SUSPEND;
3975
3976	/*
3977	* Debugging in the guest.
3978	*/
3979	case EMSTATE_DEBUG_GUEST_REM:
3980	case EMSTATE_DEBUG_GUEST_RAW:
3981	TMR3NotifySuspend(pVM, pVCpu);
3982	rc = emR3Debug(pVM, pVCpu, rc);
3983	TMR3NotifyResume(pVM, pVCpu);
3984	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
3985	break;
3986
3987	/*
3988	* Debugging in the hypervisor.
3989	*/
3990	case EMSTATE_DEBUG_HYPER:
3991	{
3992	TMR3NotifySuspend(pVM, pVCpu);
3993	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3994
3995	rc = emR3Debug(pVM, pVCpu, rc);
3996	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
3997	if (rc != VINF_SUCCESS)
3998	{
3999	/* switch to guru meditation mode */
4000	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
4001	VMMR3FatalDump(pVM, pVCpu, rc);
4002	return rc;
4003	}
4004
4005	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
4006	TMR3NotifyResume(pVM, pVCpu);
4007	break;
4008	}
4009
4010	/*
4011	* Guru meditation takes place in the debugger.
4012	*/
4013	case EMSTATE_GURU_MEDITATION:
4014	{
4015	TMR3NotifySuspend(pVM, pVCpu);
4016	VMMR3FatalDump(pVM, pVCpu, rc);
4017	emR3Debug(pVM, pVCpu, rc);
4018	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
4019	return rc;
4020	}
4021
4022	/*
4023	* The states we don't expect here.
4024	*/
4025	case EMSTATE_NONE:
4026	case EMSTATE_TERMINATING:
4027	default:
4028	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
4029	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
4030	TMR3NotifySuspend(pVM, pVCpu);
4031	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
4032	return VERR_EM_INTERNAL_ERROR;
4033	}
4034	} /* The Outer Main Loop */
4035	}
4036	else
4037	{
4038	/*
4039	* Fatal error.
4040	*/
4041	LogFlow(("EMR3ExecuteVM: returns %Rrc (longjmp / fatal error)\n", rc));
4042	TMR3NotifySuspend(pVM, pVCpu);
4043	VMMR3FatalDump(pVM, pVCpu, rc);
4044	emR3Debug(pVM, pVCpu, rc);
4045	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
4046	/** @todo change the VM state! */
4047	return rc;
4048	}
4049
4050	/* (won't ever get here). */
4051	AssertFailed();
4052	}
4053

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 19793

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