EM.cpp@ 20141

Last change on this file since 20141 was 20122, checked in by vboxsync, 16 years ago
EM.cpp: Fixed enmState assertion in EMR3ExecuteVM on restore. Restore can be handled the same way as resume after suspend.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 164.9 KB

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1	/* $Id: EM.cpp 20122 2009-05-28 14:13:40Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_em EM - The Execution Monitor / Manager
23	*
24	* The Execution Monitor/Manager is responsible for running the VM, scheduling
25	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26	* Interpreted), and keeping the CPU states in sync. The function
27	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29	* emR3RemExecute).
30	*
31	* The interpreted execution is only used to avoid switching between
32	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33	* The interpretation is thus implemented as part of EM.
34	*
35	* @see grp_em
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_EM
42	#include <VBox/em.h>
43	#include <VBox/vmm.h>
44	#ifdef VBOX_WITH_VMI
45	# include <VBox/parav.h>
46	#endif
47	#include <VBox/patm.h>
48	#include <VBox/csam.h>
49	#include <VBox/selm.h>
50	#include <VBox/trpm.h>
51	#include <VBox/iom.h>
52	#include <VBox/dbgf.h>
53	#include <VBox/pgm.h>
54	#include <VBox/rem.h>
55	#include <VBox/tm.h>
56	#include <VBox/mm.h>
57	#include <VBox/ssm.h>
58	#include <VBox/pdmapi.h>
59	#include <VBox/pdmcritsect.h>
60	#include <VBox/pdmqueue.h>
61	#include <VBox/hwaccm.h>
62	#include <VBox/patm.h>
63	#include "EMInternal.h"
64	#include <VBox/vm.h>
65	#include <VBox/cpumdis.h>
66	#include <VBox/dis.h>
67	#include <VBox/disopcode.h>
68	#include <VBox/dbgf.h>
69
70	#include <VBox/log.h>
71	#include <iprt/thread.h>
72	#include <iprt/assert.h>
73	#include <iprt/asm.h>
74	#include <iprt/semaphore.h>
75	#include <iprt/string.h>
76	#include <iprt/avl.h>
77	#include <iprt/stream.h>
78	#include <VBox/param.h>
79	#include <VBox/err.h>
80
81
82	/*******************************************************************************
83	* Defined Constants And Macros *
84	*******************************************************************************/
85	#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
86	#define EM_NOTIFY_HWACCM
87	#endif
88
89
90	/*******************************************************************************
91	* Internal Functions *
92	*******************************************************************************/
93	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
94	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
95	static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
96	static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
97	static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
98	static int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu);
99	static int emR3RawStep(PVM pVM, PVMCPU pVCpu);
100	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
101	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
102	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
103	static int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
104	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
105	static int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
106	static int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
107	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
108	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
109	static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations);
110	static EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
111
112	/**
113	* Initializes the EM.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	VMMR3DECL(int) EMR3Init(PVM pVM)
119	{
120	LogFlow(("EMR3Init\n"));
121	/*
122	* Assert alignment and sizes.
123	*/
124	AssertCompileMemberAlignment(VM, em.s, 32);
125	AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
126	AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
127	AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
128
129	/*
130	* Init the structure.
131	*/
132	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
133	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
134	if (RT_FAILURE(rc))
135	pVM->fRawR3Enabled = true;
136	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
137	if (RT_FAILURE(rc))
138	pVM->fRawR0Enabled = true;
139	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
140
141	/*
142	* Initialize the REM critical section.
143	*/
144	rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, "EM-REM");
145	AssertRCReturn(rc, rc);
146
147	/*
148	* Saved state.
149	*/
150	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
151	NULL, emR3Save, NULL,
152	NULL, emR3Load, NULL);
153	if (RT_FAILURE(rc))
154	return rc;
155
156	for (unsigned i=0;i<pVM->cCPUs;i++)
157	{
158	PVMCPU pVCpu = &pVM->aCpus[i];
159
160	pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
161
162	pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
163	pVCpu->em.s.enmPrevState = EMSTATE_NONE;
164	pVCpu->em.s.fForceRAW = false;
165
166	pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
167	pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
168	AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
169
170	# define EM_REG_COUNTER(a, b, c) \
171	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
172	AssertRC(rc);
173
174	# define EM_REG_COUNTER_USED(a, b, c) \
175	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
176	AssertRC(rc);
177
178	# define EM_REG_PROFILE(a, b, c) \
179	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
180	AssertRC(rc);
181
182	# define EM_REG_PROFILE_ADV(a, b, c) \
183	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
184	AssertRC(rc);
185
186	/*
187	* Statistics.
188	*/
189	#ifdef VBOX_WITH_STATISTICS
190	PEMSTATS pStats;
191	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
192	if (RT_FAILURE(rc))
193	return rc;
194
195	pVCpu->em.s.pStatsR3 = pStats;
196	pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
197	pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
198
199	EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
200	EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
201
202	EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
203	EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
204
205	EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
206	EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
207	EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
208	EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
209	EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
210	EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
211	EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
212	EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
213	EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
214	EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
215	EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
216	EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
217	EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
218	EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
219	EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
220	EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
221	EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
222	EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
223	EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
224	EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
225	EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
226	EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
227	EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
228	EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
229	EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
230	EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
231	EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
232	EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
233	EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
234	EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
235	EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
236	EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
237	EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
238	EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
239	EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
240	EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
241	EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
242	EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
243	EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
244	EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
245	EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
246	EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
247	EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
248	EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
249	EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
250	EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
251	EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
252	EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
253	EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
254	EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
255	EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
256	EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
257	EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
258	EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
259	EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
260	EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
261	EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
262	EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
263	EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
264	EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
265	EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
266	EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
267	EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
268	EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
269	EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
270	EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
271	EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
272	EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
273	EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
274	EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
275	EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
276	EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
277
278	EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
279	EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
280
281	EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
282	EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
283	EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
284	EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
285	EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
286	EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
287	EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
288	EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
289	EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
290	EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
291	EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
292	EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
293	EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
294	EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
295	EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
296	EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
297	EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
298	EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
299	EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
300	EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
301	EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
302	EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
303	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
304	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
305	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
306	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
307	EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
308	EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
309	EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
310	EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
311	EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
312	EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
313	EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
314	EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
315	EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
316	EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
317	EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
318	EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
319	EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
320	EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
321	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
322	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
323	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
324	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
325	EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
326	EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
327	EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
328	EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
329	EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
330	EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
331
332	EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
333	EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
334	EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
335	EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
336	EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
337	EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
338	EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
339	EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
340	EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
341	EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
342	EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
343	EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
344	EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
345	EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
346	EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
347	EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
348	EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
349	EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
350	EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
351	EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
352	EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
353	EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
354	EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
355	EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
356	EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
357	EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
358	EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
359	EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
360
361	EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
362	EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
363	EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
364	EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
365
366	EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
367	EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
368	EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
369	EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
370	EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
371	EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
372	EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
373	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 read instructions.");
374	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 read instructions.");
375	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 read instructions.");
376	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 read instructions.");
377	EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 read instructions.");
378	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 write instructions.");
379	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 write instructions.");
380	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 write instructions.");
381	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 write instructions.");
382	EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 write instructions.");
383	EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
384	EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
385	EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
386	EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
387	EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
388	EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
389	EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
390	EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
391	EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
392
393	EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
394	pVCpu->em.s.pCliStatTree = 0;
395
396	/* these should be considered for release statistics. */
397	EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
398	EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
399	EM_REG_COUNTER(&pVCpu->em.s.StatMiscEmu, "/PROF/CPU%d/EM/Emulation/Misc", "Profiling of emR3RawExecuteInstruction.");
400	EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
401	EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
402	EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
403	EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
404	EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
405	EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
406	EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
407	EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
408
409	#endif /* VBOX_WITH_STATISTICS */
410
411	EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
412	EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
413	EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
414	EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
415
416	EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
417	}
418
419	return VINF_SUCCESS;
420	}
421
422
423	/**
424	* Initializes the per-VCPU EM.
425	*
426	* @returns VBox status code.
427	* @param pVM The VM to operate on.
428	*/
429	VMMR3DECL(int) EMR3InitCPU(PVM pVM)
430	{
431	LogFlow(("EMR3InitCPU\n"));
432	return VINF_SUCCESS;
433	}
434
435
436	/**
437	* Applies relocations to data and code managed by this
438	* component. This function will be called at init and
439	* whenever the VMM need to relocate it self inside the GC.
440	*
441	* @param pVM The VM.
442	*/
443	VMMR3DECL(void) EMR3Relocate(PVM pVM)
444	{
445	LogFlow(("EMR3Relocate\n"));
446	for (unsigned i=0;i<pVM->cCPUs;i++)
447	{
448	PVMCPU pVCpu = &pVM->aCpus[i];
449
450	if (pVCpu->em.s.pStatsR3)
451	pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
452	}
453	}
454
455
456	/**
457	* Reset notification.
458	*
459	* @param pVM
460	*/
461	VMMR3DECL(void) EMR3Reset(PVM pVM)
462	{
463	LogFlow(("EMR3Reset: \n"));
464	for (unsigned i=0;i<pVM->cCPUs;i++)
465	{
466	PVMCPU pVCpu = &pVM->aCpus[i];
467
468	pVCpu->em.s.fForceRAW = false;
469	}
470	}
471
472
473	/**
474	* Terminates the EM.
475	*
476	* Termination means cleaning up and freeing all resources,
477	* the VM it self is at this point powered off or suspended.
478	*
479	* @returns VBox status code.
480	* @param pVM The VM to operate on.
481	*/
482	VMMR3DECL(int) EMR3Term(PVM pVM)
483	{
484	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
485
486	PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
487	return VINF_SUCCESS;
488	}
489
490	/**
491	* Terminates the per-VCPU EM.
492	*
493	* Termination means cleaning up and freeing all resources,
494	* the VM it self is at this point powered off or suspended.
495	*
496	* @returns VBox status code.
497	* @param pVM The VM to operate on.
498	*/
499	VMMR3DECL(int) EMR3TermCPU(PVM pVM)
500	{
501	return 0;
502	}
503
504	/**
505	* Execute state save operation.
506	*
507	* @returns VBox status code.
508	* @param pVM VM Handle.
509	* @param pSSM SSM operation handle.
510	*/
511	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
512	{
513	for (VMCPUID i = 0; i < pVM->cCPUs; i++)
514	{
515	PVMCPU pVCpu = &pVM->aCpus[i];
516
517	int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
518	AssertRCReturn(rc, rc);
519
520	Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
521	Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
522	rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
523	AssertRCReturn(rc, rc);
524	}
525	return VINF_SUCCESS;
526	}
527
528
529	/**
530	* Execute state load operation.
531	*
532	* @returns VBox status code.
533	* @param pVM VM Handle.
534	* @param pSSM SSM operation handle.
535	* @param u32Version Data layout version.
536	*/
537	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
538	{
539	int rc = VINF_SUCCESS;
540
541	/*
542	* Validate version.
543	*/
544	if ( u32Version != EM_SAVED_STATE_VERSION
545	&& u32Version != EM_SAVED_STATE_VERSION_PRE_SMP)
546	{
547	AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
548	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
549	}
550
551	/*
552	* Load the saved state.
553	*/
554	for (VMCPUID i = 0; i < pVM->cCPUs; i++)
555	{
556	PVMCPU pVCpu = &pVM->aCpus[i];
557
558	rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
559	if (RT_FAILURE(rc))
560	pVCpu->em.s.fForceRAW = false;
561
562	if (u32Version > EM_SAVED_STATE_VERSION_PRE_SMP)
563	{
564	AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
565	rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
566	AssertRCReturn(rc, rc);
567	Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
568
569	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
570	}
571	Assert(!pVCpu->em.s.pCliStatTree);
572	}
573	return rc;
574	}
575
576
577	/**
578	* Enables or disables a set of raw-mode execution modes.
579	*
580	* @returns VINF_SUCCESS on success.
581	* @returns VINF_RESCHEDULE if a rescheduling might be required.
582	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
583	*
584	* @param pVM The VM to operate on.
585	* @param enmMode The execution mode change.
586	* @thread The emulation thread.
587	*/
588	VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
589	{
590	switch (enmMode)
591	{
592	case EMRAW_NONE:
593	pVM->fRawR3Enabled = false;
594	pVM->fRawR0Enabled = false;
595	break;
596	case EMRAW_RING3_ENABLE:
597	pVM->fRawR3Enabled = true;
598	break;
599	case EMRAW_RING3_DISABLE:
600	pVM->fRawR3Enabled = false;
601	break;
602	case EMRAW_RING0_ENABLE:
603	pVM->fRawR0Enabled = true;
604	break;
605	case EMRAW_RING0_DISABLE:
606	pVM->fRawR0Enabled = false;
607	break;
608	default:
609	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
610	return VERR_INVALID_PARAMETER;
611	}
612	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
613	pVM->fRawR3Enabled, pVM->fRawR0Enabled));
614	return pVM->aCpus[0].em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
615	}
616
617
618	/**
619	* Raise a fatal error.
620	*
621	* Safely terminate the VM with full state report and stuff. This function
622	* will naturally never return.
623	*
624	* @param pVCpu VMCPU handle.
625	* @param rc VBox status code.
626	*/
627	VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
628	{
629	longjmp(pVCpu->em.s.u.FatalLongJump, rc);
630	AssertReleaseMsgFailed(("longjmp returned!\n"));
631	}
632
633
634	/**
635	* Gets the EM state name.
636	*
637	* @returns pointer to read only state name,
638	* @param enmState The state.
639	*/
640	VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
641	{
642	switch (enmState)
643	{
644	case EMSTATE_NONE: return "EMSTATE_NONE";
645	case EMSTATE_RAW: return "EMSTATE_RAW";
646	case EMSTATE_HWACC: return "EMSTATE_HWACC";
647	case EMSTATE_REM: return "EMSTATE_REM";
648	case EMSTATE_PARAV: return "EMSTATE_PARAV";
649	case EMSTATE_HALTED: return "EMSTATE_HALTED";
650	case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
651	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
652	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
653	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
654	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
655	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
656	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
657	default: return "Unknown!";
658	}
659	}
660
661
662	#ifdef VBOX_WITH_STATISTICS
663	/**
664	* Just a braindead function to keep track of cli addresses.
665	* @param pVM VM handle.
666	* @param pVMCPU VMCPU handle.
667	* @param GCPtrInstr The EIP of the cli instruction.
668	*/
669	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
670	{
671	PCLISTAT pRec;
672
673	pRec = (PCLISTAT)RTAvlPVGet(&pVCpu->em.s.pCliStatTree, (AVLPVKEY)GCPtrInstr);
674	if (!pRec)
675	{
676	/* New cli instruction; insert into the tree. */
677	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
678	Assert(pRec);
679	if (!pRec)
680	return;
681	pRec->Core.Key = (AVLPVKEY)GCPtrInstr;
682
683	char szCliStatName[32];
684	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
685	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
686
687	bool fRc = RTAvlPVInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
688	Assert(fRc); NOREF(fRc);
689	}
690	STAM_COUNTER_INC(&pRec->Counter);
691	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
692	}
693	#endif /* VBOX_WITH_STATISTICS */
694
695
696	/**
697	* Debug loop.
698	*
699	* @returns VBox status code for EM.
700	* @param pVM VM handle.
701	* @param pVCpu VMCPU handle.
702	* @param rc Current EM VBox status code..
703	*/
704	static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
705	{
706	for (;;)
707	{
708	Log(("emR3Debug: rc=%Rrc\n", rc));
709	const int rcLast = rc;
710
711	/*
712	* Debug related RC.
713	*/
714	switch (rc)
715	{
716	/*
717	* Single step an instruction.
718	*/
719	case VINF_EM_DBG_STEP:
720	if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
721	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
722	\|\| pVCpu->em.s.fForceRAW /* paranoia */)
723	rc = emR3RawStep(pVM, pVCpu);
724	else
725	{
726	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
727	rc = emR3RemStep(pVM, pVCpu);
728	}
729	break;
730
731	/*
732	* Simple events: stepped, breakpoint, stop/assertion.
733	*/
734	case VINF_EM_DBG_STEPPED:
735	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
736	break;
737
738	case VINF_EM_DBG_BREAKPOINT:
739	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
740	break;
741
742	case VINF_EM_DBG_STOP:
743	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
744	break;
745
746	case VINF_EM_DBG_HYPER_STEPPED:
747	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
748	break;
749
750	case VINF_EM_DBG_HYPER_BREAKPOINT:
751	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
752	break;
753
754	case VINF_EM_DBG_HYPER_ASSERTION:
755	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
756	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
757	break;
758
759	/*
760	* Guru meditation.
761	*/
762	case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
763	rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
764	break;
765	case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
766	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
767	break;
768
769	default: /** @todo don't use default for guru, but make special errors code! */
770	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
771	break;
772	}
773
774	/*
775	* Process the result.
776	*/
777	do
778	{
779	switch (rc)
780	{
781	/*
782	* Continue the debugging loop.
783	*/
784	case VINF_EM_DBG_STEP:
785	case VINF_EM_DBG_STOP:
786	case VINF_EM_DBG_STEPPED:
787	case VINF_EM_DBG_BREAKPOINT:
788	case VINF_EM_DBG_HYPER_STEPPED:
789	case VINF_EM_DBG_HYPER_BREAKPOINT:
790	case VINF_EM_DBG_HYPER_ASSERTION:
791	break;
792
793	/*
794	* Resuming execution (in some form) has to be done here if we got
795	* a hypervisor debug event.
796	*/
797	case VINF_SUCCESS:
798	case VINF_EM_RESUME:
799	case VINF_EM_SUSPEND:
800	case VINF_EM_RESCHEDULE:
801	case VINF_EM_RESCHEDULE_RAW:
802	case VINF_EM_RESCHEDULE_REM:
803	case VINF_EM_HALT:
804	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
805	{
806	rc = emR3RawResumeHyper(pVM, pVCpu);
807	if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
808	continue;
809	}
810	if (rc == VINF_SUCCESS)
811	rc = VINF_EM_RESCHEDULE;
812	return rc;
813
814	/*
815	* The debugger isn't attached.
816	* We'll simply turn the thing off since that's the easiest thing to do.
817	*/
818	case VERR_DBGF_NOT_ATTACHED:
819	switch (rcLast)
820	{
821	case VINF_EM_DBG_HYPER_STEPPED:
822	case VINF_EM_DBG_HYPER_BREAKPOINT:
823	case VINF_EM_DBG_HYPER_ASSERTION:
824	case VERR_TRPM_PANIC:
825	case VERR_TRPM_DONT_PANIC:
826	case VERR_VMM_RING0_ASSERTION:
827	return rcLast;
828	}
829	return VINF_EM_OFF;
830
831	/*
832	* Status codes terminating the VM in one or another sense.
833	*/
834	case VINF_EM_TERMINATE:
835	case VINF_EM_OFF:
836	case VINF_EM_RESET:
837	case VINF_EM_NO_MEMORY:
838	case VINF_EM_RAW_STALE_SELECTOR:
839	case VINF_EM_RAW_IRET_TRAP:
840	case VERR_TRPM_PANIC:
841	case VERR_TRPM_DONT_PANIC:
842	case VERR_VMM_RING0_ASSERTION:
843	case VERR_INTERNAL_ERROR:
844	case VERR_INTERNAL_ERROR_2:
845	case VERR_INTERNAL_ERROR_3:
846	case VERR_INTERNAL_ERROR_4:
847	case VERR_INTERNAL_ERROR_5:
848	case VERR_IPE_UNEXPECTED_STATUS:
849	case VERR_IPE_UNEXPECTED_INFO_STATUS:
850	case VERR_IPE_UNEXPECTED_ERROR_STATUS:
851	return rc;
852
853	/*
854	* The rest is unexpected, and will keep us here.
855	*/
856	default:
857	AssertMsgFailed(("Unxpected rc %Rrc!\n", rc));
858	break;
859	}
860	} while (false);
861	} /* debug for ever */
862	}
863
864	/**
865	* Locks REM execution to a single VCpu
866	*
867	* @param pVM VM handle.
868	*/
869	VMMR3DECL(void) EMR3RemLock(PVM pVM)
870	{
871	#ifdef IN_RING3
872	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
873	return; /* early init */
874	#else
875	Assert(PDMCritSectIsInitialized(&pVM->em.s.CritSectREM));
876	#endif
877	int rc = PDMCritSectEnter(&pVM->em.s.CritSectREM, VERR_SEM_BUSY);
878	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
879	}
880
881	/**
882	* Unlocks REM execution
883	*
884	* @param pVM VM handle.
885	*/
886	VMMR3DECL(void) EMR3RemUnlock(PVM pVM)
887	{
888	#ifdef IN_RING3
889	if (!PDMCritSectIsInitialized(&pVM->em.s.CritSectREM))
890	return; /* early init */
891	#else
892	Assert(PDMCritSectIsInitialized(&pVM->em.s.CritSectREM));
893	#endif
894	PDMCritSectLeave(&pVM->em.s.CritSectREM);
895	}
896
897	/**
898	* Steps recompiled code.
899	*
900	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
901	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
902	*
903	* @param pVM VM handle.
904	* @param pVCpu VMCPU handle.
905	*/
906	static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
907	{
908	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
909
910	EMR3RemLock(pVM);
911
912	/*
913	* Switch to REM, step instruction, switch back.
914	*/
915	int rc = REMR3State(pVM, pVCpu);
916	if (RT_SUCCESS(rc))
917	{
918	rc = REMR3Step(pVM, pVCpu);
919	REMR3StateBack(pVM, pVCpu);
920	}
921	EMR3RemUnlock(pVM);
922
923	LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
924	return rc;
925	}
926
927
928	/**
929	* Executes recompiled code.
930	*
931	* This function contains the recompiler version of the inner
932	* execution loop (the outer loop being in EMR3ExecuteVM()).
933	*
934	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
935	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
936	*
937	* @param pVM VM handle.
938	* @param pVCpu VMCPU handle.
939	* @param pfFFDone Where to store an indicator telling wheter or not
940	* FFs were done before returning.
941	*
942	*/
943	static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
944	{
945	#ifdef LOG_ENABLED
946	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
947	uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
948
949	if (pCtx->eflags.Bits.u1VM)
950	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
951	else
952	Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
953	#endif
954	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
955
956	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
957	AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
958	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo #1419 - get flat address. */
959	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
960	#endif
961
962	/* Big lock, but you are not supposed to own any lock when coming in here. */
963	EMR3RemLock(pVM);
964
965	/*
966	* Spin till we get a forced action which returns anything but VINF_SUCCESS
967	* or the REM suggests raw-mode execution.
968	*/
969	*pfFFDone = false;
970	bool fInREMState = false;
971	int rc = VINF_SUCCESS;
972
973	/* Flush the recompiler TLB if the VCPU has changed. */
974	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
975	{
976	REMFlushTBs(pVM);
977	/* Also sync the entire state. */
978	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
979	}
980	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
981
982	for (;;)
983	{
984	/*
985	* Update REM state if not already in sync.
986	*/
987	if (!fInREMState)
988	{
989	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
990	rc = REMR3State(pVM, pVCpu);
991	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
992	if (RT_FAILURE(rc))
993	break;
994	fInREMState = true;
995
996	/*
997	* We might have missed the raising of VMREQ, TIMER and some other
998	* imporant FFs while we were busy switching the state. So, check again.
999	*/
1000	if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET)
1001	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER \| VMCPU_FF_REQUEST))
1002	{
1003	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
1004	goto l_REMDoForcedActions;
1005	}
1006	}
1007
1008
1009	/*
1010	* Execute REM.
1011	*/
1012	STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
1013	rc = REMR3Run(pVM, pVCpu);
1014	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
1015
1016
1017	/*
1018	* Deal with high priority post execution FFs before doing anything else.
1019	*/
1020	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1021	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1022	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1023
1024	/*
1025	* Process the returned status code.
1026	* (Try keep this short! Call functions!)
1027	*/
1028	if (rc != VINF_SUCCESS)
1029	{
1030	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1031	break;
1032	if (rc != VINF_REM_INTERRUPED_FF)
1033	{
1034	/*
1035	* Anything which is not known to us means an internal error
1036	* and the termination of the VM!
1037	*/
1038	AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1039	break;
1040	}
1041	}
1042
1043
1044	/*
1045	* Check and execute forced actions.
1046	* Sync back the VM state before calling any of these.
1047	*/
1048	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1049	TMTimerPollVoid(pVM, pVCpu);
1050	#endif
1051	AssertCompile((VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
1052	if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
1053	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_CSAM_SCAN_PAGE)))
1054	{
1055	l_REMDoForcedActions:
1056	if (fInREMState)
1057	{
1058	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, d);
1059	REMR3StateBack(pVM, pVCpu);
1060	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, d);
1061	fInREMState = false;
1062	}
1063	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1064	rc = emR3ForcedActions(pVM, pVCpu, rc);
1065	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1066	if ( rc != VINF_SUCCESS
1067	&& rc != VINF_EM_RESCHEDULE_REM)
1068	{
1069	*pfFFDone = true;
1070	break;
1071	}
1072	}
1073
1074	} /* The Inner Loop, recompiled execution mode version. */
1075
1076
1077	/*
1078	* Returning. Sync back the VM state if required.
1079	*/
1080	if (fInREMState)
1081	{
1082	STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, e);
1083	REMR3StateBack(pVM, pVCpu);
1084	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, e);
1085	}
1086	EMR3RemUnlock(pVM);
1087
1088	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1089	return rc;
1090	}
1091
1092
1093	/**
1094	* Resumes executing hypervisor after a debug event.
1095	*
1096	* This is kind of special since our current guest state is
1097	* potentially out of sync.
1098	*
1099	* @returns VBox status code.
1100	* @param pVM The VM handle.
1101	* @param pVCpu The VMCPU handle.
1102	*/
1103	static int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
1104	{
1105	int rc;
1106	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1107	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
1108	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
1109
1110	/*
1111	* Resume execution.
1112	*/
1113	CPUMRawEnter(pVCpu, NULL);
1114	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
1115	rc = VMMR3ResumeHyper(pVM, pVCpu);
1116	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
1117	rc = CPUMRawLeave(pVCpu, NULL, rc);
1118	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1119
1120	/*
1121	* Deal with the return code.
1122	*/
1123	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1124	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1125	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1126	return rc;
1127	}
1128
1129
1130	/**
1131	* Steps rawmode.
1132	*
1133	* @returns VBox status code.
1134	* @param pVM The VM handle.
1135	* @param pVCpu The VMCPU handle.
1136	*/
1137	static int emR3RawStep(PVM pVM, PVMCPU pVCpu)
1138	{
1139	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
1140	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
1141	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
1142	int rc;
1143	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1144	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
1145	#ifndef DEBUG_sandervl
1146	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
1147	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
1148	#endif
1149	if (fGuest)
1150	{
1151	/*
1152	* Check vital forced actions, but ignore pending interrupts and timers.
1153	*/
1154	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1155	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1156	{
1157	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1158	if (rc != VINF_SUCCESS)
1159	return rc;
1160	}
1161
1162	/*
1163	* Set flags for single stepping.
1164	*/
1165	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
1166	}
1167	else
1168	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
1169
1170	/*
1171	* Single step.
1172	* We do not start time or anything, if anything we should just do a few nanoseconds.
1173	*/
1174	CPUMRawEnter(pVCpu, NULL);
1175	do
1176	{
1177	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
1178	rc = VMMR3ResumeHyper(pVM, pVCpu);
1179	else
1180	rc = VMMR3RawRunGC(pVM, pVCpu);
1181	#ifndef DEBUG_sandervl
1182	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
1183	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
1184	#endif
1185	} while ( rc == VINF_SUCCESS
1186	\|\| rc == VINF_EM_RAW_INTERRUPT);
1187	rc = CPUMRawLeave(pVCpu, NULL, rc);
1188	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1189
1190	/*
1191	* Make sure the trap flag is cleared.
1192	* (Too bad if the guest is trying to single step too.)
1193	*/
1194	if (fGuest)
1195	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1196	else
1197	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
1198
1199	/*
1200	* Deal with the return codes.
1201	*/
1202	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1203	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1204	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1205	return rc;
1206	}
1207
1208
1209	#ifdef DEBUG
1210
1211	/**
1212	* Steps hardware accelerated mode.
1213	*
1214	* @returns VBox status code.
1215	* @param pVM The VM handle.
1216	* @param pVCpu The VMCPU handle.
1217	*/
1218	static int emR3HwAccStep(PVM pVM, PVMCPU pVCpu)
1219	{
1220	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1221
1222	int rc;
1223	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1224	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS));
1225
1226	/*
1227	* Check vital forced actions, but ignore pending interrupts and timers.
1228	*/
1229	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1230	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1231	{
1232	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1233	if (rc != VINF_SUCCESS)
1234	return rc;
1235	}
1236	/*
1237	* Set flags for single stepping.
1238	*/
1239	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
1240
1241	/*
1242	* Single step.
1243	* We do not start time or anything, if anything we should just do a few nanoseconds.
1244	*/
1245	do
1246	{
1247	rc = VMMR3HwAccRunGC(pVM, pVCpu);
1248	} while ( rc == VINF_SUCCESS
1249	\|\| rc == VINF_EM_RAW_INTERRUPT);
1250	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1251
1252	/*
1253	* Make sure the trap flag is cleared.
1254	* (Too bad if the guest is trying to single step too.)
1255	*/
1256	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1257
1258	/*
1259	* Deal with the return codes.
1260	*/
1261	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1262	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1263	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1264	return rc;
1265	}
1266
1267
1268	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1269	{
1270	int rc = VINF_SUCCESS;
1271	EMSTATE enmOldState = pVCpu->em.s.enmState;
1272	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1273
1274	Log(("Single step BEGIN:\n"));
1275	for (uint32_t i = 0; i < cIterations; i++)
1276	{
1277	DBGFR3PrgStep(pVCpu);
1278	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1279	rc = emR3RawStep(pVM, pVCpu);
1280	if (rc != VINF_SUCCESS)
1281	break;
1282	}
1283	Log(("Single step END: rc=%Rrc\n", rc));
1284	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1285	pVCpu->em.s.enmState = enmOldState;
1286	return rc;
1287	}
1288
1289
1290	static int emR3SingleStepExecHwAcc(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1291	{
1292	int rc = VINF_SUCCESS;
1293	EMSTATE enmOldState = pVCpu->em.s.enmState;
1294	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1295
1296	Log(("Single step BEGIN:\n"));
1297	for (uint32_t i = 0; i < cIterations; i++)
1298	{
1299	DBGFR3PrgStep(pVCpu);
1300	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1301	rc = emR3HwAccStep(pVM, pVCpu);
1302	if ( rc != VINF_SUCCESS
1303	\|\| !HWACCMR3CanExecuteGuest(pVM, pVCpu->em.s.pCtx))
1304	break;
1305	}
1306	Log(("Single step END: rc=%Rrc\n", rc));
1307	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1308	pVCpu->em.s.enmState = enmOldState;
1309	return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
1310	}
1311
1312
1313	static int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1314	{
1315	EMSTATE enmOldState = pVCpu->em.s.enmState;
1316
1317	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1318
1319	Log(("Single step BEGIN:\n"));
1320	for (uint32_t i = 0; i < cIterations; i++)
1321	{
1322	DBGFR3PrgStep(pVCpu);
1323	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1324	emR3RemStep(pVM, pVCpu);
1325	if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1326	break;
1327	}
1328	Log(("Single step END:\n"));
1329	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1330	pVCpu->em.s.enmState = enmOldState;
1331	return VINF_EM_RESCHEDULE;
1332	}
1333
1334	#endif /* DEBUG */
1335
1336
1337	/**
1338	* Executes one (or perhaps a few more) instruction(s).
1339	*
1340	* @returns VBox status code suitable for EM.
1341	*
1342	* @param pVM VM handle.
1343	* @param pVCpu VMCPU handle
1344	* @param rcGC GC return code
1345	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1346	* instruction and prefix the log output with this text.
1347	*/
1348	#ifdef LOG_ENABLED
1349	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
1350	#else
1351	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
1352	#endif
1353	{
1354	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1355	int rc;
1356
1357	/*
1358	*
1359	* The simple solution is to use the recompiler.
1360	* The better solution is to disassemble the current instruction and
1361	* try handle as many as possible without using REM.
1362	*
1363	*/
1364
1365	#ifdef LOG_ENABLED
1366	/*
1367	* Disassemble the instruction if requested.
1368	*/
1369	if (pszPrefix)
1370	{
1371	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1372	DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
1373	}
1374	#endif /* LOG_ENABLED */
1375
1376	/*
1377	* PATM is making life more interesting.
1378	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1379	* tell PATM there is a trap in this code and have it take the appropriate actions
1380	* to allow us execute the code in REM.
1381	*/
1382	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1383	{
1384	Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
1385
1386	RTGCPTR pNewEip;
1387	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1388	switch (rc)
1389	{
1390	/*
1391	* It's not very useful to emulate a single instruction and then go back to raw
1392	* mode; just execute the whole block until IF is set again.
1393	*/
1394	case VINF_SUCCESS:
1395	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
1396	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1397	pCtx->eip = pNewEip;
1398	Assert(pCtx->eip);
1399
1400	if (pCtx->eflags.Bits.u1IF)
1401	{
1402	/*
1403	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1404	*/
1405	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1406	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1407	}
1408	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1409	{
1410	/* special case: iret, that sets IF, detected a pending irq/event */
1411	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET");
1412	}
1413	return VINF_EM_RESCHEDULE_REM;
1414
1415	/*
1416	* One instruction.
1417	*/
1418	case VINF_PATCH_EMULATE_INSTR:
1419	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
1420	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1421	pCtx->eip = pNewEip;
1422	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1423
1424	/*
1425	* The patch was disabled, hand it to the REM.
1426	*/
1427	case VERR_PATCH_DISABLED:
1428	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
1429	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
1430	pCtx->eip = pNewEip;
1431	if (pCtx->eflags.Bits.u1IF)
1432	{
1433	/*
1434	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1435	*/
1436	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1437	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1438	}
1439	return VINF_EM_RESCHEDULE_REM;
1440
1441	/* Force continued patch exection; usually due to write monitored stack. */
1442	case VINF_PATCH_CONTINUE:
1443	return VINF_SUCCESS;
1444
1445	default:
1446	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
1447	return VERR_IPE_UNEXPECTED_STATUS;
1448	}
1449	}
1450
1451	#if 0
1452	/* Try our own instruction emulator before falling back to the recompiler. */
1453	DISCPUSTATE Cpu;
1454	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1455	if (RT_SUCCESS(rc))
1456	{
1457	uint32_t size;
1458
1459	switch (Cpu.pCurInstr->opcode)
1460	{
1461	/* @todo we can do more now */
1462	case OP_MOV:
1463	case OP_AND:
1464	case OP_OR:
1465	case OP_XOR:
1466	case OP_POP:
1467	case OP_INC:
1468	case OP_DEC:
1469	case OP_XCHG:
1470	STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
1471	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1472	if (RT_SUCCESS(rc))
1473	{
1474	pCtx->rip += Cpu.opsize;
1475	#ifdef EM_NOTIFY_HWACCM
1476	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1477	HWACCMR3NotifyEmulated(pVCpu);
1478	#endif
1479	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
1480	return rc;
1481	}
1482	if (rc != VERR_EM_INTERPRETER)
1483	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
1484	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
1485	break;
1486	}
1487	}
1488	#endif /* 0 */
1489	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
1490	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
1491	EMR3RemLock(pVM);
1492	/* Flush the recompiler TLB if the VCPU has changed. */
1493	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
1494	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1495	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
1496
1497	rc = REMR3EmulateInstruction(pVM, pVCpu);
1498	EMR3RemUnlock(pVM);
1499	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
1500
1501	#ifdef EM_NOTIFY_HWACCM
1502	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1503	HWACCMR3NotifyEmulated(pVCpu);
1504	#endif
1505	return rc;
1506	}
1507
1508
1509	/**
1510	* Executes one (or perhaps a few more) instruction(s).
1511	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1512	*
1513	* @returns VBox status code suitable for EM.
1514	* @param pVM VM handle.
1515	* @param pVCpu VMCPU handle.
1516	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1517	* instruction and prefix the log output with this text.
1518	* @param rcGC GC return code
1519	*/
1520	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
1521	{
1522	#ifdef LOG_ENABLED
1523	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
1524	#else
1525	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
1526	#endif
1527	}
1528
1529	/**
1530	* Executes one (or perhaps a few more) IO instruction(s).
1531	*
1532	* @returns VBox status code suitable for EM.
1533	* @param pVM VM handle.
1534	* @param pVCpu VMCPU handle.
1535	*/
1536	int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
1537	{
1538	int rc;
1539	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1540
1541	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
1542
1543	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1544	* as io instructions tend to come in packages of more than one
1545	*/
1546	DISCPUSTATE Cpu;
1547	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
1548	if (RT_SUCCESS(rc))
1549	{
1550	rc = VINF_EM_RAW_EMULATE_INSTR;
1551
1552	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1553	{
1554	switch (Cpu.pCurInstr->opcode)
1555	{
1556	case OP_IN:
1557	{
1558	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
1559	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1560	break;
1561	}
1562
1563	case OP_OUT:
1564	{
1565	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
1566	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1567	break;
1568	}
1569	}
1570	}
1571	else if (Cpu.prefix & PREFIX_REP)
1572	{
1573	switch (Cpu.pCurInstr->opcode)
1574	{
1575	case OP_INSB:
1576	case OP_INSWD:
1577	{
1578	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
1579	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1580	break;
1581	}
1582
1583	case OP_OUTSB:
1584	case OP_OUTSWD:
1585	{
1586	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
1587	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1588	break;
1589	}
1590	}
1591	}
1592
1593	/*
1594	* Handled the I/O return codes.
1595	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1596	*/
1597	if (IOM_SUCCESS(rc))
1598	{
1599	pCtx->rip += Cpu.opsize;
1600	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1601	return rc;
1602	}
1603
1604	if (rc == VINF_EM_RAW_GUEST_TRAP)
1605	{
1606	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1607	rc = emR3RawGuestTrap(pVM, pVCpu);
1608	return rc;
1609	}
1610	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1611
1612	if (RT_FAILURE(rc))
1613	{
1614	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1615	return rc;
1616	}
1617	AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc=%Rrc\n", rc));
1618	}
1619	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
1620	return emR3RawExecuteInstruction(pVM, pVCpu, "IO: ");
1621	}
1622
1623
1624	/**
1625	* Handle a guest context trap.
1626	*
1627	* @returns VBox status code suitable for EM.
1628	* @param pVM VM handle.
1629	* @param pVCpu VMCPU handle.
1630	*/
1631	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
1632	{
1633	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1634
1635	/*
1636	* Get the trap info.
1637	*/
1638	uint8_t u8TrapNo;
1639	TRPMEVENT enmType;
1640	RTGCUINT uErrorCode;
1641	RTGCUINTPTR uCR2;
1642	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1643	if (RT_FAILURE(rc))
1644	{
1645	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
1646	return rc;
1647	}
1648
1649	/*
1650	* Traps can be directly forwarded in hardware accelerated mode.
1651	*/
1652	if (HWACCMIsEnabled(pVM))
1653	{
1654	#ifdef LOGGING_ENABLED
1655	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1656	DBGFR3DisasInstrCurrentLog(pVCpu, "Guest trap");
1657	#endif
1658	return VINF_EM_RESCHEDULE_HWACC;
1659	}
1660
1661	#if 1 /* Experimental: Review, disable if it causes trouble. */
1662	/*
1663	* Handle traps in patch code first.
1664	*
1665	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
1666	* but several traps isn't handled specially by TRPM in RC and we end up here
1667	* instead. One example is #DE.
1668	*/
1669	uint32_t uCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
1670	if ( uCpl == 0
1671	&& PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1672	{
1673	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
1674	return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
1675	}
1676	#endif
1677
1678	/*
1679	* If the guest gate is marked unpatched, then we will check again if we can patch it.
1680	* (This assumes that we've already tried and failed to dispatch the trap in
1681	* RC for the gates that already has been patched. Which is true for most high
1682	* volume traps, because these are handled specially, but not for odd ones like #DE.)
1683	*/
1684	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
1685	{
1686	CSAMR3CheckGates(pVM, u8TrapNo, 1);
1687	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
1688
1689	/* If it was successful, then we could go back to raw mode. */
1690	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
1691	{
1692	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
1693	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1694	AssertRCReturn(rc, rc);
1695
1696	TRPMERRORCODE enmError = uErrorCode != ~0U
1697	? TRPM_TRAP_HAS_ERRORCODE
1698	: TRPM_TRAP_NO_ERRORCODE;
1699	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
1700	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1701	{
1702	TRPMResetTrap(pVCpu);
1703	return VINF_EM_RESCHEDULE_RAW;
1704	}
1705	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
1706	}
1707	}
1708
1709	/*
1710	* Scan kernel code that traps; we might not get another chance.
1711	*/
1712	/** @todo move this up before the dispatching? */
1713	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1714	&& !pCtx->eflags.Bits.u1VM)
1715	{
1716	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1717	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1718	}
1719
1720	/*
1721	* Trap specific handling.
1722	*/
1723	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1724	{
1725	/*
1726	* If MONITOR & MWAIT are supported, then interpret them here.
1727	*/
1728	DISCPUSTATE cpu;
1729	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1730	if ( RT_SUCCESS(rc)
1731	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1732	{
1733	uint32_t u32Dummy, u32Features, u32ExtFeatures;
1734	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1735	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1736	{
1737	rc = TRPMResetTrap(pVCpu);
1738	AssertRC(rc);
1739
1740	uint32_t opsize;
1741	rc = EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
1742	if (RT_SUCCESS(rc))
1743	{
1744	pCtx->rip += cpu.opsize;
1745	#ifdef EM_NOTIFY_HWACCM
1746	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
1747	HWACCMR3NotifyEmulated(pVCpu);
1748	#endif
1749	return rc;
1750	}
1751	return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: ");
1752	}
1753	}
1754	}
1755	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1756	{
1757	/*
1758	* Handle I/O bitmap?
1759	*/
1760	/** @todo We're not supposed to be here with a false guest trap concerning
1761	* I/O access. We can easily handle those in RC. */
1762	DISCPUSTATE cpu;
1763	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1764	if ( RT_SUCCESS(rc)
1765	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1766	{
1767	/*
1768	* We should really check the TSS for the IO bitmap, but it's not like this
1769	* lazy approach really makes things worse.
1770	*/
1771	rc = TRPMResetTrap(pVCpu);
1772	AssertRC(rc);
1773	return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
1774	}
1775	}
1776
1777	#ifdef LOG_ENABLED
1778	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1779	DBGFR3DisasInstrCurrentLog(pVCpu, "Guest trap");
1780
1781	/* Get guest page information. */
1782	uint64_t fFlags = 0;
1783	RTGCPHYS GCPhys = 0;
1784	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
1785	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1786	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1787	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1788	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1789	#endif
1790
1791	/*
1792	* #PG has CR2.
1793	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1794	*/
1795	if (u8TrapNo == 14 /* #PG */)
1796	pCtx->cr2 = uCR2;
1797
1798	return VINF_EM_RESCHEDULE_REM;
1799	}
1800
1801
1802	/**
1803	* Handle a ring switch trap.
1804	* Need to do statistics and to install patches. The result is going to REM.
1805	*
1806	* @returns VBox status code suitable for EM.
1807	* @param pVM VM handle.
1808	* @param pVCpu VMCPU handle.
1809	*/
1810	int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
1811	{
1812	int rc;
1813	DISCPUSTATE Cpu;
1814	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1815
1816	/*
1817	* sysenter, syscall & callgate
1818	*/
1819	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1820	if (RT_SUCCESS(rc))
1821	{
1822	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1823	{
1824	if (pCtx->SysEnter.cs != 0)
1825	{
1826	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1827	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1828	if (RT_SUCCESS(rc))
1829	{
1830	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched sysenter instruction");
1831	return VINF_EM_RESCHEDULE_RAW;
1832	}
1833	}
1834	}
1835
1836	#ifdef VBOX_WITH_STATISTICS
1837	switch (Cpu.pCurInstr->opcode)
1838	{
1839	case OP_SYSENTER:
1840	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
1841	break;
1842	case OP_SYSEXIT:
1843	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
1844	break;
1845	case OP_SYSCALL:
1846	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
1847	break;
1848	case OP_SYSRET:
1849	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
1850	break;
1851	}
1852	#endif
1853	}
1854	else
1855	AssertRC(rc);
1856
1857	/* go to the REM to emulate a single instruction */
1858	return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
1859	}
1860
1861
1862	/**
1863	* Handle a trap (\#PF or \#GP) in patch code
1864	*
1865	* @returns VBox status code suitable for EM.
1866	* @param pVM VM handle.
1867	* @param pVCpu VMCPU handle.
1868	* @param pCtx CPU context
1869	* @param gcret GC return code
1870	*/
1871	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
1872	{
1873	uint8_t u8TrapNo;
1874	int rc;
1875	TRPMEVENT enmType;
1876	RTGCUINT uErrorCode;
1877	RTGCUINTPTR uCR2;
1878
1879	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1880
1881	if (gcret == VINF_PATM_PATCH_INT3)
1882	{
1883	u8TrapNo = 3;
1884	uCR2 = 0;
1885	uErrorCode = 0;
1886	}
1887	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
1888	{
1889	/* No active trap in this case. Kind of ugly. */
1890	u8TrapNo = X86_XCPT_GP;
1891	uCR2 = 0;
1892	uErrorCode = 0;
1893	}
1894	else
1895	{
1896	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1897	if (RT_FAILURE(rc))
1898	{
1899	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
1900	return rc;
1901	}
1902	/* Reset the trap as we'll execute the original instruction again. */
1903	TRPMResetTrap(pVCpu);
1904	}
1905
1906	/*
1907	* Deal with traps inside patch code.
1908	* (This code won't run outside GC.)
1909	*/
1910	if (u8TrapNo != 1)
1911	{
1912	#ifdef LOG_ENABLED
1913	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1914	DBGFR3DisasInstrCurrentLog(pVCpu, "Patch code");
1915
1916	DISCPUSTATE Cpu;
1917	int rc;
1918
1919	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1920	if ( RT_SUCCESS(rc)
1921	&& Cpu.pCurInstr->opcode == OP_IRET)
1922	{
1923	uint32_t eip, selCS, uEFlags;
1924
1925	/* Iret crashes are bad as we have already changed the flags on the stack */
1926	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
1927	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
1928	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
1929	if (rc == VINF_SUCCESS)
1930	{
1931	if ( (uEFlags & X86_EFL_VM)
1932	\|\| (selCS & X86_SEL_RPL) == 3)
1933	{
1934	uint32_t selSS, esp;
1935
1936	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
1937	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
1938
1939	if (uEFlags & X86_EFL_VM)
1940	{
1941	uint32_t selDS, selES, selFS, selGS;
1942	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
1943	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
1944	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
1945	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
1946	if (rc == VINF_SUCCESS)
1947	{
1948	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1949	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1950	}
1951	}
1952	else
1953	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
1954	}
1955	else
1956	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
1957	}
1958	}
1959	#endif /* LOG_ENABLED */
1960	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1961	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1962
1963	RTGCPTR pNewEip;
1964	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1965	switch (rc)
1966	{
1967	/*
1968	* Execute the faulting instruction.
1969	*/
1970	case VINF_SUCCESS:
1971	{
1972	/** @todo execute a whole block */
1973	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
1974	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1975	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1976
1977	pCtx->eip = pNewEip;
1978	AssertRelease(pCtx->eip);
1979
1980	if (pCtx->eflags.Bits.u1IF)
1981	{
1982	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1983	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1984	*/
1985	if ( u8TrapNo == X86_XCPT_GP
1986	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1987	{
1988	/** @todo move to PATMR3HandleTrap */
1989	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
1990	PATMR3RemovePatch(pVM, pCtx->eip);
1991	}
1992
1993	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1994	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
1995
1996	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
1997	/* Interrupts are enabled; just go back to the original instruction.
1998	return VINF_SUCCESS; */
1999	}
2000	return VINF_EM_RESCHEDULE_REM;
2001	}
2002
2003	/*
2004	* One instruction.
2005	*/
2006	case VINF_PATCH_EMULATE_INSTR:
2007	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
2008	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
2009	pCtx->eip = pNewEip;
2010	AssertRelease(pCtx->eip);
2011	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
2012
2013	/*
2014	* The patch was disabled, hand it to the REM.
2015	*/
2016	case VERR_PATCH_DISABLED:
2017	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
2018	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
2019	pCtx->eip = pNewEip;
2020	AssertRelease(pCtx->eip);
2021
2022	if (pCtx->eflags.Bits.u1IF)
2023	{
2024	/*
2025	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
2026	*/
2027	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
2028	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
2029	}
2030	return VINF_EM_RESCHEDULE_REM;
2031
2032	/* Force continued patch exection; usually due to write monitored stack. */
2033	case VINF_PATCH_CONTINUE:
2034	return VINF_SUCCESS;
2035
2036	/*
2037	* Anything else is fatal.
2038	*/
2039	default:
2040	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
2041	return VERR_IPE_UNEXPECTED_STATUS;
2042	}
2043	}
2044	return VINF_SUCCESS;
2045	}
2046
2047
2048	/**
2049	* Handle a privileged instruction.
2050	*
2051	* @returns VBox status code suitable for EM.
2052	* @param pVM VM handle.
2053	* @param pVCpu VMCPU handle;
2054	*/
2055	int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
2056	{
2057	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
2058	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
2059
2060	Assert(!pCtx->eflags.Bits.u1VM);
2061
2062	if (PATMIsEnabled(pVM))
2063	{
2064	/*
2065	* Check if in patch code.
2066	*/
2067	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2068	{
2069	#ifdef LOG_ENABLED
2070	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2071	#endif
2072	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
2073	return VERR_EM_RAW_PATCH_CONFLICT;
2074	}
2075	if ( (pCtx->ss & X86_SEL_RPL) == 0
2076	&& !pCtx->eflags.Bits.u1VM
2077	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2078	{
2079	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2080	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
2081	if (RT_SUCCESS(rc))
2082	{
2083	#ifdef LOG_ENABLED
2084	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2085	#endif
2086	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched privileged instruction");
2087	return VINF_SUCCESS;
2088	}
2089	}
2090	}
2091
2092	#ifdef LOG_ENABLED
2093	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
2094	{
2095	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2096	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
2097	}
2098	#endif
2099
2100	/*
2101	* Instruction statistics and logging.
2102	*/
2103	DISCPUSTATE Cpu;
2104	int rc;
2105
2106	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
2107	if (RT_SUCCESS(rc))
2108	{
2109	#ifdef VBOX_WITH_STATISTICS
2110	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
2111	switch (Cpu.pCurInstr->opcode)
2112	{
2113	case OP_INVLPG:
2114	STAM_COUNTER_INC(&pStats->StatInvlpg);
2115	break;
2116	case OP_IRET:
2117	STAM_COUNTER_INC(&pStats->StatIret);
2118	break;
2119	case OP_CLI:
2120	STAM_COUNTER_INC(&pStats->StatCli);
2121	emR3RecordCli(pVM, pVCpu, pCtx->rip);
2122	break;
2123	case OP_STI:
2124	STAM_COUNTER_INC(&pStats->StatSti);
2125	break;
2126	case OP_INSB:
2127	case OP_INSWD:
2128	case OP_IN:
2129	case OP_OUTSB:
2130	case OP_OUTSWD:
2131	case OP_OUT:
2132	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
2133	break;
2134
2135	case OP_MOV_CR:
2136	if (Cpu.param1.flags & USE_REG_GEN32)
2137	{
2138	//read
2139	Assert(Cpu.param2.flags & USE_REG_CR);
2140	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
2141	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
2142	}
2143	else
2144	{
2145	//write
2146	Assert(Cpu.param1.flags & USE_REG_CR);
2147	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
2148	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
2149	}
2150	break;
2151
2152	case OP_MOV_DR:
2153	STAM_COUNTER_INC(&pStats->StatMovDRx);
2154	break;
2155	case OP_LLDT:
2156	STAM_COUNTER_INC(&pStats->StatMovLldt);
2157	break;
2158	case OP_LIDT:
2159	STAM_COUNTER_INC(&pStats->StatMovLidt);
2160	break;
2161	case OP_LGDT:
2162	STAM_COUNTER_INC(&pStats->StatMovLgdt);
2163	break;
2164	case OP_SYSENTER:
2165	STAM_COUNTER_INC(&pStats->StatSysEnter);
2166	break;
2167	case OP_SYSEXIT:
2168	STAM_COUNTER_INC(&pStats->StatSysExit);
2169	break;
2170	case OP_SYSCALL:
2171	STAM_COUNTER_INC(&pStats->StatSysCall);
2172	break;
2173	case OP_SYSRET:
2174	STAM_COUNTER_INC(&pStats->StatSysRet);
2175	break;
2176	case OP_HLT:
2177	STAM_COUNTER_INC(&pStats->StatHlt);
2178	break;
2179	default:
2180	STAM_COUNTER_INC(&pStats->StatMisc);
2181	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
2182	break;
2183	}
2184	#endif /* VBOX_WITH_STATISTICS */
2185	if ( (pCtx->ss & X86_SEL_RPL) == 0
2186	&& !pCtx->eflags.Bits.u1VM
2187	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
2188	{
2189	uint32_t size;
2190
2191	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
2192	switch (Cpu.pCurInstr->opcode)
2193	{
2194	case OP_CLI:
2195	pCtx->eflags.u32 &= ~X86_EFL_IF;
2196	Assert(Cpu.opsize == 1);
2197	pCtx->rip += Cpu.opsize;
2198	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2199	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
2200
2201	case OP_STI:
2202	pCtx->eflags.u32 \|= X86_EFL_IF;
2203	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.opsize);
2204	Assert(Cpu.opsize == 1);
2205	pCtx->rip += Cpu.opsize;
2206	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2207	return VINF_SUCCESS;
2208
2209	case OP_HLT:
2210	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
2211	{
2212	PATMTRANSSTATE enmState;
2213	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
2214
2215	if (enmState == PATMTRANS_OVERWRITTEN)
2216	{
2217	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2218	Assert(rc == VERR_PATCH_DISABLED);
2219	/* Conflict detected, patch disabled */
2220	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
2221
2222	enmState = PATMTRANS_SAFE;
2223	}
2224
2225	/* The translation had better be successful. Otherwise we can't recover. */
2226	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
2227	if (enmState != PATMTRANS_OVERWRITTEN)
2228	pCtx->eip = pOrgInstrGC;
2229	}
2230	/* no break; we could just return VINF_EM_HALT here */
2231
2232	case OP_MOV_CR:
2233	case OP_MOV_DR:
2234	#ifdef LOG_ENABLED
2235	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2236	{
2237	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2238	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
2239	}
2240	#endif
2241
2242	rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2243	if (RT_SUCCESS(rc))
2244	{
2245	pCtx->rip += Cpu.opsize;
2246	#ifdef EM_NOTIFY_HWACCM
2247	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
2248	HWACCMR3NotifyEmulated(pVCpu);
2249	#endif
2250	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2251
2252	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2253	&& Cpu.param1.flags == USE_REG_CR /* write */
2254	)
2255	{
2256	/* Deal with CR0 updates inside patch code that force
2257	* us to go to the recompiler.
2258	*/
2259	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
2260	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
2261	{
2262	PATMTRANSSTATE enmState;
2263	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
2264
2265	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
2266	if (enmState == PATMTRANS_OVERWRITTEN)
2267	{
2268	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2269	Assert(rc == VERR_PATCH_DISABLED);
2270	/* Conflict detected, patch disabled */
2271	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
2272	enmState = PATMTRANS_SAFE;
2273	}
2274	/* The translation had better be successful. Otherwise we can't recover. */
2275	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
2276	if (enmState != PATMTRANS_OVERWRITTEN)
2277	pCtx->rip = pOrgInstrGC;
2278	}
2279
2280	/* Reschedule is necessary as the execution/paging mode might have changed. */
2281	return VINF_EM_RESCHEDULE;
2282	}
2283	return rc; /* can return VINF_EM_HALT as well. */
2284	}
2285	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
2286	break; /* fall back to the recompiler */
2287	}
2288	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
2289	}
2290	}
2291
2292	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2293	return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
2294
2295	return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV");
2296	}
2297
2298
2299	/**
2300	* Update the forced rawmode execution modifier.
2301	*
2302	* This function is called when we're returning from the raw-mode loop(s). If we're
2303	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2304	* if not in patch code, the flag will be cleared.
2305	*
2306	* We should never interrupt patch code while it's being executed. Cli patches can
2307	* contain big code blocks, but they are always executed with IF=0. Other patches
2308	* replace single instructions and should be atomic.
2309	*
2310	* @returns Updated rc.
2311	*
2312	* @param pVM The VM handle.
2313	* @param pVCpu The VMCPU handle.
2314	* @param pCtx The guest CPU context.
2315	* @param rc The result code.
2316	*/
2317	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
2318	{
2319	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2320	{
2321	/* ignore reschedule attempts. */
2322	switch (rc)
2323	{
2324	case VINF_EM_RESCHEDULE:
2325	case VINF_EM_RESCHEDULE_REM:
2326	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
2327	rc = VINF_SUCCESS;
2328	break;
2329	}
2330	pVCpu->em.s.fForceRAW = true;
2331	}
2332	else
2333	pVCpu->em.s.fForceRAW = false;
2334	return rc;
2335	}
2336
2337
2338	/**
2339	* Process a subset of the raw-mode return code.
2340	*
2341	* Since we have to share this with raw-mode single stepping, this inline
2342	* function has been created to avoid code duplication.
2343	*
2344	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2345	* @returns VBox status code to return to the EM main loop.
2346	*
2347	* @param pVM The VM handle
2348	* @param pVCpu The VMCPU handle
2349	* @param rc The return code.
2350	* @param pCtx The guest cpu context.
2351	*/
2352	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
2353	{
2354	switch (rc)
2355	{
2356	/*
2357	* Common & simple ones.
2358	*/
2359	case VINF_SUCCESS:
2360	break;
2361	case VINF_EM_RESCHEDULE_RAW:
2362	case VINF_EM_RESCHEDULE_HWACC:
2363	case VINF_EM_RAW_INTERRUPT:
2364	case VINF_EM_RAW_TO_R3:
2365	case VINF_EM_RAW_TIMER_PENDING:
2366	case VINF_EM_PENDING_REQUEST:
2367	rc = VINF_SUCCESS;
2368	break;
2369
2370	/*
2371	* Privileged instruction.
2372	*/
2373	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2374	case VINF_PATM_PATCH_TRAP_GP:
2375	rc = emR3RawPrivileged(pVM, pVCpu);
2376	break;
2377
2378	/*
2379	* Got a trap which needs dispatching.
2380	*/
2381	case VINF_EM_RAW_GUEST_TRAP:
2382	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2383	{
2384	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
2385	rc = VERR_EM_RAW_PATCH_CONFLICT;
2386	break;
2387	}
2388	rc = emR3RawGuestTrap(pVM, pVCpu);
2389	break;
2390
2391	/*
2392	* Trap in patch code.
2393	*/
2394	case VINF_PATM_PATCH_TRAP_PF:
2395	case VINF_PATM_PATCH_INT3:
2396	rc = emR3PatchTrap(pVM, pVCpu, pCtx, rc);
2397	break;
2398
2399	case VINF_PATM_DUPLICATE_FUNCTION:
2400	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2401	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2402	AssertRC(rc);
2403	rc = VINF_SUCCESS;
2404	break;
2405
2406	case VINF_PATM_CHECK_PATCH_PAGE:
2407	rc = PATMR3HandleMonitoredPage(pVM);
2408	AssertRC(rc);
2409	rc = VINF_SUCCESS;
2410	break;
2411
2412	/*
2413	* Patch manager.
2414	*/
2415	case VERR_EM_RAW_PATCH_CONFLICT:
2416	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
2417	break;
2418
2419	#ifdef VBOX_WITH_VMI
2420	/*
2421	* PARAV function.
2422	*/
2423	case VINF_EM_RESCHEDULE_PARAV:
2424	rc = PARAVCallFunction(pVM);
2425	break;
2426	#endif
2427
2428	/*
2429	* Memory mapped I/O access - attempt to patch the instruction
2430	*/
2431	case VINF_PATM_HC_MMIO_PATCH_READ:
2432	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2433	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2434	if (RT_FAILURE(rc))
2435	rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
2436	break;
2437
2438	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2439	AssertFailed(); /* not yet implemented. */
2440	rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
2441	break;
2442
2443	/*
2444	* Conflict or out of page tables.
2445	*
2446	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2447	* do here is to execute the pending forced actions.
2448	*/
2449	case VINF_PGM_SYNC_CR3:
2450	AssertMsg(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
2451	("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
2452	rc = VINF_SUCCESS;
2453	break;
2454
2455	/*
2456	* Paging mode change.
2457	*/
2458	case VINF_PGM_CHANGE_MODE:
2459	rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2460	if (rc == VINF_SUCCESS)
2461	rc = VINF_EM_RESCHEDULE;
2462	AssertMsg(RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
2463	break;
2464
2465	/*
2466	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2467	*/
2468	case VINF_CSAM_PENDING_ACTION:
2469	rc = VINF_SUCCESS;
2470	break;
2471
2472	/*
2473	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2474	*/
2475	case VINF_EM_RAW_INTERRUPT_PENDING:
2476	case VINF_EM_RAW_RING_SWITCH_INT:
2477	Assert(TRPMHasTrap(pVCpu));
2478	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2479
2480	if (TRPMHasTrap(pVCpu))
2481	{
2482	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2483	uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
2484	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2485	{
2486	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2487	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2488	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2489	}
2490	}
2491	rc = VINF_EM_RESCHEDULE_REM;
2492	break;
2493
2494	/*
2495	* Other ring switch types.
2496	*/
2497	case VINF_EM_RAW_RING_SWITCH:
2498	rc = emR3RawRingSwitch(pVM, pVCpu);
2499	break;
2500
2501	/*
2502	* REMGCNotifyInvalidatePage() failed because of overflow.
2503	*/
2504	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2505	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2506	EMR3RemLock(pVM);
2507	REMR3ReplayInvalidatedPages(pVM, pVCpu);
2508	EMR3RemUnlock(pVM);
2509	rc = VINF_SUCCESS;
2510	break;
2511
2512	/*
2513	* I/O Port access - emulate the instruction.
2514	*/
2515	case VINF_IOM_HC_IOPORT_READ:
2516	case VINF_IOM_HC_IOPORT_WRITE:
2517	rc = emR3RawExecuteIOInstruction(pVM, pVCpu);
2518	break;
2519
2520	/*
2521	* Memory mapped I/O access - emulate the instruction.
2522	*/
2523	case VINF_IOM_HC_MMIO_READ:
2524	case VINF_IOM_HC_MMIO_WRITE:
2525	case VINF_IOM_HC_MMIO_READ_WRITE:
2526	rc = emR3RawExecuteInstruction(pVM, pVCpu, "MMIO");
2527	break;
2528
2529	/*
2530	* (MM)IO intensive code block detected; fall back to the recompiler for better performance
2531	*/
2532	case VINF_EM_RAW_EMULATE_IO_BLOCK:
2533	rc = HWACCMR3EmulateIoBlock(pVM, pCtx);
2534	break;
2535
2536	/*
2537	* Execute instruction.
2538	*/
2539	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2540	rc = emR3RawExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
2541	break;
2542	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2543	rc = emR3RawExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
2544	break;
2545	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2546	rc = emR3RawExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
2547	break;
2548	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2549	rc = emR3RawExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
2550	break;
2551	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2552	rc = emR3RawExecuteInstruction(pVM, pVCpu, "PD FAULT: ");
2553	break;
2554
2555	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2556	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2557	rc = emR3RawPrivileged(pVM, pVCpu);
2558	break;
2559
2560	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2561	rc = emR3RawExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2562	break;
2563
2564	case VINF_EM_RAW_EMULATE_INSTR:
2565	case VINF_PATCH_EMULATE_INSTR:
2566	rc = emR3RawExecuteInstruction(pVM, pVCpu, "EMUL: ");
2567	break;
2568
2569	/*
2570	* Stale selector and iret traps => REM.
2571	*/
2572	case VINF_EM_RAW_STALE_SELECTOR:
2573	case VINF_EM_RAW_IRET_TRAP:
2574	/* We will not go to the recompiler if EIP points to patch code. */
2575	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2576	{
2577	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2578	}
2579	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
2580	rc = VINF_EM_RESCHEDULE_REM;
2581	break;
2582
2583	/*
2584	* Up a level.
2585	*/
2586	case VINF_EM_TERMINATE:
2587	case VINF_EM_OFF:
2588	case VINF_EM_RESET:
2589	case VINF_EM_SUSPEND:
2590	case VINF_EM_HALT:
2591	case VINF_EM_RESUME:
2592	case VINF_EM_NO_MEMORY:
2593	case VINF_EM_RESCHEDULE:
2594	case VINF_EM_RESCHEDULE_REM:
2595	case VINF_EM_WAIT_SIPI:
2596	break;
2597
2598	/*
2599	* Up a level and invoke the debugger.
2600	*/
2601	case VINF_EM_DBG_STEPPED:
2602	case VINF_EM_DBG_BREAKPOINT:
2603	case VINF_EM_DBG_STEP:
2604	case VINF_EM_DBG_HYPER_BREAKPOINT:
2605	case VINF_EM_DBG_HYPER_STEPPED:
2606	case VINF_EM_DBG_HYPER_ASSERTION:
2607	case VINF_EM_DBG_STOP:
2608	break;
2609
2610	/*
2611	* Up a level, dump and debug.
2612	*/
2613	case VERR_TRPM_DONT_PANIC:
2614	case VERR_TRPM_PANIC:
2615	case VERR_VMM_RING0_ASSERTION:
2616	break;
2617
2618	/*
2619	* Up a level, after HwAccM have done some release logging.
2620	*/
2621	case VERR_VMX_INVALID_VMCS_FIELD:
2622	case VERR_VMX_INVALID_VMCS_PTR:
2623	case VERR_VMX_INVALID_VMXON_PTR:
2624	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2625	case VERR_VMX_UNEXPECTED_EXCEPTION:
2626	case VERR_VMX_UNEXPECTED_EXIT_CODE:
2627	case VERR_VMX_INVALID_GUEST_STATE:
2628	case VERR_VMX_UNABLE_TO_START_VM:
2629	case VERR_VMX_UNABLE_TO_RESUME_VM:
2630	HWACCMR3CheckError(pVM, rc);
2631	break;
2632	/*
2633	* Anything which is not known to us means an internal error
2634	* and the termination of the VM!
2635	*/
2636	default:
2637	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
2638	break;
2639	}
2640	return rc;
2641	}
2642
2643
2644	/**
2645	* Check for pending raw actions
2646	*
2647	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
2648	* EM statuses.
2649	* @param pVM The VM to operate on.
2650	* @param pVCpu The VMCPU handle.
2651	*/
2652	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
2653	{
2654	return emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
2655	}
2656
2657
2658	/**
2659	* Process raw-mode specific forced actions.
2660	*
2661	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2662	*
2663	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
2664	* EM statuses.
2665	* @param pVM The VM handle.
2666	* @param pVCpu The VMCPU handle.
2667	* @param pCtx The guest CPUM register context.
2668	*/
2669	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2670	{
2671	/*
2672	* Note that the order is vitally important!
2673	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2674	*/
2675
2676
2677	/*
2678	* Sync selector tables.
2679	*/
2680	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
2681	{
2682	int rc = SELMR3UpdateFromCPUM(pVM, pVCpu);
2683	if (RT_FAILURE(rc))
2684	return rc;
2685	}
2686
2687	/*
2688	* Sync IDT.
2689	*
2690	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
2691	* and PGMShwModifyPage, so we're in for trouble if for instance a
2692	* PGMSyncCR3+pgmPoolClearAll is pending.
2693	*/
2694	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
2695	{
2696	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
2697	&& EMIsRawRing0Enabled(pVM)
2698	&& CSAMIsEnabled(pVM))
2699	{
2700	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2701	if (RT_FAILURE(rc))
2702	return rc;
2703	}
2704
2705	int rc = TRPMR3SyncIDT(pVM, pVCpu);
2706	if (RT_FAILURE(rc))
2707	return rc;
2708	}
2709
2710	/*
2711	* Sync TSS.
2712	*/
2713	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
2714	{
2715	int rc = SELMR3SyncTSS(pVM, pVCpu);
2716	if (RT_FAILURE(rc))
2717	return rc;
2718	}
2719
2720	/*
2721	* Sync page directory.
2722	*/
2723	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2724	{
2725	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2726	if (RT_FAILURE(rc))
2727	return rc;
2728
2729	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
2730
2731	/* Prefetch pages for EIP and ESP. */
2732	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2733	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2734	if (rc == VINF_SUCCESS)
2735	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2736	if (rc != VINF_SUCCESS)
2737	{
2738	if (rc != VINF_PGM_SYNC_CR3)
2739	{
2740	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
2741	return rc;
2742	}
2743	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2744	if (RT_FAILURE(rc))
2745	return rc;
2746	}
2747	/** @todo maybe prefetch the supervisor stack page as well */
2748	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
2749	}
2750
2751	/*
2752	* Allocate handy pages (just in case the above actions have consumed some pages).
2753	*/
2754	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
2755	{
2756	int rc = PGMR3PhysAllocateHandyPages(pVM);
2757	if (RT_FAILURE(rc))
2758	return rc;
2759	}
2760
2761	/*
2762	* Check whether we're out of memory now.
2763	*
2764	* This may stem from some of the above actions or operations that has been executed
2765	* since we ran FFs. The allocate handy pages must for instance always be followed by
2766	* this check.
2767	*/
2768	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2769	return VINF_EM_NO_MEMORY;
2770
2771	return VINF_SUCCESS;
2772	}
2773
2774
2775	/**
2776	* Executes raw code.
2777	*
2778	* This function contains the raw-mode version of the inner
2779	* execution loop (the outer loop being in EMR3ExecuteVM()).
2780	*
2781	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2782	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2783	*
2784	* @param pVM VM handle.
2785	* @param pVCpu VMCPU handle.
2786	* @param pfFFDone Where to store an indicator telling whether or not
2787	* FFs were done before returning.
2788	*/
2789	static int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
2790	{
2791	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
2792
2793	int rc = VERR_INTERNAL_ERROR;
2794	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
2795	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2796	pVCpu->em.s.fForceRAW = false;
2797	*pfFFDone = false;
2798
2799
2800	/*
2801	*
2802	* Spin till we get a forced action or raw mode status code resulting in
2803	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2804	*
2805	*/
2806	for (;;)
2807	{
2808	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
2809
2810	/*
2811	* Check various preconditions.
2812	*/
2813	#ifdef VBOX_STRICT
2814	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
2815	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2816	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2817	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2818	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2819	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
2820	&& PGMMapHasConflicts(pVM))
2821	{
2822	PGMMapCheck(pVM);
2823	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2824	return VERR_INTERNAL_ERROR;
2825	}
2826	#endif /* VBOX_STRICT */
2827
2828	/*
2829	* Process high priority pre-execution raw-mode FFs.
2830	*/
2831	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
2832	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2833	{
2834	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
2835	if (rc != VINF_SUCCESS)
2836	break;
2837	}
2838
2839	/*
2840	* If we're going to execute ring-0 code, the guest state needs to
2841	* be modified a bit and some of the state components (IF, SS/CS RPL,
2842	* and perhaps EIP) needs to be stored with PATM.
2843	*/
2844	rc = CPUMRawEnter(pVCpu, NULL);
2845	if (rc != VINF_SUCCESS)
2846	{
2847	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
2848	break;
2849	}
2850
2851	/*
2852	* Scan code before executing it. Don't bother with user mode or V86 code
2853	*/
2854	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2855	&& !pCtx->eflags.Bits.u1VM
2856	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2857	{
2858	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
2859	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2860	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
2861	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
2862	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2863	{
2864	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
2865	if (rc != VINF_SUCCESS)
2866	{
2867	rc = CPUMRawLeave(pVCpu, NULL, rc);
2868	break;
2869	}
2870	}
2871	}
2872
2873	#ifdef LOG_ENABLED
2874	/*
2875	* Log important stuff before entering GC.
2876	*/
2877	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2878	if (pCtx->eflags.Bits.u1VM)
2879	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2880	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2881	{
2882	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2883	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2884	}
2885	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2886	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2887	#endif /* LOG_ENABLED */
2888
2889
2890
2891	/*
2892	* Execute the code.
2893	*/
2894	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
2895	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
2896	rc = VMMR3RawRunGC(pVM, pVCpu);
2897	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
2898	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
2899
2900	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2901	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
2902
2903
2904
2905	/*
2906	* Restore the real CPU state and deal with high priority post
2907	* execution FFs before doing anything else.
2908	*/
2909	rc = CPUMRawLeave(pVCpu, NULL, rc);
2910	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
2911	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
2912	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
2913	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
2914
2915	#ifdef VBOX_STRICT
2916	/*
2917	* Assert TSS consistency & rc vs patch code.
2918	*/
2919	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2920	&& EMIsRawRing0Enabled(pVM))
2921	SELMR3CheckTSS(pVM);
2922	switch (rc)
2923	{
2924	case VINF_SUCCESS:
2925	case VINF_EM_RAW_INTERRUPT:
2926	case VINF_PATM_PATCH_TRAP_PF:
2927	case VINF_PATM_PATCH_TRAP_GP:
2928	case VINF_PATM_PATCH_INT3:
2929	case VINF_PATM_CHECK_PATCH_PAGE:
2930	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2931	case VINF_EM_RAW_GUEST_TRAP:
2932	case VINF_EM_RESCHEDULE_RAW:
2933	break;
2934
2935	default:
2936	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2937	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
2938	break;
2939	}
2940	/*
2941	* Let's go paranoid!
2942	*/
2943	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
2944	&& PGMMapHasConflicts(pVM))
2945	{
2946	PGMMapCheck(pVM);
2947	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
2948	return VERR_INTERNAL_ERROR;
2949	}
2950	#endif /* VBOX_STRICT */
2951
2952	/*
2953	* Process the returned status code.
2954	*/
2955	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2956	{
2957	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
2958	break;
2959	}
2960	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
2961	if (rc != VINF_SUCCESS)
2962	{
2963	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
2964	if (rc != VINF_SUCCESS)
2965	{
2966	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
2967	break;
2968	}
2969	}
2970
2971	/*
2972	* Check and execute forced actions.
2973	*/
2974	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2975	TMTimerPollVoid(pVM, pVCpu);
2976	#endif
2977	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
2978	if ( VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
2979	\|\| VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2980	{
2981	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2982
2983	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
2984	rc = emR3ForcedActions(pVM, pVCpu, rc);
2985	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
2986	if ( rc != VINF_SUCCESS
2987	&& rc != VINF_EM_RESCHEDULE_RAW)
2988	{
2989	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
2990	if (rc != VINF_SUCCESS)
2991	{
2992	*pfFFDone = true;
2993	break;
2994	}
2995	}
2996	}
2997	}
2998
2999	/*
3000	* Return to outer loop.
3001	*/
3002	#if defined(LOG_ENABLED) && defined(DEBUG)
3003	RTLogFlush(NULL);
3004	#endif
3005	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
3006	return rc;
3007	}
3008
3009
3010	/**
3011	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
3012	*
3013	* This function contains the raw-mode version of the inner
3014	* execution loop (the outer loop being in EMR3ExecuteVM()).
3015	*
3016	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
3017	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3018	*
3019	* @param pVM VM handle.
3020	* @param pVCpu VMCPU handle.
3021	* @param pfFFDone Where to store an indicator telling whether or not
3022	* FFs were done before returning.
3023	*/
3024	static int emR3HwAccExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
3025	{
3026	int rc = VERR_INTERNAL_ERROR;
3027	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
3028
3029	LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
3030	*pfFFDone = false;
3031
3032	STAM_COUNTER_INC(&pVCpu->em.s.StatHwAccExecuteEntry);
3033
3034	#ifdef EM_NOTIFY_HWACCM
3035	HWACCMR3NotifyScheduled(pVCpu);
3036	#endif
3037
3038	/*
3039	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
3040	*/
3041	for (;;)
3042	{
3043	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHwAccEntry, a);
3044
3045	/*
3046	* Process high priority pre-execution raw-mode FFs.
3047	*/
3048	VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
3049	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
3050	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
3051	{
3052	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
3053	if (rc != VINF_SUCCESS)
3054	break;
3055	}
3056
3057	#ifdef LOG_ENABLED
3058	/*
3059	* Log important stuff before entering GC.
3060	*/
3061	if (TRPMHasTrap(pVCpu))
3062	Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
3063
3064	uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
3065
3066	if (pVM->cCPUs == 1)
3067	{
3068	if (pCtx->eflags.Bits.u1VM)
3069	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
3070	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
3071	Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
3072	else
3073	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
3074	}
3075	else
3076	{
3077	if (pCtx->eflags.Bits.u1VM)
3078	Log(("HWV86-CPU%d: %08X IF=%d\n", pVCpu->idCpu, pCtx->eip, pCtx->eflags.Bits.u1IF));
3079	else if (CPUMIsGuestIn64BitCodeEx(pCtx))
3080	Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
3081	else
3082	Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
3083	}
3084	#endif /* LOG_ENABLED */
3085
3086	/*
3087	* Execute the code.
3088	*/
3089	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHwAccEntry, a);
3090	STAM_PROFILE_START(&pVCpu->em.s.StatHwAccExec, x);
3091	rc = VMMR3HwAccRunGC(pVM, pVCpu);
3092	STAM_PROFILE_STOP(&pVCpu->em.s.StatHwAccExec, x);
3093
3094	/*
3095	* Deal with high priority post execution FFs before doing anything else.
3096	*/
3097	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
3098	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
3099	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
3100	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
3101
3102	/*
3103	* Process the returned status code.
3104	*/
3105	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
3106	break;
3107
3108	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
3109	if (rc != VINF_SUCCESS)
3110	break;
3111
3112	/*
3113	* Check and execute forced actions.
3114	*/
3115	#ifdef VBOX_HIGH_RES_TIMERS_HACK
3116	TMTimerPollVoid(pVM, pVCpu);
3117	#endif
3118	if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK)
3119	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_MASK))
3120	{
3121	rc = emR3ForcedActions(pVM, pVCpu, rc);
3122	if ( rc != VINF_SUCCESS
3123	&& rc != VINF_EM_RESCHEDULE_HWACC)
3124	{
3125	*pfFFDone = true;
3126	break;
3127	}
3128	}
3129	}
3130
3131	/*
3132	* Return to outer loop.
3133	*/
3134	#if defined(LOG_ENABLED) && defined(DEBUG)
3135	RTLogFlush(NULL);
3136	#endif
3137	return rc;
3138	}
3139
3140
3141	/**
3142	* Decides whether to execute RAW, HWACC or REM.
3143	*
3144	* @returns new EM state
3145	* @param pVM The VM.
3146	* @param pVCpu The VMCPU handle.
3147	* @param pCtx The CPU context.
3148	*/
3149	static EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3150	{
3151	/*
3152	* When forcing raw-mode execution, things are simple.
3153	*/
3154	if (pVCpu->em.s.fForceRAW)
3155	return EMSTATE_RAW;
3156
3157	/*
3158	* We stay in the wait for SIPI state unless explicitly told otherwise.
3159	*/
3160	if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
3161	return EMSTATE_WAIT_SIPI;
3162
3163	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
3164	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
3165	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
3166
3167	X86EFLAGS EFlags = pCtx->eflags;
3168	if (HWACCMIsEnabled(pVM))
3169	{
3170	/* Hardware accelerated raw-mode:
3171	*
3172	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
3173	*/
3174	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
3175	return EMSTATE_HWACC;
3176
3177	/* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
3178	* off monitoring features essential for raw mode! */
3179	return EMSTATE_REM;
3180	}
3181
3182	/*
3183	* Standard raw-mode:
3184	*
3185	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
3186	* or 32 bits protected mode ring 0 code
3187	*
3188	* The tests are ordered by the likelyhood of being true during normal execution.
3189	*/
3190	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
3191	{
3192	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
3193	return EMSTATE_REM;
3194	}
3195
3196	#ifndef VBOX_RAW_V86
3197	if (EFlags.u32 & X86_EFL_VM) {
3198	Log2(("raw mode refused: VM_MASK\n"));
3199	return EMSTATE_REM;
3200	}
3201	#endif
3202
3203	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
3204	uint32_t u32CR0 = pCtx->cr0;
3205	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
3206	{
3207	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
3208	return EMSTATE_REM;
3209	}
3210
3211	if (pCtx->cr4 & X86_CR4_PAE)
3212	{
3213	uint32_t u32Dummy, u32Features;
3214
3215	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3216	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3217	return EMSTATE_REM;
3218	}
3219
3220	unsigned uSS = pCtx->ss;
3221	if ( pCtx->eflags.Bits.u1VM
3222	\|\| (uSS & X86_SEL_RPL) == 3)
3223	{
3224	if (!EMIsRawRing3Enabled(pVM))
3225	return EMSTATE_REM;
3226
3227	if (!(EFlags.u32 & X86_EFL_IF))
3228	{
3229	Log2(("raw mode refused: IF (RawR3)\n"));
3230	return EMSTATE_REM;
3231	}
3232
3233	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
3234	{
3235	Log2(("raw mode refused: CR0.WP + RawR0\n"));
3236	return EMSTATE_REM;
3237	}
3238	}
3239	else
3240	{
3241	if (!EMIsRawRing0Enabled(pVM))
3242	return EMSTATE_REM;
3243
3244	/* Only ring 0 supervisor code. */
3245	if ((uSS & X86_SEL_RPL) != 0)
3246	{
3247	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
3248	return EMSTATE_REM;
3249	}
3250
3251	// Let's start with pure 32 bits ring 0 code first
3252	/** @todo What's pure 32-bit mode? flat? */
3253	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
3254	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
3255	{
3256	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
3257	return EMSTATE_REM;
3258	}
3259
3260	/* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
3261	if (!(u32CR0 & X86_CR0_WP))
3262	{
3263	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
3264	return EMSTATE_REM;
3265	}
3266
3267	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
3268	{
3269	Log2(("raw r0 mode forced: patch code\n"));
3270	return EMSTATE_RAW;
3271	}
3272
3273	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
3274	if (!(EFlags.u32 & X86_EFL_IF))
3275	{
3276	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
3277	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
3278	return EMSTATE_REM;
3279	}
3280	#endif
3281
3282	/** @todo still necessary??? */
3283	if (EFlags.Bits.u2IOPL != 0)
3284	{
3285	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
3286	return EMSTATE_REM;
3287	}
3288	}
3289
3290	Assert(PGMPhysIsA20Enabled(pVCpu));
3291	return EMSTATE_RAW;
3292	}
3293
3294
3295	/**
3296	* Executes all high priority post execution force actions.
3297	*
3298	* @returns rc or a fatal status code.
3299	*
3300	* @param pVM VM handle.
3301	* @param pVCpu VMCPU handle.
3302	* @param rc The current rc.
3303	*/
3304	static int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
3305	{
3306	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
3307	PDMCritSectFF(pVCpu);
3308
3309	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
3310	CSAMR3DoPendingAction(pVM, pVCpu);
3311
3312	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3313	{
3314	if ( rc > VINF_EM_NO_MEMORY
3315	&& rc <= VINF_EM_LAST)
3316	rc = VINF_EM_NO_MEMORY;
3317	}
3318
3319	return rc;
3320	}
3321
3322
3323	/**
3324	* Executes all pending forced actions.
3325	*
3326	* Forced actions can cause execution delays and execution
3327	* rescheduling. The first we deal with using action priority, so
3328	* that for instance pending timers aren't scheduled and ran until
3329	* right before execution. The rescheduling we deal with using
3330	* return codes. The same goes for VM termination, only in that case
3331	* we exit everything.
3332	*
3333	* @returns VBox status code of equal or greater importance/severity than rc.
3334	* The most important ones are: VINF_EM_RESCHEDULE,
3335	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3336	*
3337	* @param pVM VM handle.
3338	* @param pVCpu VMCPU handle.
3339	* @param rc The current rc.
3340	*
3341	*/
3342	static int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
3343	{
3344	STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
3345	#ifdef VBOX_STRICT
3346	int rcIrq = VINF_SUCCESS;
3347	#endif
3348	int rc2;
3349	#define UPDATE_RC() \
3350	do { \
3351	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
3352	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
3353	break; \
3354	if (!rc \|\| rc2 < rc) \
3355	rc = rc2; \
3356	} while (0)
3357
3358	/*
3359	* Post execution chunk first.
3360	*/
3361	if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
3362	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
3363	{
3364	/*
3365	* Termination request.
3366	*/
3367	if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
3368	{
3369	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3370	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3371	return VINF_EM_TERMINATE;
3372	}
3373
3374	/*
3375	* Debugger Facility polling.
3376	*/
3377	if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
3378	{
3379	rc2 = DBGFR3VMMForcedAction(pVM);
3380	UPDATE_RC();
3381	}
3382
3383	/*
3384	* Postponed reset request.
3385	*/
3386	if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET_BIT))
3387	{
3388	rc2 = VMR3Reset(pVM);
3389	UPDATE_RC();
3390	}
3391
3392	/*
3393	* CSAM page scanning.
3394	*/
3395	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3396	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
3397	{
3398	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
3399
3400	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3401	Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
3402
3403	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3404	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
3405	}
3406
3407	/*
3408	* Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
3409	*/
3410	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3411	{
3412	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3413	UPDATE_RC();
3414	if (rc == VINF_EM_NO_MEMORY)
3415	return rc;
3416	}
3417
3418	/* check that we got them all */
3419	AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_PGM_NO_MEMORY));
3420	AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_CSAM_SCAN_PAGE);
3421	}
3422
3423	/*
3424	* Normal priority then.
3425	* (Executed in no particular order.)
3426	*/
3427	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
3428	{
3429	/*
3430	* PDM Queues are pending.
3431	*/
3432	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
3433	PDMR3QueueFlushAll(pVM);
3434
3435	/*
3436	* PDM DMA transfers are pending.
3437	*/
3438	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
3439	PDMR3DmaRun(pVM);
3440
3441	/*
3442	* Requests from other threads.
3443	*/
3444	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
3445	{
3446	rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY);
3447	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3448	{
3449	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
3450	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3451	return rc2;
3452	}
3453	UPDATE_RC();
3454	}
3455
3456	/* Replay the handler notification changes. */
3457	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
3458	{
3459	EMR3RemLock(pVM);
3460	REMR3ReplayHandlerNotifications(pVM);
3461	EMR3RemUnlock(pVM);
3462	}
3463
3464	/* check that we got them all */
3465	AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY));
3466	}
3467
3468	/*
3469	* Normal priority then. (per-VCPU)
3470	* (Executed in no particular order.)
3471	*/
3472	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3473	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
3474	{
3475	/*
3476	* Requests from other threads.
3477	*/
3478	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
3479	{
3480	rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu);
3481	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3482	{
3483	Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
3484	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3485	return rc2;
3486	}
3487	UPDATE_RC();
3488	}
3489
3490	/* check that we got them all */
3491	Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
3492	}
3493
3494	/*
3495	* High priority pre execution chunk last.
3496	* (Executed in ascending priority order.)
3497	*/
3498	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
3499	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
3500	{
3501	/*
3502	* Timers before interrupts.
3503	*/
3504	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
3505	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3506	TMR3TimerQueuesDo(pVM);
3507
3508	/*
3509	* The instruction following an emulated STI should always be executed!
3510	*/
3511	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
3512	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3513	{
3514	Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
3515	if (CPUMGetGuestEIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
3516	{
3517	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3518	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3519	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3520	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3521	*/
3522	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3523	}
3524	if (HWACCMR3IsActive(pVCpu))
3525	rc2 = VINF_EM_RESCHEDULE_HWACC;
3526	else
3527	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3528
3529	UPDATE_RC();
3530	}
3531
3532	/*
3533	* Interrupts.
3534	*/
3535	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
3536	&& !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
3537	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_HWACC)
3538	&& !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3539	&& PATMAreInterruptsEnabled(pVM)
3540	&& !HWACCMR3IsEventPending(pVM))
3541	{
3542	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC))
3543	{
3544	/* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3545	/** @todo this really isn't nice, should properly handle this */
3546	rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
3547	#ifdef VBOX_STRICT
3548	rcIrq = rc2;
3549	#endif
3550	UPDATE_RC();
3551	}
3552	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3553	else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
3554	{
3555	rc2 = VINF_EM_RESCHEDULE_REM;
3556	UPDATE_RC();
3557	}
3558	}
3559
3560	/*
3561	* Allocate handy pages.
3562	*/
3563	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
3564	{
3565	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3566	UPDATE_RC();
3567	}
3568
3569	/*
3570	* Debugger Facility request.
3571	*/
3572	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
3573	{
3574	rc2 = DBGFR3VMMForcedAction(pVM);
3575	UPDATE_RC();
3576	}
3577
3578	/*
3579	* Termination request.
3580	*/
3581	if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
3582	{
3583	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3584	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3585	return VINF_EM_TERMINATE;
3586	}
3587
3588	/*
3589	* Out of memory? Since most of our fellow high priority actions may cause us
3590	* to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
3591	* at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
3592	* than us since we can terminate without allocating more memory.
3593	*/
3594	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3595	{
3596	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3597	UPDATE_RC();
3598	if (rc == VINF_EM_NO_MEMORY)
3599	return rc;
3600	}
3601
3602	/*
3603	* If the virtual sync clock is still stopped, make TM restart it.
3604	*/
3605	if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
3606	TMR3VirtualSyncFF(pVM, pVCpu);
3607
3608	#ifdef DEBUG
3609	/*
3610	* Debug, pause the VM.
3611	*/
3612	if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
3613	{
3614	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3615	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3616	return VINF_EM_SUSPEND;
3617	}
3618	#endif
3619
3620	/* check that we got them all */
3621	AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY));
3622	AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_INHIBIT_INTERRUPTS));
3623	}
3624
3625	#undef UPDATE_RC
3626	Log2(("emR3ForcedActions: returns %Rrc\n", rc));
3627	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
3628	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3629	return rc;
3630	}
3631
3632	/**
3633	* Release the IOM lock if owned by the current VCPU
3634	*
3635	* @param pVM The VM to operate on.
3636	*/
3637	VMMR3DECL(void) EMR3ReleaseOwnedLocks(PVM pVM)
3638	{
3639	while (PDMCritSectIsOwner(&pVM->em.s.CritSectREM))
3640	PDMCritSectLeave(&pVM->em.s.CritSectREM);
3641	}
3642
3643
3644	/**
3645	* Execute VM.
3646	*
3647	* This function is the main loop of the VM. The emulation thread
3648	* calls this function when the VM has been successfully constructed
3649	* and we're ready for executing the VM.
3650	*
3651	* Returning from this function means that the VM is turned off or
3652	* suspended (state already saved) and deconstruction in next in line.
3653	*
3654	* All interaction from other thread are done using forced actions
3655	* and signaling of the wait object.
3656	*
3657	* @returns VBox status code, informational status codes may indicate failure.
3658	* @param pVM The VM to operate on.
3659	* @param pVCpu The VMCPU to operate on.
3660	*/
3661	VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
3662	{
3663	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3664	pVCpu->em.s.enmState, EMR3GetStateName(pVCpu->em.s.enmState), pVCpu->em.s.fForceRAW));
3665	VM_ASSERT_EMT(pVM);
3666	AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
3667	\|\| pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
3668	\|\| pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
3669	("%s\n", EMR3GetStateName(pVCpu->em.s.enmState)));
3670
3671	int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
3672	if (rc == 0)
3673	{
3674	/*
3675	* Start the virtual time.
3676	*/
3677	TMR3NotifyResume(pVM, pVCpu);
3678
3679	/*
3680	* The Outer Main Loop.
3681	*/
3682	bool fFFDone = false;
3683
3684	/* Reschedule right away to start in the right state. */
3685	rc = VINF_SUCCESS;
3686
3687	/* If resuming after a pause or a state load, restore the previous
3688	state or else we'll start executing code. Else, just reschedule. */
3689	if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
3690	&& ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
3691	\|\| pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
3692	pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
3693	else
3694	pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
3695
3696	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
3697	for (;;)
3698	{
3699	/*
3700	* Before we can schedule anything (we're here because
3701	* scheduling is required) we must service any pending
3702	* forced actions to avoid any pending action causing
3703	* immediate rescheduling upon entering an inner loop
3704	*
3705	* Do forced actions.
3706	*/
3707	if ( !fFFDone
3708	&& rc != VINF_EM_TERMINATE
3709	&& rc != VINF_EM_OFF
3710	&& ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
3711	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK)))
3712	{
3713	rc = emR3ForcedActions(pVM, pVCpu, rc);
3714	if ( ( rc == VINF_EM_RESCHEDULE_REM
3715	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3716	&& pVCpu->em.s.fForceRAW)
3717	rc = VINF_EM_RESCHEDULE_RAW;
3718	}
3719	else if (fFFDone)
3720	fFFDone = false;
3721
3722	/*
3723	* Now what to do?
3724	*/
3725	Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
3726	switch (rc)
3727	{
3728	/*
3729	* Keep doing what we're currently doing.
3730	*/
3731	case VINF_SUCCESS:
3732	break;
3733
3734	/*
3735	* Reschedule - to raw-mode execution.
3736	*/
3737	case VINF_EM_RESCHEDULE_RAW:
3738	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVCpu->em.s.enmState, EMSTATE_RAW));
3739	pVCpu->em.s.enmState = EMSTATE_RAW;
3740	break;
3741
3742	/*
3743	* Reschedule - to hardware accelerated raw-mode execution.
3744	*/
3745	case VINF_EM_RESCHEDULE_HWACC:
3746	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVCpu->em.s.enmState, EMSTATE_HWACC));
3747	Assert(!pVCpu->em.s.fForceRAW);
3748	pVCpu->em.s.enmState = EMSTATE_HWACC;
3749	break;
3750
3751	/*
3752	* Reschedule - to recompiled execution.
3753	*/
3754	case VINF_EM_RESCHEDULE_REM:
3755	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVCpu->em.s.enmState, EMSTATE_REM));
3756	pVCpu->em.s.enmState = EMSTATE_REM;
3757	break;
3758
3759	#ifdef VBOX_WITH_VMI
3760	/*
3761	* Reschedule - parav call.
3762	*/
3763	case VINF_EM_RESCHEDULE_PARAV:
3764	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVCpu->em.s.enmState, EMSTATE_PARAV));
3765	pVCpu->em.s.enmState = EMSTATE_PARAV;
3766	break;
3767	#endif
3768
3769	/*
3770	* Resume.
3771	*/
3772	case VINF_EM_RESUME:
3773	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVCpu->em.s.enmState));
3774	/* Don't reschedule in the halted or wait for SIPI case. */
3775	if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
3776	\|\| pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
3777	break;
3778	/* fall through and get scheduled. */
3779
3780	/*
3781	* Reschedule.
3782	*/
3783	case VINF_EM_RESCHEDULE:
3784	{
3785	EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
3786	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3787	pVCpu->em.s.enmState = enmState;
3788	break;
3789	}
3790
3791	/*
3792	* Halted.
3793	*/
3794	case VINF_EM_HALT:
3795	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_HALTED));
3796	pVCpu->em.s.enmState = EMSTATE_HALTED;
3797	break;
3798
3799	/*
3800	* Switch to the wait for SIPI state (application processor only)
3801	*/
3802	case VINF_EM_WAIT_SIPI:
3803	Assert(pVCpu->idCpu != 0);
3804	Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_WAIT_SIPI));
3805	pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
3806	break;
3807
3808
3809	/*
3810	* Suspend.
3811	*/
3812	case VINF_EM_SUSPEND:
3813	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
3814	pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
3815	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
3816	break;
3817
3818	/*
3819	* Reset.
3820	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3821	*/
3822	case VINF_EM_RESET:
3823	{
3824	if (pVCpu->idCpu == 0)
3825	{
3826	EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
3827	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3828	pVCpu->em.s.enmState = enmState;
3829	}
3830	else
3831	{
3832	/* All other VCPUs go into the wait for SIPI state. */
3833	pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
3834	}
3835	break;
3836	}
3837
3838	/*
3839	* Power Off.
3840	*/
3841	case VINF_EM_OFF:
3842	pVCpu->em.s.enmState = EMSTATE_TERMINATING;
3843	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
3844	TMR3NotifySuspend(pVM, pVCpu);
3845	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3846	return rc;
3847
3848	/*
3849	* Terminate the VM.
3850	*/
3851	case VINF_EM_TERMINATE:
3852	pVCpu->em.s.enmState = EMSTATE_TERMINATING;
3853	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
3854	TMR3NotifySuspend(pVM, pVCpu);
3855	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3856	return rc;
3857
3858
3859	/*
3860	* Out of memory, suspend the VM and stuff.
3861	*/
3862	case VINF_EM_NO_MEMORY:
3863	Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
3864	pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
3865	TMR3NotifySuspend(pVM, pVCpu);
3866	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3867
3868	rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
3869	N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
3870	if (rc != VINF_EM_SUSPEND)
3871	{
3872	if (RT_SUCCESS_NP(rc))
3873	{
3874	AssertLogRelMsgFailed(("%Rrc\n", rc));
3875	rc = VERR_EM_INTERNAL_ERROR;
3876	}
3877	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3878	}
3879	return rc;
3880
3881	/*
3882	* Guest debug events.
3883	*/
3884	case VINF_EM_DBG_STEPPED:
3885	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3886	case VINF_EM_DBG_STOP:
3887	case VINF_EM_DBG_BREAKPOINT:
3888	case VINF_EM_DBG_STEP:
3889	if (pVCpu->em.s.enmState == EMSTATE_RAW)
3890	{
3891	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3892	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3893	}
3894	else
3895	{
3896	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3897	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3898	}
3899	break;
3900
3901	/*
3902	* Hypervisor debug events.
3903	*/
3904	case VINF_EM_DBG_HYPER_STEPPED:
3905	case VINF_EM_DBG_HYPER_BREAKPOINT:
3906	case VINF_EM_DBG_HYPER_ASSERTION:
3907	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_HYPER));
3908	pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
3909	break;
3910
3911	/*
3912	* Guru mediations.
3913	*/
3914	case VERR_VMM_RING0_ASSERTION:
3915	Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
3916	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3917	break;
3918
3919	/*
3920	* Any error code showing up here other than the ones we
3921	* know and process above are considered to be FATAL.
3922	*
3923	* Unknown warnings and informational status codes are also
3924	* included in this.
3925	*/
3926	default:
3927	if (RT_SUCCESS_NP(rc))
3928	{
3929	AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
3930	rc = VERR_EM_INTERNAL_ERROR;
3931	}
3932	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
3933	Log(("EMR3ExecuteVM returns %d\n", rc));
3934	break;
3935	}
3936
3937	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
3938	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
3939
3940	/*
3941	* Act on the state.
3942	*/
3943	switch (pVCpu->em.s.enmState)
3944	{
3945	/*
3946	* Execute raw.
3947	*/
3948	case EMSTATE_RAW:
3949	rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
3950	break;
3951
3952	/*
3953	* Execute hardware accelerated raw.
3954	*/
3955	case EMSTATE_HWACC:
3956	rc = emR3HwAccExecute(pVM, pVCpu, &fFFDone);
3957	break;
3958
3959	/*
3960	* Execute recompiled.
3961	*/
3962	case EMSTATE_REM:
3963	rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
3964	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
3965	break;
3966
3967	#ifdef VBOX_WITH_VMI
3968	/*
3969	* Execute PARAV function.
3970	*/
3971	case EMSTATE_PARAV:
3972	rc = PARAVCallFunction(pVM);
3973	pVCpu->em.s.enmState = EMSTATE_REM;
3974	break;
3975	#endif
3976
3977	/*
3978	* Application processor execution halted until SIPI.
3979	*/
3980	case EMSTATE_WAIT_SIPI:
3981	/* no break */
3982	/*
3983	* hlt - execution halted until interrupt.
3984	*/
3985	case EMSTATE_HALTED:
3986	{
3987	STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
3988	rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
3989	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
3990	break;
3991	}
3992
3993	/*
3994	* Suspended - return to VM.cpp.
3995	*/
3996	case EMSTATE_SUSPENDED:
3997	TMR3NotifySuspend(pVM, pVCpu);
3998	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
3999	return VINF_EM_SUSPEND;
4000
4001	/*
4002	* Debugging in the guest.
4003	*/
4004	case EMSTATE_DEBUG_GUEST_REM:
4005	case EMSTATE_DEBUG_GUEST_RAW:
4006	TMR3NotifySuspend(pVM, pVCpu);
4007	rc = emR3Debug(pVM, pVCpu, rc);
4008	TMR3NotifyResume(pVM, pVCpu);
4009	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
4010	break;
4011
4012	/*
4013	* Debugging in the hypervisor.
4014	*/
4015	case EMSTATE_DEBUG_HYPER:
4016	{
4017	TMR3NotifySuspend(pVM, pVCpu);
4018	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
4019
4020	rc = emR3Debug(pVM, pVCpu, rc);
4021	Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
4022	if (rc != VINF_SUCCESS)
4023	{
4024	/* switch to guru meditation mode */
4025	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
4026	VMMR3FatalDump(pVM, pVCpu, rc);
4027	return rc;
4028	}
4029
4030	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
4031	TMR3NotifyResume(pVM, pVCpu);
4032	break;
4033	}
4034
4035	/*
4036	* Guru meditation takes place in the debugger.
4037	*/
4038	case EMSTATE_GURU_MEDITATION:
4039	{
4040	TMR3NotifySuspend(pVM, pVCpu);
4041	VMMR3FatalDump(pVM, pVCpu, rc);
4042	emR3Debug(pVM, pVCpu, rc);
4043	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
4044	return rc;
4045	}
4046
4047	/*
4048	* The states we don't expect here.
4049	*/
4050	case EMSTATE_NONE:
4051	case EMSTATE_TERMINATING:
4052	default:
4053	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
4054	pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
4055	TMR3NotifySuspend(pVM, pVCpu);
4056	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
4057	return VERR_EM_INTERNAL_ERROR;
4058	}
4059	} /* The Outer Main Loop */
4060	}
4061	else
4062	{
4063	/*
4064	* Fatal error.
4065	*/
4066	LogFlow(("EMR3ExecuteVM: returns %Rrc (longjmp / fatal error)\n", rc));
4067	TMR3NotifySuspend(pVM, pVCpu);
4068	VMMR3FatalDump(pVM, pVCpu, rc);
4069	emR3Debug(pVM, pVCpu, rc);
4070	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
4071	/** @todo change the VM state! */
4072	return rc;
4073	}
4074
4075	/* (won't ever get here). */
4076	AssertFailed();
4077	}
4078

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 20141

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