EM.cpp@ 2132

Last change on this file since 2132 was 2124, checked in by vboxsync, 18 years ago
TRPM changes to assert and report trap/interrupt types accurately.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 150.1 KB

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1	/* $Id: EM.cpp 2124 2007-04-17 12:25:17Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor/Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_em EM - The Execution Monitor/Manager
24	*
25	* The Execution Monitor/Manager is responsible for running the VM, scheduling
26	* the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27	* the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28	* the VM.
29	*
30	*/
31
32	/*******************************************************************************
33	* Header Files *
34	*******************************************************************************/
35	#define LOG_GROUP LOG_GROUP_EM
36	#include <VBox/em.h>
37	#include <VBox/vmm.h>
38	#include <VBox/patm.h>
39	#include <VBox/csam.h>
40	#include <VBox/selm.h>
41	#include <VBox/trpm.h>
42	#include <VBox/iom.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/pgm.h>
45	#include <VBox/rem.h>
46	#include <VBox/tm.h>
47	#include <VBox/mm.h>
48	#include <VBox/pdm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/patm.h>
51	#include "EMInternal.h"
52	#include <VBox/vm.h>
53	#include <VBox/cpumdis.h>
54	#include <VBox/dis.h>
55	#include <VBox/disopcode.h>
56	#include <VBox/dbgf.h>
57
58	#include <VBox/log.h>
59	#include <iprt/thread.h>
60	#include <iprt/assert.h>
61	#include <iprt/asm.h>
62	#include <iprt/semaphore.h>
63	#include <iprt/string.h>
64	#include <iprt/avl.h>
65	#include <iprt/stream.h>
66	#include <VBox/param.h>
67	#include <VBox/err.h>
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
74	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
75	static int emR3Debug(PVM pVM, int rc);
76	static int emR3RemStep(PVM pVM);
77	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
78	static int emR3RawResumeHyper(PVM pVM);
79	static int emR3RawStep(PVM pVM);
80	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
81	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
82	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
83	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
84	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
85	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
86	static int emR3ForcedActions(PVM pVM, int rc);
87	static int emR3RawGuestTrap(PVM pVM);
88
89
90	/**
91	* Initializes the EM.
92	*
93	* @returns VBox status code.
94	* @param pVM The VM to operate on.
95	*/
96	EMR3DECL(int) EMR3Init(PVM pVM)
97	{
98	LogFlow(("EMR3Init\n"));
99	/*
100	* Assert alignment and sizes.
101	*/
102	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
103	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
104	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
105	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
106
107	/*
108	* Init the structure.
109	*/
110	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
111	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
112	if (VBOX_FAILURE(rc))
113	pVM->fRawR3Enabled = true;
114	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
115	if (VBOX_FAILURE(rc))
116	pVM->fRawR0Enabled = true;
117	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
118	pVM->em.s.enmState = EMSTATE_NONE;
119	pVM->em.s.fForceRAW = false;
120
121	rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
122	AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
123	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
124	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
125
126	/*
127	* Saved state.
128	*/
129	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
130	NULL, emR3Save, NULL,
131	NULL, emR3Load, NULL);
132	if (VBOX_FAILURE(rc))
133	return rc;
134
135	/*
136	* Statistics.
137	*/
138	#ifdef VBOX_WITH_STATISTICS
139	PEMSTATS pStats;
140	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
141	if (VBOX_FAILURE(rc))
142	return rc;
143	pVM->em.s.pStatsHC = pStats;
144	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
145
146	STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
147	STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
148
149	STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
150	STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
151
152	STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
153	STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
154	STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
155	STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
156	STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
157	STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
158	STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
159	STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
160	STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
161	STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
162	STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
163	STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
164	STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
165	STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
196	STAM_REG_USED(pVM, &pStats->StatGCBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
197	STAM_REG_USED(pVM, &pStats->StatHCBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatGCBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatHCBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatGCBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatHCBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatGCCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatHCCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
204
205	STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
206	STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
207
208	STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
237	STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
238	STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
239	STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
246
247	STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
248	STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
249	STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatGCFailedBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatHCFailedBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
261	STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
262	STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
263	STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
264	STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
265	STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
266	STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
267	STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
268	STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
269	STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
270	STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
271
272	STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
273	STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
274	STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
275	STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
276
277	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
278	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
279	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
280	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
281	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
282	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
283	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
284	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
285	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
286	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
287	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
288	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
289	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
290	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
291	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
292	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
293	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
294	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
295	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
296	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
297	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
298	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
299	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
300	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
301	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
302	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
303
304	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
305	pVM->em.s.pCliStatTree = 0;
306	#endif /* VBOX_WITH_STATISTICS */
307
308	/* these should be considered for release statistics. */
309	STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
310	STAM_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
311	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
312	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
313	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
314	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
315	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
316	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
317	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
318	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
319	STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
320	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
321	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
322	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
323	STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
324	STAM_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
325
326
327	return VINF_SUCCESS;
328	}
329
330
331
332	/**
333	* Applies relocations to data and code managed by this
334	* component. This function will be called at init and
335	* whenever the VMM need to relocate it self inside the GC.
336	*
337	* @param pVM The VM.
338	*/
339	EMR3DECL(void) EMR3Relocate(PVM pVM)
340	{
341	LogFlow(("EMR3Relocate\n"));
342	if (pVM->em.s.pStatsHC)
343	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
344	}
345
346
347	/**
348	* Reset notification.
349	*
350	* @param pVM
351	*/
352	EMR3DECL(void) EMR3Reset(PVM pVM)
353	{
354	LogFlow(("EMR3Reset: \n"));
355	pVM->em.s.fForceRAW = false;
356	}
357
358
359	/**
360	* Terminates the EM.
361	*
362	* Termination means cleaning up and freeing all resources,
363	* the VM it self is at this point powered off or suspended.
364	*
365	* @returns VBox status code.
366	* @param pVM The VM to operate on.
367	*/
368	EMR3DECL(int) EMR3Term(PVM pVM)
369	{
370	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
371
372	return VINF_SUCCESS;
373	}
374
375
376	/**
377	* Execute state save operation.
378	*
379	* @returns VBox status code.
380	* @param pVM VM Handle.
381	* @param pSSM SSM operation handle.
382	*/
383	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
384	{
385	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
386	}
387
388
389	/**
390	* Execute state load operation.
391	*
392	* @returns VBox status code.
393	* @param pVM VM Handle.
394	* @param pSSM SSM operation handle.
395	* @param u32Version Data layout version.
396	*/
397	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
398	{
399	/*
400	* Validate version.
401	*/
402	if (u32Version != EM_SAVED_STATE_VERSION)
403	{
404	Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
405	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
406	}
407
408	/*
409	* Load the saved state.
410	*/
411	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
412	if (VBOX_FAILURE(rc))
413	pVM->em.s.fForceRAW = false;
414
415	Assert(pVM->em.s.pCliStatTree == 0);
416	return rc;
417	}
418
419
420	/**
421	* Enables or disables a set of raw-mode execution modes.
422	*
423	* @returns VINF_SUCCESS on success.
424	* @returns VINF_RESCHEDULE if a rescheduling might be required.
425	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
426	*
427	* @param pVM The VM to operate on.
428	* @param enmMode The execution mode change.
429	* @thread The emulation thread.
430	*/
431	EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
432	{
433	switch (enmMode)
434	{
435	case EMRAW_NONE:
436	pVM->fRawR3Enabled = false;
437	pVM->fRawR0Enabled = false;
438	break;
439	case EMRAW_RING3_ENABLE:
440	pVM->fRawR3Enabled = true;
441	break;
442	case EMRAW_RING3_DISABLE:
443	pVM->fRawR3Enabled = false;
444	break;
445	case EMRAW_RING0_ENABLE:
446	pVM->fRawR0Enabled = true;
447	break;
448	case EMRAW_RING0_DISABLE:
449	pVM->fRawR0Enabled = false;
450	break;
451	default:
452	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
453	return VERR_INVALID_PARAMETER;
454	}
455	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
456	pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
457	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
458	}
459
460
461	/**
462	* Raise a fatal error.
463	*
464	* Safely terminate the VM with full state report and stuff. This function
465	* will naturally never return.
466	*
467	* @param pVM VM handle.
468	* @param rc VBox status code.
469	*/
470	EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
471	{
472	longjmp(pVM->em.s.u.FatalLongJump, rc);
473	AssertReleaseMsgFailed(("longjmp returned!\n"));
474	}
475
476
477	/**
478	* Gets the EM state name.
479	*
480	* @returns pointer to read only state name,
481	* @param enmState The state.
482	*/
483	EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
484	{
485	switch (enmState)
486	{
487	case EMSTATE_RAW: return "EMSTATE_RAW";
488	case EMSTATE_HWACC: return "EMSTATE_HWACC";
489	case EMSTATE_REM: return "EMSTATE_REM";
490	case EMSTATE_HALTED: return "EMSTATE_HALTED";
491	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
492	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
493	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
494	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
495	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
496	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
497	default: return "Unknown!";
498	}
499	}
500
501
502	#ifdef VBOX_WITH_STATISTICS
503	/**
504	* Just a braindead function to keep track of cli addresses.
505	* @param pVM VM handle.
506	* @param pInstrGC The EIP of the cli instruction.
507	*/
508	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
509	{
510	PCLISTAT pRec;
511
512	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
513	if (!pRec)
514	{
515	/* New cli instruction; insert into the tree. */
516	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
517	Assert(pRec);
518	if (!pRec)
519	return;
520	pRec->Core.Key = (AVLPVKEY)pInstrGC;
521
522	char szCliStatName[32];
523	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
524	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
525
526	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
527	Assert(fRc); NOREF(fRc);
528	}
529	STAM_COUNTER_INC(&pRec->Counter);
530	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
531	}
532	#endif /* VBOX_WITH_STATISTICS */
533
534
535	/**
536	* Debug loop.
537	*
538	* @returns VBox status code for EM.
539	* @param pVM VM handle.
540	* @param rc Current EM VBox status code..
541	*/
542	static int emR3Debug(PVM pVM, int rc)
543	{
544	for (;;)
545	{
546	Log(("emR3Debug: rc=%Vrc\n", rc));
547	const int rcLast = rc;
548
549	/*
550	* Debug related RC.
551	*/
552	switch (rc)
553	{
554	/*
555	* Single step an instruction.
556	*/
557	case VINF_EM_DBG_STEP:
558	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
559	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
560	\|\| pVM->em.s.fForceRAW /* paranoia */)
561	rc = emR3RawStep(pVM);
562	else
563	{
564	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
565	rc = emR3RemStep(pVM);
566	}
567	break;
568
569	/*
570	* Simple events: stepped, breakpoint, stop/assertion.
571	*/
572	case VINF_EM_DBG_STEPPED:
573	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
574	break;
575
576	case VINF_EM_DBG_BREAKPOINT:
577	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
578	break;
579
580	case VINF_EM_DBG_STOP:
581	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
582	break;
583
584	case VINF_EM_DBG_HYPER_STEPPED:
585	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
586	break;
587
588	case VINF_EM_DBG_HYPER_BREAKPOINT:
589	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
590	break;
591
592	case VINF_EM_DBG_HYPER_ASSERTION:
593	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
594	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
595	break;
596
597	/*
598	* Guru meditation.
599	*/
600	default: /** @todo don't use default for guru, but make special errors code! */
601	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
602	break;
603	}
604
605	/*
606	* Process the result.
607	*/
608	do
609	{
610	switch (rc)
611	{
612	/*
613	* Continue the debugging loop.
614	*/
615	case VINF_EM_DBG_STEP:
616	case VINF_EM_DBG_STOP:
617	case VINF_EM_DBG_STEPPED:
618	case VINF_EM_DBG_BREAKPOINT:
619	case VINF_EM_DBG_HYPER_STEPPED:
620	case VINF_EM_DBG_HYPER_BREAKPOINT:
621	case VINF_EM_DBG_HYPER_ASSERTION:
622	break;
623
624	/*
625	* Resuming execution (in some form) has to be done here if we got
626	* a hypervisor debug event.
627	*/
628	case VINF_SUCCESS:
629	case VINF_EM_RESUME:
630	case VINF_EM_SUSPEND:
631	case VINF_EM_RESCHEDULE:
632	case VINF_EM_RESCHEDULE_RAW:
633	case VINF_EM_RESCHEDULE_REM:
634	case VINF_EM_HALT:
635	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
636	{
637	rc = emR3RawResumeHyper(pVM);
638	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
639	continue;
640	}
641	if (rc == VINF_SUCCESS)
642	rc = VINF_EM_RESCHEDULE;
643	return rc;
644
645	/*
646	* The debugger isn't attached.
647	* We'll simply turn the thing off since that's the easiest thing to do.
648	*/
649	case VERR_DBGF_NOT_ATTACHED:
650	switch (rcLast)
651	{
652	case VINF_EM_DBG_HYPER_ASSERTION:
653	case VINF_EM_DBG_HYPER_STEPPED:
654	case VINF_EM_DBG_HYPER_BREAKPOINT:
655	return rcLast;
656	}
657	return VINF_EM_OFF;
658
659	/*
660	* Status codes terminating the VM in one or another sense.
661	*/
662	case VINF_EM_TERMINATE:
663	case VINF_EM_OFF:
664	case VINF_EM_RESET:
665	case VINF_EM_RAW_STALE_SELECTOR:
666	case VINF_EM_RAW_IRET_TRAP:
667	case VERR_TRPM_PANIC:
668	case VERR_TRPM_DONT_PANIC:
669	case VERR_INTERNAL_ERROR:
670	return rc;
671
672	/*
673	* The rest is unexpected, and will keep us here.
674	*/
675	default:
676	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
677	break;
678	}
679	} while (false);
680	} /* debug for ever */
681	}
682
683
684	/**
685	* Steps recompiled code.
686	*
687	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
688	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
689	*
690	* @param pVM VM handle.
691	*/
692	static int emR3RemStep(PVM pVM)
693	{
694	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
695
696	/*
697	* Switch to REM, step instruction, switch back.
698	*/
699	int rc = REMR3State(pVM);
700	if (VBOX_SUCCESS(rc))
701	{
702	rc = REMR3Step(pVM);
703	REMR3StateBack(pVM);
704	}
705	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
706	return rc;
707	}
708
709	/**
710	* Executes recompiled code.
711	*
712	* This function contains the recompiler version of the inner
713	* execution loop (the outer loop being in EMR3ExecuteVM()).
714	*
715	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
716	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
717	*
718	* @param pVM VM handle.
719	* @param pfFFDone Where to store an indicator telling wheter or not
720	* FFs were done before returning.
721	*
722	*/
723	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
724	{
725	#ifdef LOG_ENABLED
726	PCPUMCTX pCtx = pVM->em.s.pCtx;
727	if (pCtx->eflags.Bits.u1VM)
728	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
729	else if ((pCtx->ss & X86_SEL_RPL) == 0)
730	Log(("EMR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
731	else if ((pCtx->ss & X86_SEL_RPL) == 3)
732	Log(("EMR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
733	#endif
734	STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
735
736	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
737	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
738	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
739	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
740	#endif
741
742	/*
743	* Spin till we get a forced action which returns anything but VINF_SUCCESS
744	* or the REM suggests raw-mode execution.
745	*/
746	*pfFFDone = false;
747	bool fInREMState = false;
748	int rc = VINF_SUCCESS;
749	for (;;)
750	{
751	/*
752	* Update REM state if not already in sync.
753	*/
754	if (!fInREMState)
755	{
756	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
757	rc = REMR3State(pVM);
758	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
759	if (VBOX_FAILURE(rc))
760	break;
761	fInREMState = true;
762
763	/*
764	* We might have missed the raising of VMREQ, TIMER and some other
765	* imporant FFs while we were busy switching the state. So, check again.
766	*/
767	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
768	{
769	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
770	goto l_REMDoForcedActions;
771	}
772	}
773
774
775	/*
776	* Execute REM.
777	*/
778	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
779	rc = REMR3Run(pVM);
780	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
781
782
783	/*
784	* Deal with high priority post execution FFs before doing anything else.
785	*/
786	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
787	rc = emR3HighPriorityPostForcedActions(pVM, rc);
788
789	/*
790	* Process the returned status code.
791	* (Try keep this short! Call functions!)
792	*/
793	if (rc != VINF_SUCCESS)
794	{
795	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
796	break;
797	if (rc != VINF_REM_INTERRUPED_FF)
798	{
799	/*
800	* Anything which is not known to us means an internal error
801	* and the termination of the VM!
802	*/
803	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
804	break;
805	}
806	}
807
808
809	/*
810	* Check and execute forced actions.
811	* Sync back the VM state before calling any of these.
812	*/
813	#ifdef VBOX_HIGH_RES_TIMERS_HACK
814	TMTimerPoll(pVM);
815	#endif
816	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
817	{
818	l_REMDoForcedActions:
819	if (fInREMState)
820	{
821	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
822	REMR3StateBack(pVM);
823	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
824	fInREMState = false;
825	}
826	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
827	rc = emR3ForcedActions(pVM, rc);
828	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
829	if ( rc != VINF_SUCCESS
830	&& rc != VINF_EM_RESCHEDULE_REM)
831	{
832	*pfFFDone = true;
833	break;
834	}
835	}
836
837	} /* The Inner Loop, recompiled execution mode version. */
838
839
840	/*
841	* Returning. Sync back the VM state if required.
842	*/
843	if (fInREMState)
844	{
845	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
846	REMR3StateBack(pVM);
847	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
848	}
849
850	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
851	return rc;
852	}
853
854
855	/**
856	* Resumes executing hypervisor after a debug event.
857	*
858	* This is kind of special since our current guest state is
859	* potentially out of sync.
860	*
861	* @returns VBox status code.
862	* @param pVM The VM handle.
863	*/
864	static int emR3RawResumeHyper(PVM pVM)
865	{
866	int rc;
867	PCPUMCTX pCtx = pVM->em.s.pCtx;
868	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
869	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
870
871	/*
872	* Resume execution.
873	*/
874	CPUMRawEnter(pVM, NULL);
875	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
876	rc = VMMR3ResumeHyper(pVM);
877	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
878	rc = CPUMRawLeave(pVM, NULL, rc);
879	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
880
881	/*
882	* Deal with the return code.
883	*/
884	rc = emR3HighPriorityPostForcedActions(pVM, rc);
885	rc = emR3RawHandleRC(pVM, pCtx, rc);
886	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
887	return rc;
888	}
889
890
891	/**
892	* Steps rawmode.
893	*
894	* @returns VBox status code.
895	* @param pVM The VM handle.
896	*/
897	static int emR3RawStep(PVM pVM)
898	{
899	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
900	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
901	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
902	int rc;
903	PCPUMCTX pCtx = pVM->em.s.pCtx;
904	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
905	#ifndef DEBUG_sandervl
906	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
907	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
908	#endif
909	if (fGuest)
910	{
911	/*
912	* Check vital forced actions, but ignore pending interrupts and timers.
913	*/
914	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
915	{
916	rc = emR3RawForcedActions(pVM, pCtx);
917	if (VBOX_FAILURE(rc))
918	return rc;
919	}
920
921	/*
922	* Set flags for single stepping.
923	*/
924	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
925	}
926	else
927	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
928
929	/*
930	* Single step.
931	* We do not start time or anything, if anything we should just do a few nanoseconds.
932	*/
933	CPUMRawEnter(pVM, NULL);
934	do
935	{
936	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
937	rc = VMMR3ResumeHyper(pVM);
938	else
939	rc = VMMR3RawRunGC(pVM);
940	#ifndef DEBUG_sandervl
941	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
942	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
943	#endif
944	} while ( rc == VINF_SUCCESS
945	\|\| rc == VINF_EM_RAW_INTERRUPT);
946	rc = CPUMRawLeave(pVM, NULL, rc);
947	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
948
949	/*
950	* Make sure the trap flag is cleared.
951	* (Too bad if the guest is trying to single step too.)
952	*/
953	if (fGuest)
954	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
955	else
956	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
957
958	/*
959	* Deal with the return codes.
960	*/
961	rc = emR3HighPriorityPostForcedActions(pVM, rc);
962	rc = emR3RawHandleRC(pVM, pCtx, rc);
963	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
964	return rc;
965	}
966
967	#ifdef DEBUG_sandervl
968	void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
969	{
970	EMSTATE enmOldState = pVM->em.s.enmState;
971	PCPUMCTX pCtx = pVM->em.s.pCtx;
972
973	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
974
975	Log(("Single step BEGIN:\n"));
976	for(uint32_t i=0;i<cIterations;i++)
977	{
978	DBGFR3PrgStep(pVM);
979	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
980	emR3RawStep(pVM);
981	}
982	Log(("Single step END:\n"));
983	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
984	pVM->em.s.enmState = enmOldState;
985	}
986
987	void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
988	{
989	EMSTATE enmOldState = pVM->em.s.enmState;
990	PCPUMCTX pCtx = pVM->em.s.pCtx;
991
992	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
993
994	Log(("Single step BEGIN:\n"));
995	for(uint32_t i=0;i<cIterations;i++)
996	{
997	DBGFR3PrgStep(pVM);
998	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
999	emR3RemStep(pVM);
1000	}
1001	Log(("Single step END:\n"));
1002	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1003	pVM->em.s.enmState = enmOldState;
1004	}
1005	#endif
1006
1007	/**
1008	* Executes one (or perhaps a few more) instruction(s).
1009	*
1010	* @returns VBox status code suitable for EM.
1011	*
1012	* @param pVM VM handle.
1013	* @param rcGC GC return code
1014	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1015	* instruction and prefix the log output with this text.
1016	*/
1017	#ifdef LOG_ENABLED
1018	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1019	#else
1020	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1021	#endif
1022	{
1023	PCPUMCTX pCtx = pVM->em.s.pCtx;
1024	int rc;
1025
1026	/*
1027	*
1028	* The simple solution is to use the recompiler.
1029	* The better solution is to disassemble the current instruction and
1030	* try handle as many as possible without using REM.
1031	*
1032	*/
1033
1034	#ifdef LOG_ENABLED
1035	/*
1036	* Disassemble the instruction if requested.
1037	*/
1038	if (pszPrefix)
1039	{
1040	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1041	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1042	}
1043	#endif /* LOG_ENABLED */
1044
1045
1046	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
1047
1048	/*
1049	* PATM is making life more interesting.
1050	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1051	* tell PATM there is a trap in this code and have it take the appropriate actions
1052	* to allow us execute the code in REM.
1053	*/
1054	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1055	{
1056	Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
1057
1058	RTGCPTR pNewEip;
1059	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1060	switch (rc)
1061	{
1062	/*
1063	* It's not very useful to emulate a single instruction and then go back to raw
1064	* mode; just execute the whole block until IF is set again.
1065	*/
1066	case VINF_SUCCESS:
1067	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1068	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1069	pCtx->eip = pNewEip;
1070	Assert(pCtx->eip);
1071
1072	if (pCtx->eflags.Bits.u1IF)
1073	{
1074	/*
1075	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1076	*/
1077	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1078	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1079	}
1080	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1081	{
1082	/* special case: iret, that sets IF, detected a pending irq/event */
1083	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1084	}
1085	return VINF_EM_RESCHEDULE_REM;
1086
1087	/*
1088	* One instruction.
1089	*/
1090	case VINF_PATCH_EMULATE_INSTR:
1091	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1092	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1093	pCtx->eip = pNewEip;
1094	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1095
1096	/*
1097	* The patch was disabled, hand it to the REM.
1098	*/
1099	case VERR_PATCH_DISABLED:
1100	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1101	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1102	pCtx->eip = pNewEip;
1103	if (pCtx->eflags.Bits.u1IF)
1104	{
1105	/*
1106	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1107	*/
1108	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1109	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1110	}
1111	return VINF_EM_RESCHEDULE_REM;
1112
1113	/* Force continued patch exection; usually due to write monitored stack. */
1114	case VINF_PATCH_CONTINUE:
1115	return VINF_SUCCESS;
1116
1117	default:
1118	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1119	return VERR_INTERNAL_ERROR;
1120	}
1121	}
1122
1123	#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1124	DISCPUSTATE Cpu;
1125	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1126	if (VBOX_SUCCESS(rc))
1127	{
1128	uint32_t size;
1129
1130	switch (Cpu.pCurInstr->opcode)
1131	{
1132	case OP_MOV:
1133	case OP_AND:
1134	case OP_OR:
1135	case OP_XOR:
1136	case OP_POP:
1137	case OP_INC:
1138	case OP_DEC:
1139	case OP_XCHG:
1140	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1141	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1142	if (VBOX_SUCCESS(rc))
1143	{
1144	pCtx->eip += Cpu.opsize;
1145	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1146	return rc;
1147	}
1148	if (rc != VERR_EM_INTERPRETER)
1149	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1150	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1151	break;
1152	}
1153	}
1154	#endif
1155	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1156	rc = REMR3EmulateInstruction(pVM);
1157	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1158
1159	return rc;
1160	}
1161
1162
1163	/**
1164	* Executes one (or perhaps a few more) instruction(s).
1165	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1166	*
1167	* @returns VBox status code suitable for EM.
1168	* @param pVM VM handle.
1169	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1170	* instruction and prefix the log output with this text.
1171	* @param rcGC GC return code
1172	*/
1173	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1174	{
1175	#ifdef LOG_ENABLED
1176	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1177	#else
1178	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1179	#endif
1180	}
1181
1182	/**
1183	* Executes one (or perhaps a few more) IO instruction(s).
1184	*
1185	* @returns VBox status code suitable for EM.
1186	* @param pVM VM handle.
1187	*/
1188	int emR3RawExecuteIOInstruction(PVM pVM)
1189	{
1190	int rc;
1191	PCPUMCTX pCtx = pVM->em.s.pCtx;
1192
1193	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1194
1195	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1196	* as io instructions tend to come in packages of more than one
1197	*/
1198	DISCPUSTATE Cpu;
1199	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1200	if (VBOX_SUCCESS(rc))
1201	{
1202	#ifdef VBOX_WITH_STATISTICS
1203	switch (Cpu.pCurInstr->opcode)
1204	{
1205	case OP_INSB:
1206	case OP_INSWD:
1207	case OP_IN:
1208	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1209	break;
1210
1211	case OP_OUTSB:
1212	case OP_OUTSWD:
1213	case OP_OUT:
1214	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1215	break;
1216	}
1217	#endif
1218
1219	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1220	{
1221	OP_PARAMVAL ParmVal;
1222	int rc;
1223	switch (Cpu.pCurInstr->opcode)
1224	{
1225	case OP_IN:
1226	{
1227	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal, PARAM_SOURCE);
1228	if ( VBOX_FAILURE(rc)
1229	\|\| ParmVal.type != PARMTYPE_IMMEDIATE)
1230	break;
1231
1232	if (!(Cpu.param1.flags & (USE_REG_GEN8 \| USE_REG_GEN16 \| USE_REG_GEN32)))
1233	break;
1234
1235	/* Make sure port access is allowed */
1236	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1237	if (rc != VINF_SUCCESS)
1238	{
1239	if (rc == VINF_EM_RAW_GUEST_TRAP)
1240	rc = emR3RawGuestTrap(pVM);
1241
1242	return rc;
1243	}
1244
1245	uint32_t u32Value = 0;
1246	switch (Cpu.param1.size)
1247	{
1248	case 1:
1249	Assert(Cpu.param1.base.reg_gen8 == USE_REG_AL);
1250	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint8_t));
1251	if (VBOX_SUCCESS(rc))
1252	{
1253	pCtx->eax = (pCtx->eax & ~0xFF) \| (uint8_t)u32Value;
1254	Log(("EMU: in8 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFF));
1255	pCtx->eip += Cpu.opsize;
1256	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1257	return rc;
1258	}
1259	AssertRC(rc);
1260	break;
1261
1262	case 2:
1263	Assert(Cpu.param1.base.reg_gen16 == USE_REG_AX);
1264	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint16_t));
1265	if (VBOX_SUCCESS(rc))
1266	{
1267	pCtx->eax = (pCtx->eax & ~0xFFFF) \| (uint16_t)u32Value;
1268	Log(("EMU: in16 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFFFF));
1269	pCtx->eip += Cpu.opsize;
1270	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1271	return rc;
1272	}
1273	AssertRC(rc);
1274	break;
1275
1276	case 4:
1277	Assert(Cpu.param1.base.reg_gen32 == USE_REG_EAX);
1278	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint32_t));
1279	if (VBOX_SUCCESS(rc))
1280	{
1281	pCtx->eax = u32Value;
1282	Log(("EMU: in32 %x, %x\n", ParmVal.val.val16, pCtx->eax));
1283	pCtx->eip += Cpu.opsize;
1284	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1285	return rc;
1286	}
1287	AssertRC(rc);
1288	break;
1289
1290	default:
1291	AssertMsgFailed(("Unexpected port size %d\n", ParmVal.size));
1292	break;
1293	}
1294	break;
1295	}
1296
1297	case OP_OUT:
1298	{
1299	// it really is the destination, but we're interested in the destination value. hence we specify PARAM_SOURCE (bit of a hack)
1300	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &ParmVal, PARAM_SOURCE);
1301	if ( VBOX_FAILURE(rc)
1302	\|\| ParmVal.type != PARMTYPE_IMMEDIATE)
1303	break;
1304	OP_PARAMVAL ParmVal2;
1305	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal2, PARAM_SOURCE);
1306	if ( VBOX_FAILURE(rc)
1307	\|\| ParmVal2.type != PARMTYPE_IMMEDIATE)
1308	break;
1309
1310	/* Make sure port access is allowed */
1311	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1312	if (rc != VINF_SUCCESS)
1313	{
1314	if (rc == VINF_EM_RAW_GUEST_TRAP)
1315	rc = emR3RawGuestTrap(pVM);
1316
1317	return rc;
1318	}
1319
1320	AssertMsg(Cpu.param2.size == ParmVal2.size, ("size %d vs %d\n", Cpu.param2.size, ParmVal2.size));
1321	switch (ParmVal2.size)
1322	{
1323	case 1:
1324	Log(("EMU: out8 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val8));
1325	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val8, sizeof(ParmVal2.val.val8));
1326	if (VBOX_SUCCESS(rc))
1327	{
1328	pCtx->eip += Cpu.opsize;
1329	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1330	return rc;
1331	}
1332	AssertRC(rc);
1333	break;
1334
1335	case 2:
1336	Log(("EMU: out16 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val16));
1337	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val16, sizeof(ParmVal2.val.val16));
1338	if (VBOX_SUCCESS(rc))
1339	{
1340	pCtx->eip += Cpu.opsize;
1341	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1342	return rc;
1343	}
1344	AssertRC(rc);
1345	break;
1346
1347	case 4:
1348	Log(("EMU: out32 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val32));
1349	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val32, sizeof(ParmVal2.val.val32));
1350	if (VBOX_SUCCESS(rc))
1351	{
1352	pCtx->eip += Cpu.opsize;
1353	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1354	return rc;
1355	}
1356	AssertRC(rc);
1357	break;
1358
1359	default:
1360	AssertMsgFailed(("Unexpected port size %d\n", ParmVal2.size));
1361	break;
1362	}
1363	break;
1364	}
1365
1366	default:
1367	break;
1368	}
1369	}//if(!(Cpu.prefix & (PREFIX_REP\|PREFIX_REPNE))
1370	else if (Cpu.prefix & PREFIX_REP)
1371	{
1372	switch (Cpu.pCurInstr->opcode)
1373	{
1374	case OP_INSB:
1375	case OP_INSWD:
1376	{
1377	/*
1378	* Do not optimize the destination address decrement case (not worth the effort)
1379	* and likewise for 16 bit address size (would need to use and update only cx/di).
1380	*/
1381	if (pCtx->eflags.Bits.u1DF \|\| Cpu.addrmode != CPUMODE_32BIT)
1382	break;
1383	/*
1384	* Get port number and transfer count directly from the registers (no need to bother the
1385	* disassembler). And get the I/O register size from the opcode / prefix.
1386	*/
1387	uint32_t uPort = pCtx->edx & 0xffff;
1388	RTGCUINTREG cTransfers = pCtx->ecx;
1389	unsigned cbUnit;
1390	if (Cpu.pCurInstr->opcode == OP_INSB)
1391	cbUnit = 1;
1392	else
1393	cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1394
1395	RTGCPTR GCPtrDst = pCtx->edi;
1396	uint32_t cpl = (pCtx->eflags.Bits.u1VM) ? 3 : (pCtx->ss & X86_SEL_RPL);
1397
1398	/* Access verification first; we can't recover from traps inside this instruction, as the port read cannot be repeated. */
1399	rc = PGMVerifyAccess(pVM, GCPtrDst, cTransfers * cbUnit,
1400	X86_PTE_RW \| ((cpl == 3) ? X86_PTE_US : 0));
1401	if (rc != VINF_SUCCESS)
1402	{
1403	Log(("EMU: rep ins%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1404	break;
1405	}
1406
1407	Log(("EMU: rep ins%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1408
1409	/* Make sure port access is allowed */
1410	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1411	if (rc != VINF_SUCCESS)
1412	{
1413	if (rc == VINF_EM_RAW_GUEST_TRAP)
1414	rc = emR3RawGuestTrap(pVM);
1415
1416	return rc;
1417	}
1418
1419	/*
1420	* If the device supports string transfers, ask it to do as
1421	* much as it wants. The rest is done with single-word transfers.
1422	*/
1423	rc = IOMIOPortReadString(pVM, uPort, &GCPtrDst, &cTransfers, cbUnit);
1424	AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1425
1426	while (cTransfers && rc == VINF_SUCCESS)
1427	{
1428	uint32_t u32Value;
1429	rc = IOMIOPortRead(pVM, uPort, &u32Value, cbUnit);
1430	AssertRC(rc);
1431	int rc2 = PGMPhysWriteGCPtrDirty(pVM, GCPtrDst, &u32Value, cbUnit);
1432	AssertRC(rc2);
1433	GCPtrDst += cbUnit;
1434	cTransfers--;
1435	}
1436	pCtx->edi += (pCtx->ecx - cTransfers) * cbUnit;
1437	pCtx->ecx = cTransfers;
1438	if (!cTransfers && VBOX_SUCCESS(rc))
1439	pCtx->eip += Cpu.opsize;
1440	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1441	return rc;
1442	}
1443	case OP_OUTSB:
1444	case OP_OUTSWD:
1445	{
1446	/*
1447	* Do not optimize the source address decrement case (not worth the effort)
1448	* and likewise for 16 bit address size (would need to use and update only cx/si).
1449	*/
1450	if (pCtx->eflags.Bits.u1DF \|\| Cpu.addrmode != CPUMODE_32BIT)
1451	break;
1452	/*
1453	* Get port number and transfer count directly from the registers (no need to bother the
1454	* disassembler). And get the I/O register size from the opcode / prefix.
1455	*/
1456	uint32_t uPort = pCtx->edx & 0xffff;
1457	RTGCUINTREG cTransfers = pCtx->ecx;
1458	unsigned cbUnit;
1459	if (Cpu.pCurInstr->opcode == OP_OUTSB)
1460	cbUnit = 1;
1461	else
1462	cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1463
1464	RTGCPTR GCPtrSrc = pCtx->esi;
1465	uint32_t cpl = (pCtx->eflags.Bits.u1VM) ? 3 : (pCtx->ss & X86_SEL_RPL);
1466
1467	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1468	rc = PGMVerifyAccess(pVM, GCPtrSrc, cTransfers * cbUnit, ((cpl == 3) ? X86_PTE_US : 0));
1469	if (rc != VINF_SUCCESS)
1470	{
1471	Log(("EMU: rep outs%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1472	break;
1473	}
1474
1475	Log(("EMU: rep outs%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1476
1477	/* Make sure port access is allowed */
1478	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1479	if (rc != VINF_SUCCESS)
1480	{
1481	if (rc == VINF_EM_RAW_GUEST_TRAP)
1482	rc = emR3RawGuestTrap(pVM);
1483
1484	return rc;
1485	}
1486
1487	/*
1488	* If the device supports string transfers, ask it to do as
1489	* much as it wants. The rest is done with single-word transfers.
1490	*/
1491	rc = IOMIOPortWriteString(pVM, uPort, &GCPtrSrc, &cTransfers, cbUnit);
1492	AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1493
1494	while (cTransfers && rc == VINF_SUCCESS)
1495	{
1496	uint32_t u32Value;
1497	rc = PGMPhysReadGCPtr(pVM, &u32Value, GCPtrSrc, cbUnit);
1498	Assert(rc == VINF_SUCCESS);
1499	rc = IOMIOPortWrite(pVM, uPort, u32Value, cbUnit);
1500	AssertRC(rc);
1501	GCPtrSrc += cbUnit;
1502	cTransfers--;
1503	}
1504	pCtx->esi += (pCtx->ecx - cTransfers) * cbUnit;
1505	pCtx->ecx = cTransfers;
1506	if (!cTransfers && VBOX_SUCCESS(rc))
1507	pCtx->eip += Cpu.opsize;
1508	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1509	return rc;
1510	}
1511	}
1512	}//if(Cpu.prefix & PREFIX_REP)
1513	}
1514
1515	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1516	return emR3RawExecuteInstruction(pVM, "IO: ");
1517	}
1518
1519
1520	/**
1521	* Handle a guest context trap.
1522	*
1523	* @returns VBox status code suitable for EM.
1524	* @param pVM VM handle.
1525	*/
1526	static int emR3RawGuestTrap(PVM pVM)
1527	{
1528	PCPUMCTX pCtx = pVM->em.s.pCtx;
1529
1530	/*
1531	* Get the trap info.
1532	*/
1533	uint8_t u8TrapNo;
1534	TRPMEVENT enmType;;
1535	RTGCUINT uErrorCode;
1536	RTGCUINTPTR uCR2;
1537	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1538	if (VBOX_FAILURE(rc))
1539	{
1540	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1541	return rc;
1542	}
1543
1544	/* Traps can be directly forwarded in hardware accelerated mode. */
1545	if (HWACCMR3IsActive(pVM))
1546	{
1547	#ifdef LOGGING_ENABLED
1548	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1549	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1550	#endif
1551	return VINF_EM_RESCHEDULE_HWACC;
1552	}
1553
1554	/** Scan kernel code that traps; we might not get another chance. */
1555	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1556	&& !pCtx->eflags.Bits.u1VM)
1557	{
1558	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1559	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
1560	}
1561
1562	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1563	{
1564	DISCPUSTATE cpu;
1565
1566	/* If MONITOR & MWAIT are supported, then interpret them here. */
1567	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1568	if ( VBOX_SUCCESS(rc)
1569	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1570	{
1571	uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1572
1573	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1574
1575	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1576	{
1577	rc = TRPMResetTrap(pVM);
1578	AssertRC(rc);
1579
1580	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1581	if (VBOX_SUCCESS(rc))
1582	{
1583	pCtx->eip += cpu.opsize;
1584	return rc;
1585	}
1586	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1587	}
1588	}
1589	}
1590	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1591	{
1592	DISCPUSTATE cpu;
1593
1594	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1595	if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1596	{
1597	/*
1598	* We should really check the TSS for the IO bitmap, but it's not like this
1599	* lazy approach really makes things worse.
1600	*/
1601	rc = TRPMResetTrap(pVM);
1602	AssertRC(rc);
1603	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1604	}
1605	}
1606
1607	#ifdef LOG_ENABLED
1608	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1609	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1610
1611	/* Get guest page information. */
1612	uint64_t fFlags = 0;
1613	RTGCPHYS GCPhys = 0;
1614	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1615	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1616	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1617	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1618	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1619	#endif
1620
1621	/*
1622	* #PG has CR2.
1623	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1624	*/
1625	if (u8TrapNo == 14 /* #PG */)
1626	pCtx->cr2 = uCR2;
1627
1628	return VINF_EM_RESCHEDULE_REM;
1629	}
1630
1631
1632	/**
1633	* Handle a ring switch trap.
1634	* Need to do statistics and to install patches. The result is going to REM.
1635	*
1636	* @returns VBox status code suitable for EM.
1637	* @param pVM VM handle.
1638	*/
1639	int emR3RawRingSwitch(PVM pVM)
1640	{
1641	int rc;
1642	DISCPUSTATE Cpu;
1643	PCPUMCTX pCtx = pVM->em.s.pCtx;
1644
1645	/*
1646	* sysenter, syscall & callgate
1647	*/
1648	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1649	if (VBOX_SUCCESS(rc))
1650	{
1651	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1652	{
1653	if (pCtx->SysEnter.cs != 0)
1654	{
1655	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1656	SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1657	if (VBOX_SUCCESS(rc))
1658	{
1659	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1660	return VINF_EM_RESCHEDULE_RAW;
1661	}
1662	}
1663	}
1664
1665	#ifdef VBOX_WITH_STATISTICS
1666	switch (Cpu.pCurInstr->opcode)
1667	{
1668	case OP_SYSENTER:
1669	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1670	break;
1671	case OP_SYSEXIT:
1672	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1673	break;
1674	case OP_SYSCALL:
1675	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1676	break;
1677	case OP_SYSRET:
1678	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1679	break;
1680	}
1681	#endif
1682	}
1683	else
1684	AssertRC(rc);
1685
1686	/* go to the REM to emulate a single instruction */
1687	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1688	}
1689
1690	/**
1691	* Handle a trap (#PF or #GP) in patch code
1692	*
1693	* @returns VBox status code suitable for EM.
1694	* @param pVM VM handle.
1695	* @param pCtx CPU context
1696	* @param gcret GC return code
1697	*/
1698	int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1699	{
1700	uint8_t u8TrapNo;
1701	int rc;
1702	TRPMEVENT enmType;
1703	RTGCUINT uErrorCode;
1704	RTGCUINTPTR uCR2;
1705
1706	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1707
1708	if (gcret == VINF_PATM_PATCH_INT3)
1709	{
1710	u8TrapNo = 3;
1711	uCR2 = 0;
1712	uErrorCode = 0;
1713	}
1714	else
1715	if (gcret == VINF_PATM_PATCH_TRAP_GP)
1716	{
1717	/* No active trap in this case. Kind of ugly. */
1718	u8TrapNo = X86_XCPT_GP;
1719	uCR2 = 0;
1720	uErrorCode = 0;
1721	}
1722	else
1723	{
1724	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1725	if (VBOX_FAILURE(rc))
1726	{
1727	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1728	return rc;
1729	}
1730	/* Reset the trap as we'll execute the original instruction again. */
1731	TRPMResetTrap(pVM);
1732	}
1733
1734	/*
1735	* Deal with traps inside patch code.
1736	* (This code won't run outside GC.)
1737	*/
1738	if (u8TrapNo != 1)
1739	{
1740	#ifdef LOG_ENABLED
1741	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1742	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1743
1744	DISCPUSTATE Cpu;
1745	int rc;
1746
1747	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1748	if ( VBOX_SUCCESS(rc)
1749	&& Cpu.pCurInstr->opcode == OP_IRET)
1750	{
1751	uint32_t eip, selCS, uEFlags;
1752
1753	/* Iret crashes are bad as we have already changed the flags on the stack */
1754	rc = PGMPhysReadGCPtr(pVM, &eip, pCtx->esp, 4);
1755	rc \|= PGMPhysReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1756	rc \|= PGMPhysReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1757	if (rc == VINF_SUCCESS)
1758	{
1759	if ( (uEFlags & X86_EFL_VM)
1760	\|\| (selCS & X86_SEL_RPL) == 3)
1761	{
1762	uint32_t selSS, esp;
1763
1764	rc \|= PGMPhysReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1765	rc \|= PGMPhysReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1766
1767	if (uEFlags & X86_EFL_VM)
1768	{
1769	uint32_t selDS, selES, selFS, selGS;
1770	rc = PGMPhysReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1771	rc \|= PGMPhysReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1772	rc \|= PGMPhysReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1773	rc \|= PGMPhysReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1774	if (rc == VINF_SUCCESS)
1775	{
1776	Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1777	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1778	}
1779	}
1780	else
1781	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1782	}
1783	else
1784	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1785	}
1786	}
1787	#endif
1788	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1789	pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1790
1791	RTGCPTR pNewEip;
1792	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1793	switch (rc)
1794	{
1795	/*
1796	* Execute the faulting instruction.
1797	*/
1798	case VINF_SUCCESS:
1799	{
1800	/** @todo execute a whole block */
1801	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1802	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1803	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1804
1805	pCtx->eip = pNewEip;
1806	AssertRelease(pCtx->eip);
1807
1808	if (pCtx->eflags.Bits.u1IF)
1809	{
1810	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1811	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1812	*/
1813	if ( u8TrapNo == X86_XCPT_GP
1814	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1815	{
1816	/** @todo move to PATMR3HandleTrap */
1817	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1818	PATMR3RemovePatch(pVM, pCtx->eip);
1819	}
1820
1821	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1822	/** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1823
1824	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1825	/* Interrupts are enabled; just go back to the original instruction.
1826	return VINF_SUCCESS; */
1827	}
1828	return VINF_EM_RESCHEDULE_REM;
1829	}
1830
1831	/*
1832	* One instruction.
1833	*/
1834	case VINF_PATCH_EMULATE_INSTR:
1835	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1836	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1837	pCtx->eip = pNewEip;
1838	AssertRelease(pCtx->eip);
1839	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1840
1841	/*
1842	* The patch was disabled, hand it to the REM.
1843	*/
1844	case VERR_PATCH_DISABLED:
1845	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1846	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1847	pCtx->eip = pNewEip;
1848	AssertRelease(pCtx->eip);
1849
1850	if (pCtx->eflags.Bits.u1IF)
1851	{
1852	/*
1853	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1854	*/
1855	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1856	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1857	}
1858	return VINF_EM_RESCHEDULE_REM;
1859
1860	/* Force continued patch exection; usually due to write monitored stack. */
1861	case VINF_PATCH_CONTINUE:
1862	return VINF_SUCCESS;
1863
1864	/*
1865	* Anything else is fatal.
1866	*/
1867	default:
1868	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1869	return VERR_INTERNAL_ERROR;
1870	}
1871	}
1872	return VINF_SUCCESS;
1873	}
1874
1875
1876	/**
1877	* Handle a privileged instruction.
1878	*
1879	* @returns VBox status code suitable for EM.
1880	* @param pVM VM handle.
1881	*/
1882	int emR3RawPrivileged(PVM pVM)
1883	{
1884	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1885	PCPUMCTX pCtx = pVM->em.s.pCtx;
1886
1887	Assert(!pCtx->eflags.Bits.u1VM);
1888
1889	if (PATMIsEnabled(pVM))
1890	{
1891	/*
1892	* Check if in patch code.
1893	*/
1894	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1895	{
1896	#ifdef LOG_ENABLED
1897	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1898	#endif
1899	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1900	return VERR_EM_RAW_PATCH_CONFLICT;
1901	}
1902	if ( (pCtx->ss & X86_SEL_RPL) == 0
1903	&& !pCtx->eflags.Bits.u1VM
1904	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1905	{
1906	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1907	SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1908	if (VBOX_SUCCESS(rc))
1909	{
1910	#ifdef LOG_ENABLED
1911	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1912	#endif
1913	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1914	return VINF_SUCCESS;
1915	}
1916	}
1917	}
1918
1919	#ifdef LOG_ENABLED
1920	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1921	{
1922	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1923	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1924	}
1925	#endif
1926
1927	/*
1928	* Instruction statistics and logging.
1929	*/
1930	DISCPUSTATE Cpu;
1931	int rc;
1932
1933	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1934	if (VBOX_SUCCESS(rc))
1935	{
1936	#ifdef VBOX_WITH_STATISTICS
1937	PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1938	switch (Cpu.pCurInstr->opcode)
1939	{
1940	case OP_INVLPG:
1941	STAM_COUNTER_INC(&pStats->StatInvlpg);
1942	break;
1943	case OP_IRET:
1944	STAM_COUNTER_INC(&pStats->StatIret);
1945	break;
1946	case OP_CLI:
1947	STAM_COUNTER_INC(&pStats->StatCli);
1948	emR3RecordCli(pVM, pCtx->eip);
1949	break;
1950	case OP_STI:
1951	STAM_COUNTER_INC(&pStats->StatSti);
1952	break;
1953	case OP_INSB:
1954	case OP_INSWD:
1955	case OP_IN:
1956	case OP_OUTSB:
1957	case OP_OUTSWD:
1958	case OP_OUT:
1959	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1960	break;
1961
1962	case OP_MOV_CR:
1963	if (Cpu.param1.flags & USE_REG_GEN32)
1964	{
1965	//read
1966	Assert(Cpu.param2.flags & USE_REG_CR);
1967	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1968	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1969	}
1970	else
1971	{
1972	//write
1973	Assert(Cpu.param1.flags & USE_REG_CR);
1974	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1975	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1976	}
1977	break;
1978
1979	case OP_MOV_DR:
1980	STAM_COUNTER_INC(&pStats->StatMovDRx);
1981	break;
1982	case OP_LLDT:
1983	STAM_COUNTER_INC(&pStats->StatMovLldt);
1984	break;
1985	case OP_LIDT:
1986	STAM_COUNTER_INC(&pStats->StatMovLidt);
1987	break;
1988	case OP_LGDT:
1989	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1990	break;
1991	case OP_SYSENTER:
1992	STAM_COUNTER_INC(&pStats->StatSysEnter);
1993	break;
1994	case OP_SYSEXIT:
1995	STAM_COUNTER_INC(&pStats->StatSysExit);
1996	break;
1997	case OP_SYSCALL:
1998	STAM_COUNTER_INC(&pStats->StatSysCall);
1999	break;
2000	case OP_SYSRET:
2001	STAM_COUNTER_INC(&pStats->StatSysRet);
2002	break;
2003	case OP_HLT:
2004	STAM_COUNTER_INC(&pStats->StatHlt);
2005	break;
2006	default:
2007	STAM_COUNTER_INC(&pStats->StatMisc);
2008	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
2009	break;
2010	}
2011	#endif
2012	if ( (pCtx->ss & X86_SEL_RPL) == 0
2013	&& !pCtx->eflags.Bits.u1VM
2014	&& SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid))
2015	{
2016	uint32_t size;
2017
2018	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
2019	switch (Cpu.pCurInstr->opcode)
2020	{
2021	case OP_CLI:
2022	pCtx->eflags.u32 &= ~X86_EFL_IF;
2023	Assert(Cpu.opsize == 1);
2024	pCtx->eip += Cpu.opsize;
2025	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2026	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
2027
2028	case OP_STI:
2029	pCtx->eflags.u32 \|= X86_EFL_IF;
2030	EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
2031	Assert(Cpu.opsize == 1);
2032	pCtx->eip += Cpu.opsize;
2033	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2034	return VINF_SUCCESS;
2035
2036	case OP_HLT:
2037	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
2038	{
2039	PATMTRANSSTATE enmState;
2040	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
2041
2042	if (enmState == PATMTRANS_OVERWRITTEN)
2043	{
2044	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2045	Assert(rc == VERR_PATCH_DISABLED);
2046	/* Conflict detected, patch disabled */
2047	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
2048
2049	enmState = PATMTRANS_SAFE;
2050	}
2051
2052	/* The translation had better be successful. Otherwise we can't recover. */
2053	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
2054	if (enmState != PATMTRANS_OVERWRITTEN)
2055	pCtx->eip = pOrgInstrGC;
2056	}
2057	/* no break; we could just return VINF_EM_HALT here */
2058
2059	case OP_MOV_CR:
2060	case OP_MOV_DR:
2061	#ifdef LOG_ENABLED
2062	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2063	{
2064	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2065	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2066	}
2067	#endif
2068
2069	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2070	if (VBOX_SUCCESS(rc))
2071	{
2072	pCtx->eip += Cpu.opsize;
2073	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2074
2075	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2076	&& Cpu.param1.flags == USE_REG_CR /* write */
2077	)
2078	{
2079	/* Reschedule is necessary as the execution/paging mode might have changed. */
2080	return VINF_EM_RESCHEDULE;
2081	}
2082	return rc; /* can return VINF_EM_HALT as well. */
2083	}
2084	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
2085	break; /* fall back to the recompiler */
2086	}
2087	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2088	}
2089	}
2090
2091	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2092	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
2093
2094	return emR3RawExecuteInstruction(pVM, "PRIV");
2095	}
2096
2097
2098	/**
2099	* Update the forced rawmode execution modifier.
2100	*
2101	* This function is called when we're returning from the raw-mode loop(s). If we're
2102	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2103	* if not in patch code, the flag will be cleared.
2104	*
2105	* We should never interrupt patch code while it's being executed. Cli patches can
2106	* contain big code blocks, but they are always executed with IF=0. Other patches
2107	* replace single instructions and should be atomic.
2108	*
2109	* @returns Updated rc.
2110	*
2111	* @param pVM The VM handle.
2112	* @param pCtx The guest CPU context.
2113	* @param rc The result code.
2114	*/
2115	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2116	{
2117	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2118	{
2119	/* ignore reschedule attempts. */
2120	switch (rc)
2121	{
2122	case VINF_EM_RESCHEDULE:
2123	case VINF_EM_RESCHEDULE_REM:
2124	rc = VINF_SUCCESS;
2125	break;
2126	}
2127	pVM->em.s.fForceRAW = true;
2128	}
2129	else
2130	pVM->em.s.fForceRAW = false;
2131	return rc;
2132	}
2133
2134
2135	/**
2136	* Process a subset of the raw-mode return code.
2137	*
2138	* Since we have to share this with raw-mode single stepping, this inline
2139	* function has been created to avoid code duplication.
2140	*
2141	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2142	* @returns VBox status code to return to the EM main loop.
2143	*
2144	* @param pVM The VM handle
2145	* @param rc The return code.
2146	* @param pCtx The guest cpu context.
2147	*/
2148	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2149	{
2150	switch (rc)
2151	{
2152	/*
2153	* Common & simple ones.
2154	*/
2155	case VINF_SUCCESS:
2156	break;
2157	case VINF_EM_RESCHEDULE_RAW:
2158	case VINF_EM_RESCHEDULE_HWACC:
2159	case VINF_EM_RAW_INTERRUPT:
2160	case VINF_EM_RAW_TO_R3:
2161	case VINF_EM_RAW_TIMER_PENDING:
2162	case VINF_EM_PENDING_REQUEST:
2163	rc = VINF_SUCCESS;
2164	break;
2165
2166	/*
2167	* Privileged instruction.
2168	*/
2169	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2170	case VINF_PATM_PATCH_TRAP_GP:
2171	rc = emR3RawPrivileged(pVM);
2172	break;
2173
2174	/*
2175	* Got a trap which needs dispatching.
2176	*/
2177	case VINF_EM_RAW_GUEST_TRAP:
2178	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2179	{
2180	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2181	rc = VERR_EM_RAW_PATCH_CONFLICT;
2182	break;
2183	}
2184
2185	Assert(TRPMHasTrap(pVM));
2186	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2187
2188	if (TRPMHasTrap(pVM))
2189	{
2190	uint8_t u8Interrupt;
2191	uint32_t uErrorCode;
2192	TRPMERRORCODE enmError = TRPM_TRAP_NO_ERRORCODE;
2193
2194	rc = TRPMQueryTrapAll(pVM, &u8Interrupt, NULL, &uErrorCode, NULL);
2195	AssertRC(rc);
2196
2197	if (uErrorCode != ~0U)
2198	enmError = TRPM_TRAP_HAS_ERRORCODE;
2199
2200	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2201	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2202	{
2203	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2204	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2205
2206	/** If it was successful, then we could go back to raw mode. */
2207	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER)
2208	{
2209	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8Interrupt, uErrorCode, enmError, TRPM_TRAP);
2210	if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
2211	{
2212	TRPMResetTrap(pVM);
2213	return VINF_EM_RESCHEDULE_RAW;
2214	}
2215	}
2216	}
2217	}
2218	rc = emR3RawGuestTrap(pVM);
2219	break;
2220
2221	/*
2222	* Trap in patch code.
2223	*/
2224	case VINF_PATM_PATCH_TRAP_PF:
2225	case VINF_PATM_PATCH_INT3:
2226	rc = emR3PatchTrap(pVM, pCtx, rc);
2227	break;
2228
2229	case VINF_PATM_DUPLICATE_FUNCTION:
2230	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2231	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2232	AssertRC(rc);
2233	rc = VINF_SUCCESS;
2234	break;
2235
2236	case VINF_PATM_CHECK_PATCH_PAGE:
2237	rc = PATMR3HandleMonitoredPage(pVM);
2238	AssertRC(rc);
2239	rc = VINF_SUCCESS;
2240	break;
2241
2242	/*
2243	* Patch manager.
2244	*/
2245	case VERR_EM_RAW_PATCH_CONFLICT:
2246	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2247	break;
2248
2249	/*
2250	* Memory mapped I/O access - attempt to patch the instruction
2251	*/
2252	case VINF_PATM_HC_MMIO_PATCH_READ:
2253	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
2254	PATMFL_MMIO_ACCESS \| (SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2255	if (VBOX_FAILURE(rc))
2256	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2257	break;
2258
2259	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2260	AssertFailed(); /* not yet implemented. */
2261	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2262	break;
2263
2264	/*
2265	* Conflict or out of page tables.
2266	*
2267	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2268	* do here is to execute the pending forced actions.
2269	*/
2270	case VINF_PGM_SYNC_CR3:
2271	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2272	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2273	rc = VINF_SUCCESS;
2274	break;
2275
2276	/*
2277	* Paging mode change.
2278	*/
2279	case VINF_PGM_CHANGE_MODE:
2280	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2281	if (VBOX_SUCCESS(rc))
2282	rc = VINF_EM_RESCHEDULE;
2283	break;
2284
2285	/*
2286	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2287	*/
2288	case VINF_CSAM_PENDING_ACTION:
2289	rc = VINF_SUCCESS;
2290	break;
2291
2292	/*
2293	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2294	*/
2295	case VINF_EM_RAW_INTERRUPT_PENDING:
2296	case VINF_EM_RAW_RING_SWITCH_INT:
2297	{
2298	uint8_t u8Interrupt;
2299
2300	Assert(TRPMHasTrap(pVM));
2301	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2302
2303	if (TRPMHasTrap(pVM))
2304	{
2305	u8Interrupt = TRPMGetTrapNo(pVM);
2306
2307	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2308	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2309	{
2310	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2311	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2312	/** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2313	}
2314	}
2315	rc = VINF_EM_RESCHEDULE_REM;
2316	break;
2317	}
2318
2319	/*
2320	* Other ring switch types.
2321	*/
2322	case VINF_EM_RAW_RING_SWITCH:
2323	rc = emR3RawRingSwitch(pVM);
2324	break;
2325
2326	/*
2327	* REMGCNotifyInvalidatePage() failed because of overflow.
2328	*/
2329	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2330	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2331	REMR3ReplayInvalidatedPages(pVM);
2332	break;
2333
2334	/*
2335	* I/O Port access - emulate the instruction.
2336	*/
2337	case VINF_IOM_HC_IOPORT_READ:
2338	case VINF_IOM_HC_IOPORT_WRITE:
2339	case VINF_IOM_HC_IOPORT_READWRITE:
2340	rc = emR3RawExecuteIOInstruction(pVM);
2341	break;
2342
2343	/*
2344	* Memory mapped I/O access - emulate the instruction.
2345	*/
2346	case VINF_IOM_HC_MMIO_READ:
2347	case VINF_IOM_HC_MMIO_WRITE:
2348	case VINF_IOM_HC_MMIO_READ_WRITE:
2349	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2350	break;
2351
2352	/*
2353	* Execute instruction.
2354	*/
2355	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2356	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2357	break;
2358	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2359	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2360	break;
2361	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2362	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2363	break;
2364	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2365	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2366	break;
2367	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2368	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2369	break;
2370
2371	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2372	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2373	rc = emR3RawPrivileged(pVM);
2374	break;
2375
2376	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2377	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2378	break;
2379
2380	case VINF_EM_RAW_EMULATE_INSTR:
2381	case VINF_PATCH_EMULATE_INSTR:
2382	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2383	break;
2384
2385	/*
2386	* Stale selector and iret traps => REM.
2387	*/
2388	case VINF_EM_RAW_STALE_SELECTOR:
2389	case VINF_EM_RAW_IRET_TRAP:
2390	/* We will not go to the recompiler if EIP points to patch code. */
2391	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2392	{
2393	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2394	}
2395	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2396	rc = VINF_EM_RESCHEDULE_REM;
2397	break;
2398
2399	/*
2400	* Up a level.
2401	*/
2402	case VINF_EM_TERMINATE:
2403	case VINF_EM_OFF:
2404	case VINF_EM_RESET:
2405	case VINF_EM_SUSPEND:
2406	case VINF_EM_HALT:
2407	case VINF_EM_RESUME:
2408	case VINF_EM_RESCHEDULE:
2409	case VINF_EM_RESCHEDULE_REM:
2410	break;
2411
2412	/*
2413	* Up a level and invoke the debugger.
2414	*/
2415	case VINF_EM_DBG_STEPPED:
2416	case VINF_EM_DBG_BREAKPOINT:
2417	case VINF_EM_DBG_STEP:
2418	case VINF_EM_DBG_HYPER_ASSERTION:
2419	case VINF_EM_DBG_HYPER_BREAKPOINT:
2420	case VINF_EM_DBG_HYPER_STEPPED:
2421	case VINF_EM_DBG_STOP:
2422	break;
2423
2424	/*
2425	* Up a level, dump and debug.
2426	*/
2427	case VERR_TRPM_DONT_PANIC:
2428	case VERR_TRPM_PANIC:
2429	break;
2430
2431	/*
2432	* Anything which is not known to us means an internal error
2433	* and the termination of the VM!
2434	*/
2435	default:
2436	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2437	break;
2438	}
2439	return rc;
2440	}
2441
2442	/**
2443	* Check for pending raw actions
2444	*
2445	* @returns VBox status code.
2446	* @param pVM The VM to operate on.
2447	*/
2448	EMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2449	{
2450	return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2451	}
2452
2453
2454	/**
2455	* Process raw-mode specific forced actions.
2456	*
2457	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2458	*
2459	* @returns VBox status code.
2460	* Only the normal success/failure stuff, no VINF_EM_*.
2461	* @param pVM The VM handle.
2462	* @param pCtx The guest CPUM register context.
2463	*/
2464	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2465	{
2466	/*
2467	* Note that the order is vitally important!
2468	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2469	*/
2470
2471
2472	/*
2473	* Sync selector tables.
2474	*/
2475	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2476	{
2477	int rc = SELMR3UpdateFromCPUM(pVM);
2478	if (VBOX_FAILURE(rc))
2479	return rc;
2480	}
2481
2482	/*
2483	* Sync IDT.
2484	*/
2485	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2486	{
2487	int rc = TRPMR3SyncIDT(pVM);
2488	if (VBOX_FAILURE(rc))
2489	return rc;
2490	}
2491
2492	/*
2493	* Sync TSS.
2494	*/
2495	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2496	{
2497	int rc = SELMR3SyncTSS(pVM);
2498	if (VBOX_FAILURE(rc))
2499	return rc;
2500	}
2501
2502	/*
2503	* Sync page directory.
2504	*/
2505	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2506	{
2507	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2508	if (VBOX_FAILURE(rc))
2509	return rc;
2510
2511	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2512
2513	/* Prefetch pages for EIP and ESP */
2514	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2515	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip));
2516	if (rc == VINF_SUCCESS)
2517	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2518	if (rc != VINF_SUCCESS)
2519	{
2520	if (rc != VINF_PGM_SYNC_CR3)
2521	return rc;
2522	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2523	if (VBOX_FAILURE(rc))
2524	return rc;
2525	}
2526	/** @todo maybe prefetch the supervisor stack page as well */
2527	}
2528
2529	return VINF_SUCCESS;
2530	}
2531
2532
2533	/**
2534	* Executes raw code.
2535	*
2536	* This function contains the raw-mode version of the inner
2537	* execution loop (the outer loop being in EMR3ExecuteVM()).
2538	*
2539	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2540	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2541	*
2542	* @param pVM VM handle.
2543	* @param pfFFDone Where to store an indicator telling whether or not
2544	* FFs were done before returning.
2545	*/
2546	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2547	{
2548	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2549
2550	int rc = VERR_INTERNAL_ERROR;
2551	PCPUMCTX pCtx = pVM->em.s.pCtx;
2552	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2553	pVM->em.s.fForceRAW = false;
2554	*pfFFDone = false;
2555
2556
2557	/*
2558	*
2559	* Spin till we get a forced action or raw mode status code resulting in
2560	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2561	*
2562	*/
2563	for (;;)
2564	{
2565	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2566
2567	/*
2568	* Check various preconditions.
2569	*/
2570	#ifdef VBOX_STRICT
2571	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2572	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2573	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2574	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2575	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2576	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2577	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2578	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2579	{
2580	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2581	return VERR_INTERNAL_ERROR;
2582	}
2583	#endif /* VBOX_STRICT */
2584
2585	/*
2586	* Process high priority pre-execution raw-mode FFs.
2587	*/
2588	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2589	{
2590	rc = emR3RawForcedActions(pVM, pCtx);
2591	if (VBOX_FAILURE(rc))
2592	break;
2593	}
2594
2595	/*
2596	* If we're going to execute ring-0 code, the guest state needs to
2597	* be modified a bit and some of the state components (IF, SS/CS RPL,
2598	* and perhaps EIP) needs to be stored with PATM.
2599	*/
2600	rc = CPUMRawEnter(pVM, NULL);
2601	if (rc != VINF_SUCCESS)
2602	{
2603	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2604	break;
2605	}
2606
2607	/*
2608	* Scan code before executing it. Don't bother with user mode or V86 code
2609	*/
2610	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2611	&& !pCtx->eflags.Bits.u1VM
2612	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2613	{
2614	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2615	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2616	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2617	}
2618
2619	#ifdef LOG_ENABLED
2620	/*
2621	* Log important stuff before entering GC.
2622	*/
2623	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2624	if (pCtx->eflags.Bits.u1VM)
2625	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2626	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2627	{
2628	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2629	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2630	}
2631	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2632	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2633	#endif /* LOG_ENABLED */
2634
2635
2636
2637	/*
2638	* Execute the code.
2639	*/
2640	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2641	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2642	VMMR3Unlock(pVM);
2643	rc = VMMR3RawRunGC(pVM);
2644	VMMR3Lock(pVM);
2645	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2646	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2647
2648	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2649	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2650
2651	/*
2652	* Restore the real CPU state and deal with high priority post
2653	* execution FFs before doing anything else.
2654	*/
2655	rc = CPUMRawLeave(pVM, NULL, rc);
2656	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2657	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2658	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2659
2660	#ifdef PGM_CACHE_VERY_STRICT
2661	/*
2662	* Page manager cache checks.
2663	*/
2664	if ( rc == VINF_EM_RAW_INTERRUPT
2665	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2666	\|\| rc == VINF_IOM_HC_IOPORT_READ
2667	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2668	\|\| rc == VINF_IOM_HC_IOPORT_READWRITE
2669	//\|\| rc == VINF_PATM_PATCH_INT3
2670	)
2671	pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2672	#endif
2673
2674	#ifdef VBOX_STRICT
2675	/*
2676	* Assert TSS consistency & rc vs patch code.
2677	*/
2678	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2679	&& EMIsRawRing0Enabled(pVM))
2680	SELMR3CheckTSS(pVM);
2681	switch (rc)
2682	{
2683	case VINF_SUCCESS:
2684	case VINF_EM_RAW_INTERRUPT:
2685	case VINF_PATM_PATCH_TRAP_PF:
2686	case VINF_PATM_PATCH_TRAP_GP:
2687	case VINF_PATM_PATCH_INT3:
2688	case VINF_PATM_CHECK_PATCH_PAGE:
2689	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2690	case VINF_EM_RAW_GUEST_TRAP:
2691	case VINF_EM_RESCHEDULE_RAW:
2692	break;
2693
2694	default:
2695	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2696	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2697	break;
2698	}
2699	/*
2700	* Let's go paranoid!
2701	*/
2702	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2703	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2704	{
2705	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2706	return VERR_INTERNAL_ERROR;
2707	}
2708	#endif /* VBOX_STRICT */
2709
2710	/*
2711	* Process the returned status code.
2712	*/
2713	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2714	{
2715	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2716	break;
2717	}
2718	rc = emR3RawHandleRC(pVM, pCtx, rc);
2719	if (rc != VINF_SUCCESS)
2720	{
2721	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2722	if (rc != VINF_SUCCESS)
2723	{
2724	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2725	break;
2726	}
2727	}
2728
2729	/*
2730	* Check and execute forced actions.
2731	*/
2732	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2733	TMTimerPoll(pVM);
2734	#endif
2735	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2736	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2737	{
2738	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2739
2740	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2741	rc = emR3ForcedActions(pVM, rc);
2742	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2743	if ( rc != VINF_SUCCESS
2744	&& rc != VINF_EM_RESCHEDULE_RAW)
2745	{
2746	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2747	if (rc != VINF_SUCCESS)
2748	{
2749	*pfFFDone = true;
2750	break;
2751	}
2752	}
2753	}
2754	}
2755
2756	/*
2757	* Return to outer loop.
2758	*/
2759	#if defined(LOG_ENABLED) && defined(DEBUG)
2760	RTLogFlush(NULL);
2761	#endif
2762	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2763	return rc;
2764	}
2765
2766
2767	/**
2768	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2769	*
2770	* This function contains the raw-mode version of the inner
2771	* execution loop (the outer loop being in EMR3ExecuteVM()).
2772	*
2773	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2774	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2775	*
2776	* @param pVM VM handle.
2777	* @param pfFFDone Where to store an indicator telling whether or not
2778	* FFs were done before returning.
2779	*/
2780	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2781	{
2782	int rc = VERR_INTERNAL_ERROR;
2783	PCPUMCTX pCtx = pVM->em.s.pCtx;
2784
2785	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2786	*pfFFDone = false;
2787
2788	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2789
2790	/*
2791	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2792	*/
2793	for (;;)
2794	{
2795	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2796
2797	/*
2798	* Check various preconditions.
2799	*/
2800	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2801
2802	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2803
2804	/*
2805	* Sync page directory.
2806	*/
2807	if (VM_FF_ISPENDING(pVM, (VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)))
2808	{
2809	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2810	if (VBOX_FAILURE(rc))
2811	return rc;
2812
2813	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2814
2815	/* Prefetch pages for EIP and ESP */
2816	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip));
2817	if (rc == VINF_SUCCESS)
2818	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2819	if (rc != VINF_SUCCESS)
2820	{
2821	if (rc != VINF_PGM_SYNC_CR3)
2822	return rc;
2823	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2824	if (VBOX_FAILURE(rc))
2825	return rc;
2826	}
2827
2828	/** @todo maybe prefetch the supervisor stack page as well */
2829	}
2830
2831	#ifdef LOG_ENABLED
2832	uint8_t u8Vector;
2833
2834	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2835	if (rc == VINF_SUCCESS)
2836	{
2837	Log(("Pending hardware interrupt %d\n", u8Vector));
2838	}
2839	/*
2840	* Log important stuff before entering GC.
2841	*/
2842	if (pCtx->eflags.Bits.u1VM)
2843	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2844	else if ((pCtx->ss & X86_SEL_RPL) == 0)
2845	Log(("HWR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
2846	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2847	Log(("HWR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
2848	#endif
2849
2850
2851	/*
2852	* Execute the code.
2853	*/
2854	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2855	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2856	VMMR3Unlock(pVM);
2857	rc = VMMR3HwAccRunGC(pVM);
2858	VMMR3Lock(pVM);
2859	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2860
2861	/*
2862	* Deal with high priority post execution FFs before doing anything else.
2863	*/
2864	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2865	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2866	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2867
2868	/*
2869	* Process the returned status code.
2870	*/
2871	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2872	break;
2873
2874	rc = emR3RawHandleRC(pVM, pCtx, rc);
2875	if (rc != VINF_SUCCESS)
2876	break;
2877
2878	/*
2879	* Check and execute forced actions.
2880	*/
2881	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2882	TMTimerPoll(pVM);
2883	#endif
2884	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2885	{
2886	rc = emR3ForcedActions(pVM, rc);
2887	if ( rc != VINF_SUCCESS
2888	&& rc != VINF_EM_RESCHEDULE_HWACC)
2889	{
2890	*pfFFDone = true;
2891	break;
2892	}
2893	}
2894	}
2895	/*
2896	* Return to outer loop.
2897	*/
2898	#if defined(LOG_ENABLED) && defined(DEBUG)
2899	RTLogFlush(NULL);
2900	#endif
2901	return rc;
2902	}
2903
2904
2905	/**
2906	* Decides whether to execute RAW, HWACC or REM.
2907	*
2908	* @returns new EM state
2909	* @param pVM The VM.
2910	* @param pCtx The CPU context.
2911	*/
2912	inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2913	{
2914	/*
2915	* When forcing raw-mode execution, things are simple.
2916	*/
2917	if (pVM->em.s.fForceRAW)
2918	return EMSTATE_RAW;
2919
2920	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2921	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2922	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2923
2924	X86EFLAGS EFlags = pCtx->eflags;
2925	if (HWACCMIsEnabled(pVM))
2926	{
2927	/* Hardware accelerated raw-mode:
2928	*
2929	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2930	*/
2931	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2932	return EMSTATE_HWACC;
2933
2934	/** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2935	return EMSTATE_REM;
2936	}
2937
2938	/* Standard raw-mode:
2939	*
2940	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2941	* or 32 bits protected mode ring 0 code
2942	*
2943	* The tests are ordered by the likelyhood of being true during normal execution.
2944	*/
2945	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2946	{
2947	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2948	return EMSTATE_REM;
2949	}
2950
2951	#ifndef VBOX_RAW_V86
2952	if (EFlags.u32 & X86_EFL_VM) {
2953	Log2(("raw mode refused: VM_MASK\n"));
2954	return EMSTATE_REM;
2955	}
2956	#endif
2957
2958	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2959	uint32_t u32CR0 = pCtx->cr0;
2960	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2961	{
2962	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2963	return EMSTATE_REM;
2964	}
2965
2966	if (pCtx->cr4 & X86_CR4_PAE)
2967	{
2968	//Log2(("raw mode refused: PAE\n"));
2969	return EMSTATE_REM;
2970	}
2971
2972	unsigned uSS = pCtx->ss;
2973	if ( pCtx->eflags.Bits.u1VM
2974	\|\| (uSS & X86_SEL_RPL) == 3)
2975	{
2976	if (!EMIsRawRing3Enabled(pVM))
2977	return EMSTATE_REM;
2978
2979	if (!(EFlags.u32 & X86_EFL_IF))
2980	{
2981	Log2(("raw mode refused: IF (RawR3)\n"));
2982	return EMSTATE_REM;
2983	}
2984
2985	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2986	{
2987	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2988	return EMSTATE_REM;
2989	}
2990	}
2991	else
2992	{
2993	if (!EMIsRawRing0Enabled(pVM))
2994	return EMSTATE_REM;
2995
2996	/* Only ring 0 supervisor code. */
2997	if ((uSS & X86_SEL_RPL) != 0)
2998	{
2999	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
3000	return EMSTATE_REM;
3001	}
3002
3003	// Let's start with pure 32 bits ring 0 code first
3004	/** @todo What's pure 32-bit mode? flat? */
3005	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
3006	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
3007	{
3008	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
3009	return EMSTATE_REM;
3010	}
3011
3012	/* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
3013	if (!(u32CR0 & X86_CR0_WP))
3014	{
3015	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
3016	return EMSTATE_REM;
3017	}
3018
3019	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
3020	{
3021	Log2(("raw r0 mode forced: patch code\n"));
3022	return EMSTATE_RAW;
3023	}
3024
3025	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
3026	if (!(EFlags.u32 & X86_EFL_IF))
3027	{
3028	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
3029	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
3030	return EMSTATE_REM;
3031	}
3032	#endif
3033
3034	/** @todo still necessary??? */
3035	if (EFlags.Bits.u2IOPL != 0)
3036	{
3037	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
3038	return EMSTATE_REM;
3039	}
3040	}
3041
3042	Assert(PGMPhysIsA20Enabled(pVM));
3043	return EMSTATE_RAW;
3044	}
3045
3046
3047	/**
3048	* Executes all high priority post execution force actions.
3049	*
3050	* @returns rc or a fatal status code.
3051	*
3052	* @param pVM VM handle.
3053	* @param rc The current rc.
3054	*/
3055	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
3056	{
3057	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
3058	PDMR3CritSectFF(pVM);
3059
3060	if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
3061	CSAMR3DoPendingAction(pVM);
3062
3063	return rc;
3064	}
3065
3066
3067	/**
3068	* Executes all pending forced actions.
3069	*
3070	* Forced actions can cause execution delays and execution
3071	* rescheduling. The first we deal with using action priority, so
3072	* that for instance pending timers aren't scheduled and ran until
3073	* right before execution. The rescheduling we deal with using
3074	* return codes. The same goes for VM termination, only in that case
3075	* we exit everything.
3076	*
3077	* @returns VBox status code of equal or greater importance/severity than rc.
3078	* The most important ones are: VINF_EM_RESCHEDULE,
3079	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3080	*
3081	* @param pVM VM handle.
3082	* @param rc The current rc.
3083	*
3084	*/
3085	static int emR3ForcedActions(PVM pVM, int rc)
3086	{
3087	#ifdef VBOX_STRICT
3088	int rcIrq = VINF_SUCCESS;
3089	#endif
3090	STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
3091
3092	#define UPDATE_RC() \
3093	do { \
3094	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
3095	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
3096	break; \
3097	if (!rc \|\| rc2 < rc) \
3098	rc = rc2; \
3099	} while (0)
3100
3101	int rc2;
3102
3103	/*
3104	* Post execution chunk first.
3105	*/
3106	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
3107	{
3108	/*
3109	* Termination request.
3110	*/
3111	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3112	{
3113	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3114	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3115	return VINF_EM_TERMINATE;
3116	}
3117
3118	/*
3119	* Debugger Facility polling.
3120	*/
3121	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3122	{
3123	rc2 = DBGFR3VMMForcedAction(pVM);
3124	UPDATE_RC();
3125	}
3126
3127	/*
3128	* Postponed reset request.
3129	*/
3130	if (VM_FF_ISSET(pVM, VM_FF_RESET))
3131	{
3132	rc2 = VMR3Reset(pVM);
3133	UPDATE_RC();
3134	VM_FF_CLEAR(pVM, VM_FF_RESET);
3135	}
3136
3137	/*
3138	* CSAM page scanning.
3139	*/
3140	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
3141	{
3142	PCPUMCTX pCtx = pVM->em.s.pCtx;
3143
3144	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3145	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3146
3147	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
3148	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3149	}
3150
3151	/* check that we got them all */
3152	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
3153	}
3154
3155	/*
3156	* Normal priority then.
3157	* (Executed in no particular order.)
3158	*/
3159	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3160	{
3161	/*
3162	* PDM Queues are pending.
3163	*/
3164	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3165	PDMR3QueueFlushAll(pVM);
3166
3167	/*
3168	* PDM DMA transfers are pending.
3169	*/
3170	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3171	PDMR3DmaRun(pVM);
3172
3173	/*
3174	* Requests from other threads.
3175	*/
3176	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3177	{
3178	rc2 = VMR3ReqProcess(pVM);
3179	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3180	{
3181	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3182	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3183	return rc2;
3184	}
3185	UPDATE_RC();
3186	}
3187
3188	/* check that we got them all */
3189	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA)));
3190	}
3191
3192	/*
3193	* Execute polling function ever so often.
3194	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING SOON!
3195	*/
3196	static unsigned cLast = 0;
3197	if (!((++cLast) % 4))
3198	PDMR3Poll(pVM);
3199
3200	/*
3201	* High priority pre execution chunk last.
3202	* (Executed in ascending priority order.)
3203	*/
3204	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3205	{
3206	/*
3207	* Timers before interrupts.
3208	*/
3209	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3210	TMR3TimerQueuesDo(pVM);
3211
3212	/*
3213	* The instruction following an emulated STI should always be executed!
3214	*/
3215	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3216	{
3217	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3218	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3219	{
3220	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3221	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3222	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3223	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3224	*/
3225	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3226	}
3227	if (HWACCMR3IsActive(pVM))
3228	rc2 = VINF_EM_RESCHEDULE_HWACC;
3229	else
3230	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3231
3232	UPDATE_RC();
3233	}
3234
3235	/*
3236	* Interrupts.
3237	*/
3238	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3239	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3240	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3241	&& PATMAreInterruptsEnabled(pVM)
3242	&& !HWACCMR3IsEventPending(pVM))
3243	{
3244	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3245	{
3246	/** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3247	/** @todo this really isn't nice, should properly handle this */
3248	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3249	#ifdef VBOX_STRICT
3250	rcIrq = rc2;
3251	#endif
3252	UPDATE_RC();
3253	}
3254	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3255	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3256	{
3257	rc2 = VINF_EM_RESCHEDULE_REM;
3258	UPDATE_RC();
3259	}
3260	}
3261
3262	/*
3263	* Debugger Facility request.
3264	*/
3265	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3266	{
3267	rc2 = DBGFR3VMMForcedAction(pVM);
3268	UPDATE_RC();
3269	}
3270
3271	/*
3272	* Termination request.
3273	*/
3274	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3275	{
3276	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3277	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3278	return VINF_EM_TERMINATE;
3279	}
3280
3281	#ifdef DEBUG
3282	/*
3283	* Debug, pause the VM.
3284	*/
3285	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3286	{
3287	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3288	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3289	return VINF_EM_SUSPEND;
3290	}
3291
3292	#endif
3293	/* check that we got them all */
3294	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS)));
3295	}
3296
3297	#undef UPDATE_RC
3298	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3299	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3300	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3301	return rc;
3302	}
3303
3304
3305	/**
3306	* Execute VM.
3307	*
3308	* This function is the main loop of the VM. The emulation thread
3309	* calls this function when the VM has been successfully constructed
3310	* and we're ready for executing the VM.
3311	*
3312	* Returning from this function means that the VM is turned off or
3313	* suspended (state already saved) and deconstruction in next in line.
3314	*
3315	* All interaction from other thread are done using forced actions
3316	* and signaling of the wait object.
3317	*
3318	* @returns VBox status code.
3319	* @param pVM The VM to operate on.
3320	*/
3321	EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3322	{
3323	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3324	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3325	VM_ASSERT_EMT(pVM);
3326	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3327
3328	VMMR3Lock(pVM);
3329
3330	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3331	if (rc == 0)
3332	{
3333	/*
3334	* Start the virtual time.
3335	*/
3336	rc = TMVirtualResume(pVM);
3337	Assert(rc == VINF_SUCCESS);
3338	rc = TMCpuTickResume(pVM);
3339	Assert(rc == VINF_SUCCESS);
3340
3341	/*
3342	* The Outer Main Loop.
3343	*/
3344	bool fFFDone = false;
3345	rc = VINF_EM_RESCHEDULE;
3346	pVM->em.s.enmState = EMSTATE_REM;
3347	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3348	for (;;)
3349	{
3350	/*
3351	* Before we can schedule anything (we're here because
3352	* scheduling is required) we must service any pending
3353	* forced actions to avoid any pending action causing
3354	* immidate rescheduling upon entering an inner loop
3355	*
3356	* Do forced actions.
3357	*/
3358	if ( !fFFDone
3359	&& rc != VINF_EM_TERMINATE
3360	&& rc != VINF_EM_OFF
3361	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3362	{
3363	rc = emR3ForcedActions(pVM, rc);
3364	if ( ( rc == VINF_EM_RESCHEDULE_REM
3365	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3366	&& pVM->em.s.fForceRAW)
3367	rc = VINF_EM_RESCHEDULE_RAW;
3368	}
3369	else if (fFFDone)
3370	fFFDone = false;
3371
3372	/*
3373	* Now what to do?
3374	*/
3375	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3376	switch (rc)
3377	{
3378	/*
3379	* Keep doing what we're currently doing.
3380	*/
3381	case VINF_SUCCESS:
3382	break;
3383
3384	/*
3385	* Reschedule - to raw-mode execution.
3386	*/
3387	case VINF_EM_RESCHEDULE_RAW:
3388	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3389	pVM->em.s.enmState = EMSTATE_RAW;
3390	break;
3391
3392	/*
3393	* Reschedule - to hardware accelerated raw-mode execution.
3394	*/
3395	case VINF_EM_RESCHEDULE_HWACC:
3396	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3397	Assert(!pVM->em.s.fForceRAW);
3398	pVM->em.s.enmState = EMSTATE_HWACC;
3399	break;
3400
3401	/*
3402	* Reschedule - to recompiled execution.
3403	*/
3404	case VINF_EM_RESCHEDULE_REM:
3405	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3406	pVM->em.s.enmState = EMSTATE_REM;
3407	break;
3408
3409	/*
3410	* Resume.
3411	*/
3412	case VINF_EM_RESUME:
3413	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3414	/* fall through and get scheduled. */
3415
3416	/*
3417	* Reschedule.
3418	*/
3419	case VINF_EM_RESCHEDULE:
3420	{
3421	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3422	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3423	pVM->em.s.enmState = enmState;
3424	break;
3425	}
3426
3427	/*
3428	* Halted.
3429	*/
3430	case VINF_EM_HALT:
3431	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3432	pVM->em.s.enmState = EMSTATE_HALTED;
3433	break;
3434
3435	/*
3436	* Suspend.
3437	*/
3438	case VINF_EM_SUSPEND:
3439	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3440	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3441	break;
3442
3443	/*
3444	* Reset.
3445	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3446	*/
3447	case VINF_EM_RESET:
3448	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3449	pVM->em.s.enmState = EMSTATE_REM;
3450	break;
3451
3452	/*
3453	* Power Off.
3454	*/
3455	case VINF_EM_OFF:
3456	pVM->em.s.enmState = EMSTATE_TERMINATING;
3457	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3458	TMVirtualPause(pVM);
3459	TMCpuTickPause(pVM);
3460	VMMR3Unlock(pVM);
3461	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3462	return rc;
3463
3464	/*
3465	* Terminate the VM.
3466	*/
3467	case VINF_EM_TERMINATE:
3468	pVM->em.s.enmState = EMSTATE_TERMINATING;
3469	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3470	TMVirtualPause(pVM);
3471	TMCpuTickPause(pVM);
3472	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3473	return rc;
3474
3475	/*
3476	* Guest debug events.
3477	*/
3478	case VINF_EM_DBG_STEPPED:
3479	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3480	case VINF_EM_DBG_STOP:
3481	case VINF_EM_DBG_BREAKPOINT:
3482	case VINF_EM_DBG_STEP:
3483	if (pVM->em.s.enmState == EMSTATE_RAW)
3484	{
3485	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3486	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3487	}
3488	else
3489	{
3490	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3491	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3492	}
3493	break;
3494
3495	/*
3496	* Hypervisor debug events.
3497	*/
3498	case VINF_EM_DBG_HYPER_STEPPED:
3499	case VINF_EM_DBG_HYPER_BREAKPOINT:
3500	case VINF_EM_DBG_HYPER_ASSERTION:
3501	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3502	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3503	break;
3504
3505	/*
3506	* Any error code showing up here other than the ones we
3507	* know and process above are considered to be FATAL.
3508	*
3509	* Unknown warnings and informational status codes are also
3510	* included in this.
3511	*/
3512	default:
3513	if (VBOX_SUCCESS(rc))
3514	{
3515	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3516	rc = VERR_EM_INTERNAL_ERROR;
3517	}
3518	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3519	Log(("EMR3ExecuteVM returns %d\n", rc));
3520	break;
3521	}
3522
3523
3524	/*
3525	* Any waiters can now be woken up
3526	*/
3527	VMMR3Unlock(pVM);
3528	VMMR3Lock(pVM);
3529
3530	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3531	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3532
3533	/*
3534	* Act on the state.
3535	*/
3536	switch (pVM->em.s.enmState)
3537	{
3538	/*
3539	* Execute raw.
3540	*/
3541	case EMSTATE_RAW:
3542	rc = emR3RawExecute(pVM, &fFFDone);
3543	break;
3544
3545	/*
3546	* Execute hardware accelerated raw.
3547	*/
3548	case EMSTATE_HWACC:
3549	rc = emR3HwAccExecute(pVM, &fFFDone);
3550	break;
3551
3552	/*
3553	* Execute recompiled.
3554	*/
3555	case EMSTATE_REM:
3556	rc = emR3RemExecute(pVM, &fFFDone);
3557	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3558	break;
3559
3560	/*
3561	* hlt - execution halted until interrupt.
3562	*/
3563	case EMSTATE_HALTED:
3564	{
3565	STAM_PROFILE_START(&pVM->em.s.StatHalted, y);
3566	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3567	STAM_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3568	break;
3569	}
3570
3571	/*
3572	* Suspended - return to VM.cpp.
3573	*/
3574	case EMSTATE_SUSPENDED:
3575	TMVirtualPause(pVM);
3576	TMCpuTickPause(pVM);
3577	VMMR3Unlock(pVM);
3578	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3579	return VINF_EM_SUSPEND;
3580
3581	/*
3582	* Debugging in the guest.
3583	*/
3584	case EMSTATE_DEBUG_GUEST_REM:
3585	case EMSTATE_DEBUG_GUEST_RAW:
3586	TMVirtualPause(pVM);
3587	TMCpuTickPause(pVM);
3588	rc = emR3Debug(pVM, rc);
3589	TMVirtualResume(pVM);
3590	TMCpuTickResume(pVM);
3591	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3592	break;
3593
3594	/*
3595	* Debugging in the hypervisor.
3596	*/
3597	case EMSTATE_DEBUG_HYPER:
3598	{
3599	TMVirtualPause(pVM);
3600	TMCpuTickPause(pVM);
3601	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3602
3603	rc = emR3Debug(pVM, rc);
3604	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3605	if (rc != VINF_SUCCESS)
3606	{
3607	/* switch to guru meditation mode */
3608	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3609	VMMR3FatalDump(pVM, rc);
3610	return rc;
3611	}
3612
3613	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3614	TMVirtualResume(pVM);
3615	TMCpuTickResume(pVM);
3616	break;
3617	}
3618
3619	/*
3620	* Guru meditation takes place in the debugger.
3621	*/
3622	case EMSTATE_GURU_MEDITATION:
3623	{
3624	/** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3625	TMVirtualPause(pVM);
3626	TMCpuTickPause(pVM);
3627	VMMR3FatalDump(pVM, rc);
3628	int rc2 = emR3Debug(pVM, rc);
3629	if (rc2 == VERR_DBGF_NOT_ATTACHED)
3630	{
3631	VMMR3Unlock(pVM);
3632	/** @todo change the VM state! */
3633	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3634	return rc;
3635	}
3636	TMVirtualResume(pVM);
3637	TMCpuTickResume(pVM);
3638	rc = rc2;
3639	/** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3640	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3641	break;
3642	}
3643
3644	/*
3645	* The states we don't expect here.
3646	*/
3647	case EMSTATE_NONE:
3648	case EMSTATE_TERMINATING:
3649	default:
3650	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3651	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3652	TMVirtualPause(pVM);
3653	TMCpuTickPause(pVM);
3654	VMMR3Unlock(pVM);
3655	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3656	return VERR_EM_INTERNAL_ERROR;
3657	}
3658	} /* The Outer Main Loop */
3659	}
3660	else
3661	{
3662	/*
3663	* Fatal error.
3664	*/
3665	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3666	TMVirtualPause(pVM);
3667	TMCpuTickPause(pVM);
3668	VMMR3FatalDump(pVM, rc);
3669	emR3Debug(pVM, rc);
3670	VMMR3Unlock(pVM);
3671	/** @todo change the VM state! */
3672	return rc;
3673	}
3674
3675	/* (won't ever get here). */
3676	AssertFailed();
3677	}
3678

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 2132

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