VirtualBox

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 2227

Last change on this file since 2227 was 2226, checked in by vboxsync, 18 years ago

Cleanup of emR3RawExecuteIOInstruction: use existing IOM functions.
Moved IOMInterpretIN & IOMInterpretOUT to the VMMAll directory.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 140.7 KB
Line 
1/* $Id: EM.cpp 2226 2007-04-19 13:48:01Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor/Manager.
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22
23/** @page pg_em EM - The Execution Monitor/Manager
24 *
25 * The Execution Monitor/Manager is responsible for running the VM, scheduling
26 * the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27 * the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28 * the VM.
29 *
30 */
31
32/*******************************************************************************
33* Header Files *
34*******************************************************************************/
35#define LOG_GROUP LOG_GROUP_EM
36#include <VBox/em.h>
37#include <VBox/vmm.h>
38#include <VBox/patm.h>
39#include <VBox/csam.h>
40#include <VBox/selm.h>
41#include <VBox/trpm.h>
42#include <VBox/iom.h>
43#include <VBox/dbgf.h>
44#include <VBox/pgm.h>
45#include <VBox/rem.h>
46#include <VBox/tm.h>
47#include <VBox/mm.h>
48#include <VBox/pdm.h>
49#include <VBox/hwaccm.h>
50#include <VBox/patm.h>
51#include "EMInternal.h"
52#include <VBox/vm.h>
53#include <VBox/cpumdis.h>
54#include <VBox/dis.h>
55#include <VBox/disopcode.h>
56#include <VBox/dbgf.h>
57
58#include <VBox/log.h>
59#include <iprt/thread.h>
60#include <iprt/assert.h>
61#include <iprt/asm.h>
62#include <iprt/semaphore.h>
63#include <iprt/string.h>
64#include <iprt/avl.h>
65#include <iprt/stream.h>
66#include <VBox/param.h>
67#include <VBox/err.h>
68
69
70/*******************************************************************************
71* Internal Functions *
72*******************************************************************************/
73static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
74static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
75static int emR3Debug(PVM pVM, int rc);
76static int emR3RemStep(PVM pVM);
77static int emR3RemExecute(PVM pVM, bool *pfFFDone);
78static int emR3RawResumeHyper(PVM pVM);
79static int emR3RawStep(PVM pVM);
80DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
81DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
82static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
83static int emR3RawExecute(PVM pVM, bool *pfFFDone);
84DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
85static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
86static int emR3ForcedActions(PVM pVM, int rc);
87static int emR3RawGuestTrap(PVM pVM);
88
89
90/**
91 * Initializes the EM.
92 *
93 * @returns VBox status code.
94 * @param pVM The VM to operate on.
95 */
96EMR3DECL(int) EMR3Init(PVM pVM)
97{
98 LogFlow(("EMR3Init\n"));
99 /*
100 * Assert alignment and sizes.
101 */
102 AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
103 AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
104 AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
105 ("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
106
107 /*
108 * Init the structure.
109 */
110 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
111 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
112 if (VBOX_FAILURE(rc))
113 pVM->fRawR3Enabled = true;
114 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
115 if (VBOX_FAILURE(rc))
116 pVM->fRawR0Enabled = true;
117 Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
118 pVM->em.s.enmState = EMSTATE_NONE;
119 pVM->em.s.fForceRAW = false;
120
121 rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
122 AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
123 pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
124 AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
125
126 /*
127 * Saved state.
128 */
129 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
130 NULL, emR3Save, NULL,
131 NULL, emR3Load, NULL);
132 if (VBOX_FAILURE(rc))
133 return rc;
134
135 /*
136 * Statistics.
137 */
138#ifdef VBOX_WITH_STATISTICS
139 PEMSTATS pStats;
140 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
141 if (VBOX_FAILURE(rc))
142 return rc;
143 pVM->em.s.pStatsHC = pStats;
144 pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
145
146 STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
147 STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
148
149 STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
150 STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
151
152 STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
153 STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
154 STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
155 STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
156 STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
157 STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
158 STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
159 STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
160 STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
161 STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
162 STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
163 STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
164 STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
165 STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
166 STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
167 STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
168 STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
169 STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
170 STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
171 STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
172 STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
173 STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
174 STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
175 STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
176 STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
177 STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
178 STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
179 STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
180 STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
181 STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
182 STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
183 STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
184 STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
185 STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
186 STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
187 STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
188 STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
189 STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
190 STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
191 STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
192 STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
193 STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
194 STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
195 STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
196 STAM_REG_USED(pVM, &pStats->StatGCBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
197 STAM_REG_USED(pVM, &pStats->StatHCBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
198 STAM_REG_USED(pVM, &pStats->StatGCBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
199 STAM_REG_USED(pVM, &pStats->StatHCBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
200 STAM_REG_USED(pVM, &pStats->StatGCBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
201 STAM_REG_USED(pVM, &pStats->StatHCBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
202 STAM_REG_USED(pVM, &pStats->StatGCCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
203 STAM_REG_USED(pVM, &pStats->StatHCCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
204
205 STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
206 STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
207
208 STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
209 STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
210 STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
211 STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
212 STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
213 STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
214 STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
215 STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
216 STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
217 STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
218 STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
219 STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
220 STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
221 STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
222 STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
223 STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
224 STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
225 STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
226 STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
227 STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
228 STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
229 STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
230 STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
231 STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
232 STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
233 STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
234 STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
235 STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
236 STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
237 STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
238 STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
239 STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
240 STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
241 STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
242 STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
243 STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
244 STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
245 STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
246
247 STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
248 STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
249 STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
250 STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
251 STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
252 STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
253 STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
254 STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
255 STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
256 STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
257 STAM_REG_USED(pVM, &pStats->StatGCFailedBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
258 STAM_REG_USED(pVM, &pStats->StatHCFailedBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
259 STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
260 STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
261 STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
262 STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
263 STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
264 STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
265 STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
266 STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
267 STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
268 STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
269 STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
270 STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
271
272 STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
273 STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
274 STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
275 STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
276
277 STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
278 STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
279 STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
280 STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
281 STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
282 STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
283 STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
284 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
285 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
286 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
287 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
288 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
289 STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
290 STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
291 STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
292 STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
293 STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
294 STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
295 STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
296 STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
297 STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
298 STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
299 STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
300 STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
301 STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
302 STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
303
304 STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
305 pVM->em.s.pCliStatTree = 0;
306#endif /* VBOX_WITH_STATISTICS */
307
308/* these should be considered for release statistics. */
309 STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
310 STAM_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
311 STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
312 STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
313 STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
314 STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
315 STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
316 STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
317 STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
318 STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
319 STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
320 STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
321 STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
322 STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
323 STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
324 STAM_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
325
326
327 return VINF_SUCCESS;
328}
329
330
331
332/**
333 * Applies relocations to data and code managed by this
334 * component. This function will be called at init and
335 * whenever the VMM need to relocate it self inside the GC.
336 *
337 * @param pVM The VM.
338 */
339EMR3DECL(void) EMR3Relocate(PVM pVM)
340{
341 LogFlow(("EMR3Relocate\n"));
342 if (pVM->em.s.pStatsHC)
343 pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
344}
345
346
347/**
348 * Reset notification.
349 *
350 * @param pVM
351 */
352EMR3DECL(void) EMR3Reset(PVM pVM)
353{
354 LogFlow(("EMR3Reset: \n"));
355 pVM->em.s.fForceRAW = false;
356}
357
358
359/**
360 * Terminates the EM.
361 *
362 * Termination means cleaning up and freeing all resources,
363 * the VM it self is at this point powered off or suspended.
364 *
365 * @returns VBox status code.
366 * @param pVM The VM to operate on.
367 */
368EMR3DECL(int) EMR3Term(PVM pVM)
369{
370 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
371
372 return VINF_SUCCESS;
373}
374
375
376/**
377 * Execute state save operation.
378 *
379 * @returns VBox status code.
380 * @param pVM VM Handle.
381 * @param pSSM SSM operation handle.
382 */
383static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
384{
385 return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
386}
387
388
389/**
390 * Execute state load operation.
391 *
392 * @returns VBox status code.
393 * @param pVM VM Handle.
394 * @param pSSM SSM operation handle.
395 * @param u32Version Data layout version.
396 */
397static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
398{
399 /*
400 * Validate version.
401 */
402 if (u32Version != EM_SAVED_STATE_VERSION)
403 {
404 Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
405 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
406 }
407
408 /*
409 * Load the saved state.
410 */
411 int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
412 if (VBOX_FAILURE(rc))
413 pVM->em.s.fForceRAW = false;
414
415 Assert(pVM->em.s.pCliStatTree == 0);
416 return rc;
417}
418
419
420/**
421 * Enables or disables a set of raw-mode execution modes.
422 *
423 * @returns VINF_SUCCESS on success.
424 * @returns VINF_RESCHEDULE if a rescheduling might be required.
425 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
426 *
427 * @param pVM The VM to operate on.
428 * @param enmMode The execution mode change.
429 * @thread The emulation thread.
430 */
431EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
432{
433 switch (enmMode)
434 {
435 case EMRAW_NONE:
436 pVM->fRawR3Enabled = false;
437 pVM->fRawR0Enabled = false;
438 break;
439 case EMRAW_RING3_ENABLE:
440 pVM->fRawR3Enabled = true;
441 break;
442 case EMRAW_RING3_DISABLE:
443 pVM->fRawR3Enabled = false;
444 break;
445 case EMRAW_RING0_ENABLE:
446 pVM->fRawR0Enabled = true;
447 break;
448 case EMRAW_RING0_DISABLE:
449 pVM->fRawR0Enabled = false;
450 break;
451 default:
452 AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
453 return VERR_INVALID_PARAMETER;
454 }
455 Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
456 pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
457 return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
458}
459
460
461/**
462 * Raise a fatal error.
463 *
464 * Safely terminate the VM with full state report and stuff. This function
465 * will naturally never return.
466 *
467 * @param pVM VM handle.
468 * @param rc VBox status code.
469 */
470EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
471{
472 longjmp(pVM->em.s.u.FatalLongJump, rc);
473 AssertReleaseMsgFailed(("longjmp returned!\n"));
474}
475
476
477/**
478 * Gets the EM state name.
479 *
480 * @returns pointer to read only state name,
481 * @param enmState The state.
482 */
483EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
484{
485 switch (enmState)
486 {
487 case EMSTATE_RAW: return "EMSTATE_RAW";
488 case EMSTATE_HWACC: return "EMSTATE_HWACC";
489 case EMSTATE_REM: return "EMSTATE_REM";
490 case EMSTATE_HALTED: return "EMSTATE_HALTED";
491 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
492 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
493 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
494 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
495 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
496 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
497 default: return "Unknown!";
498 }
499}
500
501
502#ifdef VBOX_WITH_STATISTICS
503/**
504 * Just a braindead function to keep track of cli addresses.
505 * @param pVM VM handle.
506 * @param pInstrGC The EIP of the cli instruction.
507 */
508static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
509{
510 PCLISTAT pRec;
511
512 pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
513 if (!pRec)
514 {
515 /* New cli instruction; insert into the tree. */
516 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
517 Assert(pRec);
518 if (!pRec)
519 return;
520 pRec->Core.Key = (AVLPVKEY)pInstrGC;
521
522 char szCliStatName[32];
523 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
524 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
525
526 bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
527 Assert(fRc); NOREF(fRc);
528 }
529 STAM_COUNTER_INC(&pRec->Counter);
530 STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
531}
532#endif /* VBOX_WITH_STATISTICS */
533
534
535/**
536 * Debug loop.
537 *
538 * @returns VBox status code for EM.
539 * @param pVM VM handle.
540 * @param rc Current EM VBox status code..
541 */
542static int emR3Debug(PVM pVM, int rc)
543{
544 for (;;)
545 {
546 Log(("emR3Debug: rc=%Vrc\n", rc));
547 const int rcLast = rc;
548
549 /*
550 * Debug related RC.
551 */
552 switch (rc)
553 {
554 /*
555 * Single step an instruction.
556 */
557 case VINF_EM_DBG_STEP:
558 if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
559 || pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
560 || pVM->em.s.fForceRAW /* paranoia */)
561 rc = emR3RawStep(pVM);
562 else
563 {
564 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
565 rc = emR3RemStep(pVM);
566 }
567 break;
568
569 /*
570 * Simple events: stepped, breakpoint, stop/assertion.
571 */
572 case VINF_EM_DBG_STEPPED:
573 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
574 break;
575
576 case VINF_EM_DBG_BREAKPOINT:
577 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
578 break;
579
580 case VINF_EM_DBG_STOP:
581 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
582 break;
583
584 case VINF_EM_DBG_HYPER_STEPPED:
585 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
586 break;
587
588 case VINF_EM_DBG_HYPER_BREAKPOINT:
589 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
590 break;
591
592 case VINF_EM_DBG_HYPER_ASSERTION:
593 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
594 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
595 break;
596
597 /*
598 * Guru meditation.
599 */
600 default: /** @todo don't use default for guru, but make special errors code! */
601 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
602 break;
603 }
604
605 /*
606 * Process the result.
607 */
608 do
609 {
610 switch (rc)
611 {
612 /*
613 * Continue the debugging loop.
614 */
615 case VINF_EM_DBG_STEP:
616 case VINF_EM_DBG_STOP:
617 case VINF_EM_DBG_STEPPED:
618 case VINF_EM_DBG_BREAKPOINT:
619 case VINF_EM_DBG_HYPER_STEPPED:
620 case VINF_EM_DBG_HYPER_BREAKPOINT:
621 case VINF_EM_DBG_HYPER_ASSERTION:
622 break;
623
624 /*
625 * Resuming execution (in some form) has to be done here if we got
626 * a hypervisor debug event.
627 */
628 case VINF_SUCCESS:
629 case VINF_EM_RESUME:
630 case VINF_EM_SUSPEND:
631 case VINF_EM_RESCHEDULE:
632 case VINF_EM_RESCHEDULE_RAW:
633 case VINF_EM_RESCHEDULE_REM:
634 case VINF_EM_HALT:
635 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
636 {
637 rc = emR3RawResumeHyper(pVM);
638 if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
639 continue;
640 }
641 if (rc == VINF_SUCCESS)
642 rc = VINF_EM_RESCHEDULE;
643 return rc;
644
645 /*
646 * The debugger isn't attached.
647 * We'll simply turn the thing off since that's the easiest thing to do.
648 */
649 case VERR_DBGF_NOT_ATTACHED:
650 switch (rcLast)
651 {
652 case VINF_EM_DBG_HYPER_ASSERTION:
653 case VINF_EM_DBG_HYPER_STEPPED:
654 case VINF_EM_DBG_HYPER_BREAKPOINT:
655 return rcLast;
656 }
657 return VINF_EM_OFF;
658
659 /*
660 * Status codes terminating the VM in one or another sense.
661 */
662 case VINF_EM_TERMINATE:
663 case VINF_EM_OFF:
664 case VINF_EM_RESET:
665 case VINF_EM_RAW_STALE_SELECTOR:
666 case VINF_EM_RAW_IRET_TRAP:
667 case VERR_TRPM_PANIC:
668 case VERR_TRPM_DONT_PANIC:
669 case VERR_INTERNAL_ERROR:
670 return rc;
671
672 /*
673 * The rest is unexpected, and will keep us here.
674 */
675 default:
676 AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
677 break;
678 }
679 } while (false);
680 } /* debug for ever */
681}
682
683
684/**
685 * Steps recompiled code.
686 *
687 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
688 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
689 *
690 * @param pVM VM handle.
691 */
692static int emR3RemStep(PVM pVM)
693{
694 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
695
696 /*
697 * Switch to REM, step instruction, switch back.
698 */
699 int rc = REMR3State(pVM);
700 if (VBOX_SUCCESS(rc))
701 {
702 rc = REMR3Step(pVM);
703 REMR3StateBack(pVM);
704 }
705 LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
706 return rc;
707}
708
709/**
710 * Executes recompiled code.
711 *
712 * This function contains the recompiler version of the inner
713 * execution loop (the outer loop being in EMR3ExecuteVM()).
714 *
715 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
716 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
717 *
718 * @param pVM VM handle.
719 * @param pfFFDone Where to store an indicator telling wheter or not
720 * FFs were done before returning.
721 *
722 */
723static int emR3RemExecute(PVM pVM, bool *pfFFDone)
724{
725#ifdef LOG_ENABLED
726 PCPUMCTX pCtx = pVM->em.s.pCtx;
727 if (pCtx->eflags.Bits.u1VM)
728 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
729 else if ((pCtx->ss & X86_SEL_RPL) == 0)
730 Log(("EMR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
731 else if ((pCtx->ss & X86_SEL_RPL) == 3)
732 Log(("EMR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
733#endif
734 STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
735
736#if defined(VBOX_STRICT) && defined(DEBUG_bird)
737 AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
738 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
739 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
740#endif
741
742 /*
743 * Spin till we get a forced action which returns anything but VINF_SUCCESS
744 * or the REM suggests raw-mode execution.
745 */
746 *pfFFDone = false;
747 bool fInREMState = false;
748 int rc = VINF_SUCCESS;
749 for (;;)
750 {
751 /*
752 * Update REM state if not already in sync.
753 */
754 if (!fInREMState)
755 {
756 STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
757 rc = REMR3State(pVM);
758 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
759 if (VBOX_FAILURE(rc))
760 break;
761 fInREMState = true;
762
763 /*
764 * We might have missed the raising of VMREQ, TIMER and some other
765 * imporant FFs while we were busy switching the state. So, check again.
766 */
767 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_TIMER | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_RESET))
768 {
769 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
770 goto l_REMDoForcedActions;
771 }
772 }
773
774
775 /*
776 * Execute REM.
777 */
778 STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
779 rc = REMR3Run(pVM);
780 STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
781
782
783 /*
784 * Deal with high priority post execution FFs before doing anything else.
785 */
786 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
787 rc = emR3HighPriorityPostForcedActions(pVM, rc);
788
789 /*
790 * Process the returned status code.
791 * (Try keep this short! Call functions!)
792 */
793 if (rc != VINF_SUCCESS)
794 {
795 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
796 break;
797 if (rc != VINF_REM_INTERRUPED_FF)
798 {
799 /*
800 * Anything which is not known to us means an internal error
801 * and the termination of the VM!
802 */
803 AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
804 break;
805 }
806 }
807
808
809 /*
810 * Check and execute forced actions.
811 * Sync back the VM state before calling any of these.
812 */
813#ifdef VBOX_HIGH_RES_TIMERS_HACK
814 TMTimerPoll(pVM);
815#endif
816 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION | VM_FF_CSAM_SCAN_PAGE)))
817 {
818l_REMDoForcedActions:
819 if (fInREMState)
820 {
821 STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
822 REMR3StateBack(pVM);
823 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
824 fInREMState = false;
825 }
826 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
827 rc = emR3ForcedActions(pVM, rc);
828 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
829 if ( rc != VINF_SUCCESS
830 && rc != VINF_EM_RESCHEDULE_REM)
831 {
832 *pfFFDone = true;
833 break;
834 }
835 }
836
837 } /* The Inner Loop, recompiled execution mode version. */
838
839
840 /*
841 * Returning. Sync back the VM state if required.
842 */
843 if (fInREMState)
844 {
845 STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
846 REMR3StateBack(pVM);
847 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
848 }
849
850 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
851 return rc;
852}
853
854
855/**
856 * Resumes executing hypervisor after a debug event.
857 *
858 * This is kind of special since our current guest state is
859 * potentially out of sync.
860 *
861 * @returns VBox status code.
862 * @param pVM The VM handle.
863 */
864static int emR3RawResumeHyper(PVM pVM)
865{
866 int rc;
867 PCPUMCTX pCtx = pVM->em.s.pCtx;
868 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
869 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
870
871 /*
872 * Resume execution.
873 */
874 CPUMRawEnter(pVM, NULL);
875 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_RF);
876 rc = VMMR3ResumeHyper(pVM);
877 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
878 rc = CPUMRawLeave(pVM, NULL, rc);
879 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
880
881 /*
882 * Deal with the return code.
883 */
884 rc = emR3HighPriorityPostForcedActions(pVM, rc);
885 rc = emR3RawHandleRC(pVM, pCtx, rc);
886 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
887 return rc;
888}
889
890
891/**
892 * Steps rawmode.
893 *
894 * @returns VBox status code.
895 * @param pVM The VM handle.
896 */
897static int emR3RawStep(PVM pVM)
898{
899 Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
900 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
901 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
902 int rc;
903 PCPUMCTX pCtx = pVM->em.s.pCtx;
904 bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
905#ifndef DEBUG_sandervl
906 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
907 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
908#endif
909 if (fGuest)
910 {
911 /*
912 * Check vital forced actions, but ignore pending interrupts and timers.
913 */
914 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
915 {
916 rc = emR3RawForcedActions(pVM, pCtx);
917 if (VBOX_FAILURE(rc))
918 return rc;
919 }
920
921 /*
922 * Set flags for single stepping.
923 */
924 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
925 }
926 else
927 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
928
929 /*
930 * Single step.
931 * We do not start time or anything, if anything we should just do a few nanoseconds.
932 */
933 CPUMRawEnter(pVM, NULL);
934 do
935 {
936 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
937 rc = VMMR3ResumeHyper(pVM);
938 else
939 rc = VMMR3RawRunGC(pVM);
940#ifndef DEBUG_sandervl
941 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
942 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
943#endif
944 } while ( rc == VINF_SUCCESS
945 || rc == VINF_EM_RAW_INTERRUPT);
946 rc = CPUMRawLeave(pVM, NULL, rc);
947 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
948
949 /*
950 * Make sure the trap flag is cleared.
951 * (Too bad if the guest is trying to single step too.)
952 */
953 if (fGuest)
954 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
955 else
956 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
957
958 /*
959 * Deal with the return codes.
960 */
961 rc = emR3HighPriorityPostForcedActions(pVM, rc);
962 rc = emR3RawHandleRC(pVM, pCtx, rc);
963 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
964 return rc;
965}
966
967/**
968 * Steps hardware accelerated mode.
969 *
970 * @returns VBox status code.
971 * @param pVM The VM handle.
972 */
973static int emR3HwAccStep(PVM pVM)
974{
975 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
976
977 int rc;
978 PCPUMCTX pCtx = pVM->em.s.pCtx;
979 VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_TSS));
980
981 /*
982 * Check vital forced actions, but ignore pending interrupts and timers.
983 */
984 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
985 {
986 rc = emR3RawForcedActions(pVM, pCtx);
987 if (VBOX_FAILURE(rc))
988 return rc;
989 }
990
991 /*
992 * Set flags for single stepping.
993 */
994 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
995
996 /*
997 * Single step.
998 * We do not start time or anything, if anything we should just do a few nanoseconds.
999 */
1000 do
1001 {
1002 rc = VMMR3HwAccRunGC(pVM);
1003 } while ( rc == VINF_SUCCESS
1004 || rc == VINF_EM_RAW_INTERRUPT);
1005 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1006
1007 /*
1008 * Make sure the trap flag is cleared.
1009 * (Too bad if the guest is trying to single step too.)
1010 */
1011 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1012
1013 /*
1014 * Deal with the return codes.
1015 */
1016 rc = emR3HighPriorityPostForcedActions(pVM, rc);
1017 rc = emR3RawHandleRC(pVM, pCtx, rc);
1018 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1019 return rc;
1020}
1021
1022#ifdef DEBUG_sandervl
1023void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1024{
1025 EMSTATE enmOldState = pVM->em.s.enmState;
1026 PCPUMCTX pCtx = pVM->em.s.pCtx;
1027
1028 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1029
1030 Log(("Single step BEGIN:\n"));
1031 for(uint32_t i=0;i<cIterations;i++)
1032 {
1033 DBGFR3PrgStep(pVM);
1034 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1035 emR3RawStep(pVM);
1036 }
1037 Log(("Single step END:\n"));
1038 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1039 pVM->em.s.enmState = enmOldState;
1040}
1041
1042void emR3SingleStepExecHwAcc(PVM pVM, uint32_t cIterations)
1043{
1044 EMSTATE enmOldState = pVM->em.s.enmState;
1045 PCPUMCTX pCtx = pVM->em.s.pCtx;
1046
1047 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1048
1049 Log(("Single step BEGIN:\n"));
1050 for(uint32_t i=0;i<cIterations;i++)
1051 {
1052 DBGFR3PrgStep(pVM);
1053 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1054 emR3HwAccStep(pVM);
1055 }
1056 Log(("Single step END:\n"));
1057 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1058 pVM->em.s.enmState = enmOldState;
1059}
1060
1061void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1062{
1063 EMSTATE enmOldState = pVM->em.s.enmState;
1064 PCPUMCTX pCtx = pVM->em.s.pCtx;
1065
1066 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1067
1068 Log(("Single step BEGIN:\n"));
1069 for(uint32_t i=0;i<cIterations;i++)
1070 {
1071 DBGFR3PrgStep(pVM);
1072 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1073 emR3RemStep(pVM);
1074 }
1075 Log(("Single step END:\n"));
1076 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1077 pVM->em.s.enmState = enmOldState;
1078}
1079#endif
1080
1081/**
1082 * Executes one (or perhaps a few more) instruction(s).
1083 *
1084 * @returns VBox status code suitable for EM.
1085 *
1086 * @param pVM VM handle.
1087 * @param rcGC GC return code
1088 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1089 * instruction and prefix the log output with this text.
1090 */
1091#ifdef LOG_ENABLED
1092static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1093#else
1094static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1095#endif
1096{
1097 PCPUMCTX pCtx = pVM->em.s.pCtx;
1098 int rc;
1099
1100 /*
1101 *
1102 * The simple solution is to use the recompiler.
1103 * The better solution is to disassemble the current instruction and
1104 * try handle as many as possible without using REM.
1105 *
1106 */
1107
1108#ifdef LOG_ENABLED
1109 /*
1110 * Disassemble the instruction if requested.
1111 */
1112 if (pszPrefix)
1113 {
1114 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1115 DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1116 }
1117#endif /* LOG_ENABLED */
1118
1119 /*
1120 * PATM is making life more interesting.
1121 * We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1122 * tell PATM there is a trap in this code and have it take the appropriate actions
1123 * to allow us execute the code in REM.
1124 */
1125 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1126 {
1127 Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
1128
1129 RTGCPTR pNewEip;
1130 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1131 switch (rc)
1132 {
1133 /*
1134 * It's not very useful to emulate a single instruction and then go back to raw
1135 * mode; just execute the whole block until IF is set again.
1136 */
1137 case VINF_SUCCESS:
1138 Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1139 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1140 pCtx->eip = pNewEip;
1141 Assert(pCtx->eip);
1142
1143 if (pCtx->eflags.Bits.u1IF)
1144 {
1145 /*
1146 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1147 */
1148 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1149 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1150 }
1151 else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1152 {
1153 /* special case: iret, that sets IF, detected a pending irq/event */
1154 return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1155 }
1156 return VINF_EM_RESCHEDULE_REM;
1157
1158 /*
1159 * One instruction.
1160 */
1161 case VINF_PATCH_EMULATE_INSTR:
1162 Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1163 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1164 pCtx->eip = pNewEip;
1165 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1166
1167 /*
1168 * The patch was disabled, hand it to the REM.
1169 */
1170 case VERR_PATCH_DISABLED:
1171 Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1172 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1173 pCtx->eip = pNewEip;
1174 if (pCtx->eflags.Bits.u1IF)
1175 {
1176 /*
1177 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1178 */
1179 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1180 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1181 }
1182 return VINF_EM_RESCHEDULE_REM;
1183
1184 /* Force continued patch exection; usually due to write monitored stack. */
1185 case VINF_PATCH_CONTINUE:
1186 return VINF_SUCCESS;
1187
1188 default:
1189 AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1190 return VERR_INTERNAL_ERROR;
1191 }
1192 }
1193
1194#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1195 DISCPUSTATE Cpu;
1196 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1197 if (VBOX_SUCCESS(rc))
1198 {
1199 uint32_t size;
1200
1201 switch (Cpu.pCurInstr->opcode)
1202 {
1203 case OP_MOV:
1204 case OP_AND:
1205 case OP_OR:
1206 case OP_XOR:
1207 case OP_POP:
1208 case OP_INC:
1209 case OP_DEC:
1210 case OP_XCHG:
1211 STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1212 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1213 if (VBOX_SUCCESS(rc))
1214 {
1215 pCtx->eip += Cpu.opsize;
1216 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1217 return rc;
1218 }
1219 if (rc != VERR_EM_INTERPRETER)
1220 AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1221 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1222 break;
1223 }
1224 }
1225#endif
1226 STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1227 rc = REMR3EmulateInstruction(pVM);
1228 STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1229
1230 return rc;
1231}
1232
1233
1234/**
1235 * Executes one (or perhaps a few more) instruction(s).
1236 * This is just a wrapper for discarding pszPrefix in non-logging builds.
1237 *
1238 * @returns VBox status code suitable for EM.
1239 * @param pVM VM handle.
1240 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1241 * instruction and prefix the log output with this text.
1242 * @param rcGC GC return code
1243 */
1244DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1245{
1246#ifdef LOG_ENABLED
1247 return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1248#else
1249 return emR3RawExecuteInstructionWorker(pVM, rcGC);
1250#endif
1251}
1252
1253/**
1254 * Executes one (or perhaps a few more) IO instruction(s).
1255 *
1256 * @returns VBox status code suitable for EM.
1257 * @param pVM VM handle.
1258 */
1259int emR3RawExecuteIOInstruction(PVM pVM)
1260{
1261 int rc;
1262 PCPUMCTX pCtx = pVM->em.s.pCtx;
1263
1264 STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1265
1266 /** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1267 * as io instructions tend to come in packages of more than one
1268 */
1269 DISCPUSTATE Cpu;
1270 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1271 if (VBOX_SUCCESS(rc))
1272 {
1273 if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE)))
1274 {
1275 switch (Cpu.pCurInstr->opcode)
1276 {
1277 case OP_IN:
1278 {
1279 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1280
1281 rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1282 if (rc == VINF_SUCCESS)
1283 {
1284 pCtx->eip += Cpu.opsize;
1285 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1286 return VINF_SUCCESS;
1287 }
1288 else
1289 if (rc == VINF_EM_RAW_GUEST_TRAP)
1290 {
1291 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1292 rc = emR3RawGuestTrap(pVM);
1293 return rc;
1294 }
1295 /* emulate in the recompiler */
1296 break;
1297 }
1298
1299 case OP_OUT:
1300 {
1301 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1302
1303 rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1304 if (rc == VINF_SUCCESS)
1305 {
1306 pCtx->eip += Cpu.opsize;
1307 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1308 return VINF_SUCCESS;
1309 }
1310 else
1311 if (rc == VINF_EM_RAW_GUEST_TRAP)
1312 {
1313 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1314 rc = emR3RawGuestTrap(pVM);
1315 return rc;
1316 }
1317 /* emulate in the recompiler */
1318 break;
1319 }
1320
1321 default:
1322 break;
1323 }
1324 }//if(!(Cpu.prefix & (PREFIX_REP|PREFIX_REPNE))
1325 else if (Cpu.prefix & PREFIX_REP)
1326 {
1327 switch (Cpu.pCurInstr->opcode)
1328 {
1329 case OP_INSB:
1330 case OP_INSWD:
1331 {
1332 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1333 rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1334 if (rc == VINF_SUCCESS)
1335 {
1336 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1337 pCtx->eip += Cpu.opsize;
1338 return rc;
1339 }
1340 else
1341 if (rc == VINF_EM_RAW_GUEST_TRAP)
1342 {
1343 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1344 rc = emR3RawGuestTrap(pVM);
1345 return rc;
1346 }
1347 /* emulate in the recompiler */
1348 break;
1349 }
1350 case OP_OUTSB:
1351 case OP_OUTSWD:
1352 {
1353 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1354 rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1355 if (rc == VINF_SUCCESS)
1356 {
1357 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1358 pCtx->eip += Cpu.opsize;
1359 return rc;
1360 }
1361 else
1362 if (rc == VINF_EM_RAW_GUEST_TRAP)
1363 {
1364 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1365 rc = emR3RawGuestTrap(pVM);
1366 return rc;
1367 }
1368 /* emulate in the recompiler */
1369 break;
1370 }
1371 }
1372 }//if(Cpu.prefix & PREFIX_REP)
1373 }
1374
1375 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1376 return emR3RawExecuteInstruction(pVM, "IO: ");
1377}
1378
1379
1380/**
1381 * Handle a guest context trap.
1382 *
1383 * @returns VBox status code suitable for EM.
1384 * @param pVM VM handle.
1385 */
1386static int emR3RawGuestTrap(PVM pVM)
1387{
1388 PCPUMCTX pCtx = pVM->em.s.pCtx;
1389
1390 /*
1391 * Get the trap info.
1392 */
1393 uint8_t u8TrapNo;
1394 TRPMEVENT enmType;;
1395 RTGCUINT uErrorCode;
1396 RTGCUINTPTR uCR2;
1397 int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1398 if (VBOX_FAILURE(rc))
1399 {
1400 AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1401 return rc;
1402 }
1403
1404 /* Traps can be directly forwarded in hardware accelerated mode. */
1405 if (HWACCMR3IsActive(pVM))
1406 {
1407#ifdef LOGGING_ENABLED
1408 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1409 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1410#endif
1411 return VINF_EM_RESCHEDULE_HWACC;
1412 }
1413
1414 /** Scan kernel code that traps; we might not get another chance. */
1415 if ( (pCtx->ss & X86_SEL_RPL) <= 1
1416 && !pCtx->eflags.Bits.u1VM)
1417 {
1418 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1419 CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
1420 }
1421
1422 if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1423 {
1424 DISCPUSTATE cpu;
1425
1426 /* If MONITOR & MWAIT are supported, then interpret them here. */
1427 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1428 if ( VBOX_SUCCESS(rc)
1429 && (cpu.pCurInstr->opcode == OP_MONITOR || cpu.pCurInstr->opcode == OP_MWAIT))
1430 {
1431 uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1432
1433 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1434
1435 if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1436 {
1437 rc = TRPMResetTrap(pVM);
1438 AssertRC(rc);
1439
1440 rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1441 if (VBOX_SUCCESS(rc))
1442 {
1443 pCtx->eip += cpu.opsize;
1444 return rc;
1445 }
1446 return emR3RawExecuteInstruction(pVM, "Monitor: ");
1447 }
1448 }
1449 }
1450 else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1451 {
1452 DISCPUSTATE cpu;
1453
1454 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1455 if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1456 {
1457 /*
1458 * We should really check the TSS for the IO bitmap, but it's not like this
1459 * lazy approach really makes things worse.
1460 */
1461 rc = TRPMResetTrap(pVM);
1462 AssertRC(rc);
1463 return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1464 }
1465 }
1466
1467#ifdef LOG_ENABLED
1468 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1469 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1470
1471 /* Get guest page information. */
1472 uint64_t fFlags = 0;
1473 RTGCPHYS GCPhys = 0;
1474 int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1475 Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1476 pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1477 fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1478 fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1479#endif
1480
1481 /*
1482 * #PG has CR2.
1483 * (Because of stuff like above we must set CR2 in a delayed fashion.)
1484 */
1485 if (u8TrapNo == 14 /* #PG */)
1486 pCtx->cr2 = uCR2;
1487
1488 return VINF_EM_RESCHEDULE_REM;
1489}
1490
1491
1492/**
1493 * Handle a ring switch trap.
1494 * Need to do statistics and to install patches. The result is going to REM.
1495 *
1496 * @returns VBox status code suitable for EM.
1497 * @param pVM VM handle.
1498 */
1499int emR3RawRingSwitch(PVM pVM)
1500{
1501 int rc;
1502 DISCPUSTATE Cpu;
1503 PCPUMCTX pCtx = pVM->em.s.pCtx;
1504
1505 /*
1506 * sysenter, syscall & callgate
1507 */
1508 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1509 if (VBOX_SUCCESS(rc))
1510 {
1511 if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1512 {
1513 if (pCtx->SysEnter.cs != 0)
1514 {
1515 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1516 SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1517 if (VBOX_SUCCESS(rc))
1518 {
1519 DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1520 return VINF_EM_RESCHEDULE_RAW;
1521 }
1522 }
1523 }
1524
1525#ifdef VBOX_WITH_STATISTICS
1526 switch (Cpu.pCurInstr->opcode)
1527 {
1528 case OP_SYSENTER:
1529 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1530 break;
1531 case OP_SYSEXIT:
1532 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1533 break;
1534 case OP_SYSCALL:
1535 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1536 break;
1537 case OP_SYSRET:
1538 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1539 break;
1540 }
1541#endif
1542 }
1543 else
1544 AssertRC(rc);
1545
1546 /* go to the REM to emulate a single instruction */
1547 return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1548}
1549
1550/**
1551 * Handle a trap (#PF or #GP) in patch code
1552 *
1553 * @returns VBox status code suitable for EM.
1554 * @param pVM VM handle.
1555 * @param pCtx CPU context
1556 * @param gcret GC return code
1557 */
1558int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1559{
1560 uint8_t u8TrapNo;
1561 int rc;
1562 TRPMEVENT enmType;
1563 RTGCUINT uErrorCode;
1564 RTGCUINTPTR uCR2;
1565
1566 Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1567
1568 if (gcret == VINF_PATM_PATCH_INT3)
1569 {
1570 u8TrapNo = 3;
1571 uCR2 = 0;
1572 uErrorCode = 0;
1573 }
1574 else
1575 if (gcret == VINF_PATM_PATCH_TRAP_GP)
1576 {
1577 /* No active trap in this case. Kind of ugly. */
1578 u8TrapNo = X86_XCPT_GP;
1579 uCR2 = 0;
1580 uErrorCode = 0;
1581 }
1582 else
1583 {
1584 rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1585 if (VBOX_FAILURE(rc))
1586 {
1587 AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1588 return rc;
1589 }
1590 /* Reset the trap as we'll execute the original instruction again. */
1591 TRPMResetTrap(pVM);
1592 }
1593
1594 /*
1595 * Deal with traps inside patch code.
1596 * (This code won't run outside GC.)
1597 */
1598 if (u8TrapNo != 1)
1599 {
1600#ifdef LOG_ENABLED
1601 DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1602 DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1603
1604 DISCPUSTATE Cpu;
1605 int rc;
1606
1607 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1608 if ( VBOX_SUCCESS(rc)
1609 && Cpu.pCurInstr->opcode == OP_IRET)
1610 {
1611 uint32_t eip, selCS, uEFlags;
1612
1613 /* Iret crashes are bad as we have already changed the flags on the stack */
1614 rc = PGMPhysReadGCPtr(pVM, &eip, pCtx->esp, 4);
1615 rc |= PGMPhysReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1616 rc |= PGMPhysReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1617 if (rc == VINF_SUCCESS)
1618 {
1619 if ( (uEFlags & X86_EFL_VM)
1620 || (selCS & X86_SEL_RPL) == 3)
1621 {
1622 uint32_t selSS, esp;
1623
1624 rc |= PGMPhysReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1625 rc |= PGMPhysReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1626
1627 if (uEFlags & X86_EFL_VM)
1628 {
1629 uint32_t selDS, selES, selFS, selGS;
1630 rc = PGMPhysReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1631 rc |= PGMPhysReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1632 rc |= PGMPhysReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1633 rc |= PGMPhysReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1634 if (rc == VINF_SUCCESS)
1635 {
1636 Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1637 Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1638 }
1639 }
1640 else
1641 Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1642 }
1643 else
1644 Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1645 }
1646 }
1647#endif
1648 Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1649 pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1650
1651 RTGCPTR pNewEip;
1652 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1653 switch (rc)
1654 {
1655 /*
1656 * Execute the faulting instruction.
1657 */
1658 case VINF_SUCCESS:
1659 {
1660 /** @todo execute a whole block */
1661 Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1662 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1663 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1664
1665 pCtx->eip = pNewEip;
1666 AssertRelease(pCtx->eip);
1667
1668 if (pCtx->eflags.Bits.u1IF)
1669 {
1670 /* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1671 * int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1672 */
1673 if ( u8TrapNo == X86_XCPT_GP
1674 && PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1675 {
1676 /** @todo move to PATMR3HandleTrap */
1677 Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1678 PATMR3RemovePatch(pVM, pCtx->eip);
1679 }
1680
1681 /** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1682 /** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1683
1684 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1685 /* Interrupts are enabled; just go back to the original instruction.
1686 return VINF_SUCCESS; */
1687 }
1688 return VINF_EM_RESCHEDULE_REM;
1689 }
1690
1691 /*
1692 * One instruction.
1693 */
1694 case VINF_PATCH_EMULATE_INSTR:
1695 Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1696 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1697 pCtx->eip = pNewEip;
1698 AssertRelease(pCtx->eip);
1699 return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1700
1701 /*
1702 * The patch was disabled, hand it to the REM.
1703 */
1704 case VERR_PATCH_DISABLED:
1705 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1706 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1707 pCtx->eip = pNewEip;
1708 AssertRelease(pCtx->eip);
1709
1710 if (pCtx->eflags.Bits.u1IF)
1711 {
1712 /*
1713 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1714 */
1715 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1716 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1717 }
1718 return VINF_EM_RESCHEDULE_REM;
1719
1720 /* Force continued patch exection; usually due to write monitored stack. */
1721 case VINF_PATCH_CONTINUE:
1722 return VINF_SUCCESS;
1723
1724 /*
1725 * Anything else is *fatal*.
1726 */
1727 default:
1728 AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1729 return VERR_INTERNAL_ERROR;
1730 }
1731 }
1732 return VINF_SUCCESS;
1733}
1734
1735
1736/**
1737 * Handle a privileged instruction.
1738 *
1739 * @returns VBox status code suitable for EM.
1740 * @param pVM VM handle.
1741 */
1742int emR3RawPrivileged(PVM pVM)
1743{
1744 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1745 PCPUMCTX pCtx = pVM->em.s.pCtx;
1746
1747 Assert(!pCtx->eflags.Bits.u1VM);
1748
1749 if (PATMIsEnabled(pVM))
1750 {
1751 /*
1752 * Check if in patch code.
1753 */
1754 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1755 {
1756#ifdef LOG_ENABLED
1757 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1758#endif
1759 AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1760 return VERR_EM_RAW_PATCH_CONFLICT;
1761 }
1762 if ( (pCtx->ss & X86_SEL_RPL) == 0
1763 && !pCtx->eflags.Bits.u1VM
1764 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
1765 {
1766 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1767 SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1768 if (VBOX_SUCCESS(rc))
1769 {
1770#ifdef LOG_ENABLED
1771 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1772#endif
1773 DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1774 return VINF_SUCCESS;
1775 }
1776 }
1777 }
1778
1779#ifdef LOG_ENABLED
1780 if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1781 {
1782 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1783 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1784 }
1785#endif
1786
1787 /*
1788 * Instruction statistics and logging.
1789 */
1790 DISCPUSTATE Cpu;
1791 int rc;
1792
1793 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1794 if (VBOX_SUCCESS(rc))
1795 {
1796#ifdef VBOX_WITH_STATISTICS
1797 PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1798 switch (Cpu.pCurInstr->opcode)
1799 {
1800 case OP_INVLPG:
1801 STAM_COUNTER_INC(&pStats->StatInvlpg);
1802 break;
1803 case OP_IRET:
1804 STAM_COUNTER_INC(&pStats->StatIret);
1805 break;
1806 case OP_CLI:
1807 STAM_COUNTER_INC(&pStats->StatCli);
1808 emR3RecordCli(pVM, pCtx->eip);
1809 break;
1810 case OP_STI:
1811 STAM_COUNTER_INC(&pStats->StatSti);
1812 break;
1813 case OP_INSB:
1814 case OP_INSWD:
1815 case OP_IN:
1816 case OP_OUTSB:
1817 case OP_OUTSWD:
1818 case OP_OUT:
1819 AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1820 break;
1821
1822 case OP_MOV_CR:
1823 if (Cpu.param1.flags & USE_REG_GEN32)
1824 {
1825 //read
1826 Assert(Cpu.param2.flags & USE_REG_CR);
1827 Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1828 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1829 }
1830 else
1831 {
1832 //write
1833 Assert(Cpu.param1.flags & USE_REG_CR);
1834 Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1835 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1836 }
1837 break;
1838
1839 case OP_MOV_DR:
1840 STAM_COUNTER_INC(&pStats->StatMovDRx);
1841 break;
1842 case OP_LLDT:
1843 STAM_COUNTER_INC(&pStats->StatMovLldt);
1844 break;
1845 case OP_LIDT:
1846 STAM_COUNTER_INC(&pStats->StatMovLidt);
1847 break;
1848 case OP_LGDT:
1849 STAM_COUNTER_INC(&pStats->StatMovLgdt);
1850 break;
1851 case OP_SYSENTER:
1852 STAM_COUNTER_INC(&pStats->StatSysEnter);
1853 break;
1854 case OP_SYSEXIT:
1855 STAM_COUNTER_INC(&pStats->StatSysExit);
1856 break;
1857 case OP_SYSCALL:
1858 STAM_COUNTER_INC(&pStats->StatSysCall);
1859 break;
1860 case OP_SYSRET:
1861 STAM_COUNTER_INC(&pStats->StatSysRet);
1862 break;
1863 case OP_HLT:
1864 STAM_COUNTER_INC(&pStats->StatHlt);
1865 break;
1866 default:
1867 STAM_COUNTER_INC(&pStats->StatMisc);
1868 Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1869 break;
1870 }
1871#endif
1872 if ( (pCtx->ss & X86_SEL_RPL) == 0
1873 && !pCtx->eflags.Bits.u1VM
1874 && SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid))
1875 {
1876 uint32_t size;
1877
1878 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1879 switch (Cpu.pCurInstr->opcode)
1880 {
1881 case OP_CLI:
1882 pCtx->eflags.u32 &= ~X86_EFL_IF;
1883 Assert(Cpu.opsize == 1);
1884 pCtx->eip += Cpu.opsize;
1885 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1886 return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1887
1888 case OP_STI:
1889 pCtx->eflags.u32 |= X86_EFL_IF;
1890 EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
1891 Assert(Cpu.opsize == 1);
1892 pCtx->eip += Cpu.opsize;
1893 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1894 return VINF_SUCCESS;
1895
1896 case OP_HLT:
1897 if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1898 {
1899 PATMTRANSSTATE enmState;
1900 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1901
1902 if (enmState == PATMTRANS_OVERWRITTEN)
1903 {
1904 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1905 Assert(rc == VERR_PATCH_DISABLED);
1906 /* Conflict detected, patch disabled */
1907 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1908
1909 enmState = PATMTRANS_SAFE;
1910 }
1911
1912 /* The translation had better be successful. Otherwise we can't recover. */
1913 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1914 if (enmState != PATMTRANS_OVERWRITTEN)
1915 pCtx->eip = pOrgInstrGC;
1916 }
1917 /* no break; we could just return VINF_EM_HALT here */
1918
1919 case OP_MOV_CR:
1920 case OP_MOV_DR:
1921#ifdef LOG_ENABLED
1922 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1923 {
1924 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1925 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1926 }
1927#endif
1928
1929 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1930 if (VBOX_SUCCESS(rc))
1931 {
1932 pCtx->eip += Cpu.opsize;
1933 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1934
1935 if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1936 && Cpu.param1.flags == USE_REG_CR /* write */
1937 )
1938 {
1939 /* Reschedule is necessary as the execution/paging mode might have changed. */
1940 return VINF_EM_RESCHEDULE;
1941 }
1942 return rc; /* can return VINF_EM_HALT as well. */
1943 }
1944 AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1945 break; /* fall back to the recompiler */
1946 }
1947 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1948 }
1949 }
1950
1951 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1952 return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1953
1954 return emR3RawExecuteInstruction(pVM, "PRIV");
1955}
1956
1957
1958/**
1959 * Update the forced rawmode execution modifier.
1960 *
1961 * This function is called when we're returning from the raw-mode loop(s). If we're
1962 * in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1963 * if not in patch code, the flag will be cleared.
1964 *
1965 * We should never interrupt patch code while it's being executed. Cli patches can
1966 * contain big code blocks, but they are always executed with IF=0. Other patches
1967 * replace single instructions and should be atomic.
1968 *
1969 * @returns Updated rc.
1970 *
1971 * @param pVM The VM handle.
1972 * @param pCtx The guest CPU context.
1973 * @param rc The result code.
1974 */
1975DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
1976{
1977 if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1978 {
1979 /* ignore reschedule attempts. */
1980 switch (rc)
1981 {
1982 case VINF_EM_RESCHEDULE:
1983 case VINF_EM_RESCHEDULE_REM:
1984 rc = VINF_SUCCESS;
1985 break;
1986 }
1987 pVM->em.s.fForceRAW = true;
1988 }
1989 else
1990 pVM->em.s.fForceRAW = false;
1991 return rc;
1992}
1993
1994
1995/**
1996 * Process a subset of the raw-mode return code.
1997 *
1998 * Since we have to share this with raw-mode single stepping, this inline
1999 * function has been created to avoid code duplication.
2000 *
2001 * @returns VINF_SUCCESS if it's ok to continue raw mode.
2002 * @returns VBox status code to return to the EM main loop.
2003 *
2004 * @param pVM The VM handle
2005 * @param rc The return code.
2006 * @param pCtx The guest cpu context.
2007 */
2008DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2009{
2010 switch (rc)
2011 {
2012 /*
2013 * Common & simple ones.
2014 */
2015 case VINF_SUCCESS:
2016 break;
2017 case VINF_EM_RESCHEDULE_RAW:
2018 case VINF_EM_RESCHEDULE_HWACC:
2019 case VINF_EM_RAW_INTERRUPT:
2020 case VINF_EM_RAW_TO_R3:
2021 case VINF_EM_RAW_TIMER_PENDING:
2022 case VINF_EM_PENDING_REQUEST:
2023 rc = VINF_SUCCESS;
2024 break;
2025
2026 /*
2027 * Privileged instruction.
2028 */
2029 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2030 case VINF_PATM_PATCH_TRAP_GP:
2031 rc = emR3RawPrivileged(pVM);
2032 break;
2033
2034 /*
2035 * Got a trap which needs dispatching.
2036 */
2037 case VINF_EM_RAW_GUEST_TRAP:
2038 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2039 {
2040 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2041 rc = VERR_EM_RAW_PATCH_CONFLICT;
2042 break;
2043 }
2044
2045 Assert(TRPMHasTrap(pVM));
2046 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2047
2048 if (TRPMHasTrap(pVM))
2049 {
2050 uint8_t u8Interrupt;
2051 uint32_t uErrorCode;
2052 TRPMERRORCODE enmError = TRPM_TRAP_NO_ERRORCODE;
2053
2054 rc = TRPMQueryTrapAll(pVM, &u8Interrupt, NULL, &uErrorCode, NULL);
2055 AssertRC(rc);
2056
2057 if (uErrorCode != ~0U)
2058 enmError = TRPM_TRAP_HAS_ERRORCODE;
2059
2060 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2061 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2062 {
2063 CSAMR3CheckGates(pVM, u8Interrupt, 1);
2064 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2065
2066 /** If it was successful, then we could go back to raw mode. */
2067 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER)
2068 {
2069 rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8Interrupt, uErrorCode, enmError, TRPM_TRAP);
2070 if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
2071 {
2072 TRPMResetTrap(pVM);
2073 return VINF_EM_RESCHEDULE_RAW;
2074 }
2075 }
2076 }
2077 }
2078 rc = emR3RawGuestTrap(pVM);
2079 break;
2080
2081 /*
2082 * Trap in patch code.
2083 */
2084 case VINF_PATM_PATCH_TRAP_PF:
2085 case VINF_PATM_PATCH_INT3:
2086 rc = emR3PatchTrap(pVM, pCtx, rc);
2087 break;
2088
2089 case VINF_PATM_DUPLICATE_FUNCTION:
2090 Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2091 rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2092 AssertRC(rc);
2093 rc = VINF_SUCCESS;
2094 break;
2095
2096 case VINF_PATM_CHECK_PATCH_PAGE:
2097 rc = PATMR3HandleMonitoredPage(pVM);
2098 AssertRC(rc);
2099 rc = VINF_SUCCESS;
2100 break;
2101
2102 /*
2103 * Patch manager.
2104 */
2105 case VERR_EM_RAW_PATCH_CONFLICT:
2106 AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2107 break;
2108
2109 /*
2110 * Memory mapped I/O access - attempt to patch the instruction
2111 */
2112 case VINF_PATM_HC_MMIO_PATCH_READ:
2113 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
2114 PATMFL_MMIO_ACCESS | (SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2115 if (VBOX_FAILURE(rc))
2116 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2117 break;
2118
2119 case VINF_PATM_HC_MMIO_PATCH_WRITE:
2120 AssertFailed(); /* not yet implemented. */
2121 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2122 break;
2123
2124 /*
2125 * Conflict or out of page tables.
2126 *
2127 * VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2128 * do here is to execute the pending forced actions.
2129 */
2130 case VINF_PGM_SYNC_CR3:
2131 AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2132 ("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2133 rc = VINF_SUCCESS;
2134 break;
2135
2136 /*
2137 * Paging mode change.
2138 */
2139 case VINF_PGM_CHANGE_MODE:
2140 rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2141 if (VBOX_SUCCESS(rc))
2142 rc = VINF_EM_RESCHEDULE;
2143 break;
2144
2145 /*
2146 * CSAM wants to perform a task in ring-3. It has set an FF action flag.
2147 */
2148 case VINF_CSAM_PENDING_ACTION:
2149 rc = VINF_SUCCESS;
2150 break;
2151
2152 /*
2153 * Invoked Interrupt gate - must directly (!) go to the recompiler.
2154 */
2155 case VINF_EM_RAW_INTERRUPT_PENDING:
2156 case VINF_EM_RAW_RING_SWITCH_INT:
2157 {
2158 uint8_t u8Interrupt;
2159
2160 Assert(TRPMHasTrap(pVM));
2161 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2162
2163 if (TRPMHasTrap(pVM))
2164 {
2165 u8Interrupt = TRPMGetTrapNo(pVM);
2166
2167 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2168 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2169 {
2170 CSAMR3CheckGates(pVM, u8Interrupt, 1);
2171 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2172 /** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2173 }
2174 }
2175 rc = VINF_EM_RESCHEDULE_REM;
2176 break;
2177 }
2178
2179 /*
2180 * Other ring switch types.
2181 */
2182 case VINF_EM_RAW_RING_SWITCH:
2183 rc = emR3RawRingSwitch(pVM);
2184 break;
2185
2186 /*
2187 * REMGCNotifyInvalidatePage() failed because of overflow.
2188 */
2189 case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2190 Assert((pCtx->ss & X86_SEL_RPL) != 1);
2191 REMR3ReplayInvalidatedPages(pVM);
2192 break;
2193
2194 /*
2195 * I/O Port access - emulate the instruction.
2196 */
2197 case VINF_IOM_HC_IOPORT_READ:
2198 case VINF_IOM_HC_IOPORT_WRITE:
2199 case VINF_IOM_HC_IOPORT_READWRITE:
2200 rc = emR3RawExecuteIOInstruction(pVM);
2201 break;
2202
2203 /*
2204 * Memory mapped I/O access - emulate the instruction.
2205 */
2206 case VINF_IOM_HC_MMIO_READ:
2207 case VINF_IOM_HC_MMIO_WRITE:
2208 case VINF_IOM_HC_MMIO_READ_WRITE:
2209 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2210 break;
2211
2212 /*
2213 * Execute instruction.
2214 */
2215 case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2216 rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2217 break;
2218 case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2219 rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2220 break;
2221 case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2222 rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2223 break;
2224 case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2225 rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2226 break;
2227 case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2228 rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2229 break;
2230
2231 case VINF_EM_RAW_EMULATE_INSTR_HLT:
2232 /** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2233 rc = emR3RawPrivileged(pVM);
2234 break;
2235
2236 case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2237 rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2238 break;
2239
2240 case VINF_EM_RAW_EMULATE_INSTR:
2241 case VINF_PATCH_EMULATE_INSTR:
2242 rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2243 break;
2244
2245 /*
2246 * Stale selector and iret traps => REM.
2247 */
2248 case VINF_EM_RAW_STALE_SELECTOR:
2249 case VINF_EM_RAW_IRET_TRAP:
2250 /* We will not go to the recompiler if EIP points to patch code. */
2251 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2252 {
2253 pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2254 }
2255 LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2256 rc = VINF_EM_RESCHEDULE_REM;
2257 break;
2258
2259 /*
2260 * Up a level.
2261 */
2262 case VINF_EM_TERMINATE:
2263 case VINF_EM_OFF:
2264 case VINF_EM_RESET:
2265 case VINF_EM_SUSPEND:
2266 case VINF_EM_HALT:
2267 case VINF_EM_RESUME:
2268 case VINF_EM_RESCHEDULE:
2269 case VINF_EM_RESCHEDULE_REM:
2270 break;
2271
2272 /*
2273 * Up a level and invoke the debugger.
2274 */
2275 case VINF_EM_DBG_STEPPED:
2276 case VINF_EM_DBG_BREAKPOINT:
2277 case VINF_EM_DBG_STEP:
2278 case VINF_EM_DBG_HYPER_ASSERTION:
2279 case VINF_EM_DBG_HYPER_BREAKPOINT:
2280 case VINF_EM_DBG_HYPER_STEPPED:
2281 case VINF_EM_DBG_STOP:
2282 break;
2283
2284 /*
2285 * Up a level, dump and debug.
2286 */
2287 case VERR_TRPM_DONT_PANIC:
2288 case VERR_TRPM_PANIC:
2289 break;
2290
2291 /*
2292 * Anything which is not known to us means an internal error
2293 * and the termination of the VM!
2294 */
2295 default:
2296 AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2297 break;
2298 }
2299 return rc;
2300}
2301
2302/**
2303 * Check for pending raw actions
2304 *
2305 * @returns VBox status code.
2306 * @param pVM The VM to operate on.
2307 */
2308EMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2309{
2310 return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2311}
2312
2313
2314/**
2315 * Process raw-mode specific forced actions.
2316 *
2317 * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2318 *
2319 * @returns VBox status code.
2320 * Only the normal success/failure stuff, no VINF_EM_*.
2321 * @param pVM The VM handle.
2322 * @param pCtx The guest CPUM register context.
2323 */
2324static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2325{
2326 /*
2327 * Note that the order is *vitally* important!
2328 * Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2329 */
2330
2331
2332 /*
2333 * Sync selector tables.
2334 */
2335 if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT))
2336 {
2337 int rc = SELMR3UpdateFromCPUM(pVM);
2338 if (VBOX_FAILURE(rc))
2339 return rc;
2340 }
2341
2342 /*
2343 * Sync IDT.
2344 */
2345 if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2346 {
2347 int rc = TRPMR3SyncIDT(pVM);
2348 if (VBOX_FAILURE(rc))
2349 return rc;
2350 }
2351
2352 /*
2353 * Sync TSS.
2354 */
2355 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2356 {
2357 int rc = SELMR3SyncTSS(pVM);
2358 if (VBOX_FAILURE(rc))
2359 return rc;
2360 }
2361
2362 /*
2363 * Sync page directory.
2364 */
2365 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2366 {
2367 int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2368 if (VBOX_FAILURE(rc))
2369 return rc;
2370
2371 Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT));
2372
2373 /* Prefetch pages for EIP and ESP */
2374 /** @todo This is rather expensive. Should investigate if it really helps at all. */
2375 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip));
2376 if (rc == VINF_SUCCESS)
2377 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2378 if (rc != VINF_SUCCESS)
2379 {
2380 if (rc != VINF_PGM_SYNC_CR3)
2381 return rc;
2382 rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2383 if (VBOX_FAILURE(rc))
2384 return rc;
2385 }
2386 /** @todo maybe prefetch the supervisor stack page as well */
2387 }
2388
2389 return VINF_SUCCESS;
2390}
2391
2392
2393/**
2394 * Executes raw code.
2395 *
2396 * This function contains the raw-mode version of the inner
2397 * execution loop (the outer loop being in EMR3ExecuteVM()).
2398 *
2399 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2400 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2401 *
2402 * @param pVM VM handle.
2403 * @param pfFFDone Where to store an indicator telling whether or not
2404 * FFs were done before returning.
2405 */
2406static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2407{
2408 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2409
2410 int rc = VERR_INTERNAL_ERROR;
2411 PCPUMCTX pCtx = pVM->em.s.pCtx;
2412 LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2413 pVM->em.s.fForceRAW = false;
2414 *pfFFDone = false;
2415
2416
2417 /*
2418 *
2419 * Spin till we get a forced action or raw mode status code resulting in
2420 * in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2421 *
2422 */
2423 for (;;)
2424 {
2425 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2426
2427 /*
2428 * Check various preconditions.
2429 */
2430#ifdef VBOX_STRICT
2431 Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2432 Assert(!(pCtx->cr4 & X86_CR4_PAE));
2433 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) == 3 || (pCtx->ss & X86_SEL_RPL) == 0);
2434 AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2435 || PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2436 ("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2437 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2438 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2439 {
2440 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2441 return VERR_INTERNAL_ERROR;
2442 }
2443#endif /* VBOX_STRICT */
2444
2445 /*
2446 * Process high priority pre-execution raw-mode FFs.
2447 */
2448 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2449 {
2450 rc = emR3RawForcedActions(pVM, pCtx);
2451 if (VBOX_FAILURE(rc))
2452 break;
2453 }
2454
2455 /*
2456 * If we're going to execute ring-0 code, the guest state needs to
2457 * be modified a bit and some of the state components (IF, SS/CS RPL,
2458 * and perhaps EIP) needs to be stored with PATM.
2459 */
2460 rc = CPUMRawEnter(pVM, NULL);
2461 if (rc != VINF_SUCCESS)
2462 {
2463 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2464 break;
2465 }
2466
2467 /*
2468 * Scan code before executing it. Don't bother with user mode or V86 code
2469 */
2470 if ( (pCtx->ss & X86_SEL_RPL) <= 1
2471 && !pCtx->eflags.Bits.u1VM
2472 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
2473 {
2474 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2475 CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2476 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2477 }
2478
2479#ifdef LOG_ENABLED
2480 /*
2481 * Log important stuff before entering GC.
2482 */
2483 PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2484 if (pCtx->eflags.Bits.u1VM)
2485 Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2486 else if ((pCtx->ss & X86_SEL_RPL) == 1)
2487 {
2488 bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2489 Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2490 }
2491 else if ((pCtx->ss & X86_SEL_RPL) == 3)
2492 Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2493#endif /* LOG_ENABLED */
2494
2495
2496
2497 /*
2498 * Execute the code.
2499 */
2500 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2501 STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2502 VMMR3Unlock(pVM);
2503 rc = VMMR3RawRunGC(pVM);
2504 VMMR3Lock(pVM);
2505 STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2506 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2507
2508 LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2509 LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2510
2511 /*
2512 * Restore the real CPU state and deal with high priority post
2513 * execution FFs before doing anything else.
2514 */
2515 rc = CPUMRawLeave(pVM, NULL, rc);
2516 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2517 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2518 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2519
2520#ifdef PGM_CACHE_VERY_STRICT
2521 /*
2522 * Page manager cache checks.
2523 */
2524 if ( rc == VINF_EM_RAW_INTERRUPT
2525 || rc == VINF_EM_RAW_GUEST_TRAP
2526 || rc == VINF_IOM_HC_IOPORT_READ
2527 || rc == VINF_IOM_HC_IOPORT_WRITE
2528 || rc == VINF_IOM_HC_IOPORT_READWRITE
2529 //|| rc == VINF_PATM_PATCH_INT3
2530 )
2531 pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2532#endif
2533
2534#ifdef VBOX_STRICT
2535 /*
2536 * Assert TSS consistency & rc vs patch code.
2537 */
2538 if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS | VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2539 && EMIsRawRing0Enabled(pVM))
2540 SELMR3CheckTSS(pVM);
2541 switch (rc)
2542 {
2543 case VINF_SUCCESS:
2544 case VINF_EM_RAW_INTERRUPT:
2545 case VINF_PATM_PATCH_TRAP_PF:
2546 case VINF_PATM_PATCH_TRAP_GP:
2547 case VINF_PATM_PATCH_INT3:
2548 case VINF_PATM_CHECK_PATCH_PAGE:
2549 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2550 case VINF_EM_RAW_GUEST_TRAP:
2551 case VINF_EM_RESCHEDULE_RAW:
2552 break;
2553
2554 default:
2555 if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2556 LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2557 break;
2558 }
2559 /*
2560 * Let's go paranoid!
2561 */
2562 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2563 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2564 {
2565 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2566 return VERR_INTERNAL_ERROR;
2567 }
2568#endif /* VBOX_STRICT */
2569
2570 /*
2571 * Process the returned status code.
2572 */
2573 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2574 {
2575 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2576 break;
2577 }
2578 rc = emR3RawHandleRC(pVM, pCtx, rc);
2579 if (rc != VINF_SUCCESS)
2580 {
2581 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2582 if (rc != VINF_SUCCESS)
2583 {
2584 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2585 break;
2586 }
2587 }
2588
2589 /*
2590 * Check and execute forced actions.
2591 */
2592#ifdef VBOX_HIGH_RES_TIMERS_HACK
2593 TMTimerPoll(pVM);
2594#endif
2595 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2596 if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2597 {
2598 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) != 1);
2599
2600 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2601 rc = emR3ForcedActions(pVM, rc);
2602 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2603 if ( rc != VINF_SUCCESS
2604 && rc != VINF_EM_RESCHEDULE_RAW)
2605 {
2606 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2607 if (rc != VINF_SUCCESS)
2608 {
2609 *pfFFDone = true;
2610 break;
2611 }
2612 }
2613 }
2614 }
2615
2616 /*
2617 * Return to outer loop.
2618 */
2619#if defined(LOG_ENABLED) && defined(DEBUG)
2620 RTLogFlush(NULL);
2621#endif
2622 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2623 return rc;
2624}
2625
2626
2627/**
2628 * Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2629 *
2630 * This function contains the raw-mode version of the inner
2631 * execution loop (the outer loop being in EMR3ExecuteVM()).
2632 *
2633 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2634 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2635 *
2636 * @param pVM VM handle.
2637 * @param pfFFDone Where to store an indicator telling whether or not
2638 * FFs were done before returning.
2639 */
2640static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2641{
2642 int rc = VERR_INTERNAL_ERROR;
2643 PCPUMCTX pCtx = pVM->em.s.pCtx;
2644
2645 LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2646 *pfFFDone = false;
2647
2648 STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2649
2650 /*
2651 * Spin till we get a forced action which returns anything but VINF_SUCCESS.
2652 */
2653 for (;;)
2654 {
2655 STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2656
2657 /*
2658 * Check various preconditions.
2659 */
2660 VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_TSS));
2661
2662 /*
2663 * Process high priority pre-execution raw-mode FFs.
2664 */
2665 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2666 {
2667 rc = emR3RawForcedActions(pVM, pCtx);
2668 if (VBOX_FAILURE(rc))
2669 break;
2670 }
2671
2672#ifdef LOG_ENABLED
2673 uint8_t u8Vector;
2674
2675 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2676 if (rc == VINF_SUCCESS)
2677 {
2678 Log(("Pending hardware interrupt %d\n", u8Vector));
2679 }
2680 /*
2681 * Log important stuff before entering GC.
2682 */
2683 if (pCtx->eflags.Bits.u1VM)
2684 Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2685 else if ((pCtx->ss & X86_SEL_RPL) == 0)
2686 Log(("HWR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
2687 else if ((pCtx->ss & X86_SEL_RPL) == 3)
2688 Log(("HWR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
2689#endif
2690
2691
2692 /*
2693 * Execute the code.
2694 */
2695 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2696 STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2697 VMMR3Unlock(pVM);
2698 rc = VMMR3HwAccRunGC(pVM);
2699 VMMR3Lock(pVM);
2700 STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2701
2702 /*
2703 * Deal with high priority post execution FFs before doing anything else.
2704 */
2705 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2706 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2707 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2708
2709 /*
2710 * Process the returned status code.
2711 */
2712 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2713 break;
2714
2715 rc = emR3RawHandleRC(pVM, pCtx, rc);
2716 if (rc != VINF_SUCCESS)
2717 break;
2718
2719 /*
2720 * Check and execute forced actions.
2721 */
2722#ifdef VBOX_HIGH_RES_TIMERS_HACK
2723 TMTimerPoll(pVM);
2724#endif
2725 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2726 {
2727 rc = emR3ForcedActions(pVM, rc);
2728 if ( rc != VINF_SUCCESS
2729 && rc != VINF_EM_RESCHEDULE_HWACC)
2730 {
2731 *pfFFDone = true;
2732 break;
2733 }
2734 }
2735 }
2736 /*
2737 * Return to outer loop.
2738 */
2739#if defined(LOG_ENABLED) && defined(DEBUG)
2740 RTLogFlush(NULL);
2741#endif
2742 return rc;
2743}
2744
2745
2746/**
2747 * Decides whether to execute RAW, HWACC or REM.
2748 *
2749 * @returns new EM state
2750 * @param pVM The VM.
2751 * @param pCtx The CPU context.
2752 */
2753inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2754{
2755 /*
2756 * When forcing raw-mode execution, things are simple.
2757 */
2758 if (pVM->em.s.fForceRAW)
2759 return EMSTATE_RAW;
2760
2761 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2762 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2763 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2764
2765 X86EFLAGS EFlags = pCtx->eflags;
2766 if (HWACCMIsEnabled(pVM))
2767 {
2768 /* Hardware accelerated raw-mode:
2769 *
2770 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2771 */
2772 if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2773 return EMSTATE_HWACC;
2774
2775 /** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2776 return EMSTATE_REM;
2777 }
2778
2779 /* Standard raw-mode:
2780 *
2781 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2782 * or 32 bits protected mode ring 0 code
2783 *
2784 * The tests are ordered by the likelyhood of being true during normal execution.
2785 */
2786 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
2787 {
2788 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2789 return EMSTATE_REM;
2790 }
2791
2792#ifndef VBOX_RAW_V86
2793 if (EFlags.u32 & X86_EFL_VM) {
2794 Log2(("raw mode refused: VM_MASK\n"));
2795 return EMSTATE_REM;
2796 }
2797#endif
2798
2799 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2800 uint32_t u32CR0 = pCtx->cr0;
2801 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
2802 {
2803 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2804 return EMSTATE_REM;
2805 }
2806
2807 if (pCtx->cr4 & X86_CR4_PAE)
2808 {
2809 //Log2(("raw mode refused: PAE\n"));
2810 return EMSTATE_REM;
2811 }
2812
2813 unsigned uSS = pCtx->ss;
2814 if ( pCtx->eflags.Bits.u1VM
2815 || (uSS & X86_SEL_RPL) == 3)
2816 {
2817 if (!EMIsRawRing3Enabled(pVM))
2818 return EMSTATE_REM;
2819
2820 if (!(EFlags.u32 & X86_EFL_IF))
2821 {
2822 Log2(("raw mode refused: IF (RawR3)\n"));
2823 return EMSTATE_REM;
2824 }
2825
2826 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2827 {
2828 Log2(("raw mode refused: CR0.WP + RawR0\n"));
2829 return EMSTATE_REM;
2830 }
2831 }
2832 else
2833 {
2834 if (!EMIsRawRing0Enabled(pVM))
2835 return EMSTATE_REM;
2836
2837 /* Only ring 0 supervisor code. */
2838 if ((uSS & X86_SEL_RPL) != 0)
2839 {
2840 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2841 return EMSTATE_REM;
2842 }
2843
2844 // Let's start with pure 32 bits ring 0 code first
2845 /** @todo What's pure 32-bit mode? flat? */
2846 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2847 || !(pCtx->csHid.Attr.n.u1DefBig))
2848 {
2849 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2850 return EMSTATE_REM;
2851 }
2852
2853 /* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2854 if (!(u32CR0 & X86_CR0_WP))
2855 {
2856 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2857 return EMSTATE_REM;
2858 }
2859
2860 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2861 {
2862 Log2(("raw r0 mode forced: patch code\n"));
2863 return EMSTATE_RAW;
2864 }
2865
2866#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2867 if (!(EFlags.u32 & X86_EFL_IF))
2868 {
2869 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2870 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2871 return EMSTATE_REM;
2872 }
2873#endif
2874
2875 /** @todo still necessary??? */
2876 if (EFlags.Bits.u2IOPL != 0)
2877 {
2878 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2879 return EMSTATE_REM;
2880 }
2881 }
2882
2883 Assert(PGMPhysIsA20Enabled(pVM));
2884 return EMSTATE_RAW;
2885}
2886
2887
2888/**
2889 * Executes all high priority post execution force actions.
2890 *
2891 * @returns rc or a fatal status code.
2892 *
2893 * @param pVM VM handle.
2894 * @param rc The current rc.
2895 */
2896static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2897{
2898 if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2899 PDMR3CritSectFF(pVM);
2900
2901 if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
2902 CSAMR3DoPendingAction(pVM);
2903
2904 return rc;
2905}
2906
2907
2908/**
2909 * Executes all pending forced actions.
2910 *
2911 * Forced actions can cause execution delays and execution
2912 * rescheduling. The first we deal with using action priority, so
2913 * that for instance pending timers aren't scheduled and ran until
2914 * right before execution. The rescheduling we deal with using
2915 * return codes. The same goes for VM termination, only in that case
2916 * we exit everything.
2917 *
2918 * @returns VBox status code of equal or greater importance/severity than rc.
2919 * The most important ones are: VINF_EM_RESCHEDULE,
2920 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2921 *
2922 * @param pVM VM handle.
2923 * @param rc The current rc.
2924 *
2925 */
2926static int emR3ForcedActions(PVM pVM, int rc)
2927{
2928#ifdef VBOX_STRICT
2929 int rcIrq = VINF_SUCCESS;
2930#endif
2931 STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2932
2933#define UPDATE_RC() \
2934 do { \
2935 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2936 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
2937 break; \
2938 if (!rc || rc2 < rc) \
2939 rc = rc2; \
2940 } while (0)
2941
2942 int rc2;
2943
2944 /*
2945 * Post execution chunk first.
2946 */
2947 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2948 {
2949 /*
2950 * Termination request.
2951 */
2952 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
2953 {
2954 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
2955 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2956 return VINF_EM_TERMINATE;
2957 }
2958
2959 /*
2960 * Debugger Facility polling.
2961 */
2962 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
2963 {
2964 rc2 = DBGFR3VMMForcedAction(pVM);
2965 UPDATE_RC();
2966 }
2967
2968 /*
2969 * Postponed reset request.
2970 */
2971 if (VM_FF_ISSET(pVM, VM_FF_RESET))
2972 {
2973 rc2 = VMR3Reset(pVM);
2974 UPDATE_RC();
2975 VM_FF_CLEAR(pVM, VM_FF_RESET);
2976 }
2977
2978 /*
2979 * CSAM page scanning.
2980 */
2981 if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
2982 {
2983 PCPUMCTX pCtx = pVM->em.s.pCtx;
2984
2985 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
2986 Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
2987
2988 CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2989 VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
2990 }
2991
2992 /* check that we got them all */
2993 Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_CSAM_SCAN_PAGE)));
2994 }
2995
2996 /*
2997 * Normal priority then.
2998 * (Executed in no particular order.)
2999 */
3000 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3001 {
3002 /*
3003 * PDM Queues are pending.
3004 */
3005 if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3006 PDMR3QueueFlushAll(pVM);
3007
3008 /*
3009 * PDM DMA transfers are pending.
3010 */
3011 if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3012 PDMR3DmaRun(pVM);
3013
3014 /*
3015 * Requests from other threads.
3016 */
3017 if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3018 {
3019 rc2 = VMR3ReqProcess(pVM);
3020 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE)
3021 {
3022 Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3023 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3024 return rc2;
3025 }
3026 UPDATE_RC();
3027 }
3028
3029 /* check that we got them all */
3030 Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA)));
3031 }
3032
3033 /*
3034 * Execute polling function ever so often.
3035 * THIS IS A HACK, IT WILL BE *REPLACED* BY PROPER ASYNC NETWORKING SOON!
3036 */
3037 static unsigned cLast = 0;
3038 if (!((++cLast) % 4))
3039 PDMR3Poll(pVM);
3040
3041 /*
3042 * High priority pre execution chunk last.
3043 * (Executed in ascending priority order.)
3044 */
3045 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3046 {
3047 /*
3048 * Timers before interrupts.
3049 */
3050 if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3051 TMR3TimerQueuesDo(pVM);
3052
3053 /*
3054 * The instruction following an emulated STI should *always* be executed!
3055 */
3056 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3057 {
3058 Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3059 if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3060 {
3061 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3062 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3063 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3064 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3065 */
3066 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3067 }
3068 if (HWACCMR3IsActive(pVM))
3069 rc2 = VINF_EM_RESCHEDULE_HWACC;
3070 else
3071 rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3072
3073 UPDATE_RC();
3074 }
3075
3076 /*
3077 * Interrupts.
3078 */
3079 if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3080 && (!rc || rc >= VINF_EM_RESCHEDULE_RAW)
3081 && !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3082 && PATMAreInterruptsEnabled(pVM)
3083 && !HWACCMR3IsEventPending(pVM))
3084 {
3085 if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
3086 {
3087 /** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3088 /** @todo this really isn't nice, should properly handle this */
3089 rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3090#ifdef VBOX_STRICT
3091 rcIrq = rc2;
3092#endif
3093 UPDATE_RC();
3094 }
3095 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3096 else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3097 {
3098 rc2 = VINF_EM_RESCHEDULE_REM;
3099 UPDATE_RC();
3100 }
3101 }
3102
3103 /*
3104 * Debugger Facility request.
3105 */
3106 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3107 {
3108 rc2 = DBGFR3VMMForcedAction(pVM);
3109 UPDATE_RC();
3110 }
3111
3112 /*
3113 * Termination request.
3114 */
3115 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3116 {
3117 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3118 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3119 return VINF_EM_TERMINATE;
3120 }
3121
3122#ifdef DEBUG
3123 /*
3124 * Debug, pause the VM.
3125 */
3126 if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3127 {
3128 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3129 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3130 return VINF_EM_SUSPEND;
3131 }
3132
3133#endif
3134 /* check that we got them all */
3135 Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER | VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC | VM_FF_DBGF | VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_SELM_SYNC_TSS | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TERMINATE | VM_FF_DEBUG_SUSPEND | VM_FF_INHIBIT_INTERRUPTS)));
3136 }
3137
3138#undef UPDATE_RC
3139 Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3140 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3141 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
3142 return rc;
3143}
3144
3145
3146/**
3147 * Execute VM.
3148 *
3149 * This function is the main loop of the VM. The emulation thread
3150 * calls this function when the VM has been successfully constructed
3151 * and we're ready for executing the VM.
3152 *
3153 * Returning from this function means that the VM is turned off or
3154 * suspended (state already saved) and deconstruction in next in line.
3155 *
3156 * All interaction from other thread are done using forced actions
3157 * and signaling of the wait object.
3158 *
3159 * @returns VBox status code.
3160 * @param pVM The VM to operate on.
3161 */
3162EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3163{
3164 LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3165 pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3166 VM_ASSERT_EMT(pVM);
3167 Assert(pVM->em.s.enmState == EMSTATE_NONE || pVM->em.s.enmState == EMSTATE_SUSPENDED);
3168
3169 VMMR3Lock(pVM);
3170
3171 int rc = setjmp(pVM->em.s.u.FatalLongJump);
3172 if (rc == 0)
3173 {
3174 /*
3175 * Start the virtual time.
3176 */
3177 rc = TMVirtualResume(pVM);
3178 Assert(rc == VINF_SUCCESS);
3179 rc = TMCpuTickResume(pVM);
3180 Assert(rc == VINF_SUCCESS);
3181
3182 /*
3183 * The Outer Main Loop.
3184 */
3185 bool fFFDone = false;
3186 rc = VINF_EM_RESCHEDULE;
3187 pVM->em.s.enmState = EMSTATE_REM;
3188 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3189 for (;;)
3190 {
3191 /*
3192 * Before we can schedule anything (we're here because
3193 * scheduling is required) we must service any pending
3194 * forced actions to avoid any pending action causing
3195 * immidate rescheduling upon entering an inner loop
3196 *
3197 * Do forced actions.
3198 */
3199 if ( !fFFDone
3200 && rc != VINF_EM_TERMINATE
3201 && rc != VINF_EM_OFF
3202 && VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3203 {
3204 rc = emR3ForcedActions(pVM, rc);
3205 if ( ( rc == VINF_EM_RESCHEDULE_REM
3206 || rc == VINF_EM_RESCHEDULE_HWACC)
3207 && pVM->em.s.fForceRAW)
3208 rc = VINF_EM_RESCHEDULE_RAW;
3209 }
3210 else if (fFFDone)
3211 fFFDone = false;
3212
3213 /*
3214 * Now what to do?
3215 */
3216 Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3217 switch (rc)
3218 {
3219 /*
3220 * Keep doing what we're currently doing.
3221 */
3222 case VINF_SUCCESS:
3223 break;
3224
3225 /*
3226 * Reschedule - to raw-mode execution.
3227 */
3228 case VINF_EM_RESCHEDULE_RAW:
3229 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3230 pVM->em.s.enmState = EMSTATE_RAW;
3231 break;
3232
3233 /*
3234 * Reschedule - to hardware accelerated raw-mode execution.
3235 */
3236 case VINF_EM_RESCHEDULE_HWACC:
3237 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3238 Assert(!pVM->em.s.fForceRAW);
3239 pVM->em.s.enmState = EMSTATE_HWACC;
3240 break;
3241
3242 /*
3243 * Reschedule - to recompiled execution.
3244 */
3245 case VINF_EM_RESCHEDULE_REM:
3246 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3247 pVM->em.s.enmState = EMSTATE_REM;
3248 break;
3249
3250 /*
3251 * Resume.
3252 */
3253 case VINF_EM_RESUME:
3254 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3255 /* fall through and get scheduled. */
3256
3257 /*
3258 * Reschedule.
3259 */
3260 case VINF_EM_RESCHEDULE:
3261 {
3262 EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3263 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3264 pVM->em.s.enmState = enmState;
3265 break;
3266 }
3267
3268 /*
3269 * Halted.
3270 */
3271 case VINF_EM_HALT:
3272 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3273 pVM->em.s.enmState = EMSTATE_HALTED;
3274 break;
3275
3276 /*
3277 * Suspend.
3278 */
3279 case VINF_EM_SUSPEND:
3280 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3281 pVM->em.s.enmState = EMSTATE_SUSPENDED;
3282 break;
3283
3284 /*
3285 * Reset.
3286 * We might end up doing a double reset for now, we'll have to clean up the mess later.
3287 */
3288 case VINF_EM_RESET:
3289 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3290 pVM->em.s.enmState = EMSTATE_REM;
3291 break;
3292
3293 /*
3294 * Power Off.
3295 */
3296 case VINF_EM_OFF:
3297 pVM->em.s.enmState = EMSTATE_TERMINATING;
3298 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3299 TMVirtualPause(pVM);
3300 TMCpuTickPause(pVM);
3301 VMMR3Unlock(pVM);
3302 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3303 return rc;
3304
3305 /*
3306 * Terminate the VM.
3307 */
3308 case VINF_EM_TERMINATE:
3309 pVM->em.s.enmState = EMSTATE_TERMINATING;
3310 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3311 TMVirtualPause(pVM);
3312 TMCpuTickPause(pVM);
3313 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3314 return rc;
3315
3316 /*
3317 * Guest debug events.
3318 */
3319 case VINF_EM_DBG_STEPPED:
3320 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3321 case VINF_EM_DBG_STOP:
3322 case VINF_EM_DBG_BREAKPOINT:
3323 case VINF_EM_DBG_STEP:
3324 if (pVM->em.s.enmState == EMSTATE_RAW)
3325 {
3326 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3327 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3328 }
3329 else
3330 {
3331 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3332 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3333 }
3334 break;
3335
3336 /*
3337 * Hypervisor debug events.
3338 */
3339 case VINF_EM_DBG_HYPER_STEPPED:
3340 case VINF_EM_DBG_HYPER_BREAKPOINT:
3341 case VINF_EM_DBG_HYPER_ASSERTION:
3342 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3343 pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3344 break;
3345
3346 /*
3347 * Any error code showing up here other than the ones we
3348 * know and process above are considered to be FATAL.
3349 *
3350 * Unknown warnings and informational status codes are also
3351 * included in this.
3352 */
3353 default:
3354 if (VBOX_SUCCESS(rc))
3355 {
3356 AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3357 rc = VERR_EM_INTERNAL_ERROR;
3358 }
3359 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3360 Log(("EMR3ExecuteVM returns %d\n", rc));
3361 break;
3362 }
3363
3364
3365 /*
3366 * Any waiters can now be woken up
3367 */
3368 VMMR3Unlock(pVM);
3369 VMMR3Lock(pVM);
3370
3371 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3372 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3373
3374 /*
3375 * Act on the state.
3376 */
3377 switch (pVM->em.s.enmState)
3378 {
3379 /*
3380 * Execute raw.
3381 */
3382 case EMSTATE_RAW:
3383 rc = emR3RawExecute(pVM, &fFFDone);
3384 break;
3385
3386 /*
3387 * Execute hardware accelerated raw.
3388 */
3389 case EMSTATE_HWACC:
3390 rc = emR3HwAccExecute(pVM, &fFFDone);
3391 break;
3392
3393 /*
3394 * Execute recompiled.
3395 */
3396 case EMSTATE_REM:
3397 rc = emR3RemExecute(pVM, &fFFDone);
3398 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3399 break;
3400
3401 /*
3402 * hlt - execution halted until interrupt.
3403 */
3404 case EMSTATE_HALTED:
3405 {
3406 STAM_PROFILE_START(&pVM->em.s.StatHalted, y);
3407 rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3408 STAM_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3409 break;
3410 }
3411
3412 /*
3413 * Suspended - return to VM.cpp.
3414 */
3415 case EMSTATE_SUSPENDED:
3416 TMVirtualPause(pVM);
3417 TMCpuTickPause(pVM);
3418 VMMR3Unlock(pVM);
3419 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3420 return VINF_EM_SUSPEND;
3421
3422 /*
3423 * Debugging in the guest.
3424 */
3425 case EMSTATE_DEBUG_GUEST_REM:
3426 case EMSTATE_DEBUG_GUEST_RAW:
3427 TMVirtualPause(pVM);
3428 TMCpuTickPause(pVM);
3429 rc = emR3Debug(pVM, rc);
3430 TMVirtualResume(pVM);
3431 TMCpuTickResume(pVM);
3432 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3433 break;
3434
3435 /*
3436 * Debugging in the hypervisor.
3437 */
3438 case EMSTATE_DEBUG_HYPER:
3439 {
3440 TMVirtualPause(pVM);
3441 TMCpuTickPause(pVM);
3442 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3443
3444 rc = emR3Debug(pVM, rc);
3445 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3446 if (rc != VINF_SUCCESS)
3447 {
3448 /* switch to guru meditation mode */
3449 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3450 VMMR3FatalDump(pVM, rc);
3451 return rc;
3452 }
3453
3454 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3455 TMVirtualResume(pVM);
3456 TMCpuTickResume(pVM);
3457 break;
3458 }
3459
3460 /*
3461 * Guru meditation takes place in the debugger.
3462 */
3463 case EMSTATE_GURU_MEDITATION:
3464 {
3465 /** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3466 TMVirtualPause(pVM);
3467 TMCpuTickPause(pVM);
3468 VMMR3FatalDump(pVM, rc);
3469 int rc2 = emR3Debug(pVM, rc);
3470 if (rc2 == VERR_DBGF_NOT_ATTACHED)
3471 {
3472 VMMR3Unlock(pVM);
3473 /** @todo change the VM state! */
3474 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3475 return rc;
3476 }
3477 TMVirtualResume(pVM);
3478 TMCpuTickResume(pVM);
3479 rc = rc2;
3480 /** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3481 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3482 break;
3483 }
3484
3485 /*
3486 * The states we don't expect here.
3487 */
3488 case EMSTATE_NONE:
3489 case EMSTATE_TERMINATING:
3490 default:
3491 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3492 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3493 TMVirtualPause(pVM);
3494 TMCpuTickPause(pVM);
3495 VMMR3Unlock(pVM);
3496 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3497 return VERR_EM_INTERNAL_ERROR;
3498 }
3499 } /* The Outer Main Loop */
3500 }
3501 else
3502 {
3503 /*
3504 * Fatal error.
3505 */
3506 LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3507 TMVirtualPause(pVM);
3508 TMCpuTickPause(pVM);
3509 VMMR3FatalDump(pVM, rc);
3510 emR3Debug(pVM, rc);
3511 VMMR3Unlock(pVM);
3512 /** @todo change the VM state! */
3513 return rc;
3514 }
3515
3516 /* (won't ever get here). */
3517 AssertFailed();
3518}
3519
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